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| author | Paul Faria <paulfaria@google.com> | 2024-04-29 22:08:00 +0000 |
|---|---|---|
| committer | Gerrit Code Review <noreply-gerritcodereview@google.com> | 2024-04-29 22:08:00 +0000 |
| commit | 2866e1567b87343d0a7e3fa01fc67c442d276d82 (patch) | |
| tree | a1ea903581d733b7fa3ec83574c592ae4dfc3c16 | |
| parent | 29b0a3fb9503a12bf35fc50442db6baa5118d6af (diff) | |
| parent | 64a83f4bbf7e8c99995edb8db241bcae804bffa1 (diff) | |
| download | binary_translation-2866e1567b87343d0a7e3fa01fc67c442d276d82.tar.gz | |
Merge "[interpreter/riscv64] Do not mask alignment check" into main
| -rw-r--r-- | interpreter/riscv64/interpreter.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/interpreter/riscv64/interpreter.h b/interpreter/riscv64/interpreter.h index 469b4728..561772f1 100644 --- a/interpreter/riscv64/interpreter.h +++ b/interpreter/riscv64/interpreter.h @@ -2944,7 +2944,7 @@ class Interpreter { void OpVectorToMask(uint8_t dst, Args... args) { // All args, except dst must be aligned at kRegistersInvolved amount. We'll merge them // together and then do a combined check for all of them at once. - if (!IsAligned<kRegistersInvolved>(OrValuesOnlyForType<Vec>(args...) | dst)) { + if (!IsAligned<kRegistersInvolved>(OrValuesOnlyForType<Vec>(args...))) { return Undefined(); } SIMD128Register original_result(state_->cpu.v[dst]); |