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-rw-r--r--lib/Target/ARM64/ARM64InstrFormats.td194
1 files changed, 110 insertions, 84 deletions
diff --git a/lib/Target/ARM64/ARM64InstrFormats.td b/lib/Target/ARM64/ARM64InstrFormats.td
index 86ddb0722a..ea6484985e 100644
--- a/lib/Target/ARM64/ARM64InstrFormats.td
+++ b/lib/Target/ARM64/ARM64InstrFormats.td
@@ -191,7 +191,7 @@ def SImm7s4Operand : AsmOperandClass {
}
def simm7s4 : Operand<i32> {
let ParserMatchClass = SImm7s4Operand;
- let PrintMethod = "printImmScale4";
+ let PrintMethod = "printImmScale<4>";
}
// simm7s8 predicate - True if the immediate is a multiple of 8 in the range
@@ -202,7 +202,7 @@ def SImm7s8Operand : AsmOperandClass {
}
def simm7s8 : Operand<i32> {
let ParserMatchClass = SImm7s8Operand;
- let PrintMethod = "printImmScale8";
+ let PrintMethod = "printImmScale<8>";
}
// simm7s16 predicate - True if the immediate is a multiple of 16 in the range
@@ -213,7 +213,7 @@ def SImm7s16Operand : AsmOperandClass {
}
def simm7s16 : Operand<i32> {
let ParserMatchClass = SImm7s16Operand;
- let PrintMethod = "printImmScale16";
+ let PrintMethod = "printImmScale<16>";
}
// imm0_65535 predicate - True if the immediate is in the range [0,65535].
@@ -222,6 +222,7 @@ def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
return ((uint32_t)Imm) < 65536;
}]> {
let ParserMatchClass = Imm0_65535Operand;
+ let PrintMethod = "printHexImm";
}
def Imm1_8Operand : AsmOperandClass {
@@ -452,6 +453,7 @@ def imm0_255 : Operand<i32>, ImmLeaf<i32, [{
return ((uint32_t)Imm) < 256;
}]> {
let ParserMatchClass = Imm0_255Operand;
+ let PrintMethod = "printHexImm";
}
// imm0_127 predicate - True if the immediate is in the range [0,127]
@@ -460,6 +462,7 @@ def imm0_127 : Operand<i32>, ImmLeaf<i32, [{
return ((uint32_t)Imm) < 128;
}]> {
let ParserMatchClass = Imm0_127Operand;
+ let PrintMethod = "printHexImm";
}
// NOTE: These imm0_N operands have to be of type i64 because i64 is the size
@@ -724,6 +727,7 @@ class CRmSystemI<Operand crmtype, bits<3> opc, string asm>
def MRSSystemRegisterOperand : AsmOperandClass {
let Name = "MRSSystemRegister";
let ParserMethod = "tryParseSysReg";
+ let DiagnosticType = "MRS";
}
// concatenation of 1, op0, op1, CRn, CRm, op2. 16-bit immediate.
def mrs_sysreg_op : Operand<i32> {
@@ -735,6 +739,7 @@ def mrs_sysreg_op : Operand<i32> {
def MSRSystemRegisterOperand : AsmOperandClass {
let Name = "MSRSystemRegister";
let ParserMethod = "tryParseSysReg";
+ let DiagnosticType = "MSR";
}
def msr_sysreg_op : Operand<i32> {
let ParserMatchClass = MSRSystemRegisterOperand;
@@ -749,7 +754,7 @@ class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
let Inst{19-5} = systemreg;
}
-// FIXME: Some of these def CPSR, others don't. Best way to model that?
+// FIXME: Some of these def NZCV, others don't. Best way to model that?
// Explicitly modeling each of the system register as a register class
// would do it, but feels like overkill at this point.
class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
@@ -759,28 +764,29 @@ class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
let Inst{19-5} = systemreg;
}
-def SystemCPSRFieldOperand : AsmOperandClass {
- let Name = "SystemCPSRField";
+def SystemPStateFieldOperand : AsmOperandClass {
+ let Name = "SystemPStateField";
let ParserMethod = "tryParseSysReg";
}
-def cpsrfield_op : Operand<i32> {
- let ParserMatchClass = SystemCPSRFieldOperand;
- let PrintMethod = "printSystemCPSRField";
+def pstatefield_op : Operand<i32> {
+ let ParserMatchClass = SystemPStateFieldOperand;
+ let PrintMethod = "printSystemPStateField";
}
-let Defs = [CPSR] in
-class MSRcpsrI : SimpleSystemI<0, (ins cpsrfield_op:$cpsr_field, imm0_15:$imm),
- "msr", "\t$cpsr_field, $imm">,
- Sched<[WriteSys]> {
- bits<6> cpsrfield;
+let Defs = [NZCV] in
+class MSRpstateI
+ : SimpleSystemI<0, (ins pstatefield_op:$pstate_field, imm0_15:$imm),
+ "msr", "\t$pstate_field, $imm">,
+ Sched<[WriteSys]> {
+ bits<6> pstatefield;
bits<4> imm;
let Inst{20-19} = 0b00;
- let Inst{18-16} = cpsrfield{5-3};
+ let Inst{18-16} = pstatefield{5-3};
let Inst{15-12} = 0b0100;
let Inst{11-8} = imm;
- let Inst{7-5} = cpsrfield{2-0};
+ let Inst{7-5} = pstatefield{2-0};
- let DecoderMethod = "DecodeSystemCPSRInstruction";
+ let DecoderMethod = "DecodeSystemPStateInstruction";
}
// SYS and SYSL generic system instructions.
@@ -879,11 +885,11 @@ def am_brcond : Operand<OtherVT> {
class BranchCond : I<(outs), (ins dotCcode:$cond, am_brcond:$target),
"b", "$cond\t$target", "",
- [(ARM64brcond bb:$target, imm:$cond, CPSR)]>,
+ [(ARM64brcond bb:$target, imm:$cond, NZCV)]>,
Sched<[WriteBr]> {
let isBranch = 1;
let isTerminator = 1;
- let Uses = [CPSR];
+ let Uses = [NZCV];
bits<4> cond;
bits<19> target;
@@ -1038,7 +1044,7 @@ class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
: I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
asm, "\t$Rd, $Rn, $Rm", "", pattern>,
Sched<[WriteI]> {
- let Uses = [CPSR];
+ let Uses = [NZCV];
bits<5> Rd;
bits<5> Rn;
bits<5> Rm;
@@ -1053,14 +1059,14 @@ class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
class BaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
SDNode OpNode>
: BaseBaseAddSubCarry<isSub, regtype, asm,
- [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, CPSR))]>;
+ [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
class BaseAddSubCarrySetFlags<bit isSub, RegisterClass regtype, string asm,
SDNode OpNode>
: BaseBaseAddSubCarry<isSub, regtype, asm,
- [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, CPSR)),
- (implicit CPSR)]> {
- let Defs = [CPSR];
+ [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
+ (implicit NZCV)]> {
+ let Defs = [NZCV];
}
multiclass AddSubCarry<bit isSub, string asm, string asm_setflags,
@@ -1272,6 +1278,7 @@ class ADRI<bit page, string asm, Operand adr, list<dag> pattern>
def movimm32_imm : Operand<i32> {
let ParserMatchClass = Imm0_65535Operand;
let EncoderMethod = "getMoveWideImmOpValue";
+ let PrintMethod = "printHexImm";
}
def movimm32_shift : Operand<i32> {
let PrintMethod = "printShifter";
@@ -1518,7 +1525,7 @@ multiclass AddSub<bit isSub, string mnemonic,
}
multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode> {
- let isCompare = 1, Defs = [CPSR] in {
+ let isCompare = 1, Defs = [NZCV] in {
// Add/Subtract immediate
def Wri : BaseAddSubImm<isSub, 1, GPR32, GPR32sp, addsub_shifted_imm32,
mnemonic, OpNode> {
@@ -1561,7 +1568,7 @@ multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode> {
let Inst{14-13} = 0b11;
let Inst{31} = 1;
}
- } // Defs = [CPSR]
+ } // Defs = [NZCV]
// Register/register aliases with no shift when SP is not used.
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
@@ -1766,7 +1773,7 @@ multiclass LogicalImm<bits<2> opc, string mnemonic, SDNode OpNode> {
}
multiclass LogicalImmS<bits<2> opc, string mnemonic, SDNode OpNode> {
- let isCompare = 1, Defs = [CPSR] in {
+ let isCompare = 1, Defs = [NZCV] in {
def Wri : BaseLogicalImm<opc, GPR32, GPR32, logical_imm32, mnemonic,
[(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_imm32:$imm))]> {
let Inst{31} = 0;
@@ -1776,7 +1783,7 @@ multiclass LogicalImmS<bits<2> opc, string mnemonic, SDNode OpNode> {
[(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_imm64:$imm))]> {
let Inst{31} = 1;
}
- } // end Defs = [CPSR]
+ } // end Defs = [NZCV]
}
class BaseLogicalRegPseudo<RegisterClass regtype, SDPatternOperator OpNode>
@@ -1807,10 +1814,10 @@ multiclass LogicalReg<bits<2> opc, bit N, string mnemonic,
!cast<Instruction>(NAME#"Xrs"), GPR64>;
}
-// Split from LogicalReg to allow setting CPSR Defs
+// Split from LogicalReg to allow setting NZCV Defs
multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic,
SDPatternOperator OpNode = null_frag> {
- let Defs = [CPSR], mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
+ let Defs = [NZCV], mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
@@ -1822,7 +1829,7 @@ multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic,
[(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_shifted_reg64:$Rm))]> {
let Inst{31} = 1;
}
- } // Defs = [CPSR]
+ } // Defs = [NZCV]
def : LogicalRegAlias<mnemonic,
!cast<Instruction>(NAME#"Wrs"), GPR32>;
@@ -1845,8 +1852,8 @@ class BaseCondSetFlagsImm<bit op, RegisterClass regtype, string asm>
: I<(outs), (ins regtype:$Rn, imm0_31:$imm, imm0_15:$nzcv, ccode:$cond),
asm, "\t$Rn, $imm, $nzcv, $cond", "", []>,
Sched<[WriteI]> {
- let Uses = [CPSR];
- let Defs = [CPSR];
+ let Uses = [NZCV];
+ let Defs = [NZCV];
bits<5> Rn;
bits<5> imm;
@@ -1877,8 +1884,8 @@ class BaseCondSetFlagsReg<bit op, RegisterClass regtype, string asm>
: I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
Sched<[WriteI]> {
- let Uses = [CPSR];
- let Defs = [CPSR];
+ let Uses = [NZCV];
+ let Defs = [NZCV];
bits<5> Rn;
bits<5> Rm;
@@ -1912,9 +1919,9 @@ class BaseCondSelect<bit op, bits<2> op2, RegisterClass regtype, string asm>
: I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
asm, "\t$Rd, $Rn, $Rm, $cond", "",
[(set regtype:$Rd,
- (ARM64csel regtype:$Rn, regtype:$Rm, (i32 imm:$cond), CPSR))]>,
+ (ARM64csel regtype:$Rn, regtype:$Rm, (i32 imm:$cond), NZCV))]>,
Sched<[WriteI]> {
- let Uses = [CPSR];
+ let Uses = [NZCV];
bits<5> Rd;
bits<5> Rn;
@@ -1945,9 +1952,9 @@ class BaseCondSelectOp<bit op, bits<2> op2, RegisterClass regtype, string asm,
asm, "\t$Rd, $Rn, $Rm, $cond", "",
[(set regtype:$Rd,
(ARM64csel regtype:$Rn, (frag regtype:$Rm),
- (i32 imm:$cond), CPSR))]>,
+ (i32 imm:$cond), NZCV))]>,
Sched<[WriteI]> {
- let Uses = [CPSR];
+ let Uses = [NZCV];
bits<5> Rd;
bits<5> Rn;
@@ -1976,11 +1983,11 @@ multiclass CondSelectOp<bit op, bits<2> op2, string asm, PatFrag frag> {
let Inst{31} = 1;
}
- def : Pat<(ARM64csel (frag GPR32:$Rm), GPR32:$Rn, (i32 imm:$cond), CPSR),
+ def : Pat<(ARM64csel (frag GPR32:$Rm), GPR32:$Rn, (i32 imm:$cond), NZCV),
(!cast<Instruction>(NAME # Wr) GPR32:$Rn, GPR32:$Rm,
(inv_cond_XFORM imm:$cond))>;
- def : Pat<(ARM64csel (frag GPR64:$Rm), GPR64:$Rn, (i32 imm:$cond), CPSR),
+ def : Pat<(ARM64csel (frag GPR64:$Rm), GPR64:$Rn, (i32 imm:$cond), NZCV),
(!cast<Instruction>(NAME # Xr) GPR64:$Rn, GPR64:$Rm,
(inv_cond_XFORM imm:$cond))>;
}
@@ -2008,7 +2015,7 @@ def MemoryIndexed8Operand : AsmOperandClass {
}
def am_indexed8 : Operand<i64>,
ComplexPattern<i64, 2, "SelectAddrModeIndexed8", []> {
- let PrintMethod = "printAMIndexed8";
+ let PrintMethod = "printAMIndexed<8>";
let EncoderMethod
= "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale1>";
let ParserMatchClass = MemoryIndexed8Operand;
@@ -2023,7 +2030,7 @@ def MemoryIndexed16Operand : AsmOperandClass {
}
def am_indexed16 : Operand<i64>,
ComplexPattern<i64, 2, "SelectAddrModeIndexed16", []> {
- let PrintMethod = "printAMIndexed16";
+ let PrintMethod = "printAMIndexed<16>";
let EncoderMethod
= "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale2>";
let ParserMatchClass = MemoryIndexed16Operand;
@@ -2038,7 +2045,7 @@ def MemoryIndexed32Operand : AsmOperandClass {
}
def am_indexed32 : Operand<i64>,
ComplexPattern<i64, 2, "SelectAddrModeIndexed32", []> {
- let PrintMethod = "printAMIndexed32";
+ let PrintMethod = "printAMIndexed<32>";
let EncoderMethod
= "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale4>";
let ParserMatchClass = MemoryIndexed32Operand;
@@ -2053,7 +2060,7 @@ def MemoryIndexed64Operand : AsmOperandClass {
}
def am_indexed64 : Operand<i64>,
ComplexPattern<i64, 2, "SelectAddrModeIndexed64", []> {
- let PrintMethod = "printAMIndexed64";
+ let PrintMethod = "printAMIndexed<64>";
let EncoderMethod
= "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale8>";
let ParserMatchClass = MemoryIndexed64Operand;
@@ -2068,7 +2075,7 @@ def MemoryIndexed128Operand : AsmOperandClass {
}
def am_indexed128 : Operand<i64>,
ComplexPattern<i64, 2, "SelectAddrModeIndexed128", []> {
- let PrintMethod = "printAMIndexed128";
+ let PrintMethod = "printAMIndexed<128>";
let EncoderMethod
= "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale16>";
let ParserMatchClass = MemoryIndexed128Operand;
@@ -2192,7 +2199,7 @@ def MemROAsmOperand64 : MemROAsmOperand<64>;
def MemROAsmOperand128 : MemROAsmOperand<128>;
class ro_indexed<int sz> : Operand<i64> { // ComplexPattern<...>
- let PrintMethod = "printMemoryRegOffset"#sz;
+ let PrintMethod = "printMemoryRegOffset<" # sz # ">";
let MIOperandInfo = (ops GPR64sp:$base, GPR64:$offset, i32imm:$extend);
}
@@ -2460,12 +2467,12 @@ def MemoryUnscaledOperand : AsmOperandClass {
let DiagnosticType = "InvalidMemoryIndexedSImm9";
}
class am_unscaled_operand : Operand<i64> {
- let PrintMethod = "printAMUnscaled";
+ let PrintMethod = "printAMIndexed<8>";
let ParserMatchClass = MemoryUnscaledOperand;
let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
}
class am_unscaled_wb_operand : Operand<i64> {
- let PrintMethod = "printAMUnscaledWB";
+ let PrintMethod = "printAMIndexedWB<8>";
let ParserMatchClass = MemoryUnscaledOperand;
let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
}
@@ -2787,12 +2794,12 @@ def MemoryIndexed32SImm7 : AsmOperandClass {
let DiagnosticType = "InvalidMemoryIndexed32SImm7";
}
def am_indexed32simm7 : Operand<i32> { // ComplexPattern<...>
- let PrintMethod = "printAMIndexed32";
+ let PrintMethod = "printAMIndexed<32>";
let ParserMatchClass = MemoryIndexed32SImm7;
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
}
def am_indexed32simm7_wb : Operand<i32> { // ComplexPattern<...>
- let PrintMethod = "printAMIndexed32WB";
+ let PrintMethod = "printAMIndexedWB<32>";
let ParserMatchClass = MemoryIndexed32SImm7;
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
}
@@ -2802,12 +2809,12 @@ def MemoryIndexed64SImm7 : AsmOperandClass {
let DiagnosticType = "InvalidMemoryIndexed64SImm7";
}
def am_indexed64simm7 : Operand<i32> { // ComplexPattern<...>
- let PrintMethod = "printAMIndexed64";
+ let PrintMethod = "printAMIndexed<64>";
let ParserMatchClass = MemoryIndexed64SImm7;
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
}
def am_indexed64simm7_wb : Operand<i32> { // ComplexPattern<...>
- let PrintMethod = "printAMIndexed64WB";
+ let PrintMethod = "printAMIndexedWB<64>";
let ParserMatchClass = MemoryIndexed64SImm7;
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
}
@@ -2817,12 +2824,12 @@ def MemoryIndexed128SImm7 : AsmOperandClass {
let DiagnosticType = "InvalidMemoryIndexed128SImm7";
}
def am_indexed128simm7 : Operand<i32> { // ComplexPattern<...>
- let PrintMethod = "printAMIndexed128";
+ let PrintMethod = "printAMIndexed<128>";
let ParserMatchClass = MemoryIndexed128SImm7;
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
}
def am_indexed128simm7_wb : Operand<i32> { // ComplexPattern<...>
- let PrintMethod = "printAMIndexed128WB";
+ let PrintMethod = "printAMIndexedWB<128>";
let ParserMatchClass = MemoryIndexed128SImm7;
let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
}
@@ -3606,27 +3613,27 @@ class BaseTwoOperandFPComparison<bit signalAllNans, RegisterClass regtype,
multiclass FPComparison<bit signalAllNans, string asm,
SDPatternOperator OpNode = null_frag> {
- let Defs = [CPSR] in {
+ let Defs = [NZCV] in {
def Srr : BaseTwoOperandFPComparison<signalAllNans, FPR32, asm,
- [(OpNode FPR32:$Rn, (f32 FPR32:$Rm)), (implicit CPSR)]> {
+ [(OpNode FPR32:$Rn, (f32 FPR32:$Rm)), (implicit NZCV)]> {
let Inst{22} = 0;
}
def Sri : BaseOneOperandFPComparison<signalAllNans, FPR32, asm,
- [(OpNode (f32 FPR32:$Rn), fpimm0), (implicit CPSR)]> {
+ [(OpNode (f32 FPR32:$Rn), fpimm0), (implicit NZCV)]> {
let Inst{22} = 0;
}
def Drr : BaseTwoOperandFPComparison<signalAllNans, FPR64, asm,
- [(OpNode FPR64:$Rn, (f64 FPR64:$Rm)), (implicit CPSR)]> {
+ [(OpNode FPR64:$Rn, (f64 FPR64:$Rm)), (implicit NZCV)]> {
let Inst{22} = 1;
}
def Dri : BaseOneOperandFPComparison<signalAllNans, FPR64, asm,
- [(OpNode (f64 FPR64:$Rn), fpimm0), (implicit CPSR)]> {
+ [(OpNode (f64 FPR64:$Rn), fpimm0), (implicit NZCV)]> {
let Inst{22} = 1;
}
- } // Defs = [CPSR]
+ } // Defs = [NZCV]
}
//---
@@ -3655,7 +3662,7 @@ class BaseFPCondComparison<bit signalAllNans,
}
multiclass FPCondComparison<bit signalAllNans, string asm> {
- let Defs = [CPSR], Uses = [CPSR] in {
+ let Defs = [NZCV], Uses = [NZCV] in {
def Srr : BaseFPCondComparison<signalAllNans, FPR32, asm> {
let Inst{22} = 0;
}
@@ -3663,7 +3670,7 @@ multiclass FPCondComparison<bit signalAllNans, string asm> {
def Drr : BaseFPCondComparison<signalAllNans, FPR64, asm> {
let Inst{22} = 1;
}
- } // Defs = [CPSR], Uses = [CPSR]
+ } // Defs = [NZCV], Uses = [NZCV]
}
//---
@@ -3675,7 +3682,7 @@ class BaseFPCondSelect<RegisterClass regtype, ValueType vt, string asm>
asm, "\t$Rd, $Rn, $Rm, $cond", "",
[(set regtype:$Rd,
(ARM64csel (vt regtype:$Rn), regtype:$Rm,
- (i32 imm:$cond), CPSR))]>,
+ (i32 imm:$cond), NZCV))]>,
Sched<[WriteF]> {
bits<5> Rd;
bits<5> Rn;
@@ -3692,7 +3699,7 @@ class BaseFPCondSelect<RegisterClass regtype, ValueType vt, string asm>
}
multiclass FPCondSelect<string asm> {
- let Uses = [CPSR] in {
+ let Uses = [NZCV] in {
def Srrr : BaseFPCondSelect<FPR32, f32, asm> {
let Inst{22} = 0;
}
@@ -3700,7 +3707,7 @@ multiclass FPCondSelect<string asm> {
def Drrr : BaseFPCondSelect<FPR64, f64, asm> {
let Inst{22} = 1;
}
- } // Uses = [CPSR]
+ } // Uses = [NZCV]
}
//---
@@ -4415,11 +4422,12 @@ multiclass SIMDMixedTwoVector<bit U, bits<5> opc, string asm,
}
class BaseSIMDCmpTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
- RegisterOperand regtype, string asm, string kind,
+ RegisterOperand regtype,
+ string asm, string kind, string zero,
ValueType dty, ValueType sty, SDNode OpNode>
: I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
- "{\t$Rd" # kind # ", $Rn" # kind # ", #0" #
- "|" # kind # "\t$Rd, $Rn, #0}", "",
+ "{\t$Rd" # kind # ", $Rn" # kind # ", #" # zero #
+ "|" # kind # "\t$Rd, $Rn, #" # zero # "}", "",
[(set (dty regtype:$Rd), (OpNode (sty regtype:$Rn)))]>,
Sched<[WriteV]> {
bits<5> Rd;
@@ -4440,25 +4448,25 @@ class BaseSIMDCmpTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
multiclass SIMDCmpTwoVector<bit U, bits<5> opc, string asm,
SDNode OpNode> {
def v8i8rz : BaseSIMDCmpTwoVector<0, U, 0b00, opc, V64,
- asm, ".8b",
+ asm, ".8b", "0",
v8i8, v8i8, OpNode>;
def v16i8rz : BaseSIMDCmpTwoVector<1, U, 0b00, opc, V128,
- asm, ".16b",
+ asm, ".16b", "0",
v16i8, v16i8, OpNode>;
def v4i16rz : BaseSIMDCmpTwoVector<0, U, 0b01, opc, V64,
- asm, ".4h",
+ asm, ".4h", "0",
v4i16, v4i16, OpNode>;
def v8i16rz : BaseSIMDCmpTwoVector<1, U, 0b01, opc, V128,
- asm, ".8h",
+ asm, ".8h", "0",
v8i16, v8i16, OpNode>;
def v2i32rz : BaseSIMDCmpTwoVector<0, U, 0b10, opc, V64,
- asm, ".2s",
+ asm, ".2s", "0",
v2i32, v2i32, OpNode>;
def v4i32rz : BaseSIMDCmpTwoVector<1, U, 0b10, opc, V128,
- asm, ".4s",
+ asm, ".4s", "0",
v4i32, v4i32, OpNode>;
def v2i64rz : BaseSIMDCmpTwoVector<1, U, 0b11, opc, V128,
- asm, ".2d",
+ asm, ".2d", "0",
v2i64, v2i64, OpNode>;
}
@@ -4466,14 +4474,27 @@ multiclass SIMDCmpTwoVector<bit U, bits<5> opc, string asm,
multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
string asm, SDNode OpNode> {
def v2i32rz : BaseSIMDCmpTwoVector<0, U, {S,0}, opc, V64,
- asm, ".2s",
+ asm, ".2s", "0.0",
v2i32, v2f32, OpNode>;
def v4i32rz : BaseSIMDCmpTwoVector<1, U, {S,0}, opc, V128,
- asm, ".4s",
+ asm, ".4s", "0.0",
v4i32, v4f32, OpNode>;
def v2i64rz : BaseSIMDCmpTwoVector<1, U, {S,1}, opc, V128,
- asm, ".2d",
+ asm, ".2d", "0.0",
v2i64, v2f64, OpNode>;
+
+ def : InstAlias<asm # " $Vd.2s, $Vn.2s, #0",
+ (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
+ def : InstAlias<asm # " $Vd.4s, $Vn.4s, #0",
+ (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
+ def : InstAlias<asm # " $Vd.2d, $Vn.2d, #0",
+ (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
+ def : InstAlias<asm # ".2s $Vd, $Vn, #0",
+ (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
+ def : InstAlias<asm # ".4s $Vd, $Vn, #0",
+ (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
+ def : InstAlias<asm # ".2d $Vd, $Vn, #0",
+ (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
}
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
@@ -5182,9 +5203,9 @@ class BaseSIMDTwoScalarTied<bit U, bits<2> size, bits<5> opcode,
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
class BaseSIMDCmpTwoScalar<bit U, bits<2> size, bits<5> opcode,
- RegisterClass regtype, string asm>
+ RegisterClass regtype, string asm, string zero>
: I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
- "\t$Rd, $Rn, #0", "", []>,
+ "\t$Rd, $Rn, #" # zero, "", []>,
Sched<[WriteV]> {
bits<5> Rd;
bits<5> Rn;
@@ -5214,7 +5235,7 @@ class SIMDInexactCvtTwoScalar<bits<5> opcode, string asm>
multiclass SIMDCmpTwoScalarD<bit U, bits<5> opc, string asm,
SDPatternOperator OpNode> {
- def v1i64rz : BaseSIMDCmpTwoScalar<U, 0b11, opc, FPR64, asm>;
+ def v1i64rz : BaseSIMDCmpTwoScalar<U, 0b11, opc, FPR64, asm, "0">;
def : Pat<(v1i64 (OpNode FPR64:$Rn)),
(!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
@@ -5222,8 +5243,13 @@ multiclass SIMDCmpTwoScalarD<bit U, bits<5> opc, string asm,
multiclass SIMDCmpTwoScalarSD<bit U, bit S, bits<5> opc, string asm,
SDPatternOperator OpNode> {
- def v1i64rz : BaseSIMDCmpTwoScalar<U, {S,1}, opc, FPR64, asm>;
- def v1i32rz : BaseSIMDCmpTwoScalar<U, {S,0}, opc, FPR32, asm>;
+ def v1i64rz : BaseSIMDCmpTwoScalar<U, {S,1}, opc, FPR64, asm, "0.0">;
+ def v1i32rz : BaseSIMDCmpTwoScalar<U, {S,0}, opc, FPR32, asm, "0.0">;
+
+ def : InstAlias<asm # " $Rd, $Rn, #0",
+ (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rd, FPR64:$Rn)>;
+ def : InstAlias<asm # " $Rd, $Rn, #0",
+ (!cast<Instruction>(NAME # v1i32rz) FPR32:$Rd, FPR32:$Rn)>;
def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))),
(!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-05 00:54:43 +0000