diff options
Diffstat (limited to 'include/lib/cpus/aarch64/neoverse_n2.h')
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_n2.h | 35 |
1 files changed, 23 insertions, 12 deletions
diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h index 948f96511..a1e676ec2 100644 --- a/include/lib/cpus/aarch64/neoverse_n2.h +++ b/include/lib/cpus/aarch64/neoverse_n2.h @@ -8,37 +8,48 @@ #define NEOVERSE_N2_H /* Neoverse N2 ID register for revision r0p0 */ -#define NEOVERSE_N2_MIDR U(0x410FD490) +#define NEOVERSE_N2_MIDR U(0x410FD490) /******************************************************************************* * CPU Power control register ******************************************************************************/ -#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) +#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 -#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) -#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) +#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) +#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 -#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) +#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 +#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) +#define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) /******************************************************************************* * CPU Auxiliary Control register 2 specific definitions. ******************************************************************************/ -#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 -#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) /******************************************************************************* * CPU Auxiliary Control register 5 specific definitions. ******************************************************************************/ -#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 -#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) +#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5 +#define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) +#define CPUECTLR2_EL1_PF_MODE_LSB U(11) +#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) #endif /* NEOVERSE_N2_H */ |