diff options
Diffstat (limited to 'include/arch/aarch64/arch_helpers.h')
| -rw-r--r-- | include/arch/aarch64/arch_helpers.h | 43 |
1 files changed, 41 insertions, 2 deletions
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index a41b3258e..733bb23c4 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -233,8 +233,10 @@ void dcsw_op_all(u_register_t op_type); void disable_mmu_el1(void); void disable_mmu_el3(void); +void disable_mpu_el2(void); void disable_mmu_icache_el1(void); void disable_mmu_icache_el3(void); +void disable_mpu_icache_el2(void); /******************************************************************************* * Misc. accessor prototypes @@ -440,6 +442,8 @@ DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0) DEFINE_SYSREG_READ_FUNC(cntpct_el0) DEFINE_SYSREG_RW_FUNCS(cnthctl_el2) +DEFINE_SYSREG_RW_FUNCS(vtcr_el2) + #define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \ CNTP_CTL_ENABLE_MASK) #define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \ @@ -505,6 +509,9 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1) DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3) DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2) +DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(smcr_el3, SMCR_EL3) + DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1) DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1) @@ -532,9 +539,20 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1) DEFINE_SYSREG_READ_FUNC(rndr) DEFINE_SYSREG_READ_FUNC(rndrrs) +/* FEAT_HCX Register */ +DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2) + /* DynamIQ Shared Unit power management */ DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1) +/* CPU Power/Performance Management registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(cpuppmcr_el3, CPUPPMCR_EL3) +DEFINE_RENAME_SYSREG_RW_FUNCS(cpumpmmcr_el3, CPUMPMMCR_EL3) + +/* Armv9.2 RME Registers */ +DEFINE_RENAME_SYSREG_RW_FUNCS(gptbr_el3, GPTBR_EL3) +DEFINE_RENAME_SYSREG_RW_FUNCS(gpccr_el3, GPCCR_EL3) + #define IS_IN_EL(x) \ (GET_EL(read_CurrentEl()) == MODE_EL##x) @@ -578,7 +596,28 @@ static inline uint64_t el_implemented(unsigned int el) } } -/* Previously defined accesor functions with incomplete register names */ +/* + * TLBIPAALLOS instruction + * (TLB Inivalidate GPT Information by PA, + * All Entries, Outer Shareable) + */ +static inline void tlbipaallos(void) +{ + __asm__("SYS #6,c8,c1,#4"); +} + +/* + * Invalidate cached copies of GPT entries + * from TLBs by physical address + * + * @pa: the starting address for the range + * of invalidation + * @size: size of the range of invalidation + */ +void gpt_tlbi_by_pa(uint64_t pa, size_t size); + + +/* Previously defined accessor functions with incomplete register names */ #define read_current_el() read_CurrentEl() |