diff options
Diffstat (limited to 'share/doc/gcc-linaro-aarch64-linux-gnu/html/gcc/SH-Options.html')
| -rw-r--r-- | share/doc/gcc-linaro-aarch64-linux-gnu/html/gcc/SH-Options.html | 102 |
1 files changed, 51 insertions, 51 deletions
diff --git a/share/doc/gcc-linaro-aarch64-linux-gnu/html/gcc/SH-Options.html b/share/doc/gcc-linaro-aarch64-linux-gnu/html/gcc/SH-Options.html index 5b2aa90..b4a88bd 100644 --- a/share/doc/gcc-linaro-aarch64-linux-gnu/html/gcc/SH-Options.html +++ b/share/doc/gcc-linaro-aarch64-linux-gnu/html/gcc/SH-Options.html @@ -59,91 +59,91 @@ Up: <a rel="up" accesskey="u" href="Submodel-Options.html#Submodel-Options" <p>These ‘<samp><span class="samp">-m</span></samp>’ options are defined for the SH implementations: <dl> -<dt><code>-m1</code><dd><a name="index-m1-2081"></a>Generate code for the SH1. +<dt><code>-m1</code><dd><a name="index-m1-2083"></a>Generate code for the SH1. - <br><dt><code>-m2</code><dd><a name="index-m2-2082"></a>Generate code for the SH2. + <br><dt><code>-m2</code><dd><a name="index-m2-2084"></a>Generate code for the SH2. <br><dt><code>-m2e</code><dd>Generate code for the SH2e. - <br><dt><code>-m2a-nofpu</code><dd><a name="index-m2a_002dnofpu-2083"></a>Generate code for the SH2a without FPU, or for a SH2a-FPU in such a way + <br><dt><code>-m2a-nofpu</code><dd><a name="index-m2a_002dnofpu-2085"></a>Generate code for the SH2a without FPU, or for a SH2a-FPU in such a way that the floating-point unit is not used. - <br><dt><code>-m2a-single-only</code><dd><a name="index-m2a_002dsingle_002donly-2084"></a>Generate code for the SH2a-FPU, in such a way that no double-precision + <br><dt><code>-m2a-single-only</code><dd><a name="index-m2a_002dsingle_002donly-2086"></a>Generate code for the SH2a-FPU, in such a way that no double-precision floating-point operations are used. - <br><dt><code>-m2a-single</code><dd><a name="index-m2a_002dsingle-2085"></a>Generate code for the SH2a-FPU assuming the floating-point unit is in + <br><dt><code>-m2a-single</code><dd><a name="index-m2a_002dsingle-2087"></a>Generate code for the SH2a-FPU assuming the floating-point unit is in single-precision mode by default. - <br><dt><code>-m2a</code><dd><a name="index-m2a-2086"></a>Generate code for the SH2a-FPU assuming the floating-point unit is in + <br><dt><code>-m2a</code><dd><a name="index-m2a-2088"></a>Generate code for the SH2a-FPU assuming the floating-point unit is in double-precision mode by default. - <br><dt><code>-m3</code><dd><a name="index-m3-2087"></a>Generate code for the SH3. + <br><dt><code>-m3</code><dd><a name="index-m3-2089"></a>Generate code for the SH3. - <br><dt><code>-m3e</code><dd><a name="index-m3e-2088"></a>Generate code for the SH3e. + <br><dt><code>-m3e</code><dd><a name="index-m3e-2090"></a>Generate code for the SH3e. - <br><dt><code>-m4-nofpu</code><dd><a name="index-m4_002dnofpu-2089"></a>Generate code for the SH4 without a floating-point unit. + <br><dt><code>-m4-nofpu</code><dd><a name="index-m4_002dnofpu-2091"></a>Generate code for the SH4 without a floating-point unit. - <br><dt><code>-m4-single-only</code><dd><a name="index-m4_002dsingle_002donly-2090"></a>Generate code for the SH4 with a floating-point unit that only + <br><dt><code>-m4-single-only</code><dd><a name="index-m4_002dsingle_002donly-2092"></a>Generate code for the SH4 with a floating-point unit that only supports single-precision arithmetic. - <br><dt><code>-m4-single</code><dd><a name="index-m4_002dsingle-2091"></a>Generate code for the SH4 assuming the floating-point unit is in + <br><dt><code>-m4-single</code><dd><a name="index-m4_002dsingle-2093"></a>Generate code for the SH4 assuming the floating-point unit is in single-precision mode by default. - <br><dt><code>-m4</code><dd><a name="index-m4-2092"></a>Generate code for the SH4. + <br><dt><code>-m4</code><dd><a name="index-m4-2094"></a>Generate code for the SH4. - <br><dt><code>-m4a-nofpu</code><dd><a name="index-m4a_002dnofpu-2093"></a>Generate code for the SH4al-dsp, or for a SH4a in such a way that the + <br><dt><code>-m4a-nofpu</code><dd><a name="index-m4a_002dnofpu-2095"></a>Generate code for the SH4al-dsp, or for a SH4a in such a way that the floating-point unit is not used. - <br><dt><code>-m4a-single-only</code><dd><a name="index-m4a_002dsingle_002donly-2094"></a>Generate code for the SH4a, in such a way that no double-precision + <br><dt><code>-m4a-single-only</code><dd><a name="index-m4a_002dsingle_002donly-2096"></a>Generate code for the SH4a, in such a way that no double-precision floating-point operations are used. - <br><dt><code>-m4a-single</code><dd><a name="index-m4a_002dsingle-2095"></a>Generate code for the SH4a assuming the floating-point unit is in + <br><dt><code>-m4a-single</code><dd><a name="index-m4a_002dsingle-2097"></a>Generate code for the SH4a assuming the floating-point unit is in single-precision mode by default. - <br><dt><code>-m4a</code><dd><a name="index-m4a-2096"></a>Generate code for the SH4a. + <br><dt><code>-m4a</code><dd><a name="index-m4a-2098"></a>Generate code for the SH4a. - <br><dt><code>-m4al</code><dd><a name="index-m4al-2097"></a>Same as <samp><span class="option">-m4a-nofpu</span></samp>, except that it implicitly passes + <br><dt><code>-m4al</code><dd><a name="index-m4al-2099"></a>Same as <samp><span class="option">-m4a-nofpu</span></samp>, except that it implicitly passes <samp><span class="option">-dsp</span></samp> to the assembler. GCC doesn't generate any DSP instructions at the moment. - <br><dt><code>-mb</code><dd><a name="index-mb-2098"></a>Compile code for the processor in big-endian mode. + <br><dt><code>-mb</code><dd><a name="index-mb-2100"></a>Compile code for the processor in big-endian mode. - <br><dt><code>-ml</code><dd><a name="index-ml-2099"></a>Compile code for the processor in little-endian mode. + <br><dt><code>-ml</code><dd><a name="index-ml-2101"></a>Compile code for the processor in little-endian mode. - <br><dt><code>-mdalign</code><dd><a name="index-mdalign-2100"></a>Align doubles at 64-bit boundaries. Note that this changes the calling + <br><dt><code>-mdalign</code><dd><a name="index-mdalign-2102"></a>Align doubles at 64-bit boundaries. Note that this changes the calling conventions, and thus some functions from the standard C library will not work unless you recompile it first with <samp><span class="option">-mdalign</span></samp>. - <br><dt><code>-mrelax</code><dd><a name="index-mrelax-2101"></a>Shorten some address references at link time, when possible; uses the + <br><dt><code>-mrelax</code><dd><a name="index-mrelax-2103"></a>Shorten some address references at link time, when possible; uses the linker option <samp><span class="option">-relax</span></samp>. - <br><dt><code>-mbigtable</code><dd><a name="index-mbigtable-2102"></a>Use 32-bit offsets in <code>switch</code> tables. The default is to use + <br><dt><code>-mbigtable</code><dd><a name="index-mbigtable-2104"></a>Use 32-bit offsets in <code>switch</code> tables. The default is to use 16-bit offsets. - <br><dt><code>-mbitops</code><dd><a name="index-mbitops-2103"></a>Enable the use of bit manipulation instructions on SH2A. + <br><dt><code>-mbitops</code><dd><a name="index-mbitops-2105"></a>Enable the use of bit manipulation instructions on SH2A. - <br><dt><code>-mfmovd</code><dd><a name="index-mfmovd-2104"></a>Enable the use of the instruction <code>fmovd</code>. Check <samp><span class="option">-mdalign</span></samp> for + <br><dt><code>-mfmovd</code><dd><a name="index-mfmovd-2106"></a>Enable the use of the instruction <code>fmovd</code>. Check <samp><span class="option">-mdalign</span></samp> for alignment constraints. - <br><dt><code>-mhitachi</code><dd><a name="index-mhitachi-2105"></a>Comply with the calling conventions defined by Renesas. + <br><dt><code>-mhitachi</code><dd><a name="index-mhitachi-2107"></a>Comply with the calling conventions defined by Renesas. - <br><dt><code>-mrenesas</code><dd><a name="index-mhitachi-2106"></a>Comply with the calling conventions defined by Renesas. + <br><dt><code>-mrenesas</code><dd><a name="index-mhitachi-2108"></a>Comply with the calling conventions defined by Renesas. - <br><dt><code>-mno-renesas</code><dd><a name="index-mhitachi-2107"></a>Comply with the calling conventions defined for GCC before the Renesas + <br><dt><code>-mno-renesas</code><dd><a name="index-mhitachi-2109"></a>Comply with the calling conventions defined for GCC before the Renesas conventions were available. This option is the default for all targets of the SH toolchain. - <br><dt><code>-mnomacsave</code><dd><a name="index-mnomacsave-2108"></a>Mark the <code>MAC</code> register as call-clobbered, even if + <br><dt><code>-mnomacsave</code><dd><a name="index-mnomacsave-2110"></a>Mark the <code>MAC</code> register as call-clobbered, even if <samp><span class="option">-mhitachi</span></samp> is given. - <br><dt><code>-mieee</code><br><dt><code>-mno-ieee</code><dd><a name="index-mieee-2109"></a><a name="index-mnoieee-2110"></a>Control the IEEE compliance of floating-point comparisons, which affects the + <br><dt><code>-mieee</code><br><dt><code>-mno-ieee</code><dd><a name="index-mieee-2111"></a><a name="index-mnoieee-2112"></a>Control the IEEE compliance of floating-point comparisons, which affects the handling of cases where the result of a comparison is unordered. By default <samp><span class="option">-mieee</span></samp> is implicitly enabled. If <samp><span class="option">-ffinite-math-only</span></samp> is enabled <samp><span class="option">-mno-ieee</span></samp> is implicitly set, which results in faster floating-point greater-equal and less-equal comparisons. The implcit settings can be overridden by specifying either <samp><span class="option">-mieee</span></samp> or <samp><span class="option">-mno-ieee</span></samp>. - <br><dt><code>-minline-ic_invalidate</code><dd><a name="index-minline_002dic_005finvalidate-2111"></a>Inline code to invalidate instruction cache entries after setting up + <br><dt><code>-minline-ic_invalidate</code><dd><a name="index-minline_002dic_005finvalidate-2113"></a>Inline code to invalidate instruction cache entries after setting up nested function trampolines. This option has no effect if -musermode is in effect and the selected code generation option (e.g. -m4) does not allow the use of the icbi @@ -154,30 +154,30 @@ manipulate the instruction cache address array directly with an associative write. This not only requires privileged mode, but it will also fail if the cache line had been mapped via the TLB and has become unmapped. - <br><dt><code>-misize</code><dd><a name="index-misize-2112"></a>Dump instruction size and location in the assembly code. + <br><dt><code>-misize</code><dd><a name="index-misize-2114"></a>Dump instruction size and location in the assembly code. - <br><dt><code>-mpadstruct</code><dd><a name="index-mpadstruct-2113"></a>This option is deprecated. It pads structures to multiple of 4 bytes, + <br><dt><code>-mpadstruct</code><dd><a name="index-mpadstruct-2115"></a>This option is deprecated. It pads structures to multiple of 4 bytes, which is incompatible with the SH ABI. - <br><dt><code>-msoft-atomic</code><dd><a name="index-msoft_002datomic-2114"></a>Generate GNU/Linux compatible gUSA software atomic sequences for the atomic + <br><dt><code>-msoft-atomic</code><dd><a name="index-msoft_002datomic-2116"></a>Generate GNU/Linux compatible gUSA software atomic sequences for the atomic built-in functions. The generated atomic sequences require support from the interrupt / exception handling code of the system and are only suitable for single-core systems. They will not perform correctly on multi-core systems. This option is enabled by default when the target is <code>sh-*-linux*</code>. For details on the atomic built-in functions see <a href="_005f_005fatomic-Builtins.html#g_t_005f_005fatomic-Builtins">__atomic Builtins</a>. - <br><dt><code>-mspace</code><dd><a name="index-mspace-2115"></a>Optimize for space instead of speed. Implied by <samp><span class="option">-Os</span></samp>. + <br><dt><code>-mspace</code><dd><a name="index-mspace-2117"></a>Optimize for space instead of speed. Implied by <samp><span class="option">-Os</span></samp>. - <br><dt><code>-mprefergot</code><dd><a name="index-mprefergot-2116"></a>When generating position-independent code, emit function calls using + <br><dt><code>-mprefergot</code><dd><a name="index-mprefergot-2118"></a>When generating position-independent code, emit function calls using the Global Offset Table instead of the Procedure Linkage Table. - <br><dt><code>-musermode</code><dd><a name="index-musermode-2117"></a>Don't generate privileged mode only code; implies -mno-inline-ic_invalidate + <br><dt><code>-musermode</code><dd><a name="index-musermode-2119"></a>Don't generate privileged mode only code; implies -mno-inline-ic_invalidate if the inlined code would not work in user mode. This is the default when the target is <code>sh-*-linux*</code>. - <br><dt><code>-multcost=</code><var>number</var><dd><a name="index-multcost_003d_0040var_007bnumber_007d-2118"></a>Set the cost to assume for a multiply insn. + <br><dt><code>-multcost=</code><var>number</var><dd><a name="index-multcost_003d_0040var_007bnumber_007d-2120"></a>Set the cost to assume for a multiply insn. - <br><dt><code>-mdiv=</code><var>strategy</var><dd><a name="index-mdiv_003d_0040var_007bstrategy_007d-2119"></a>Set the division strategy to use for SHmedia code. <var>strategy</var> must be + <br><dt><code>-mdiv=</code><var>strategy</var><dd><a name="index-mdiv_003d_0040var_007bstrategy_007d-2121"></a>Set the division strategy to use for SHmedia code. <var>strategy</var> must be one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp . "fp" performs the operation in floating point. This has a very high latency, @@ -215,26 +215,26 @@ by inserting a test to skip a number of operations in this case; this test slows down the case of larger dividends. inv20u assumes the case of a such a small dividend to be unlikely, and inv20l assumes it to be likely. - <br><dt><code>-maccumulate-outgoing-args</code><dd><a name="index-maccumulate_002doutgoing_002dargs-2120"></a>Reserve space once for outgoing arguments in the function prologue rather + <br><dt><code>-maccumulate-outgoing-args</code><dd><a name="index-maccumulate_002doutgoing_002dargs-2122"></a>Reserve space once for outgoing arguments in the function prologue rather than around each call. Generally beneficial for performance and size. Also needed for unwinding to avoid changing the stack frame around conditional code. - <br><dt><code>-mdivsi3_libfunc=</code><var>name</var><dd><a name="index-mdivsi3_005flibfunc_003d_0040var_007bname_007d-2121"></a>Set the name of the library function used for 32-bit signed division to + <br><dt><code>-mdivsi3_libfunc=</code><var>name</var><dd><a name="index-mdivsi3_005flibfunc_003d_0040var_007bname_007d-2123"></a>Set the name of the library function used for 32-bit signed division to <var>name</var>. This only affect the name used in the call and inv:call division strategies, and the compiler will still expect the same sets of input/output/clobbered registers as if this option was not present. - <br><dt><code>-mfixed-range=</code><var>register-range</var><dd><a name="index-mfixed_002drange-2122"></a>Generate code treating the given register range as fixed registers. + <br><dt><code>-mfixed-range=</code><var>register-range</var><dd><a name="index-mfixed_002drange-2124"></a>Generate code treating the given register range as fixed registers. A fixed register is one that the register allocator can not use. This is useful when compiling kernel code. A register range is specified as two registers separated by a dash. Multiple register ranges can be specified separated by a comma. - <br><dt><code>-madjust-unroll</code><dd><a name="index-madjust_002dunroll-2123"></a>Throttle unrolling to avoid thrashing target registers. + <br><dt><code>-madjust-unroll</code><dd><a name="index-madjust_002dunroll-2125"></a>Throttle unrolling to avoid thrashing target registers. This option only has an effect if the gcc code base supports the TARGET_ADJUST_UNROLL_MAX target hook. - <br><dt><code>-mindexed-addressing</code><dd><a name="index-mindexed_002daddressing-2124"></a>Enable the use of the indexed addressing mode for SHmedia32/SHcompact. + <br><dt><code>-mindexed-addressing</code><dd><a name="index-mindexed_002daddressing-2126"></a>Enable the use of the indexed addressing mode for SHmedia32/SHcompact. This is only safe if the hardware and/or OS implement 32-bit wrap-around semantics for the indexed addressing mode. The architecture allows the implementation of processors with 64-bit MMU, which the OS could use to @@ -242,10 +242,10 @@ get 32-bit addressing, but since no current hardware implementation supports this or any other way to make the indexed addressing mode safe to use in the 32-bit ABI, the default is <samp><span class="option">-mno-indexed-addressing</span></samp>. - <br><dt><code>-mgettrcost=</code><var>number</var><dd><a name="index-mgettrcost_003d_0040var_007bnumber_007d-2125"></a>Set the cost assumed for the gettr instruction to <var>number</var>. + <br><dt><code>-mgettrcost=</code><var>number</var><dd><a name="index-mgettrcost_003d_0040var_007bnumber_007d-2127"></a>Set the cost assumed for the gettr instruction to <var>number</var>. The default is 2 if <samp><span class="option">-mpt-fixed</span></samp> is in effect, 100 otherwise. - <br><dt><code>-mpt-fixed</code><dd><a name="index-mpt_002dfixed-2126"></a>Assume pt* instructions won't trap. This will generally generate better + <br><dt><code>-mpt-fixed</code><dd><a name="index-mpt_002dfixed-2128"></a>Assume pt* instructions won't trap. This will generally generate better scheduled code, but is unsafe on current hardware. The current architecture definition says that ptabs and ptrel trap when the target anded with 3 is 3. This has the unintentional effect of making it unsafe to schedule ptabs / @@ -262,7 +262,7 @@ is -mno-pt-fixed. Unless the user specifies a specific cost with this deters register allocation using target registers for storing ordinary integers. - <br><dt><code>-minvalid-symbols</code><dd><a name="index-minvalid_002dsymbols-2127"></a>Assume symbols might be invalid. Ordinary function symbols generated by + <br><dt><code>-minvalid-symbols</code><dd><a name="index-minvalid_002dsymbols-2129"></a>Assume symbols might be invalid. Ordinary function symbols generated by the compiler will always be valid to load with movi/shori/ptabs or movi/shori/ptrel, but with assembler and/or linker tricks it is possible to generate symbols that will cause ptabs / ptrel to trap. @@ -270,22 +270,22 @@ This option is only meaningful when <samp><span class="option">-mno-pt-fixed</sp It will then prevent cross-basic-block cse, hoisting and most scheduling of symbol loads. The default is <samp><span class="option">-mno-invalid-symbols</span></samp>. - <br><dt><code>-mbranch-cost=</code><var>num</var><dd><a name="index-mbranch_002dcost_003d_0040var_007bnum_007d-2128"></a>Assume <var>num</var> to be the cost for a branch instruction. Higher numbers + <br><dt><code>-mbranch-cost=</code><var>num</var><dd><a name="index-mbranch_002dcost_003d_0040var_007bnum_007d-2130"></a>Assume <var>num</var> to be the cost for a branch instruction. Higher numbers will make the compiler try to generate more branch-free code if possible. If not specified the value is selected depending on the processor type that is being compiled for. - <br><dt><code>-mcbranchdi</code><dd><a name="index-mcbranchdi-2129"></a>Enable the <code>cbranchdi4</code> instruction pattern. + <br><dt><code>-mcbranchdi</code><dd><a name="index-mcbranchdi-2131"></a>Enable the <code>cbranchdi4</code> instruction pattern. - <br><dt><code>-mcmpeqdi</code><dd><a name="index-mcmpeqdi-2130"></a>Emit the <code>cmpeqdi_t</code> instruction pattern even when <samp><span class="option">-mcbranchdi</span></samp> + <br><dt><code>-mcmpeqdi</code><dd><a name="index-mcmpeqdi-2132"></a>Emit the <code>cmpeqdi_t</code> instruction pattern even when <samp><span class="option">-mcbranchdi</span></samp> is in effect. - <br><dt><code>-mfused-madd</code><dd><a name="index-mfused_002dmadd-2131"></a>Allow the usage of the <code>fmac</code> instruction (floating-point + <br><dt><code>-mfused-madd</code><dd><a name="index-mfused_002dmadd-2133"></a>Allow the usage of the <code>fmac</code> instruction (floating-point multiply-accumulate) if the processor type supports it. Enabling this option might generate code that produces different numeric floating-point results compared to strict IEEE 754 arithmetic. - <br><dt><code>-mpretend-cmove</code><dd><a name="index-mpretend_002dcmove-2132"></a>Prefer zero-displacement conditional branches for conditional move instruction + <br><dt><code>-mpretend-cmove</code><dd><a name="index-mpretend_002dcmove-2134"></a>Prefer zero-displacement conditional branches for conditional move instruction patterns. This can result in faster code on the SH4 processor. </dl> |