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1 files changed, 90 insertions, 90 deletions
diff --git a/share/doc/gcc-linaro-aarch64-linux-gnu/html/gcc/RS_002f6000-and-PowerPC-Options.html b/share/doc/gcc-linaro-aarch64-linux-gnu/html/gcc/RS_002f6000-and-PowerPC-Options.html index 08753c0..b1a40e9 100644 --- a/share/doc/gcc-linaro-aarch64-linux-gnu/html/gcc/RS_002f6000-and-PowerPC-Options.html +++ b/share/doc/gcc-linaro-aarch64-linux-gnu/html/gcc/RS_002f6000-and-PowerPC-Options.html @@ -57,10 +57,10 @@ Up: <a rel="up" accesskey="u" href="Submodel-Options.html#Submodel-Options" <h4 class="subsection">3.17.35 IBM RS/6000 and PowerPC Options</h4> -<p><a name="index-RS_002f6000-and-PowerPC-Options-1865"></a><a name="index-IBM-RS_002f6000-and-PowerPC-Options-1866"></a> +<p><a name="index-RS_002f6000-and-PowerPC-Options-1867"></a><a name="index-IBM-RS_002f6000-and-PowerPC-Options-1868"></a> These ‘<samp><span class="samp">-m</span></samp>’ options are defined for the IBM RS/6000 and PowerPC: <dl> -<dt><code>-mpower</code><dt><code>-mno-power</code><dt><code>-mpower2</code><dt><code>-mno-power2</code><dt><code>-mpowerpc</code><dt><code>-mno-powerpc</code><dt><code>-mpowerpc-gpopt</code><dt><code>-mno-powerpc-gpopt</code><dt><code>-mpowerpc-gfxopt</code><dt><code>-mno-powerpc-gfxopt</code><dt><code>-mpowerpc64</code><dt><code>-mno-powerpc64</code><dt><code>-mmfcrf</code><dt><code>-mno-mfcrf</code><dt><code>-mpopcntb</code><dt><code>-mno-popcntb</code><dt><code>-mpopcntd</code><dt><code>-mno-popcntd</code><dt><code>-mfprnd</code><dt><code>-mno-fprnd</code><dt><code>-mcmpb</code><dt><code>-mno-cmpb</code><dt><code>-mmfpgpr</code><dt><code>-mno-mfpgpr</code><dt><code>-mhard-dfp</code><dt><code>-mno-hard-dfp</code><dd><a name="index-mpower-1867"></a><a name="index-mno_002dpower-1868"></a><a name="index-mpower2-1869"></a><a name="index-mno_002dpower2-1870"></a><a name="index-mpowerpc-1871"></a><a name="index-mno_002dpowerpc-1872"></a><a name="index-mpowerpc_002dgpopt-1873"></a><a name="index-mno_002dpowerpc_002dgpopt-1874"></a><a name="index-mpowerpc_002dgfxopt-1875"></a><a name="index-mno_002dpowerpc_002dgfxopt-1876"></a><a name="index-mpowerpc64-1877"></a><a name="index-mno_002dpowerpc64-1878"></a><a name="index-mmfcrf-1879"></a><a name="index-mno_002dmfcrf-1880"></a><a name="index-mpopcntb-1881"></a><a name="index-mno_002dpopcntb-1882"></a><a name="index-mpopcntd-1883"></a><a name="index-mno_002dpopcntd-1884"></a><a name="index-mfprnd-1885"></a><a name="index-mno_002dfprnd-1886"></a><a name="index-mcmpb-1887"></a><a name="index-mno_002dcmpb-1888"></a><a name="index-mmfpgpr-1889"></a><a name="index-mno_002dmfpgpr-1890"></a><a name="index-mhard_002ddfp-1891"></a><a name="index-mno_002dhard_002ddfp-1892"></a>GCC supports two related instruction set architectures for the +<dt><code>-mpower</code><dt><code>-mno-power</code><dt><code>-mpower2</code><dt><code>-mno-power2</code><dt><code>-mpowerpc</code><dt><code>-mno-powerpc</code><dt><code>-mpowerpc-gpopt</code><dt><code>-mno-powerpc-gpopt</code><dt><code>-mpowerpc-gfxopt</code><dt><code>-mno-powerpc-gfxopt</code><dt><code>-mpowerpc64</code><dt><code>-mno-powerpc64</code><dt><code>-mmfcrf</code><dt><code>-mno-mfcrf</code><dt><code>-mpopcntb</code><dt><code>-mno-popcntb</code><dt><code>-mpopcntd</code><dt><code>-mno-popcntd</code><dt><code>-mfprnd</code><dt><code>-mno-fprnd</code><dt><code>-mcmpb</code><dt><code>-mno-cmpb</code><dt><code>-mmfpgpr</code><dt><code>-mno-mfpgpr</code><dt><code>-mhard-dfp</code><dt><code>-mno-hard-dfp</code><dd><a name="index-mpower-1869"></a><a name="index-mno_002dpower-1870"></a><a name="index-mpower2-1871"></a><a name="index-mno_002dpower2-1872"></a><a name="index-mpowerpc-1873"></a><a name="index-mno_002dpowerpc-1874"></a><a name="index-mpowerpc_002dgpopt-1875"></a><a name="index-mno_002dpowerpc_002dgpopt-1876"></a><a name="index-mpowerpc_002dgfxopt-1877"></a><a name="index-mno_002dpowerpc_002dgfxopt-1878"></a><a name="index-mpowerpc64-1879"></a><a name="index-mno_002dpowerpc64-1880"></a><a name="index-mmfcrf-1881"></a><a name="index-mno_002dmfcrf-1882"></a><a name="index-mpopcntb-1883"></a><a name="index-mno_002dpopcntb-1884"></a><a name="index-mpopcntd-1885"></a><a name="index-mno_002dpopcntd-1886"></a><a name="index-mfprnd-1887"></a><a name="index-mno_002dfprnd-1888"></a><a name="index-mcmpb-1889"></a><a name="index-mno_002dcmpb-1890"></a><a name="index-mmfpgpr-1891"></a><a name="index-mno_002dmfpgpr-1892"></a><a name="index-mhard_002ddfp-1893"></a><a name="index-mno_002dhard_002ddfp-1894"></a>GCC supports two related instruction set architectures for the RS/6000 and PowerPC. The <dfn>POWER</dfn> instruction set are those instructions supported by the ‘<samp><span class="samp">rios</span></samp>’ chip set used in the original RS/6000 systems and the <dfn>PowerPC</dfn> instruction set is the @@ -129,7 +129,7 @@ the MQ register. Specifying both <samp><span class="option">-mpower</span></sam permits GCC to use any instruction from either architecture and to allow use of the MQ register; specify this for the Motorola MPC601. - <br><dt><code>-mnew-mnemonics</code><dt><code>-mold-mnemonics</code><dd><a name="index-mnew_002dmnemonics-1893"></a><a name="index-mold_002dmnemonics-1894"></a>Select which mnemonics to use in the generated assembler code. With + <br><dt><code>-mnew-mnemonics</code><dt><code>-mold-mnemonics</code><dd><a name="index-mnew_002dmnemonics-1895"></a><a name="index-mold_002dmnemonics-1896"></a>Select which mnemonics to use in the generated assembler code. With <samp><span class="option">-mnew-mnemonics</span></samp>, GCC uses the assembler mnemonics defined for the PowerPC architecture. With <samp><span class="option">-mold-mnemonics</span></samp> it uses the assembler mnemonics defined for the POWER architecture. Instructions @@ -142,7 +142,7 @@ value of these option. Unless you are building a cross-compiler, you should normally not specify either <samp><span class="option">-mnew-mnemonics</span></samp> or <samp><span class="option">-mold-mnemonics</span></samp>, but should instead accept the default. - <br><dt><code>-mcpu=</code><var>cpu_type</var><dd><a name="index-mcpu-1895"></a>Set architecture type, register usage, choice of mnemonics, and + <br><dt><code>-mcpu=</code><var>cpu_type</var><dd><a name="index-mcpu-1897"></a>Set architecture type, register usage, choice of mnemonics, and instruction scheduling parameters for machine type <var>cpu_type</var>. Supported values for <var>cpu_type</var> are ‘<samp><span class="samp">401</span></samp>’, ‘<samp><span class="samp">403</span></samp>’, ‘<samp><span class="samp">405</span></samp>’, ‘<samp><span class="samp">405fp</span></samp>’, ‘<samp><span class="samp">440</span></samp>’, ‘<samp><span class="samp">440fp</span></samp>’, ‘<samp><span class="samp">464</span></samp>’, ‘<samp><span class="samp">464fp</span></samp>’, @@ -193,7 +193,7 @@ AIX does not have full support for these options. You may still enable or disable them individually if you're sure it'll work in your environment. - <br><dt><code>-mtune=</code><var>cpu_type</var><dd><a name="index-mtune-1896"></a>Set the instruction scheduling parameters for machine type + <br><dt><code>-mtune=</code><var>cpu_type</var><dd><a name="index-mtune-1898"></a>Set the instruction scheduling parameters for machine type <var>cpu_type</var>, but do not set the architecture type, register usage, or choice of mnemonics, as <samp><span class="option">-mcpu=</span><var>cpu_type</var></samp> would. The same values for <var>cpu_type</var> are used for <samp><span class="option">-mtune</span></samp> as for @@ -201,56 +201,56 @@ values for <var>cpu_type</var> are used for <samp><span class="option">-mtune</s architecture, registers, and mnemonics set by <samp><span class="option">-mcpu</span></samp>, but the scheduling parameters set by <samp><span class="option">-mtune</span></samp>. - <br><dt><code>-mcmodel=small</code><dd><a name="index-mcmodel_003dsmall-1897"></a>Generate PowerPC64 code for the small model: The TOC is limited to + <br><dt><code>-mcmodel=small</code><dd><a name="index-mcmodel_003dsmall-1899"></a>Generate PowerPC64 code for the small model: The TOC is limited to 64k. - <br><dt><code>-mcmodel=medium</code><dd><a name="index-mcmodel_003dmedium-1898"></a>Generate PowerPC64 code for the medium model: The TOC and other static + <br><dt><code>-mcmodel=medium</code><dd><a name="index-mcmodel_003dmedium-1900"></a>Generate PowerPC64 code for the medium model: The TOC and other static data may be up to a total of 4G in size. - <br><dt><code>-mcmodel=large</code><dd><a name="index-mcmodel_003dlarge-1899"></a>Generate PowerPC64 code for the large model: The TOC may be up to 4G + <br><dt><code>-mcmodel=large</code><dd><a name="index-mcmodel_003dlarge-1901"></a>Generate PowerPC64 code for the large model: The TOC may be up to 4G in size. Other data and code is only limited by the 64-bit address space. - <br><dt><code>-maltivec</code><dt><code>-mno-altivec</code><dd><a name="index-maltivec-1900"></a><a name="index-mno_002daltivec-1901"></a>Generate code that uses (does not use) AltiVec instructions, and also + <br><dt><code>-maltivec</code><dt><code>-mno-altivec</code><dd><a name="index-maltivec-1902"></a><a name="index-mno_002daltivec-1903"></a>Generate code that uses (does not use) AltiVec instructions, and also enable the use of built-in functions that allow more direct access to the AltiVec instruction set. You may also need to set <samp><span class="option">-mabi=altivec</span></samp> to adjust the current ABI with AltiVec ABI enhancements. - <br><dt><code>-mvrsave</code><dt><code>-mno-vrsave</code><dd><a name="index-mvrsave-1902"></a><a name="index-mno_002dvrsave-1903"></a>Generate VRSAVE instructions when generating AltiVec code. + <br><dt><code>-mvrsave</code><dt><code>-mno-vrsave</code><dd><a name="index-mvrsave-1904"></a><a name="index-mno_002dvrsave-1905"></a>Generate VRSAVE instructions when generating AltiVec code. - <br><dt><code>-mgen-cell-microcode</code><dd><a name="index-mgen_002dcell_002dmicrocode-1904"></a>Generate Cell microcode instructions + <br><dt><code>-mgen-cell-microcode</code><dd><a name="index-mgen_002dcell_002dmicrocode-1906"></a>Generate Cell microcode instructions - <br><dt><code>-mwarn-cell-microcode</code><dd><a name="index-mwarn_002dcell_002dmicrocode-1905"></a>Warning when a Cell microcode instruction is going to emitted. An example + <br><dt><code>-mwarn-cell-microcode</code><dd><a name="index-mwarn_002dcell_002dmicrocode-1907"></a>Warning when a Cell microcode instruction is going to emitted. An example of a Cell microcode instruction is a variable shift. - <br><dt><code>-msecure-plt</code><dd><a name="index-msecure_002dplt-1906"></a>Generate code that allows ld and ld.so to build executables and shared + <br><dt><code>-msecure-plt</code><dd><a name="index-msecure_002dplt-1908"></a>Generate code that allows ld and ld.so to build executables and shared libraries with non-exec .plt and .got sections. This is a PowerPC 32-bit SYSV ABI option. - <br><dt><code>-mbss-plt</code><dd><a name="index-mbss_002dplt-1907"></a>Generate code that uses a BSS .plt section that ld.so fills in, and + <br><dt><code>-mbss-plt</code><dd><a name="index-mbss_002dplt-1909"></a>Generate code that uses a BSS .plt section that ld.so fills in, and requires .plt and .got sections that are both writable and executable. This is a PowerPC 32-bit SYSV ABI option. - <br><dt><code>-misel</code><dt><code>-mno-isel</code><dd><a name="index-misel-1908"></a><a name="index-mno_002disel-1909"></a>This switch enables or disables the generation of ISEL instructions. + <br><dt><code>-misel</code><dt><code>-mno-isel</code><dd><a name="index-misel-1910"></a><a name="index-mno_002disel-1911"></a>This switch enables or disables the generation of ISEL instructions. <br><dt><code>-misel=</code><var>yes/no</var><dd>This switch has been deprecated. Use <samp><span class="option">-misel</span></samp> and <samp><span class="option">-mno-isel</span></samp> instead. - <br><dt><code>-mspe</code><dt><code>-mno-spe</code><dd><a name="index-mspe-1910"></a><a name="index-mno_002dspe-1911"></a>This switch enables or disables the generation of SPE simd + <br><dt><code>-mspe</code><dt><code>-mno-spe</code><dd><a name="index-mspe-1912"></a><a name="index-mno_002dspe-1913"></a>This switch enables or disables the generation of SPE simd instructions. - <br><dt><code>-mpaired</code><dt><code>-mno-paired</code><dd><a name="index-mpaired-1912"></a><a name="index-mno_002dpaired-1913"></a>This switch enables or disables the generation of PAIRED simd + <br><dt><code>-mpaired</code><dt><code>-mno-paired</code><dd><a name="index-mpaired-1914"></a><a name="index-mno_002dpaired-1915"></a>This switch enables or disables the generation of PAIRED simd instructions. <br><dt><code>-mspe=</code><var>yes/no</var><dd>This option has been deprecated. Use <samp><span class="option">-mspe</span></samp> and <samp><span class="option">-mno-spe</span></samp> instead. - <br><dt><code>-mvsx</code><dt><code>-mno-vsx</code><dd><a name="index-mvsx-1914"></a><a name="index-mno_002dvsx-1915"></a>Generate code that uses (does not use) vector/scalar (VSX) + <br><dt><code>-mvsx</code><dt><code>-mno-vsx</code><dd><a name="index-mvsx-1916"></a><a name="index-mno_002dvsx-1917"></a>Generate code that uses (does not use) vector/scalar (VSX) instructions, and also enable the use of built-in functions that allow more direct access to the VSX instruction set. - <br><dt><code>-mfloat-gprs=</code><var>yes/single/double/no</var><dt><code>-mfloat-gprs</code><dd><a name="index-mfloat_002dgprs-1916"></a>This switch enables or disables the generation of floating-point + <br><dt><code>-mfloat-gprs=</code><var>yes/single/double/no</var><dt><code>-mfloat-gprs</code><dd><a name="index-mfloat_002dgprs-1918"></a>This switch enables or disables the generation of floating-point operations on the general-purpose registers for architectures that support it. @@ -265,14 +265,14 @@ general-purpose registers. <p>This option is currently only available on the MPC854x. - <br><dt><code>-m32</code><dt><code>-m64</code><dd><a name="index-m32-1917"></a><a name="index-m64-1918"></a>Generate code for 32-bit or 64-bit environments of Darwin and SVR4 + <br><dt><code>-m32</code><dt><code>-m64</code><dd><a name="index-m32-1919"></a><a name="index-m64-1920"></a>Generate code for 32-bit or 64-bit environments of Darwin and SVR4 targets (including GNU/Linux). The 32-bit environment sets int, long and pointer to 32 bits and generates code that runs on any PowerPC variant. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits, and generates code for PowerPC64, as for <samp><span class="option">-mpowerpc64</span></samp>. - <br><dt><code>-mfull-toc</code><dt><code>-mno-fp-in-toc</code><dt><code>-mno-sum-in-toc</code><dt><code>-mminimal-toc</code><dd><a name="index-mfull_002dtoc-1919"></a><a name="index-mno_002dfp_002din_002dtoc-1920"></a><a name="index-mno_002dsum_002din_002dtoc-1921"></a><a name="index-mminimal_002dtoc-1922"></a>Modify generation of the TOC (Table Of Contents), which is created for + <br><dt><code>-mfull-toc</code><dt><code>-mno-fp-in-toc</code><dt><code>-mno-sum-in-toc</code><dt><code>-mminimal-toc</code><dd><a name="index-mfull_002dtoc-1921"></a><a name="index-mno_002dfp_002din_002dtoc-1922"></a><a name="index-mno_002dsum_002din_002dtoc-1923"></a><a name="index-mminimal_002dtoc-1924"></a>Modify generation of the TOC (Table Of Contents), which is created for every executable file. The <samp><span class="option">-mfull-toc</span></samp> option is selected by default. In that case, GCC will allocate at least one TOC entry for each unique non-automatic variable reference in your program. GCC @@ -296,13 +296,13 @@ option, GCC will produce code that is slower and larger but which uses extremely little TOC space. You may wish to use this option only on files that contain less frequently executed code. - <br><dt><code>-maix64</code><dt><code>-maix32</code><dd><a name="index-maix64-1923"></a><a name="index-maix32-1924"></a>Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit + <br><dt><code>-maix64</code><dt><code>-maix32</code><dd><a name="index-maix64-1925"></a><a name="index-maix32-1926"></a>Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit <code>long</code> type, and the infrastructure needed to support them. Specifying <samp><span class="option">-maix64</span></samp> implies <samp><span class="option">-mpowerpc64</span></samp> and <samp><span class="option">-mpowerpc</span></samp>, while <samp><span class="option">-maix32</span></samp> disables the 64-bit ABI and implies <samp><span class="option">-mno-powerpc64</span></samp>. GCC defaults to <samp><span class="option">-maix32</span></samp>. - <br><dt><code>-mxl-compat</code><dt><code>-mno-xl-compat</code><dd><a name="index-mxl_002dcompat-1925"></a><a name="index-mno_002dxl_002dcompat-1926"></a>Produce code that conforms more closely to IBM XL compiler semantics + <br><dt><code>-mxl-compat</code><dt><code>-mno-xl-compat</code><dd><a name="index-mxl_002dcompat-1927"></a><a name="index-mno_002dxl_002dcompat-1928"></a>Produce code that conforms more closely to IBM XL compiler semantics when using AIX-compatible ABI. Pass floating-point arguments to prototyped functions beyond the register save area (RSA) on the stack in addition to argument FPRs. Do not assume that most significant @@ -320,7 +320,7 @@ stack is inefficient and rarely needed, this option is not enabled by default and only is necessary when calling subroutines compiled by IBM XL compilers without optimization. - <br><dt><code>-mpe</code><dd><a name="index-mpe-1927"></a>Support <dfn>IBM RS/6000 SP</dfn> <dfn>Parallel Environment</dfn> (PE). Link an + <br><dt><code>-mpe</code><dd><a name="index-mpe-1929"></a>Support <dfn>IBM RS/6000 SP</dfn> <dfn>Parallel Environment</dfn> (PE). Link an application written to use message passing with special startup code to enable the application to run. The system must have PE installed in the standard location (<samp><span class="file">/usr/lpp/ppe.poe/</span></samp>), or the <samp><span class="file">specs</span></samp> file @@ -329,7 +329,7 @@ appropriate directory location. The Parallel Environment does not support threads, so the <samp><span class="option">-mpe</span></samp> option and the <samp><span class="option">-pthread</span></samp> option are incompatible. - <br><dt><code>-malign-natural</code><dt><code>-malign-power</code><dd><a name="index-malign_002dnatural-1928"></a><a name="index-malign_002dpower-1929"></a>On AIX, 32-bit Darwin, and 64-bit PowerPC GNU/Linux, the option + <br><dt><code>-malign-natural</code><dt><code>-malign-power</code><dd><a name="index-malign_002dnatural-1930"></a><a name="index-malign_002dpower-1931"></a>On AIX, 32-bit Darwin, and 64-bit PowerPC GNU/Linux, the option <samp><span class="option">-malign-natural</span></samp> overrides the ABI-defined alignment of larger types, such as floating-point doubles, on their natural size-based boundary. The option <samp><span class="option">-malign-power</span></samp> instructs GCC to follow the ABI-specified @@ -338,23 +338,23 @@ alignment rules. GCC defaults to the standard alignment defined in the ABI. <p>On 64-bit Darwin, natural alignment is the default, and <samp><span class="option">-malign-power</span></samp> is not supported. - <br><dt><code>-msoft-float</code><dt><code>-mhard-float</code><dd><a name="index-msoft_002dfloat-1930"></a><a name="index-mhard_002dfloat-1931"></a>Generate code that does not use (uses) the floating-point register set. + <br><dt><code>-msoft-float</code><dt><code>-mhard-float</code><dd><a name="index-msoft_002dfloat-1932"></a><a name="index-mhard_002dfloat-1933"></a>Generate code that does not use (uses) the floating-point register set. Software floating-point emulation is provided if you use the <samp><span class="option">-msoft-float</span></samp> option, and pass the option to GCC when linking. - <br><dt><code>-msingle-float</code><dt><code>-mdouble-float</code><dd><a name="index-msingle_002dfloat-1932"></a><a name="index-mdouble_002dfloat-1933"></a>Generate code for single- or double-precision floating-point operations. + <br><dt><code>-msingle-float</code><dt><code>-mdouble-float</code><dd><a name="index-msingle_002dfloat-1934"></a><a name="index-mdouble_002dfloat-1935"></a>Generate code for single- or double-precision floating-point operations. <samp><span class="option">-mdouble-float</span></samp> implies <samp><span class="option">-msingle-float</span></samp>. - <br><dt><code>-msimple-fpu</code><dd><a name="index-msimple_002dfpu-1934"></a>Do not generate sqrt and div instructions for hardware floating-point unit. + <br><dt><code>-msimple-fpu</code><dd><a name="index-msimple_002dfpu-1936"></a>Do not generate sqrt and div instructions for hardware floating-point unit. - <br><dt><code>-mfpu</code><dd><a name="index-mfpu-1935"></a>Specify type of floating-point unit. Valid values are <var>sp_lite</var> + <br><dt><code>-mfpu</code><dd><a name="index-mfpu-1937"></a>Specify type of floating-point unit. Valid values are <var>sp_lite</var> (equivalent to -msingle-float -msimple-fpu), <var>dp_lite</var> (equivalent to -mdouble-float -msimple-fpu), <var>sp_full</var> (equivalent to -msingle-float), and <var>dp_full</var> (equivalent to -mdouble-float). - <br><dt><code>-mxilinx-fpu</code><dd><a name="index-mxilinx_002dfpu-1936"></a>Perform optimizations for the floating-point unit on Xilinx PPC 405/440. + <br><dt><code>-mxilinx-fpu</code><dd><a name="index-mxilinx_002dfpu-1938"></a>Perform optimizations for the floating-point unit on Xilinx PPC 405/440. - <br><dt><code>-mmultiple</code><dt><code>-mno-multiple</code><dd><a name="index-mmultiple-1937"></a><a name="index-mno_002dmultiple-1938"></a>Generate code that uses (does not use) the load multiple word + <br><dt><code>-mmultiple</code><dt><code>-mno-multiple</code><dd><a name="index-mmultiple-1939"></a><a name="index-mno_002dmultiple-1940"></a>Generate code that uses (does not use) the load multiple word instructions and the store multiple word instructions. These instructions are generated by default on POWER systems, and not generated on PowerPC systems. Do not use <samp><span class="option">-mmultiple</span></samp> on little-endian @@ -362,7 +362,7 @@ PowerPC systems, since those instructions do not work when the processor is in little-endian mode. The exceptions are PPC740 and PPC750 which permit these instructions in little-endian mode. - <br><dt><code>-mstring</code><dt><code>-mno-string</code><dd><a name="index-mstring-1939"></a><a name="index-mno_002dstring-1940"></a>Generate code that uses (does not use) the load string instructions + <br><dt><code>-mstring</code><dt><code>-mno-string</code><dd><a name="index-mstring-1941"></a><a name="index-mno_002dstring-1942"></a>Generate code that uses (does not use) the load string instructions and the store string word instructions to save multiple registers and do small block moves. These instructions are generated by default on POWER systems, and not generated on PowerPC systems. Do not use @@ -371,7 +371,7 @@ instructions do not work when the processor is in little-endian mode. The exceptions are PPC740 and PPC750 which permit these instructions in little-endian mode. - <br><dt><code>-mupdate</code><dt><code>-mno-update</code><dd><a name="index-mupdate-1941"></a><a name="index-mno_002dupdate-1942"></a>Generate code that uses (does not use) the load or store instructions + <br><dt><code>-mupdate</code><dt><code>-mno-update</code><dd><a name="index-mupdate-1943"></a><a name="index-mno_002dupdate-1944"></a>Generate code that uses (does not use) the load or store instructions that update the base register to the address of the calculated memory location. These instructions are generated by default. If you use <samp><span class="option">-mno-update</span></samp>, there is a small window between the time that the @@ -379,29 +379,29 @@ stack pointer is updated and the address of the previous frame is stored, which means code that walks the stack frame across interrupts or signals may get corrupted data. - <br><dt><code>-mavoid-indexed-addresses</code><dt><code>-mno-avoid-indexed-addresses</code><dd><a name="index-mavoid_002dindexed_002daddresses-1943"></a><a name="index-mno_002davoid_002dindexed_002daddresses-1944"></a>Generate code that tries to avoid (not avoid) the use of indexed load + <br><dt><code>-mavoid-indexed-addresses</code><dt><code>-mno-avoid-indexed-addresses</code><dd><a name="index-mavoid_002dindexed_002daddresses-1945"></a><a name="index-mno_002davoid_002dindexed_002daddresses-1946"></a>Generate code that tries to avoid (not avoid) the use of indexed load or store instructions. These instructions can incur a performance penalty on Power6 processors in certain situations, such as when stepping through large arrays that cross a 16M boundary. This option is enabled by default when targetting Power6 and disabled otherwise. - <br><dt><code>-mfused-madd</code><dt><code>-mno-fused-madd</code><dd><a name="index-mfused_002dmadd-1945"></a><a name="index-mno_002dfused_002dmadd-1946"></a>Generate code that uses (does not use) the floating-point multiply and + <br><dt><code>-mfused-madd</code><dt><code>-mno-fused-madd</code><dd><a name="index-mfused_002dmadd-1947"></a><a name="index-mno_002dfused_002dmadd-1948"></a>Generate code that uses (does not use) the floating-point multiply and accumulate instructions. These instructions are generated by default if hardware floating point is used. The machine-dependent <samp><span class="option">-mfused-madd</span></samp> option is now mapped to the machine-independent <samp><span class="option">-ffp-contract=fast</span></samp> option, and <samp><span class="option">-mno-fused-madd</span></samp> is mapped to <samp><span class="option">-ffp-contract=off</span></samp>. - <br><dt><code>-mmulhw</code><dt><code>-mno-mulhw</code><dd><a name="index-mmulhw-1947"></a><a name="index-mno_002dmulhw-1948"></a>Generate code that uses (does not use) the half-word multiply and + <br><dt><code>-mmulhw</code><dt><code>-mno-mulhw</code><dd><a name="index-mmulhw-1949"></a><a name="index-mno_002dmulhw-1950"></a>Generate code that uses (does not use) the half-word multiply and multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors. These instructions are generated by default when targetting those processors. - <br><dt><code>-mdlmzb</code><dt><code>-mno-dlmzb</code><dd><a name="index-mdlmzb-1949"></a><a name="index-mno_002ddlmzb-1950"></a>Generate code that uses (does not use) the string-search ‘<samp><span class="samp">dlmzb</span></samp>’ + <br><dt><code>-mdlmzb</code><dt><code>-mno-dlmzb</code><dd><a name="index-mdlmzb-1951"></a><a name="index-mno_002ddlmzb-1952"></a>Generate code that uses (does not use) the string-search ‘<samp><span class="samp">dlmzb</span></samp>’ instruction on the IBM 405, 440, 464 and 476 processors. This instruction is generated by default when targetting those processors. - <br><dt><code>-mno-bit-align</code><dt><code>-mbit-align</code><dd><a name="index-mno_002dbit_002dalign-1951"></a><a name="index-mbit_002dalign-1952"></a>On System V.4 and embedded PowerPC systems do not (do) force structures + <br><dt><code>-mno-bit-align</code><dt><code>-mbit-align</code><dd><a name="index-mno_002dbit_002dalign-1953"></a><a name="index-mbit_002dalign-1954"></a>On System V.4 and embedded PowerPC systems do not (do) force structures and unions that contain bit-fields to be aligned to the base type of the bit-field. @@ -411,10 +411,10 @@ boundary and has a size of 4 bytes. By using <samp><span class="option">-mno-bi the structure is aligned to a 1-byte boundary and is 1 byte in size. - <br><dt><code>-mno-strict-align</code><dt><code>-mstrict-align</code><dd><a name="index-mno_002dstrict_002dalign-1953"></a><a name="index-mstrict_002dalign-1954"></a>On System V.4 and embedded PowerPC systems do not (do) assume that + <br><dt><code>-mno-strict-align</code><dt><code>-mstrict-align</code><dd><a name="index-mno_002dstrict_002dalign-1955"></a><a name="index-mstrict_002dalign-1956"></a>On System V.4 and embedded PowerPC systems do not (do) assume that unaligned memory references will be handled by the system. - <br><dt><code>-mrelocatable</code><dt><code>-mno-relocatable</code><dd><a name="index-mrelocatable-1955"></a><a name="index-mno_002drelocatable-1956"></a>Generate code that allows (does not allow) a static executable to be + <br><dt><code>-mrelocatable</code><dt><code>-mno-relocatable</code><dd><a name="index-mrelocatable-1957"></a><a name="index-mno_002drelocatable-1958"></a>Generate code that allows (does not allow) a static executable to be relocated to a different address at run time. A simple embedded PowerPC system loader should relocate the entire contents of <code>.got2</code> and 4-byte locations listed in the <code>.fixup</code> section, @@ -423,42 +423,42 @@ work, all objects linked together must be compiled with <samp><span class="option">-mrelocatable</span></samp> or <samp><span class="option">-mrelocatable-lib</span></samp>. <samp><span class="option">-mrelocatable</span></samp> code aligns the stack to an 8-byte boundary. - <br><dt><code>-mrelocatable-lib</code><dt><code>-mno-relocatable-lib</code><dd><a name="index-mrelocatable_002dlib-1957"></a><a name="index-mno_002drelocatable_002dlib-1958"></a>Like <samp><span class="option">-mrelocatable</span></samp>, <samp><span class="option">-mrelocatable-lib</span></samp> generates a + <br><dt><code>-mrelocatable-lib</code><dt><code>-mno-relocatable-lib</code><dd><a name="index-mrelocatable_002dlib-1959"></a><a name="index-mno_002drelocatable_002dlib-1960"></a>Like <samp><span class="option">-mrelocatable</span></samp>, <samp><span class="option">-mrelocatable-lib</span></samp> generates a <code>.fixup</code> section to allow static executables to be relocated at run time, but <samp><span class="option">-mrelocatable-lib</span></samp> does not use the smaller stack alignment of <samp><span class="option">-mrelocatable</span></samp>. Objects compiled with <samp><span class="option">-mrelocatable-lib</span></samp> may be linked with objects compiled with any combination of the <samp><span class="option">-mrelocatable</span></samp> options. - <br><dt><code>-mno-toc</code><dt><code>-mtoc</code><dd><a name="index-mno_002dtoc-1959"></a><a name="index-mtoc-1960"></a>On System V.4 and embedded PowerPC systems do not (do) assume that + <br><dt><code>-mno-toc</code><dt><code>-mtoc</code><dd><a name="index-mno_002dtoc-1961"></a><a name="index-mtoc-1962"></a>On System V.4 and embedded PowerPC systems do not (do) assume that register 2 contains a pointer to a global area pointing to the addresses used in the program. - <br><dt><code>-mlittle</code><dt><code>-mlittle-endian</code><dd><a name="index-mlittle-1961"></a><a name="index-mlittle_002dendian-1962"></a>On System V.4 and embedded PowerPC systems compile code for the + <br><dt><code>-mlittle</code><dt><code>-mlittle-endian</code><dd><a name="index-mlittle-1963"></a><a name="index-mlittle_002dendian-1964"></a>On System V.4 and embedded PowerPC systems compile code for the processor in little-endian mode. The <samp><span class="option">-mlittle-endian</span></samp> option is the same as <samp><span class="option">-mlittle</span></samp>. - <br><dt><code>-mbig</code><dt><code>-mbig-endian</code><dd><a name="index-mbig-1963"></a><a name="index-mbig_002dendian-1964"></a>On System V.4 and embedded PowerPC systems compile code for the + <br><dt><code>-mbig</code><dt><code>-mbig-endian</code><dd><a name="index-mbig-1965"></a><a name="index-mbig_002dendian-1966"></a>On System V.4 and embedded PowerPC systems compile code for the processor in big-endian mode. The <samp><span class="option">-mbig-endian</span></samp> option is the same as <samp><span class="option">-mbig</span></samp>. - <br><dt><code>-mdynamic-no-pic</code><dd><a name="index-mdynamic_002dno_002dpic-1965"></a>On Darwin and Mac OS X systems, compile code so that it is not + <br><dt><code>-mdynamic-no-pic</code><dd><a name="index-mdynamic_002dno_002dpic-1967"></a>On Darwin and Mac OS X systems, compile code so that it is not relocatable, but that its external references are relocatable. The resulting code is suitable for applications, but not shared libraries. - <br><dt><code>-msingle-pic-base</code><dd><a name="index-msingle_002dpic_002dbase-1966"></a>Treat the register used for PIC addressing as read-only, rather than + <br><dt><code>-msingle-pic-base</code><dd><a name="index-msingle_002dpic_002dbase-1968"></a>Treat the register used for PIC addressing as read-only, rather than loading it in the prologue for each function. The runtime system is responsible for initializing this register with an appropriate value before execution begins. - <br><dt><code>-mprioritize-restricted-insns=</code><var>priority</var><dd><a name="index-mprioritize_002drestricted_002dinsns-1967"></a>This option controls the priority that is assigned to + <br><dt><code>-mprioritize-restricted-insns=</code><var>priority</var><dd><a name="index-mprioritize_002drestricted_002dinsns-1969"></a>This option controls the priority that is assigned to dispatch-slot restricted instructions during the second scheduling pass. The argument <var>priority</var> takes the value <var>0/1/2</var> to assign <var>no/highest/second-highest</var> priority to dispatch slot restricted instructions. - <br><dt><code>-msched-costly-dep=</code><var>dependence_type</var><dd><a name="index-msched_002dcostly_002ddep-1968"></a>This option controls which dependences are considered costly + <br><dt><code>-msched-costly-dep=</code><var>dependence_type</var><dd><a name="index-msched_002dcostly_002ddep-1970"></a>This option controls which dependences are considered costly by the target during instruction scheduling. The argument <var>dependence_type</var> takes one of the following values: <var>no</var>: no dependence is costly, @@ -467,7 +467,7 @@ by the target during instruction scheduling. The argument <var>store_to_load</var>: any dependence from store to load is costly, <var>number</var>: any dependence for which latency >= <var>number</var> is costly. - <br><dt><code>-minsert-sched-nops=</code><var>scheme</var><dd><a name="index-minsert_002dsched_002dnops-1969"></a>This option controls which nop insertion scheme will be used during + <br><dt><code>-minsert-sched-nops=</code><var>scheme</var><dd><a name="index-minsert_002dsched_002dnops-1971"></a>This option controls which nop insertion scheme will be used during the second scheduling pass. The argument <var>scheme</var> takes one of the following values: <var>no</var>: Don't insert nops. @@ -479,52 +479,52 @@ to a new group, according to the estimated processor grouping. <var>number</var>: Insert nops to force costly dependent insns into separate groups. Insert <var>number</var> nops to force an insn to a new group. - <br><dt><code>-mcall-sysv</code><dd><a name="index-mcall_002dsysv-1970"></a>On System V.4 and embedded PowerPC systems compile code using calling + <br><dt><code>-mcall-sysv</code><dd><a name="index-mcall_002dsysv-1972"></a>On System V.4 and embedded PowerPC systems compile code using calling conventions that adheres to the March 1995 draft of the System V Application Binary Interface, PowerPC processor supplement. This is the default unless you configured GCC using ‘<samp><span class="samp">powerpc-*-eabiaix</span></samp>’. - <br><dt><code>-mcall-sysv-eabi</code><dt><code>-mcall-eabi</code><dd><a name="index-mcall_002dsysv_002deabi-1971"></a><a name="index-mcall_002deabi-1972"></a>Specify both <samp><span class="option">-mcall-sysv</span></samp> and <samp><span class="option">-meabi</span></samp> options. + <br><dt><code>-mcall-sysv-eabi</code><dt><code>-mcall-eabi</code><dd><a name="index-mcall_002dsysv_002deabi-1973"></a><a name="index-mcall_002deabi-1974"></a>Specify both <samp><span class="option">-mcall-sysv</span></samp> and <samp><span class="option">-meabi</span></samp> options. - <br><dt><code>-mcall-sysv-noeabi</code><dd><a name="index-mcall_002dsysv_002dnoeabi-1973"></a>Specify both <samp><span class="option">-mcall-sysv</span></samp> and <samp><span class="option">-mno-eabi</span></samp> options. + <br><dt><code>-mcall-sysv-noeabi</code><dd><a name="index-mcall_002dsysv_002dnoeabi-1975"></a>Specify both <samp><span class="option">-mcall-sysv</span></samp> and <samp><span class="option">-mno-eabi</span></samp> options. - <br><dt><code>-mcall-aixdesc</code><dd><a name="index-m-1974"></a>On System V.4 and embedded PowerPC systems compile code for the AIX + <br><dt><code>-mcall-aixdesc</code><dd><a name="index-m-1976"></a>On System V.4 and embedded PowerPC systems compile code for the AIX operating system. - <br><dt><code>-mcall-linux</code><dd><a name="index-mcall_002dlinux-1975"></a>On System V.4 and embedded PowerPC systems compile code for the + <br><dt><code>-mcall-linux</code><dd><a name="index-mcall_002dlinux-1977"></a>On System V.4 and embedded PowerPC systems compile code for the Linux-based GNU system. - <br><dt><code>-mcall-freebsd</code><dd><a name="index-mcall_002dfreebsd-1976"></a>On System V.4 and embedded PowerPC systems compile code for the + <br><dt><code>-mcall-freebsd</code><dd><a name="index-mcall_002dfreebsd-1978"></a>On System V.4 and embedded PowerPC systems compile code for the FreeBSD operating system. - <br><dt><code>-mcall-netbsd</code><dd><a name="index-mcall_002dnetbsd-1977"></a>On System V.4 and embedded PowerPC systems compile code for the + <br><dt><code>-mcall-netbsd</code><dd><a name="index-mcall_002dnetbsd-1979"></a>On System V.4 and embedded PowerPC systems compile code for the NetBSD operating system. - <br><dt><code>-mcall-openbsd</code><dd><a name="index-mcall_002dnetbsd-1978"></a>On System V.4 and embedded PowerPC systems compile code for the + <br><dt><code>-mcall-openbsd</code><dd><a name="index-mcall_002dnetbsd-1980"></a>On System V.4 and embedded PowerPC systems compile code for the OpenBSD operating system. - <br><dt><code>-maix-struct-return</code><dd><a name="index-maix_002dstruct_002dreturn-1979"></a>Return all structures in memory (as specified by the AIX ABI). + <br><dt><code>-maix-struct-return</code><dd><a name="index-maix_002dstruct_002dreturn-1981"></a>Return all structures in memory (as specified by the AIX ABI). - <br><dt><code>-msvr4-struct-return</code><dd><a name="index-msvr4_002dstruct_002dreturn-1980"></a>Return structures smaller than 8 bytes in registers (as specified by the + <br><dt><code>-msvr4-struct-return</code><dd><a name="index-msvr4_002dstruct_002dreturn-1982"></a>Return structures smaller than 8 bytes in registers (as specified by the SVR4 ABI). - <br><dt><code>-mabi=</code><var>abi-type</var><dd><a name="index-mabi-1981"></a>Extend the current ABI with a particular extension, or remove such extension. + <br><dt><code>-mabi=</code><var>abi-type</var><dd><a name="index-mabi-1983"></a>Extend the current ABI with a particular extension, or remove such extension. Valid values are <var>altivec</var>, <var>no-altivec</var>, <var>spe</var>, <var>no-spe</var>, <var>ibmlongdouble</var>, <var>ieeelongdouble</var>. - <br><dt><code>-mabi=spe</code><dd><a name="index-mabi_003dspe-1982"></a>Extend the current ABI with SPE ABI extensions. This does not change + <br><dt><code>-mabi=spe</code><dd><a name="index-mabi_003dspe-1984"></a>Extend the current ABI with SPE ABI extensions. This does not change the default ABI, instead it adds the SPE ABI extensions to the current ABI. - <br><dt><code>-mabi=no-spe</code><dd><a name="index-mabi_003dno_002dspe-1983"></a>Disable Booke SPE ABI extensions for the current ABI. + <br><dt><code>-mabi=no-spe</code><dd><a name="index-mabi_003dno_002dspe-1985"></a>Disable Booke SPE ABI extensions for the current ABI. - <br><dt><code>-mabi=ibmlongdouble</code><dd><a name="index-mabi_003dibmlongdouble-1984"></a>Change the current ABI to use IBM extended-precision long double. + <br><dt><code>-mabi=ibmlongdouble</code><dd><a name="index-mabi_003dibmlongdouble-1986"></a>Change the current ABI to use IBM extended-precision long double. This is a PowerPC 32-bit SYSV ABI option. - <br><dt><code>-mabi=ieeelongdouble</code><dd><a name="index-mabi_003dieeelongdouble-1985"></a>Change the current ABI to use IEEE extended-precision long double. + <br><dt><code>-mabi=ieeelongdouble</code><dd><a name="index-mabi_003dieeelongdouble-1987"></a>Change the current ABI to use IEEE extended-precision long double. This is a PowerPC 32-bit Linux ABI option. - <br><dt><code>-mprototype</code><dt><code>-mno-prototype</code><dd><a name="index-mprototype-1986"></a><a name="index-mno_002dprototype-1987"></a>On System V.4 and embedded PowerPC systems assume that all calls to + <br><dt><code>-mprototype</code><dt><code>-mno-prototype</code><dd><a name="index-mprototype-1988"></a><a name="index-mno_002dprototype-1989"></a>On System V.4 and embedded PowerPC systems assume that all calls to variable argument functions are properly prototyped. Otherwise, the compiler must insert an instruction before every non prototyped call to set or clear bit 6 of the condition code register (<var>CR</var>) to @@ -533,30 +533,30 @@ registers in case the function takes variable arguments. With <samp><span class="option">-mprototype</span></samp>, only calls to prototyped variable argument functions will set or clear the bit. - <br><dt><code>-msim</code><dd><a name="index-msim-1988"></a>On embedded PowerPC systems, assume that the startup module is called + <br><dt><code>-msim</code><dd><a name="index-msim-1990"></a>On embedded PowerPC systems, assume that the startup module is called <samp><span class="file">sim-crt0.o</span></samp> and that the standard C libraries are <samp><span class="file">libsim.a</span></samp> and <samp><span class="file">libc.a</span></samp>. This is the default for ‘<samp><span class="samp">powerpc-*-eabisim</span></samp>’ configurations. - <br><dt><code>-mmvme</code><dd><a name="index-mmvme-1989"></a>On embedded PowerPC systems, assume that the startup module is called + <br><dt><code>-mmvme</code><dd><a name="index-mmvme-1991"></a>On embedded PowerPC systems, assume that the startup module is called <samp><span class="file">crt0.o</span></samp> and the standard C libraries are <samp><span class="file">libmvme.a</span></samp> and <samp><span class="file">libc.a</span></samp>. - <br><dt><code>-mads</code><dd><a name="index-mads-1990"></a>On embedded PowerPC systems, assume that the startup module is called + <br><dt><code>-mads</code><dd><a name="index-mads-1992"></a>On embedded PowerPC systems, assume that the startup module is called <samp><span class="file">crt0.o</span></samp> and the standard C libraries are <samp><span class="file">libads.a</span></samp> and <samp><span class="file">libc.a</span></samp>. - <br><dt><code>-myellowknife</code><dd><a name="index-myellowknife-1991"></a>On embedded PowerPC systems, assume that the startup module is called + <br><dt><code>-myellowknife</code><dd><a name="index-myellowknife-1993"></a>On embedded PowerPC systems, assume that the startup module is called <samp><span class="file">crt0.o</span></samp> and the standard C libraries are <samp><span class="file">libyk.a</span></samp> and <samp><span class="file">libc.a</span></samp>. - <br><dt><code>-mvxworks</code><dd><a name="index-mvxworks-1992"></a>On System V.4 and embedded PowerPC systems, specify that you are + <br><dt><code>-mvxworks</code><dd><a name="index-mvxworks-1994"></a>On System V.4 and embedded PowerPC systems, specify that you are compiling for a VxWorks system. - <br><dt><code>-memb</code><dd><a name="index-memb-1993"></a>On embedded PowerPC systems, set the <var>PPC_EMB</var> bit in the ELF flags + <br><dt><code>-memb</code><dd><a name="index-memb-1995"></a>On embedded PowerPC systems, set the <var>PPC_EMB</var> bit in the ELF flags header to indicate that ‘<samp><span class="samp">eabi</span></samp>’ extended relocations are used. - <br><dt><code>-meabi</code><dt><code>-mno-eabi</code><dd><a name="index-meabi-1994"></a><a name="index-mno_002deabi-1995"></a>On System V.4 and embedded PowerPC systems do (do not) adhere to the + <br><dt><code>-meabi</code><dt><code>-mno-eabi</code><dd><a name="index-meabi-1996"></a><a name="index-mno_002deabi-1997"></a>On System V.4 and embedded PowerPC systems do (do not) adhere to the Embedded Applications Binary Interface (eabi) which is a set of modifications to the System V.4 specifications. Selecting <samp><span class="option">-meabi</span></samp> means that the stack is aligned to an 8-byte boundary, a function @@ -569,7 +569,7 @@ do not call an initialization function from <code>main</code>, and the small data area. The <samp><span class="option">-meabi</span></samp> option is on by default if you configured GCC using one of the ‘<samp><span class="samp">powerpc*-*-eabi*</span></samp>’ options. - <br><dt><code>-msdata=eabi</code><dd><a name="index-msdata_003deabi-1996"></a>On System V.4 and embedded PowerPC systems, put small initialized + <br><dt><code>-msdata=eabi</code><dd><a name="index-msdata_003deabi-1998"></a>On System V.4 and embedded PowerPC systems, put small initialized <code>const</code> global and static data in the ‘<samp><span class="samp">.sdata2</span></samp>’ section, which is pointed to by register <code>r2</code>. Put small initialized non-<code>const</code> global and static data in the ‘<samp><span class="samp">.sdata</span></samp>’ section, @@ -579,42 +579,42 @@ the ‘<samp><span class="samp">.sdata</span></samp>’ section. The <s incompatible with the <samp><span class="option">-mrelocatable</span></samp> option. The <samp><span class="option">-msdata=eabi</span></samp> option also sets the <samp><span class="option">-memb</span></samp> option. - <br><dt><code>-msdata=sysv</code><dd><a name="index-msdata_003dsysv-1997"></a>On System V.4 and embedded PowerPC systems, put small global and static + <br><dt><code>-msdata=sysv</code><dd><a name="index-msdata_003dsysv-1999"></a>On System V.4 and embedded PowerPC systems, put small global and static data in the ‘<samp><span class="samp">.sdata</span></samp>’ section, which is pointed to by register <code>r13</code>. Put small uninitialized global and static data in the ‘<samp><span class="samp">.sbss</span></samp>’ section, which is adjacent to the ‘<samp><span class="samp">.sdata</span></samp>’ section. The <samp><span class="option">-msdata=sysv</span></samp> option is incompatible with the <samp><span class="option">-mrelocatable</span></samp> option. - <br><dt><code>-msdata=default</code><dt><code>-msdata</code><dd><a name="index-msdata_003ddefault-1998"></a><a name="index-msdata-1999"></a>On System V.4 and embedded PowerPC systems, if <samp><span class="option">-meabi</span></samp> is used, + <br><dt><code>-msdata=default</code><dt><code>-msdata</code><dd><a name="index-msdata_003ddefault-2000"></a><a name="index-msdata-2001"></a>On System V.4 and embedded PowerPC systems, if <samp><span class="option">-meabi</span></samp> is used, compile code the same as <samp><span class="option">-msdata=eabi</span></samp>, otherwise compile code the same as <samp><span class="option">-msdata=sysv</span></samp>. - <br><dt><code>-msdata=data</code><dd><a name="index-msdata_003ddata-2000"></a>On System V.4 and embedded PowerPC systems, put small global + <br><dt><code>-msdata=data</code><dd><a name="index-msdata_003ddata-2002"></a>On System V.4 and embedded PowerPC systems, put small global data in the ‘<samp><span class="samp">.sdata</span></samp>’ section. Put small uninitialized global data in the ‘<samp><span class="samp">.sbss</span></samp>’ section. Do not use register <code>r13</code> to address small data however. This is the default behavior unless other <samp><span class="option">-msdata</span></samp> options are used. - <br><dt><code>-msdata=none</code><dt><code>-mno-sdata</code><dd><a name="index-msdata_003dnone-2001"></a><a name="index-mno_002dsdata-2002"></a>On embedded PowerPC systems, put all initialized global and static data + <br><dt><code>-msdata=none</code><dt><code>-mno-sdata</code><dd><a name="index-msdata_003dnone-2003"></a><a name="index-mno_002dsdata-2004"></a>On embedded PowerPC systems, put all initialized global and static data in the ‘<samp><span class="samp">.data</span></samp>’ section, and all uninitialized data in the ‘<samp><span class="samp">.bss</span></samp>’ section. - <br><dt><code>-mblock-move-inline-limit=</code><var>num</var><dd><a name="index-mblock_002dmove_002dinline_002dlimit-2003"></a>Inline all block moves (such as calls to <code>memcpy</code> or structure + <br><dt><code>-mblock-move-inline-limit=</code><var>num</var><dd><a name="index-mblock_002dmove_002dinline_002dlimit-2005"></a>Inline all block moves (such as calls to <code>memcpy</code> or structure copies) less than or equal to <var>num</var> bytes. The minimum value for <var>num</var> is 32 bytes on 32-bit targets and 64 bytes on 64-bit targets. The default value is target-specific. - <br><dt><code>-G </code><var>num</var><dd><a name="index-G-2004"></a><a name="index-smaller-data-references-_0028PowerPC_0029-2005"></a><a name="index-g_t_002esdata_002f_002esdata2-references-_0028PowerPC_0029-2006"></a>On embedded PowerPC systems, put global and static items less than or + <br><dt><code>-G </code><var>num</var><dd><a name="index-G-2006"></a><a name="index-smaller-data-references-_0028PowerPC_0029-2007"></a><a name="index-g_t_002esdata_002f_002esdata2-references-_0028PowerPC_0029-2008"></a>On embedded PowerPC systems, put global and static items less than or equal to <var>num</var> bytes into the small data or bss sections instead of the normal data or bss section. By default, <var>num</var> is 8. The <samp><span class="option">-G </span><var>num</var></samp> switch is also passed to the linker. All modules should be compiled with the same <samp><span class="option">-G </span><var>num</var></samp> value. - <br><dt><code>-mregnames</code><dt><code>-mno-regnames</code><dd><a name="index-mregnames-2007"></a><a name="index-mno_002dregnames-2008"></a>On System V.4 and embedded PowerPC systems do (do not) emit register + <br><dt><code>-mregnames</code><dt><code>-mno-regnames</code><dd><a name="index-mregnames-2009"></a><a name="index-mno_002dregnames-2010"></a>On System V.4 and embedded PowerPC systems do (do not) emit register names in the assembly language output using symbolic forms. - <br><dt><code>-mlongcall</code><dt><code>-mno-longcall</code><dd><a name="index-mlongcall-2009"></a><a name="index-mno_002dlongcall-2010"></a>By default assume that all calls are far away so that a longer more + <br><dt><code>-mlongcall</code><dt><code>-mno-longcall</code><dd><a name="index-mlongcall-2011"></a><a name="index-mno_002dlongcall-2012"></a>By default assume that all calls are far away so that a longer more expensive calling sequence is required. This is required for calls further than 32 megabytes (33,554,432 bytes) from the current location. A short call will be generated if the compiler knows @@ -645,16 +645,16 @@ to use or discard it. <p>In the future, we may cause GCC to ignore all longcall specifications when the linker is known to generate glue. - <br><dt><code>-mtls-markers</code><dt><code>-mno-tls-markers</code><dd><a name="index-mtls_002dmarkers-2011"></a><a name="index-mno_002dtls_002dmarkers-2012"></a>Mark (do not mark) calls to <code>__tls_get_addr</code> with a relocation + <br><dt><code>-mtls-markers</code><dt><code>-mno-tls-markers</code><dd><a name="index-mtls_002dmarkers-2013"></a><a name="index-mno_002dtls_002dmarkers-2014"></a>Mark (do not mark) calls to <code>__tls_get_addr</code> with a relocation specifying the function argument. The relocation allows ld to reliably associate function call with argument setup instructions for TLS optimization, which in turn allows gcc to better schedule the sequence. - <br><dt><code>-pthread</code><dd><a name="index-pthread-2013"></a>Adds support for multithreading with the <dfn>pthreads</dfn> library. + <br><dt><code>-pthread</code><dd><a name="index-pthread-2015"></a>Adds support for multithreading with the <dfn>pthreads</dfn> library. This option sets flags for both the preprocessor and linker. - <br><dt><code>-mrecip</code><dt><code>-mno-recip</code><dd><a name="index-mrecip-2014"></a>This option will enable GCC to use the reciprocal estimate and + <br><dt><code>-mrecip</code><dt><code>-mno-recip</code><dd><a name="index-mrecip-2016"></a>This option will enable GCC to use the reciprocal estimate and reciprocal square root estimate instructions with additional Newton-Raphson steps to increase precision instead of doing a divide or square root and divide for floating-point arguments. You should use @@ -667,7 +667,7 @@ instruction, the precision of the sequence can be decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994) for reciprocal square roots. - <br><dt><code>-mrecip=</code><var>opt</var><dd><a name="index-mrecip_003dopt-2015"></a>This option allows to control which reciprocal estimate instructions + <br><dt><code>-mrecip=</code><var>opt</var><dd><a name="index-mrecip_003dopt-2017"></a>This option allows to control which reciprocal estimate instructions may be used. <var>opt</var> is a comma separated list of options, which may be preceded by a <code>!</code> to invert the option: <code>all</code>: enable all estimate instructions, @@ -685,7 +685,7 @@ all of the reciprocal estimate instructions, except for the <code>FRSQRTE</code>, <code>XSRSQRTEDP</code>, and <code>XVRSQRTEDP</code> instructions which handle the double-precision reciprocal square root calculations. - <br><dt><code>-mrecip-precision</code><dt><code>-mno-recip-precision</code><dd><a name="index-mrecip_002dprecision-2016"></a>Assume (do not assume) that the reciprocal estimate instructions + <br><dt><code>-mrecip-precision</code><dt><code>-mno-recip-precision</code><dd><a name="index-mrecip_002dprecision-2018"></a>Assume (do not assume) that the reciprocal estimate instructions provide higher-precision estimates than is mandated by the PowerPC ABI. Selecting <samp><span class="option">-mcpu=power6</span></samp> or <samp><span class="option">-mcpu=power7</span></samp> automatically selects <samp><span class="option">-mrecip-precision</span></samp>. The double-precision @@ -693,7 +693,7 @@ square root estimate instructions are not generated by default on low-precision machines, since they do not provide an estimate that converges after three steps. - <br><dt><code>-mveclibabi=</code><var>type</var><dd><a name="index-mveclibabi-2017"></a>Specifies the ABI type to use for vectorizing intrinsics using an + <br><dt><code>-mveclibabi=</code><var>type</var><dd><a name="index-mveclibabi-2019"></a>Specifies the ABI type to use for vectorizing intrinsics using an external library. The only type supported at present is <code>mass</code>, which specifies to use IBM's Mathematical Acceleration Subsystem (MASS) libraries for vectorizing intrinsics using external libraries. @@ -715,13 +715,13 @@ for power7. Both <samp><span class="option">-ftree-vectorize</span></samp> and <samp><span class="option">-funsafe-math-optimizations</span></samp> have to be enabled. The MASS libraries will have to be specified at link time. - <br><dt><code>-mfriz</code><dt><code>-mno-friz</code><dd><a name="index-mfriz-2018"></a>Generate (do not generate) the <code>friz</code> instruction when the + <br><dt><code>-mfriz</code><dt><code>-mno-friz</code><dd><a name="index-mfriz-2020"></a>Generate (do not generate) the <code>friz</code> instruction when the <samp><span class="option">-funsafe-math-optimizations</span></samp> option is used to optimize rounding of floating-point values to 64-bit integer and back to floating point. The <code>friz</code> instruction does not return the same value if the floating-point number is too large to fit in an integer. - <br><dt><code>-mpointers-to-nested-functions</code><dt><code>-mno-pointers-to-nested-functions</code><dd><a name="index-mpointers_002dto_002dnested_002dfunctions-2019"></a>Generate (do not generate) code to load up the static chain register + <br><dt><code>-mpointers-to-nested-functions</code><dt><code>-mno-pointers-to-nested-functions</code><dd><a name="index-mpointers_002dto_002dnested_002dfunctions-2021"></a>Generate (do not generate) code to load up the static chain register (<var>r11</var>) when calling through a pointer on AIX and 64-bit Linux systems where a function pointer points to a 3-word descriptor giving the function address, TOC value to be loaded in register <var>r2</var>, and @@ -731,7 +731,7 @@ not be able to call through pointers to nested functions or pointers to functions compiled in other languages that use the static chain if you use the <samp><span class="option">-mno-pointers-to-nested-functions</span></samp>. - <br><dt><code>-msave-toc-indirect</code><dt><code>-mno-save-toc-indirect</code><dd><a name="index-msave_002dtoc_002dindirect-2020"></a>Generate (do not generate) code to save the TOC value in the reserved + <br><dt><code>-msave-toc-indirect</code><dt><code>-mno-save-toc-indirect</code><dd><a name="index-msave_002dtoc_002dindirect-2022"></a>Generate (do not generate) code to save the TOC value in the reserved stack location in the function prologue if the function calls through a pointer on AIX and 64-bit Linux systems. If the TOC value is not saved in the prologue, it is saved just before the call through the |