Merge branch 'LA.UM.9.12.C10.11.00.00.840.201' via branch 'qcom-msm-4.19-7250' into android-msm-pixel-4.19android-t-beta-2_r0.3 android-msm-redbull-4.19-t-beta-2

Bug: 210578498 Signed-off-by: JohnnLee <johnnlee@google.com> Change-Id: Ib9f997412e7ba7d0d933f8958ef6ba225e2283bc
author: JohnnLee <johnnlee@google.com> 2022-01-05 18:37:44 +0800
committer: JohnnLee <johnnlee@google.com> 2022-01-05 18:38:18 +0800
commit: 0a9d6a7a641c752059414bf71c8821313d91d390 (patch)
tree: d757baebb4d172bf452befb0c6b88cb813628bcf
parent: 9aa479ab86afd2c5c0114143de441b7b404f3101 (diff)
parent: e15a3ffd15056de6bd8f149434d1e5034d957ea5 (diff)
download: devicetree-android-msm-redbull-4.19-t-beta-2.tar.gz
146 files changed, 15039 insertions, 966 deletions
diff --git a/NOTICE b/NOTICE
new file mode 100644
index 00000000..0ba0e148
--- /dev/null
+++ b/NOTICE
@@ -0,0 +1,40 @@
+This NOTICE file contains certain notices of software components included
+with the software that Qualcomm Technologies, Inc. ("Qualcomm Technologies") is required to
+provide you. Notwithstanding anything in the notices in this file, your use
+of these software components together with the Qualcomm Technologies software (Qualcomm Technologies
+software hereinafter referred to as "Software") is subject to the terms of
+your license from Qualcomm Technologies. Compliance with all copyright laws and software
+license agreements included in the notice section of this file are the
+responsibility of the user. Except as may be granted by separate express
+written agreement, this file provides no license to any patents,
+trademarks, copyrights, or other intellectual property.
+
+Copyright (c) 2021 Qualcomm Technologies, Inc. All rights reserved.
+Qualcomm is a registered trademark and registered service mark of
+QUALCOMM Incorporated. All other trademarks and service marks are the
+property of their respective owners.
+________________________________________
+NOTICES
+________________________________________
+/*
+ * Copyright (C) 2008 Shanghai awinic technology co.,ltd. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS
+ * IN THE SOFTWARE.
+ */
diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt
index 0660e025..c3d4a810 100644
--- a/bindings/arm/msm/msm.txt
+++ b/bindings/arm/msm/msm.txt
@@ -59,6 +59,9 @@ SoCs:
 - BENGAL
   compatible = "qcom,bengal"
 
+- KHAJE
+  compatible = "qcom,khaje"
+
 - SCUBA
   compatible = "qcom,scuba"
 
@@ -247,6 +250,9 @@ compatible = "qcom,bengal-qrd"
 compatible = "qcom,bengal-idp"
 compatible = "qcom,bengalp"
 compatible = "qcom,bengalp-idp"
+compatible = "qcom,khaje-idp"
+compatible = "qcom,khaje-qrd"
+compatible = "qcom,khaje-atp"
 compatible = "qcom,scuba-rumi"
 compatible = "qcom,scuba-idp"
 compatible = "qcom,scuba-qrd"
diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt
index 35fcde1f..67a6f450 100644
--- a/bindings/clock/qcom,debugcc.txt
+++ b/bindings/clock/qcom,debugcc.txt
@@ -5,8 +5,9 @@ Required properties :
 - compatible: Shall contain "qcom,kona-debugcc", "qcom,lito-debugcc",
 		"qcom,bengal-debugcc", "qcom,lagoon-debugcc"
 		"qcom,sdm660-debugcc" "qcom,sdm429w-debugcc"
-		"qcom,msm8937-debugcc" "qcom,msm8917-debugcc"
-		"qcom,sdm429w-debugcc "or "qcom,qm215-debugcc".
+		"qcom,sdm439-debugcc", "qcom,sdm429-debugcc"
+		"qcom,qm215-debugcc" or "qcom,khaje-debugcc".
+
 - qcom,gcc: phandle to the GCC device node.
 - qcom,videocc: phandle to the Video CC device node.
 - qcom,camcc: phandle to the Camera CC device node.
diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt
index de9da083..725cd3a5 100644
--- a/bindings/clock/qcom,dispcc.txt
+++ b/bindings/clock/qcom,dispcc.txt
@@ -9,7 +9,8 @@ Required properties :
 		"qcom,lito-dispcc"
 		"qcom,bengal-dispcc"
 		"qcom,lagoon-dispcc"
-		"qcom,scuba-dispcc".
+		"qcom,scuba-dispcc"
+		"qcom,khaje-dispcc".
 - reg : shall contain base register location and length.
 - vdd_mm-supply: phandle to the MM_CX rail that needs to be voted on behalf
 of the clocks.
diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt
index 2f066cd5..932c0243 100644
--- a/bindings/clock/qcom,gcc.txt
+++ b/bindings/clock/qcom,gcc.txt
@@ -31,10 +31,12 @@ Required properties :
 			"qcom,gcc-msm8917"
 			"qcom,gcc-msm8937"
 			"qcom,gcc-sdm429w"
+			"qcom,gcc-sdm450"
 			"qcom,gcc-mdss-msm8937"
 			"qcom,gcc-mdss-qm215"
 			"qcom,gcc-mdss-sdm429w"
 			"qcom,gcc-mdss-sdm439"
+			"qcom,khaje-gcc"
 
 - reg : shall contain base register location and length
 - #clock-cells : shall contain 1
diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt
index 0d5a86e5..c9e1a757 100644
--- a/bindings/clock/qcom,gpucc.txt
+++ b/bindings/clock/qcom,gpucc.txt
@@ -9,7 +9,8 @@ Required properties :
 		"qcom,lagoon-gpucc",
 		"qcom,gpu-sdm660",
 		"qcom,gpucc-sdm660",
-		"qcom,gpucc-sdm630".
+		"qcom,gpucc-sdm630",
+		"qcom,khaje-gpucc".
 
 - reg: shall contain base register offset and size.
 - reg-names: names of registers listed in the same order as in the reg property.
diff --git a/bindings/clock/qcom,rpmcc.txt b/bindings/clock/qcom,rpmcc.txt
index 2c167462..d99daf4c 100644
--- a/bindings/clock/qcom,rpmcc.txt
+++ b/bindings/clock/qcom,rpmcc.txt
@@ -20,6 +20,7 @@ Required properties :
 			"qcom,rpmcc-sdm660", "qcom,rpmcc"
 			"qcom,rpmcc-sdm439", "qcom,rpmcc"
 			"qcom,rpmcc-qm215", "qcom,rpmcc"
+			"qcom,rpmcc-sdm450", "qcom,rpmcc"
 
 - #clock-cells : shall contain 1
 
diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt
index 8301c02e..3de21e43 100644
--- a/bindings/cnss/cnss-wlan.txt
+++ b/bindings/cnss/cnss-wlan.txt
@@ -82,6 +82,7 @@ Optional properties:
   - qcom,bt-en-gpio: QCA6490 requires synchronization for BT and WLAN GPIO
                    enable to resolve PMU power up issues. Provide BT GPIO using
                    this config param.
+  - qcom,sw-ctrl-gpio: Switch control GPIO for device power control
 
 Example:
 
diff --git a/bindings/display/msm/sde.txt b/bindings/display/msm/sde.txt
index 00108a47..73c73c15 100644
--- a/bindings/display/msm/sde.txt
+++ b/bindings/display/msm/sde.txt
@@ -282,6 +282,13 @@ Optional properties:
 				DSPP offsets. Since LTM hardware is represented as part of
 				DSPP block, the LTM offsets are calculated based on the
 				corresponding DSPP base.
+- qcom,sde-dspp-rc-version:	A u32 value indicating the version of the RC hardware.
+- qcom,sde-dspp-rc-off:	Array of u32 offsets indicate the RC block offsets from the
+				DSPP offsets. Since RC hardware is represented as part of
+				DSPP block, the RC offsets are calculated based on the
+				corresponding DSPP base.
+- qcom,sde-dspp-rc-size:	A u32 value indicating the RC block address range.
+- qcom,sde-dspp-rc-mem-size:	A u32 value indicating the RC block shared memory size.
 - qcom,sde-vbif-id:		Array of vbif ids corresponding to the
 				offsets defined in property: qcom,sde-vbif-off.
 - qcom,sde-vbif-default-ot-rd-limit:	A u32 value indicates the default read OT limit
diff --git a/bindings/gpu/adreno.txt b/bindings/gpu/adreno.txt
index 390b44c4..0858c6c0 100644
--- a/bindings/gpu/adreno.txt
+++ b/bindings/gpu/adreno.txt
@@ -140,6 +140,19 @@ Optional Properties:
 				mask   - mask for the relevant bits in the efuse register.
 				shift  - number of bits to right shift to get the speed bin
 				value.
+
+- qcom,gpu-speed-bin-vectors:
+				GPU speed bin vectors property is the series of all the vectors
+				in format specified below. Values from individual fuses are read,
+				masked and shifted to form a value. At the end all fuse values
+				are ordered together to form final speed bin value.
+				<offset mask shift>
+				<offset mask shift>
+				<  ..   ..    ..  >
+				offset - offset of the efuse register from the base.
+				mask   - mask for the relevant bits in the efuse register.
+				shift  - number of bits to right shift.
+
 - qcom,gpu-disable-fuse:	GPU disable fuse
 				<offset mask shift>
 				offset - offset of the efuse register from the base.
diff --git a/bindings/interrupt-controller/qcom,mpm.txt b/bindings/interrupt-controller/qcom,mpm.txt
index f67d2c3f..dce7af96 100644
--- a/bindings/interrupt-controller/qcom,mpm.txt
+++ b/bindings/interrupt-controller/qcom,mpm.txt
@@ -30,6 +30,7 @@ Properties:
 		"qcom,mpm-gic-bengal"
 		"qcom,mpm-gic-scuba"
 		"qcom,mpm-gic-sdm660"
+		"qcom,mpm-gic-khaje"
 
 - interrupts:
 	Usage: required
diff --git a/bindings/leds/leds-aw2016.txt b/bindings/leds/leds-aw2016.txt
new file mode 100644
index 00000000..de2c921c
--- /dev/null
+++ b/bindings/leds/leds-aw2016.txt
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2008 Shanghai awinic technology co.,ltd. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+Awinic. AW2016 LED
+
+AW2016 LED device supports 3 LED channels and the driver
+register each channel as a single LED class device and
+exports interfaces to update brightness, set timer trigger
+and enable HW based blink functionalities.
+
+- compatible
+  Usage: required
+  Value type: <string>
+  Definition: Must be "awinic,aw2016_led"
+
+- reg
+  Usage: required
+  Value type: <u32>
+  Definition: The 7-bit I2C address for AW2016 chip.
+
+Properties for child properties:
+- awinic,name
+  Usage: required
+  Value type: <string>
+  Definition: Name of the LED which will be register as the LED class
+	device name.
+
+- awinic,id
+  Usage: required
+  Value type: <u32>
+  Definition: It represents the LED hardware channel index. The valid
+	values are: 0, 1, 2.
+
+- awinic,imax
+  Usage: required
+  Value type: <u32>
+  Definition: The setting of the maximum current for the given LED channel,
+	the valid values are: 0, 1, 2, 3, and the corresponding current
+	setting are: 15mA, 30mA, 5mA, 10mA.
+
+- awinic,led-current
+  Usage: required
+  Value type: <u32>
+  Definition: The setting of the current when the LED channel is enabled.
+
+- awinic,max-brightness
+  Usage: required
+  Value type: <u32>
+  Definition: The maximum brightness value for the LED class device.
+
+- awinic,rise-time-ms
+  Usage: required
+  Value type <u32>
+  Definition: The duration of the led ramping from 0 to maximum brightness
+	when breath function is enabled.
+
+- awinic,hold-time-ms
+  Usage: required
+  Value type: <u32>
+  Definition: The duration of the led staying at the maximum brightness
+	when breath function is enabled.
+
+- awinic,fall-time-ms
+  Usage: required
+  Value type: <u32>
+  Definition: The duration of the led ramping down from maximum brightness
+	to 0 when breath function is enabled.
+
+- awinic,off-time-ms
+  Usage: required
+  Value type: <u32>
+  Definition: The duration of the led staying at 0 brightness when breath
+	function is enabled.
+
+Example:
+	awinic@64 {
+		compatible = "awinic,aw2016_led";
+		reg = <0x64>;
+
+		awinic,red {
+			awinic,name = "red";
+			awinic,id = <0>;
+			awinic,imax = <2>;
+			awinic,led-current = <3>;
+			awinic,max-brightness = <255>;
+			awinic,rise-time-ms = <6>;
+			awinic,hold-time-ms = <0>;
+			awinic,fall-time-ms = <6>;
+			awinic,off-time-ms = <4>;
+		};
+
+		awinic,green {
+			awinic,name = "green";
+			awinic,id = <1>;
+			awinic,imax = <2>;
+			awinic,led-current = <3>;
+			awinic,max-brightness = <255>;
+			awinic,rise-time-ms = <6>;
+			awinic,hold-time-ms = <0>;
+			awinic,fall-time-ms = <6>;
+			awinic,off-time-ms = <4>;
+		};
+
+		awinic,blue {
+			awinic,name = "blue";
+			awinic,id = <2>;
+			awinic,imax = <2>;
+			awinic,led-current = <3>;
+			awinic,max-brightness = <255>;
+			awinic,rise-time-ms = <6>;
+			awinic,hold-time-ms = <0>;
+			awinic,fall-time-ms = <6>;
+			awinic,off-time-ms = <4>;
+		};
+	};
+
diff --git a/bindings/leds/leds-qpnp-flash-v2.txt b/bindings/leds/leds-qpnp-flash-v2.txt
index a282b4c8..682f8afb 100644
--- a/bindings/leds/leds-qpnp-flash-v2.txt
+++ b/bindings/leds/leds-qpnp-flash-v2.txt
@@ -22,6 +22,12 @@ Optional properties:
 			  128, 192. Unit is uS.
 - qcom,warmup-delay-us	: Integer type to specify warm up delay. Valid values are 32, 64,
 			  128, 192. Unit is uS.
+- qcom,ramp-up-step	: Integer property to specify flash current ramp up time
+			  step. Unit is in nS. Allowed values are: 200, 400, 800, 1600,
+			  3200, 6400, 12800, 25600.
+- qcom,ramp-down-step	: Integer property to specify flash current ramp down
+			  time step. Unit is in nS. Allowed values are: 200, 400, 800, 1600,
+			  3200, 6400, 12800, 25600.
 - qcom,short-circuit-det	: Boolean property which enables short circuit fault detection.
 - qcom,open-circuit-det		: Boolean property which enables open circuit fault detection.
 - qcom,vph-droop-det		: Boolean property which enables VPH droop detection.
diff --git a/bindings/pinctrl/qcom,khaje-pinctrl.txt b/bindings/pinctrl/qcom,khaje-pinctrl.txt
new file mode 100644
index 00000000..822c0c48
--- /dev/null
+++ b/bindings/pinctrl/qcom,khaje-pinctrl.txt
@@ -0,0 +1,188 @@
+Qualcomm Technologies, Inc. KHAJE TLMM block
+
+This binding describes the Top Level Mode Multiplexer block found in the
+KHAJE platform.
+
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: must be "qcom,khaje-pinctrl"
+
+- reg:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: the base address and size of the TLMM register space.
+
+- interrupts:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: should specify the TLMM summary IRQ.
+
+- interrupt-controller:
+	Usage: required
+	Value type: <none>
+	Definition: identifies this node as an interrupt controller
+
+- #interrupt-cells:
+	Usage: required
+	Value type: <u32>
+	Definition: must be 2. Specifying the pin number and flags, as defined
+		    in <dt-bindings/interrupt-controller/irq.h>
+
+- gpio-controller:
+	Usage: required
+	Value type: <none>
+	Definition: identifies this node as a gpio controller
+
+- #gpio-cells:
+	Usage: required
+	Value type: <u32>
+	Definition: must be 2. Specifying the pin number and flags, as defined
+		    in <dt-bindings/gpio/gpio.h>
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+
+PIN CONFIGURATION NODES:
+
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+- pins:
+	Usage: required
+	Value type: <string-array>
+	Definition: List of gpio pins affected by the properties specified in
+		    this subnode.
+
+		    Valid pins are:
+		      gpio0-gpio112
+		        Supports mux, bias and drive-strength
+
+		      sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
+		      sdc2_data sdc1_rclk
+		        Supports bias and drive-strength
+
+- function:
+	Usage: required
+	Value type: <string>
+	Definition: Specify the alternative function to be configured for the
+		    specified pins. Functions are only valid for gpio pins.
+		    Valid values are:
+
+		    blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
+		    bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
+		    qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
+		    dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
+		    blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
+		    mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
+		    atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
+		    cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
+		    pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
+		    qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
+		    qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
+		    atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
+		    atest_usb20, atest_char0, dac_calib10, qdss_stm10,
+		    qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
+		    blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
+		    qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
+		    qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
+		    dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
+		    qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
+		    dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
+		    dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
+		    dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
+		    dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
+		    sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
+		    qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
+		    uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
+		    blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
+		    qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
+		    blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
+		    cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
+		    blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
+		    qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
+		    isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
+		    qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
+		    sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
+		    gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
+		    qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
+		    tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
+		    qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
+		    sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
+		    sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
+		    ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
+		    blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
+		    pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
+		    qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
+		    qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
+		    gpio
+
+- bias-disable:
+	Usage: optional
+	Value type: <none>
+	Definition: The specified pins should be configued as no pull.
+
+- bias-pull-down:
+	Usage: optional
+	Value type: <none>
+	Definition: The specified pins should be configued as pull down.
+
+- bias-pull-up:
+	Usage: optional
+	Value type: <none>
+	Definition: The specified pins should be configued as pull up.
+
+- output-high:
+	Usage: optional
+	Value type: <none>
+	Definition: The specified pins are configured in output mode, driven
+		    high.
+		    Not valid for sdc pins.
+
+- output-low:
+	Usage: optional
+	Value type: <none>
+	Definition: The specified pins are configured in output mode, driven
+		    low.
+		    Not valid for sdc pins.
+
+- drive-strength:
+	Usage: optional
+	Value type: <u32>
+	Definition: Selects the drive strength for the specified pins, in mA.
+		    Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+
+Example:
+
+	tlmm: pinctrl@400000 {
+		compatible = "qcom,khaje-pinctrl";
+		reg = <0x400000 0xc00000>;
+		interrupts = <0 227 0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
diff --git a/bindings/power/supply/qcom/qpnp-linear-charger.txt b/bindings/power/supply/qcom/qpnp-linear-charger.txt
index e2540015..82ae6b49 100644
--- a/bindings/power/supply/qcom/qpnp-linear-charger.txt
+++ b/bindings/power/supply/qcom/qpnp-linear-charger.txt
@@ -18,6 +18,8 @@ Parent node required properties:
 - qcom,vddsafe-mv:			Maximum Vdd voltage in mV.
 - qcom,vinmin-mv:			Minimum input voltage in mV.
 - qcom,ibatsafe-ma:			Safety battery current setting
+- qcom,v-cutoff-mv:			Cutoff voltage where the battery
+					is considered dead in mV.
 
 Parent node optional properties:
 - qcom,vbatweak-uv:			Weak battery voltage threshold in uV,
diff --git a/bindings/power/supply/qcom/qpnp-smb5.txt b/bindings/power/supply/qcom/qpnp-smb5.txt
index f261dbd6..c1359c1c 100644
--- a/bindings/power/supply/qcom/qpnp-smb5.txt
+++ b/bindings/power/supply/qcom/qpnp-smb5.txt
@@ -368,9 +368,17 @@ Charger specific properties:
   Usage:      optional
   Value type: <u32>
   Definition: Specifies the maximum input current limit that can be configured
-		for HVDCP2 adapter.
+		for HVDCP2 adapter when it's working at 5V and 9V.
 		If left unspecified, the default value is 3000mA.
 
+- qcom,hvdcp2-12v-max-icl-ua
+  Usage:      optional
+  Value type: <u32>
+  Definition: Specifies the maximum input current limit that can be configured
+		for HVDCP2 adapter when it's working at 12V.
+		If left unspecified, the default value is the same value
+		specified in "qcom,hvdcp2-max-icl-ua".
+
 - qcom,hvdcp3-max-icl-ua
   Usage:      optional
   Value type: <u32>
diff --git a/bindings/power/supply/qcom/smb1398-charger.txt b/bindings/power/supply/qcom/smb1398-charger.txt
index 5f1588f6..5764c68d 100644
--- a/bindings/power/supply/qcom/smb1398-charger.txt
+++ b/bindings/power/supply/qcom/smb1398-charger.txt
@@ -28,6 +28,10 @@ Charger specific properties:
 	      mode (auto transition between DIV2 CP and 3-level buck) as a
 	      pre-regulator stand between wireless receiver and downstream
 	      chargers.
+	      "qcom,smb1394-div2-cp-primary" for SMB1394 working in DIV2 mode as
+	      a primary companion charger.
+	      "qcom,smb1394-div2-cp-secondary" for SMB1394 working in DIV2 mode as
+	      a secondary companion charger.
 
 - interrupts
   Usage:      optional
diff --git a/bindings/regulator/qcom,pm8008-regulator.txt b/bindings/regulator/qcom,pm8008-regulator.txt
index a5cf233d..905194af 100644
--- a/bindings/regulator/qcom,pm8008-regulator.txt
+++ b/bindings/regulator/qcom,pm8008-regulator.txt
@@ -62,7 +62,7 @@ PM8008 chip regulator specific properties:
 - compatible:
   Usage: required
   Value type: <string>
-  Definition: must be "qcom,pm8008-regulator"
+  Definition: must be "qcom,pm8008-regulator" or "qcom,pm8010-regulator"
 
 - <pin>-supply:
   Usage: optional
diff --git a/bindings/sound/qcom-audio-dev.txt b/bindings/sound/qcom-audio-dev.txt
index 9875cb2c..ffef4409 100644
--- a/bindings/sound/qcom-audio-dev.txt
+++ b/bindings/sound/qcom-audio-dev.txt
@@ -1873,6 +1873,7 @@ Optional properties:
 - qcom,rxtx-bolero-codec: Property to specify RX-TX macros supported.
 - qcom,wsa-bolero-codec: Property to specify WSA macro supported.
 - qcom,tdm-audio-intf: Property to specify if Aux PCM interface is used for the target
+- qcom,wcd-datalane-mismatch: Property to specify if wcd datalane mismatch.
 
 Example:
 	bengal_snd: sound {
@@ -1885,6 +1886,7 @@ Example:
 		qcom,va-bolero-codec = <1>;
 		qcom,rxtx-bolero-codec = <1>;
 		qcom,tdm-audio-intf = <1>;
+		qcom,wcd-datalane-mismatch = <1>;
 
 		asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>,
 				<&loopback>, <&compress>, <&hostless>,
@@ -2005,6 +2007,10 @@ Optional properties:
 - qcom,msm-mi2s-master: This property is used to inform machine driver
   if MSM is the clock master of mi2s. 1 means master and 0 means slave. The
   first entry is primary mi2s; the second entry is secondary mi2s, and so on.
+- qcom,tdm-clk-attribute: This property is used to set the clock attribute for tdm.
+  The first entry is primary tdm; the second entry is secondary tdm, and so on.
+- qcom,mi2s-clk-attribute: This property is used to set the clock attribute for mi2s.
+  The first entry is primary mi2s; the second entry is secondary mi2s, and so on.
 - qcom,msm-mbhc-hphl-swh: This property is used to distinguish headset HPHL
   switch type on target typically the switch type will be normally open or
   normally close, value for this property 0 for normally close and 1 for
@@ -2151,6 +2157,27 @@ Example:
 
 };
 
+Required properties:
+- compatible : "qcom,spf-core-platform"
+
+Required properties:
+- compatible : "qcom,audio-pkt-core-platform"
+
+Required properties:
+- compatible : "qcom,gpr"
+
+Required properties:
+- compatible : "qcom,spf_core"
+
+Required properties:
+- compatible : "qcom,audio-pkt"
+
+Required properties:
+- compatible : "qcom,audio_prm"
+
+Required properties:
+- compatible : "qcom,voice_mhi_gpr"
+
 * LITO ASoC Machine driver
 
 Required properties:
diff --git a/bindings/thermal/qcom,rpm-smd-cdev.txt b/bindings/thermal/qcom,rpm-smd-cdev.txt
new file mode 100644
index 00000000..0a5da03c
--- /dev/null
+++ b/bindings/thermal/qcom,rpm-smd-cdev.txt
@@ -0,0 +1,27 @@
+Qualcomm Technologies, Inc. RPM SMD cooling device
+
+The RPM shared memory(SMD) cooling device, will be used to set
+different thermal band level to RPM hardware. When threshold violation
+occurs, RPM SMD cooling device sends pre-configured thermal band level
+to RPM hardware via SMD.
+
+Required Parameters:
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: should be "qcom,rpm-smd-cooling-device"
+
+- #cooling-cells:
+	Usage: required
+	Value type: <integer>
+	Definition: Must be 2. This is required by of-thermal and refer the doc
+		<devicetree/bindings/thermal/thermal.txt> for more details.
+
+Example:
+
+&rpm_bus {
+	rpm_smd_cdev: rpm-smd-cdev {
+		compatible = "qcom,rpm-smd-cooling-device";
+		#cooling-cells = <2>;
+	};
+};
diff --git a/bindings/vendor-prefixes.txt b/bindings/vendor-prefixes.txt
index e2f0ec8a..a9ca78a7 100644
--- a/bindings/vendor-prefixes.txt
+++ b/bindings/vendor-prefixes.txt
@@ -52,6 +52,7 @@ avago	Avago Technologies
 avia	avia semiconductor
 avic	Shanghai AVIC Optoelectronics Co., Ltd.
 avnet	Avnet, Inc.
+awinic  Shanghai Awinic Electronic Technology Co., LTD.
 axentia	Axentia Technologies AB
 axis	Axis Communications AB
 bananapi BIPAI KEJI LIMITED
diff --git a/qcom/Makefile b/qcom/Makefile
index 82469d56..6d723dcb 100644
--- a/qcom/Makefile
+++ b/qcom/Makefile
@@ -4,18 +4,21 @@ ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
         dtbo-$(CONFIG_ARCH_KONA) += \
                 kona-cdp-overlay.dtbo \
                 kona-cdp-lcd-overlay.dtbo \
+                kona-cdp-lcd-tron-overlay.dtbo \
                 kona-mtp-overlay.dtbo \
                 kona-mtp-ws-overlay.dtbo \
 		kona-sa-mtp-overlay.dtbo \
                 kona-xr-overlay.dtbo \
                 kona-rumi-overlay.dtbo \
                 kona-qrd-overlay.dtbo \
-		kona-xrfusion-overlay.dtbo \
-		kona-xrfusion-ult-overlay.dtbo \
+                kona-xrfusion-overlay.dtbo \
+                kona-xrfusion-ult-overlay.dtbo \
+                kona-arglass-overlay.dtbo \
                 kona-hdk-overlay.dtbo
 
 kona-cdp-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
 kona-cdp-lcd-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
+kona-cdp-lcd-tron-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
 kona-mtp-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
 kona-mtp-ws-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
 kona-sa-mtp-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
@@ -24,6 +27,7 @@ kona-rumi-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
 kona-qrd-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
 kona-xrfusion-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
 kona-xrfusion-ult-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
+kona-arglass-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
 kona-hdk-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
 else
 dtb-$(CONFIG_ARCH_KONA) += kona-rumi.dtb \
@@ -31,10 +35,12 @@ dtb-$(CONFIG_ARCH_KONA) += kona-rumi.dtb \
         kona-mtp-ws.dtb \
         kona-mtp-sa.dtb \
         kona-xr.dtb \
-	kona-xrfusion.dtb \
-	kona-xrfusion-ult.dtb \
+        kona-xrfusion.dtb \
+        kona-xrfusion-ult.dtb \
+        kona-arglass.dtb \
         kona-cdp.dtb \
         kona-cdp-lcd.dtb \
+        kona-cdp-lcd-tron.dtb \
         kona-qrd.dtb \
         kona-v2-rumi.dtb \
         kona-v2-mtp.dtb \
@@ -42,8 +48,9 @@ dtb-$(CONFIG_ARCH_KONA) += kona-rumi.dtb \
         kona-v2-mtp-sa.dtb \
         kona-v2-cdp.dtb \
         kona-v2-qrd.dtb \
-	kona-v2-xrfusion.dtb \
-	kona-v2-xrfusion-ult.dtb \
+        kona-v2-xrfusion.dtb \
+        kona-v2-xrfusion-ult.dtb \
+        kona-v2-arglass.dtb \
         kona-hdk.dtb \
         kona-v2.1-mtp.dtb \
         kona-v2.1-mtp-ws.dtb \
@@ -51,9 +58,11 @@ dtb-$(CONFIG_ARCH_KONA) += kona-rumi.dtb \
         kona-v2.1-cdp.dtb \
         kona-v2.1-qrd.dtb \
         kona-v2.1-hdk.dtb \
-	kona-v2.1-xrfusion.dtb \
-	kona-v2.1-xrfusion-ult.dtb \
+        kona-v2.1-xrfusion.dtb \
+        kona-v2.1-xrfusion-ult.dtb \
+        kona-v2.1-arglass.dtb \
         qrb5165-iot-rb5.dtb \
+        qrb5165n-iot-rb5.dtb \
         kona-v2.1-iot-rb5.dtb
 endif
 
@@ -186,7 +195,8 @@ dtb-$(CONFIG_ARCH_BENGAL) += bengal-rumi.dtb \
 		bengal-iot-idp-usbc.dtb \
 		bengalp-iot-idp-2gb.dtb \
 		bengalp-iot-idp-usbc-2gb.dtb \
-		bengalp-iot-idp-usbc.dtb
+		bengalp-iot-idp-usbc.dtb \
+		bengalp-iot-idp-2gb.dtb
 endif
 
 ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
@@ -231,6 +241,42 @@ dtb-$(CONFIG_ARCH_SCUBA) += scuba-rumi.dtb \
 endif
 
 ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
+        dtbo-$(CONFIG_ARCH_KHAJE) += \
+		khaje-idp-overlay.dtbo \
+		khaje-qrd-overlay.dtbo \
+		khaje-qrd-hvdcp3p5-overlay.dtbo \
+		khaje-qrd-nowcd9375-overlay.dtbo \
+		khaje-idp-nopmi-overlay.dtbo \
+		khaje-idp-usbc-overlay.dtbo \
+		khaje-idp-pm8010-overlay.dtbo \
+		khaje-qrd-nopmi-overlay.dtbo \
+		khaje-idps-display-90hz-overlay.dtbo \
+		khaje-atp-overlay.dtbo
+
+khaje-idp-overlay.dtbo-base := khaje.dtb
+khaje-qrd-overlay.dtbo-base := khaje.dtb
+khaje-qrd-hvdcp3p5-overlay.dtbo-base := khaje.dtb
+khaje-qrd-nowcd9375-overlay.dtbo-base := khaje.dtb
+khaje-idp-nopmi-overlay.dtbo-base := khaje.dtb
+khaje-idp-usbc-overlay.dtbo-base := khaje.dtb
+khaje-idp-pm8010-overlay.dtbo-base := khaje.dtb
+khaje-qrd-nopmi-overlay.dtbo-base := khaje.dtb
+khaje-idps-display-90hz-overlay.dtbo-base := khaje.dtb
+khaje-atp-overlay.dtbo-base := khaje.dtb
+else
+dtb-$(CONFIG_ARCH_KHAJE) += khaje-idp.dtb \
+		khaje-qrd.dtb \
+		khaje-qrd-hvdcp3p5.dtb \
+		khaje-qrd-nowcd9375.dtb \
+		khaje-idp-nopmi.dtb \
+		khaje-idp-usbc.dtb \
+		khaje-idp-pm8010.dtb \
+		khaje-qrd-nopmi.dtb \
+		khaje-idps-display-90hz.dtb \
+		khaje-atp.dtb
+endif
+
+ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
         dtbo-$(CONFIG_ARCH_SDM660) += \
                 sdm660-mtp-external-codec-overlay.dtbo \
                 sdm660-mtp-internal-codec-overlay.dtbo \
diff --git a/qcom/bengal-coresight.dtsi b/qcom/bengal-coresight.dtsi
index c5b6c25a..5bd4d1dd 100644
--- a/qcom/bengal-coresight.dtsi
+++ b/qcom/bengal-coresight.dtsi
@@ -1289,6 +1289,8 @@
 
 		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
 		clock-names = "apb_pclk";
+		coresight-ctis = <&cti0>;
+		coresight-csr = <&csr>;
 		ports {
 			#address-cells = <1>;
 			#size-cells = <0>;
diff --git a/qcom/bengal-pinctrl.dtsi b/qcom/bengal-pinctrl.dtsi
index 6b3126e2..b322d1af 100644
--- a/qcom/bengal-pinctrl.dtsi
+++ b/qcom/bengal-pinctrl.dtsi
@@ -1183,7 +1183,7 @@
 
 		pm8008_interrupt: pm8008_interrupt {
 			mux {
-				pins = "gpior25";
+				pins = "gpio25";
 				function = "gpio";
 			};
 
diff --git a/qcom/bengal-qrd-nopmi.dtsi b/qcom/bengal-qrd-nopmi.dtsi
new file mode 100644
index 00000000..413bac37
--- /dev/null
+++ b/qcom/bengal-qrd-nopmi.dtsi
@@ -0,0 +1,24 @@
+#include "bengal-qrd.dtsi"
+
+&led_flash_rear {
+	/delete-property/ flash-source;
+	/delete-property/ torch-source;
+	/delete-property/ switch-source;
+};
+
+&led_flash_rear_aux {
+	/delete-property/ flash-source;
+	/delete-property/ torch-source;
+	/delete-property/ switch-source;
+};
+
+&led_flash_rear_aux2 {
+	/delete-property/ flash-source;
+	/delete-property/ torch-source;
+	/delete-property/ switch-source;
+};
+
+&sde_dsi {
+	/delete-property/ lab-supply;
+	/delete-property/ ibb-supply;
+};
diff --git a/qcom/bengal-qrd-overlay.dts b/qcom/bengal-qrd-overlay.dts
index b2dff929..3d020cf5 100644
--- a/qcom/bengal-qrd-overlay.dts
+++ b/qcom/bengal-qrd-overlay.dts
@@ -1,8 +1,9 @@
 /dts-v1/;
 /plugin/;
 
-#include "bengal-pmi632.dtsi"
 #include "bengal-qrd.dtsi"
+#include "bengal-qrd-pmi632.dtsi"
+#include "bengal-thermal-pmi632-overlay.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. Bengal QRD";
diff --git a/qcom/bengal-qrd-pmi632.dtsi b/qcom/bengal-qrd-pmi632.dtsi
new file mode 100644
index 00000000..706b1f9c
--- /dev/null
+++ b/qcom/bengal-qrd-pmi632.dtsi
@@ -0,0 +1,94 @@
+#include "bengal-pmi632.dtsi"
+
+&soc {
+	qrd_batterydata: qcom,battery-data {
+		qcom,batt-id-range-pct = <15>;
+		#include "qg-batterydata-atl466271_3300mAh.dtsi"
+	};
+};
+
+&pmi632_qg {
+	qcom,battery-data = <&qrd_batterydata>;
+	qcom,qg-iterm-ma = <100>;
+	qcom,hold-soc-while-full;
+	qcom,linearize-soc;
+	qcom,qg-use-s7-ocv;
+};
+
+&pmi632_charger {
+	qcom,battery-data = <&qrd_batterydata>;
+	qcom,suspend-input-on-debug-batt;
+	qcom,sw-jeita-enable;
+	qcom,step-charging-enable;
+	/* SMB1355 only */
+	qcom,sec-charger-config = <2>;
+	qcom,hvdcp2-max-icl-ua = <2000000>;
+	dpdm-supply = <&qusb_phy0>;
+	qcom,charger-temp-max = <800>;
+	qcom,smb-temp-max = <800>;
+	qcom,auto-recharge-soc = <98>;
+	qcom,flash-disable-soc = <10>;
+	qcom,hw-die-temp-mitigation;
+	qcom,hw-connector-mitigation;
+	qcom,connector-internal-pull-kohm = <100>;
+	qcom,float-option = <1>;
+	qcom,thermal-mitigation = <4200000 3500000 3000000
+			2500000 2000000 1500000 1000000 500000>;
+};
+
+&pmi632_gpios {
+	smb_en {
+		smb_en_default: smb_en_default {
+			pins = "gpio2";
+			function = "func1";
+			output-enable;
+		};
+	};
+
+	pmi632_sense {
+		/* GPIO 7 and 8 are external-sense pins for PMI632 */
+		pmi632_sense_default: pmi632_sense_default {
+			pins = "gpio7", "gpio8";
+			bias-high-impedance;	/* disable the GPIO */
+			bias-disable;		/* no-pull */
+		};
+	};
+
+	pmi632_ctm {
+		/* Disable GPIO1 for h/w base mitigation */
+		pmi632_ctm_default: pmi632_ctm_default {
+			pins = "gpio1";
+			bias-high-impedance;	/* disable the GPIO */
+			bias-disable;		/* no-pull */
+		};
+	};
+};
+
+&usb0 {
+	extcon = <&pmi632_charger>, <&eud>;
+};
+
+&smb1355 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&smb_int_default>;
+	interrupt-parent = <&tlmm>;
+	interrupts = <105 IRQ_TYPE_LEVEL_LOW>;
+	status = "ok";
+};
+
+&smb1355_charger {
+	pinctrl-names = "default";
+	pinctrl-0 = <&smb_en_default &pmi632_sense_default &pmi632_ctm_default>;
+	qcom,parallel-mode = <1>;
+	qcom,disable-ctm;
+	qcom,hw-die-temp-mitigation;
+	status = "ok";
+};
+
+&dsi_td4330_truly_v2_video {
+	qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>;
+};
+
+&dsi_td4330_truly_v2_cmd {
+	qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>;
+};
diff --git a/qcom/bengal-qrd.dts b/qcom/bengal-qrd.dts
index d80d65e2..bb526083 100644
--- a/qcom/bengal-qrd.dts
+++ b/qcom/bengal-qrd.dts
@@ -1,8 +1,9 @@
 /dts-v1/;
 
 #include "bengal.dtsi"
-#include "bengal-pmi632.dtsi"
 #include "bengal-qrd.dtsi"
+#include "bengal-qrd-pmi632.dtsi"
+#include "bengal-thermal-pmi632-overlay.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. Bengal QRD";
diff --git a/qcom/bengal-qrd.dtsi b/qcom/bengal-qrd.dtsi
index 851535cf..2f457586 100644
--- a/qcom/bengal-qrd.dtsi
+++ b/qcom/bengal-qrd.dtsi
@@ -2,7 +2,6 @@
 #include <dt-bindings/iio/qcom,spmi-vadc.h>
 #include <dt-bindings/input/input.h>
 #include "bengal-thermal-overlay.dtsi"
-#include "bengal-thermal-pmi632-overlay.dtsi"
 #include "bengal-audio-overlay.dtsi"
 #include "bengal-sde-display.dtsi"
 #include "camera/bengal-camera-sensor-qrd.dtsi"
@@ -12,70 +11,6 @@
 	#include "smb1355.dtsi"
 };
 
-&soc {
-	qrd_batterydata: qcom,battery-data {
-		qcom,batt-id-range-pct = <15>;
-		#include "qg-batterydata-atl466271_3300mAh.dtsi"
-	};
-};
-
-&pmi632_qg {
-	qcom,battery-data = <&qrd_batterydata>;
-	qcom,qg-iterm-ma = <100>;
-	qcom,hold-soc-while-full;
-	qcom,linearize-soc;
-	qcom,qg-use-s7-ocv;
-};
-
-&pmi632_charger {
-	qcom,battery-data = <&qrd_batterydata>;
-	qcom,suspend-input-on-debug-batt;
-	qcom,sw-jeita-enable;
-	qcom,step-charging-enable;
-	/* SMB1355 only */
-	qcom,sec-charger-config = <2>;
-	qcom,hvdcp2-max-icl-ua = <2000000>;
-	dpdm-supply = <&qusb_phy0>;
-	qcom,charger-temp-max = <800>;
-	qcom,smb-temp-max = <800>;
-	qcom,auto-recharge-soc = <98>;
-	qcom,flash-disable-soc = <10>;
-	qcom,hw-die-temp-mitigation;
-	qcom,hw-connector-mitigation;
-	qcom,connector-internal-pull-kohm = <100>;
-	qcom,float-option = <1>;
-	qcom,thermal-mitigation = <4200000 3500000 3000000
-			2500000 2000000 1500000 1000000 500000>;
-};
-
-&pmi632_gpios {
-	smb_en {
-		smb_en_default: smb_en_default {
-			pins = "gpio2";
-			function = "func1";
-			output-enable;
-		};
-	};
-
-	pmi632_sense {
-		/* GPIO 7 and 8 are external-sense pins for PMI632 */
-		pmi632_sense_default: pmi632_sense_default {
-			pins = "gpio7", "gpio8";
-			bias-high-impedance;	/* disable the GPIO */
-			bias-disable;		/* no-pull */
-		};
-	};
-
-	pmi632_ctm {
-		/* Disable GPIO1 for h/w base mitigation */
-		pmi632_ctm_default: pmi632_ctm_default {
-			pins = "gpio1";
-			bias-high-impedance;	/* disable the GPIO */
-			bias-disable;		/* no-pull */
-		};
-	};
-};
-
 &pm6125_gpios {
 	key_vol_up {
 		key_vol_up_default: key_vol_up_default {
@@ -88,10 +23,6 @@
 	};
 };
 
-&usb0 {
-	extcon = <&pmi632_charger>, <&eud>;
-};
-
 &qusb_phy0 {
 	qcom,qusb-phy-init-seq = <0xf8 0x80
 				0xb3 0x84
@@ -261,23 +192,6 @@
 	};
 };
 
-&smb1355 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&smb_int_default>;
-	interrupt-parent = <&tlmm>;
-	interrupts = <105 IRQ_TYPE_LEVEL_LOW>;
-	status = "ok";
-};
-
-&smb1355_charger {
-	pinctrl-names = "default";
-	pinctrl-0 = <&smb_en_default &pmi632_sense_default &pmi632_ctm_default>;
-	qcom,parallel-mode = <1>;
-	qcom,disable-ctm;
-	qcom,hw-die-temp-mitigation;
-	status = "ok";
-};
-
 &ufsphy_mem {
 	compatible = "qcom,ufs-phy-qmp-v3-660";
 
@@ -319,7 +233,6 @@
 	qcom,mdss-dsi-bl-min-level = <1>;
 	qcom,mdss-dsi-bl-max-level = <4095>;
 	qcom,platform-reset-gpio = <&tlmm 82 0>;
-	qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>;
 };
 
 &dsi_td4330_truly_v2_cmd {
@@ -331,7 +244,6 @@
 	qcom,mdss-dsi-bl-max-level = <4095>;
 	qcom,platform-te-gpio = <&tlmm 81 0>;
 	qcom,platform-reset-gpio = <&tlmm 82 0>;
-	qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>;
 };
 
 &sde_dsi {
diff --git a/qcom/bengal-thermal.dtsi b/qcom/bengal-thermal.dtsi
index 8f0ba2c0..0cc49b16 100644
--- a/qcom/bengal-thermal.dtsi
+++ b/qcom/bengal-thermal.dtsi
@@ -957,6 +957,30 @@
 		};
 	};
 
+	mapss-lowc {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "low_limits_cap";
+		thermal-sensors = <&tsens0 0>;
+		wake-capable-sensor;
+		tracks-low;
+
+		trips {
+			mapss_cap_trip: mapss-cap-trip {
+				temperature = <5000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			lmh_cpu_cdev {
+				trip = <&mapss_cap_trip>;
+				cooling-device = <&lmh_cpu_vdd 1 1>;
+			};
+		};
+	};
+
 	mapss-lowf {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
@@ -996,16 +1020,16 @@
 		};
 	};
 
-	mapss-lowc {
+	camera-lowc {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-governor = "low_limits_cap";
-		thermal-sensors = <&tsens0 0>;
+		thermal-sensors = <&tsens0 3>;
 		wake-capable-sensor;
 		tracks-low;
 
 		trips {
-			mapss_cap_trip: mapss-cap-trip {
+			camera_cap_trip: camera-cap-trip {
 				temperature = <5000>;
 				hysteresis = <5000>;
 				type = "passive";
@@ -1014,7 +1038,7 @@
 
 		cooling-maps {
 			lmh_cpu_cdev {
-				trip = <&mapss_cap_trip>;
+				trip = <&camera_cap_trip>;
 				cooling-device = <&lmh_cpu_vdd 1 1>;
 			};
 		};
@@ -1059,30 +1083,6 @@
 		};
 	};
 
-	camera-lowc {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-governor = "low_limits_cap";
-		thermal-sensors = <&tsens0 3>;
-		wake-capable-sensor;
-		tracks-low;
-
-		trips {
-			camera_cap_trip: camera-cap-trip {
-				temperature = <5000>;
-				hysteresis = <5000>;
-				type = "passive";
-			};
-		};
-
-		cooling-maps {
-			lmh_cpu_cdev {
-				trip = <&camera_cap_trip>;
-				cooling-device = <&lmh_cpu_vdd 1 1>;
-			};
-		};
-	};
-
 	quiet-therm-step {
 		polling-delay-passive = <2000>;
 		polling-delay = <0>;
diff --git a/qcom/bengal-usb.dtsi b/qcom/bengal-usb.dtsi
index f079a776..f3f2d38b 100644
--- a/qcom/bengal-usb.dtsi
+++ b/qcom/bengal-usb.dtsi
@@ -88,6 +88,7 @@
 			snps,dis_enblslpm_quirk;
 			snps,has-lpm-erratum;
 			snps,hird-threshold = /bits/ 8 <0x10>;
+			snps,usb3-u1u2-disable;
 			snps,usb3_lpm_capable;
 			usb-core-id = <0>;
 			maximum-speed = "super-speed";
diff --git a/qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi b/qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi
new file mode 100644
index 00000000..4525814b
--- /dev/null
+++ b/qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi
@@ -0,0 +1,100 @@
+&mdss_mdp {
+	dsi_dual_arglass_seeya_video: qcom,mdss_dsi_arglass_seeya_video {
+	qcom,mdss-dsi-panel-name =
+		"sy049wdm02 uoled video mode dsi seeya panel with DSC";
+	qcom,mdss-dsi-panel-type = "dsi_video_mode";
+	qcom,dsi-ctrl-num = <0 1>;
+	qcom,dsi-phy-num = <0 1>;
+
+	qcom,mdss-dsi-virtual-channel-id = <0>;
+	qcom,mdss-dsi-stream = <0>;
+	qcom,mdss-dsi-bpp = <24>;
+	qcom,mdss-dsi-border-color = <0>;
+	qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+	qcom,mdss-dsi-bllp-eof-power-mode;
+	qcom,mdss-dsi-bllp-power-mode;
+	qcom,mdss-dsi-lane-0-state;
+	qcom,mdss-dsi-lane-1-state;
+	qcom,mdss-dsi-lane-2-state;
+	qcom,mdss-dsi-lane-3-state;
+	qcom,mdss-dsi-dma-trigger = "trigger_sw";
+	qcom,mdss-dsi-mdp-trigger = "none";
+	qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 50>;
+	qcom,adjust-timer-wakeup-ms = <1>;
+	qcom,mdss-dsi-panel-hdr-enabled;
+	qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+		17000 15500 30000 8000 3000>;
+	qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+	qcom,mdss-dsi-panel-blackness-level = <3230>;
+
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-width = <1920>;
+			qcom,mdss-dsi-panel-height = <1080>;
+			qcom,mdss-dsi-h-front-porch = <88>;
+			qcom,mdss-dsi-h-back-porch = <148>;
+			qcom,mdss-dsi-h-pulse-width = <44>;
+			qcom,mdss-dsi-h-sync-skew = <0>;
+			qcom,mdss-dsi-v-back-porch = <36>;
+			qcom,mdss-dsi-v-front-porch = <5>;
+			qcom,mdss-dsi-v-pulse-width = <5>;
+			qcom,mdss-dsi-h-left-border = <0>;
+			qcom,mdss-dsi-panel-framerate = <60>;
+			qcom,mdss-dsi-on-command = [
+				39 01 00 00 00 00 02 53 29
+				39 01 00 00 00 00 03 51 FF 01
+				39 01 00 00 00 00 02 03 00
+				39 01 00 00 00 00 07 80 00 E0 E0 0E 00 31
+				39 01 00 00 00 00 08 81 03 04 00 29 00 05 00
+				39 01 00 00 00 00 08 82 03 04 00 29 00 05 01
+				39 01 00 00 00 00 02 35 00
+				39 01 00 00 00 00 02 26 20
+				/* CMD2 P1 */
+				39 01 00 00 00 00 03 F0 AA 11
+				39 01 00 00 00 00 02 C0 00
+				39 01 00 00 00 00 0C C2 03 FF 03 FF 03 FF 03 FF 82 00 00
+				/* CMD2 P2 */
+				39 01 00 00 00 00 03 F0 AA 12
+				39 01 00 00 00 00 03 BF 37 A9
+				/* H mirror dsi1 */
+				39 01 00 00 00 00 03 FF 5A 80
+				39 01 00 00 00 00 02 65 2F
+				39 01 00 00 00 00 02 F2 01
+				39 01 00 00 00 00 02 36 02
+				/* V mirror dsi0 */
+				39 01 00 04 00 00 03 FF 5A 80
+				39 01 00 04 00 00 02 65 2F
+				39 01 00 04 00 00 02 F2 01
+				39 01 00 04 00 00 02 36 01
+				39 01 00 04 00 00 03 F0 AA 13
+				39 01 00 04 00 00 02 65 01
+				39 01 00 04 00 00 02 C1 A2
+				39 01 00 04 00 00 07 C4 12 53 64 31 42 56
+				39 01 00 04 00 00 03 F0 AA 16
+				39 01 00 04 00 00 07 B6 12 53 64 31 42 56
+				39 01 00 04 00 00 03 B0 00 55
+				/* CMD3 P0 */
+				39 01 00 00 00 00 03 FF 5A 80
+				39 01 00 00 00 00 02 65 2F
+				39 01 00 00 00 00 02 F2 01
+				/* CMD3 P1 */
+				39 01 00 00 00 00 03 FF 5A 81
+				39 01 00 00 00 00 02 65 05
+				39 01 00 00 00 00 02 F2 22
+				39 01 00 00 00 00 02 65 0A
+				39 01 00 00 00 00 02 F2 00
+				39 01 00 00 00 00 02 65 16
+				39 01 00 00 00 00 0F F9 01 5F 61 64 67 6A 6D 6F 75 7B 80 86 8B 91
+				05 01 00 00 cb 00 02 11 00
+				05 01 00 00 00 00 02 29 00
+				39 01 00 00 00 00 03 F0 AA 11
+			];
+			qcom,mdss-dsi-off-command = [05 01 00 00 0a 00
+				02 28 00 05 01 00 00 3c 00 02 10 00];
+
+			qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+			qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+			};
+		};
+	};
+};
diff --git a/qcom/dsi-panel-nt36672e-fhd-plus-120hz-video.dtsi b/qcom/dsi-panel-nt36672e-fhd-plus-120hz-video.dtsi
new file mode 100644
index 00000000..26624076
--- /dev/null
+++ b/qcom/dsi-panel-nt36672e-fhd-plus-120hz-video.dtsi
@@ -0,0 +1,334 @@
+&mdss_mdp {
+	dsi_nt36672e_fhd_plus_120hz_video: qcom,mdss_dsi_nt36672e_fhd_plus_120hz_video {
+		qcom,mdss-dsi-panel-name =
+			"nt36672e fhd plus 120Hz Video panel";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,dsi-ctrl-num = <0>;
+		qcom,dsi-phy-num = <0>;
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-traffic-mode = "burst_mode";
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-dsi-tx-eot-append;
+		qcom,adjust-timer-wakeup-ms = <1>;
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750
+						 15800 13250 34450 7500 3000>;
+		qcom,mdss-dsi-panel-peak-brightness = <6450000>;
+		qcom,mdss-dsi-panel-blackness-level = <4961>;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0 {
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <2408>;
+				qcom,mdss-dsi-h-front-porch = <76>;
+				qcom,mdss-dsi-h-back-porch = <60>;
+				qcom,mdss-dsi-h-pulse-width = <10>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <10>;
+				qcom,mdss-dsi-v-front-porch = <46>;
+				qcom,mdss-dsi-v-pulse-width = <10>;
+				qcom,mdss-dsi-panel-framerate = <120>;
+				qcom,mdss-dsi-on-command = [
+					15 01 00 00 00 00 02 FB 01
+					15 01 00 00 00 00 02 B0 00
+					15 01 00 00 00 00 02 C0 03
+					39 01 00 00 00 00 11 C1 89 28 00 08 00 AA 02 0E 00 2B 00 07
+											 0D B7 0C B7
+					39 01 00 00 00 00 03 C2 1B A0
+					15 01 00 00 00 00 02 FF 20
+					15 01 00 00 00 00 02 FB 01
+					15 01 00 00 00 00 02 01 66
+					15 01 00 00 00 00 02 06 40
+					15 01 00 00 00 00 02 07 38
+					15 01 00 00 00 00 02 2F 83
+					15 01 00 00 00 00 02 69 91
+					15 01 00 00 00 00 02 95 D1
+					15 01 00 00 00 00 02 96 D1
+					15 01 00 00 00 00 02 F2 64
+					15 01 00 00 00 00 02 F4 64
+					15 01 00 00 00 00 02 F6 64
+					15 01 00 00 00 00 02 F8 64
+
+					15 01 00 00 00 00 02 89 1C
+					15 01 00 00 00 00 02 8A 1C
+					15 01 00 00 00 00 02 8B 1C
+					15 01 00 00 00 00 02 8C 1C
+
+					15 01 00 00 00 00 02 FF 24
+					15 01 00 00 00 00 02 FB 01
+					15 01 00 00 00 00 02 01 0F
+					15 01 00 00 00 00 02 03 0C
+					15 01 00 00 00 00 02 05 1D
+
+					15 01 00 00 00 00 02 08 2F
+					15 01 00 00 00 00 02 09 2E
+					15 01 00 00 00 00 02 0A 2D
+					15 01 00 00 00 00 02 0B 2C
+
+					15 01 00 00 00 00 02 11 17
+					15 01 00 00 00 00 02 12 13
+					15 01 00 00 00 00 02 13 15
+					15 01 00 00 00 00 02 15 14
+					15 01 00 00 00 00 02 16 16
+					15 01 00 00 00 00 02 17 18
+					15 01 00 00 00 00 02 1B 01
+					15 01 00 00 00 00 02 1D 1D
+
+					15 01 00 00 00 00 02 20 2F
+					15 01 00 00 00 00 02 21 2E
+					15 01 00 00 00 00 02 22 2D
+					15 01 00 00 00 00 02 23 2C
+
+					15 01 00 00 00 00 02 29 17
+					15 01 00 00 00 00 02 2A 13
+					15 01 00 00 00 00 02 2B 15
+					15 01 00 00 00 00 02 2F 14
+					15 01 00 00 00 00 02 30 16
+					15 01 00 00 00 00 02 31 18
+					15 01 00 00 00 00 02 32 04
+					15 01 00 00 00 00 02 34 10
+					15 01 00 00 00 00 02 35 1F
+					15 01 00 00 00 00 02 36 1F
+					15 01 00 00 00 00 02 4D 14
+					15 01 00 00 00 00 02 4E 36
+					15 01 00 00 00 00 02 4F 36
+					15 01 00 00 00 00 02 53 36
+					15 01 00 00 00 00 02 71 30
+					15 01 00 00 00 00 02 79 11
+					15 01 00 00 00 00 02 7A 82
+					15 01 00 00 00 00 02 7B 8F
+					15 01 00 00 00 00 02 7D 04
+					15 01 00 00 00 00 02 80 04
+					15 01 00 00 00 00 02 81 04
+					15 01 00 00 00 00 02 82 13
+					15 01 00 00 00 00 02 84 31
+					15 01 00 00 00 00 02 85 00
+					15 01 00 00 00 00 02 86 00
+					15 01 00 00 00 00 02 87 00
+
+					15 01 00 00 00 00 02 90 13
+					15 01 00 00 00 00 02 92 31
+					15 01 00 00 00 00 02 93 00
+					15 01 00 00 00 00 02 94 00
+					15 01 00 00 00 00 02 95 00
+					15 01 00 00 00 00 02 9C F4
+					15 01 00 00 00 00 02 9D 01
+					15 01 00 00 00 00 02 A0 0F
+					15 01 00 00 00 00 02 A2 0F
+					15 01 00 00 00 00 02 A3 02
+					15 01 00 00 00 00 02 A4 04
+					15 01 00 00 00 00 02 A5 04
+					15 01 00 00 00 00 02 C4 40
+					15 01 00 00 00 00 02 C6 C0
+					15 01 00 00 00 00 02 C9 00
+					15 01 00 00 00 00 02 D9 80
+					15 01 00 00 00 00 02 E9 02
+
+					15 01 00 00 00 00 02 FF 25
+					15 01 00 00 00 00 02 FB 01
+					15 01 00 00 00 00 02 19 E4
+					15 01 00 00 00 00 02 21 40
+					15 01 00 00 00 00 02 66 D8
+					15 01 00 00 00 00 02 68 50
+					15 01 00 00 00 00 02 69 10
+					15 01 00 00 00 00 02 6B 00
+					15 01 00 00 00 00 02 6D 0D
+					15 01 00 00 00 00 02 6E 48
+
+					15 01 00 00 00 00 02 72 41
+					15 01 00 00 00 00 02 73 4A
+					15 01 00 00 00 00 02 74 D0
+					15 01 00 00 00 00 02 77 62
+					15 01 00 00 00 00 02 79 81
+					15 01 00 00 00 00 02 7D 03
+					15 01 00 00 00 00 02 7E 15
+					15 01 00 00 00 00 02 7F 00
+					15 01 00 00 00 00 02 84 4D
+					15 01 00 00 00 00 02 CF 80
+					15 01 00 00 00 00 02 D6 80
+					15 01 00 00 00 00 02 D7 80
+					15 01 00 00 00 00 02 EF 20
+					15 01 00 00 00 00 02 F0 84
+
+					15 01 00 00 00 00 02 FF 26
+					15 01 00 00 00 00 02 FB 01
+					15 01 00 00 00 00 02 80 05
+					15 01 00 00 00 00 02 81 0F
+					15 01 00 00 00 00 02 83 01
+					15 01 00 00 00 00 02 84 03
+					15 01 00 00 00 00 02 85 01
+					15 01 00 00 00 00 02 86 03
+					15 01 00 00 00 00 02 87 01
+					15 01 00 00 00 00 02 88 05
+					15 01 00 00 00 00 02 8A 1A
+					15 01 00 00 00 00 02 8B 11
+					15 01 00 00 00 00 02 8C 24
+					15 01 00 00 00 00 02 8E 42
+					15 01 00 00 00 00 02 8F 11
+					15 01 00 00 00 00 02 90 11
+					15 01 00 00 00 00 02 91 11
+					15 01 00 00 00 00 02 9A 80
+					15 01 00 00 00 00 02 9B 04
+					15 01 00 00 00 00 02 9C 00
+					15 01 00 00 00 00 02 9D 00
+					15 01 00 00 00 00 02 9E 00
+
+					15 01 00 00 00 00 02 FF 27
+					15 01 00 00 00 00 02 FB 01
+					15 01 00 00 00 00 02 01 68
+					15 01 00 00 00 00 02 20 81
+					15 01 00 00 00 00 02 21 6A
+					15 01 00 00 00 00 02 25 81
+					15 01 00 00 00 00 02 26 94
+					15 01 00 00 00 00 02 6E 00
+					15 01 00 00 00 00 02 6F 00
+					15 01 00 00 00 00 02 70 00
+					15 01 00 00 00 00 02 71 00
+					15 01 00 00 00 00 02 72 00
+					15 01 00 00 00 00 02 75 00
+					15 01 00 00 00 00 02 76 00
+					15 01 00 00 00 00 02 77 00
+					15 01 00 00 00 00 02 7D 09
+					15 01 00 00 00 00 02 7E 67
+					15 01 00 00 00 00 02 80 23
+					15 01 00 00 00 00 02 82 09
+					15 01 00 00 00 00 02 83 67
+					15 01 00 00 00 00 02 88 01
+					15 01 00 00 00 00 02 89 10
+					15 01 00 00 00 00 02 A5 10
+					15 01 00 00 00 00 02 A6 23
+					15 01 00 00 00 00 02 A7 01
+					15 01 00 00 00 00 02 B6 40
+
+					15 01 00 00 00 00 02 FF 2A
+					15 01 00 00 00 00 02 FB 01
+					15 01 00 00 00 00 02 00 91
+					15 01 00 00 00 00 02 03 20
+					15 01 00 00 00 00 02 07 50
+					15 01 00 00 00 00 02 0A 70
+					15 01 00 00 00 00 02 0C 04
+					15 01 00 00 00 00 02 0D 40
+					15 01 00 00 00 00 02 0F 01
+					15 01 00 00 00 00 02 11 E0
+					15 01 00 00 00 00 02 15 0F
+					15 01 00 00 00 00 02 16 A4
+					15 01 00 00 00 00 02 19 0F
+					15 01 00 00 00 00 02 1A 78
+					15 01 00 00 00 00 02 1B 23
+					15 01 00 00 00 00 02 1D 36
+					15 01 00 00 00 00 02 1E 3E
+					15 01 00 00 00 00 02 1F 3E
+					15 01 00 00 00 00 02 20 3E
+					15 01 00 00 00 00 02 28 FD
+					15 01 00 00 00 00 02 29 12
+					15 01 00 00 00 00 02 2A E1
+					15 01 00 00 00 00 02 2D 0A
+					15 01 00 00 00 00 02 30 49
+					15 01 00 00 00 00 02 33 96
+					15 01 00 00 00 00 02 34 FF
+					15 01 00 00 00 00 02 35 40
+					15 01 00 00 00 00 02 36 DE
+					15 01 00 00 00 00 02 37 F9
+					15 01 00 00 00 00 02 38 45
+					15 01 00 00 00 00 02 39 D9
+					15 01 00 00 00 00 02 3A 49
+					15 01 00 00 00 00 02 4A F0
+
+					15 01 00 00 00 00 02 FF 20
+					15 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 11 B0 00 00 00 17 00 46 00 63 00 81 00 96
+										 00 AB 00 BD
+					39 01 00 00 00 00 11 B1 00 CF 01 03 01 2F 01 6E 01 9D 01 E7
+										 02 22 02 24
+					39 01 00 00 00 00 11 B2 02 5D 02 9B 02 C4 02 F9 03 1B 03 48
+										 03 56 03 65
+					39 01 00 00 00 00 0F B3 03 75 03 87 03 9B 03 B1 03 CA 03 D7
+										 00 00
+					39 01 00 00 00 00 11 B4 00 00 00 19 00 4B 00 69 00 87 00 9C
+										 00 B2 00 C3
+					39 01 00 00 00 00 11 B5 00 D5 01 0B 01 35 01 73 01 A3 01 EC
+										 02 27 02 29
+					39 01 00 00 00 00 11 B6 02 60 02 9F 02 C7 02 FB 03 1D 03 4C
+										 03 5A 03 69
+					39 01 00 00 00 00 0F B7 03 7A 03 8C 03 A0 03 B5 03 CB 03 D7
+										 00 00
+					39 01 00 00 00 00 11 B8 00 00 00 19 00 4D 00 6A 00 87 00 9C
+										 00 B1 00 C2
+					39 01 00 00 00 00 11 B9 00 D3 01 08 01 32 01 70 01 9F 01 E8
+										 02 23 02 25
+					39 01 00 00 00 00 11 BA 02 5C 02 9B 02 C3 02 F8 03 1A 03 4C
+										 03 5B 03 6B
+					39 01 00 00 00 00 0F BB 03 7D 03 92 03 A7 03 BB 03 CE 03 D7
+										 00 00
+
+					15 01 00 00 00 00 02 FF 21
+					15 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 11 B0 00 00 00 17 00 46 00 63 00 81 00 96
+										 00 AB 00 BD
+					39 01 00 00 00 00 11 B1 00 CF 01 03 01 2F 01 6E 01 9D 01 E7
+										 02 22 02 24
+					39 01 00 00 00 00 11 B2 02 5D 02 9B 02 C4 02 F9 03 1B 03 48
+										 03 56 03 65
+					39 01 00 00 00 00 0F B3 03 75 03 87 03 9B 03 B1 03 CA 03 D7
+										 00 00
+					39 01 00 00 00 00 11 B4 00 00 00 19 00 4B 00 69 00 87 00 9C
+										 00 B2 00 C3
+					39 01 00 00 00 00 11 B5 00 D5 01 0B 01 35 01 73 01 A3 01 EC
+										 02 27 02 29
+					39 01 00 00 00 00 11 B6 02 60 02 9F 02 C7 02 FB 03 1D 03 4C
+										 03 5A 03 69
+					39 01 00 00 00 00 0F B7 03 7A 03 8C 03 A0 03 B5 03 CB 03 D7
+										 00 00
+					39 01 00 00 00 00 11 B8 00 00 00 19 00 4D 00 6A 00 87 00 9C
+										 00 B1 00 C2
+					39 01 00 00 00 00 11 B9 00 D3 01 08 01 32 01 70 01 9F 01 E8
+										 02 23 02 25
+					39 01 00 00 00 00 11 BA 02 5C 02 9B 02 C3 02 F8 03 1A 03 4C
+										 03 5B 03 6B
+					39 01 00 00 00 00 0F BB 03 7D 03 92 03 A7 03 BB 03 CE 03 D7
+										 00 00
+
+					15 01 00 00 00 00 02 FF 10
+					15 01 00 00 00 00 02 FF F0
+					15 01 00 00 00 00 02 FB 01
+					15 01 00 00 00 00 02 5A 00
+					15 01 00 00 00 00 02 FF 10
+
+					15 01 00 00 00 00 02 FF 10
+					15 01 00 00 00 00 02 FB 01
+
+					15 01 00 00 00 00 02 51 FF   //CABC
+					15 01 00 00 00 00 02 53 2C
+					15 01 00 00 00 00 02 55 01
+
+					05 01 00 00 C8 00 01 11
+					05 01 00 00 96 00 01 29
+				];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command = [
+					05 01 00 00 10 00 01 28
+					05 01 00 00 32 00 01 10
+				];
+				qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+				qcom,compression-mode = "dsc";
+				qcom,mdss-dsc-slice-height = <8>;
+				qcom,mdss-dsc-slice-width = <540>;
+				qcom,mdss-dsc-slice-per-pkt = <1>;
+				qcom,mdss-dsc-bit-per-component = <8>;
+				qcom,mdss-dsc-bit-per-pixel = <8>;
+				qcom,mdss-dsc-block-prediction-enable;
+			};
+		};
+	};
+};
diff --git a/qcom/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi b/qcom/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi
new file mode 100644
index 00000000..92f70b56
--- /dev/null
+++ b/qcom/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi
@@ -0,0 +1,312 @@
+&mdss_mdp {
+	dsi_nt36672e_fhd_plus_60_video: qcom,mdss_dsi_nt36672e_fhd_plus_60_video {
+		qcom,mdss-dsi-panel-name =
+			"nt36672e 60 Hz fhd plus video mode panel without DSC";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,dsi-ctrl-num = <0>;
+		qcom,dsi-phy-num = <0>;
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-traffic-mode = "burst_mode";
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-dsi-tx-eot-append;
+		qcom,adjust-timer-wakeup-ms = <1>;
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <39000 16000 33750
+						 39800 13250 34450 7500 3000>;
+		qcom,mdss-dsi-panel-peak-brightness = <6450000>;
+		qcom,mdss-dsi-panel-blackness-level = <4961>;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0 {
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <2408>;
+				qcom,mdss-dsi-h-front-porch = <76>;
+				qcom,mdss-dsi-h-back-porch = <56>;
+				qcom,mdss-dsi-h-pulse-width = <12>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <10>;
+				qcom,mdss-dsi-v-front-porch = <46>;
+				qcom,mdss-dsi-v-pulse-width = <10>;
+				qcom,mdss-dsi-panel-framerate = <60>;
+				qcom,mdss-dsi-on-command = [
+					39 01 00 00 00 00 02 FF 10
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 B0 00
+					39 01 00 00 00 00 02 C0 00
+					39 01 00 00 00 00 11 C1 89 28 00 08 00 AA 02 0E 00 2B 00 07 0D B7 0C B7
+					39 01 00 00 00 00 03 C2 1B A0
+					39 01 00 00 00 00 02 FF 20
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 01 66
+					39 01 00 00 00 00 02 06 40
+					39 01 00 00 00 00 02 07 38
+					39 01 00 00 00 00 02 2F 83
+					39 01 00 00 00 00 02 69 91
+					39 01 00 00 00 00 02 95 D1
+					39 01 00 00 00 00 02 96 D1
+					39 01 00 00 00 00 02 F2 64
+					39 01 00 00 00 00 02 F3 54
+					39 01 00 00 00 00 02 F4 64
+					39 01 00 00 00 00 02 F5 54
+					39 01 00 00 00 00 02 F6 64
+					39 01 00 00 00 00 02 F7 54
+					39 01 00 00 00 00 02 F8 64
+					39 01 00 00 00 00 02 F9 54
+					39 01 00 00 00 00 02 FF 24
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 01 0F
+					39 01 00 00 00 00 02 03 0C
+					39 01 00 00 00 00 02 05 1D
+					39 01 00 00 00 00 02 08 2F
+					39 01 00 00 00 00 02 09 2E
+					39 01 00 00 00 00 02 0A 2D
+					39 01 00 00 00 00 02 0B 2C
+					39 01 00 00 00 00 02 11 17
+					39 01 00 00 00 00 02 12 13
+					39 01 00 00 00 00 02 13 15
+					39 01 00 00 00 00 02 15 14
+					39 01 00 00 00 00 02 16 16
+					39 01 00 00 00 00 02 17 18
+					39 01 00 00 00 00 02 1B 01
+					39 01 00 00 00 00 02 1D 1D
+					39 01 00 00 00 00 02 20 2F
+					39 01 00 00 00 00 02 21 2E
+					39 01 00 00 00 00 02 22 2D
+					39 01 00 00 00 00 02 23 2C
+					39 01 00 00 00 00 02 29 17
+					39 01 00 00 00 00 02 2A 13
+					39 01 00 00 00 00 02 2B 15
+					39 01 00 00 00 00 02 2F 14
+					39 01 00 00 00 00 02 30 16
+					39 01 00 00 00 00 02 31 18
+					39 01 00 00 00 00 02 32 04
+					39 01 00 00 00 00 02 34 10
+					39 01 00 00 00 00 02 35 1F
+					39 01 00 00 00 00 02 36 1F
+					39 01 00 00 00 00 02 4D 14
+					39 01 00 00 00 00 02 4E 36
+					39 01 00 00 00 00 02 4F 36
+					39 01 00 00 00 00 02 53 36
+					39 01 00 00 00 00 02 71 30
+					39 01 00 00 00 00 02 79 11
+					39 01 00 00 00 00 02 7A 82
+					39 01 00 00 00 00 02 7B 8F
+					39 01 00 00 00 00 02 7D 04
+					39 01 00 00 00 00 02 80 04
+					39 01 00 00 00 00 02 81 04
+					39 01 00 00 00 00 02 82 13
+					39 01 00 00 00 00 02 84 31
+					39 01 00 00 00 00 02 85 00
+					39 01 00 00 00 00 02 86 00
+					39 01 00 00 00 00 02 87 00
+					39 01 00 00 00 00 02 90 13
+					39 01 00 00 00 00 02 92 31
+					39 01 00 00 00 00 02 93 00
+					39 01 00 00 00 00 02 94 00
+					39 01 00 00 00 00 02 95 00
+					39 01 00 00 00 00 02 9C F4
+					39 01 00 00 00 00 02 9D 01
+					39 01 00 00 00 00 02 A0 0F
+					39 01 00 00 00 00 02 A2 0F
+					39 01 00 00 00 00 02 A3 02
+					39 01 00 00 00 00 02 A4 04
+					39 01 00 00 00 00 02 A5 04
+					39 01 00 00 00 00 02 C6 C0
+					39 01 00 00 00 00 02 C9 00
+					39 01 00 00 00 00 02 D9 80
+					39 01 00 00 00 00 02 E9 02
+					39 01 00 00 00 00 02 FF 25
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 18 22
+					39 01 00 00 00 00 02 19 E4
+					39 01 00 00 00 00 02 21 40
+					39 01 00 00 00 00 02 66 D8
+					39 01 00 00 00 00 02 68 50
+					39 01 00 00 00 00 02 69 10
+					39 01 00 00 00 00 02 6B 00
+					39 01 00 00 00 00 02 6D 0D
+					39 01 00 00 00 00 02 6E 48
+					39 01 00 00 00 00 02 72 41
+					39 01 00 00 00 00 02 73 4A
+					39 01 00 00 00 00 02 74 D0
+					39 01 00 00 00 00 02 77 62
+					39 01 00 00 00 00 02 79 7E
+					39 01 00 00 00 00 02 7D 03
+					39 01 00 00 00 00 02 7E 15
+					39 01 00 00 00 00 02 7F 00
+					39 01 00 00 00 00 02 84 4D
+					39 01 00 00 00 00 02 CF 80
+					39 01 00 00 00 00 02 D6 80
+					39 01 00 00 00 00 02 D7 80
+					39 01 00 00 00 00 02 EF 20
+					39 01 00 00 00 00 02 F0 84
+					39 01 00 00 00 00 02 FF 26
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 81 0F
+					39 01 00 00 00 00 02 83 01
+					39 01 00 00 00 00 02 84 03
+					39 01 00 00 00 00 02 85 01
+					39 01 00 00 00 00 02 86 03
+					39 01 00 00 00 00 02 87 01
+					39 01 00 00 00 00 02 88 05
+					39 01 00 00 00 00 02 8A 1A
+					39 01 00 00 00 00 02 8B 11
+					39 01 00 00 00 00 02 8C 24
+					39 01 00 00 00 00 02 8E 42
+					39 01 00 00 00 00 02 8F 11
+					39 01 00 00 00 00 02 90 11
+					39 01 00 00 00 00 02 91 11
+					39 01 00 00 00 00 02 9A 80
+					39 01 00 00 00 00 02 9B 04
+					39 01 00 00 00 00 02 9C 00
+					39 01 00 00 00 00 02 9D 00
+					39 01 00 00 00 00 02 9E 00
+					39 01 00 00 00 00 02 FF 27
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 01 68
+					39 01 00 00 00 00 02 20 81
+					39 01 00 00 00 00 02 21 6A
+					39 01 00 00 00 00 02 25 81
+					39 01 00 00 00 00 02 26 94
+					39 01 00 00 00 00 02 6E 00
+					39 01 00 00 00 00 02 6F 00
+					39 01 00 00 00 00 02 70 00
+					39 01 00 00 00 00 02 71 00
+					39 01 00 00 00 00 02 72 00
+					39 01 00 00 00 00 02 75 00
+					39 01 00 00 00 00 02 76 00
+					39 01 00 00 00 00 02 77 00
+					39 01 00 00 00 00 02 7D 09
+					39 01 00 00 00 00 02 7E 67
+					39 01 00 00 00 00 02 80 23
+					39 01 00 00 00 00 02 82 09
+					39 01 00 00 00 00 02 83 67
+					39 01 00 00 00 00 02 88 01
+					39 01 00 00 00 00 02 89 10
+					39 01 00 00 00 00 02 A5 10
+					39 01 00 00 00 00 02 A6 23
+					39 01 00 00 00 00 02 A7 01
+					39 01 00 00 00 00 02 B6 40
+					39 01 00 00 00 00 02 E5 02
+					39 01 00 00 00 00 02 E6 D3
+					39 01 00 00 00 00 02 EB 03
+					39 01 00 00 00 00 02 EC 28
+					39 01 00 00 00 00 02 FF 2A
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 00 91
+					39 01 00 00 00 00 02 03 20
+					39 01 00 00 00 00 02 07 50
+					39 01 00 00 00 00 02 0A 70
+					39 01 00 00 00 00 02 0C 04
+					39 01 00 00 00 00 02 0D 40
+					39 01 00 00 00 00 02 0F 01
+					39 01 00 00 00 00 02 11 E0
+					39 01 00 00 00 00 02 15 0F
+					39 01 00 00 00 00 02 16 A4
+					39 01 00 00 00 00 02 19 0F
+					39 01 00 00 00 00 02 1A 78
+					39 01 00 00 00 00 02 1B 23
+					39 01 00 00 00 00 02 1D 36
+					39 01 00 00 00 00 02 1E 3E
+					39 01 00 00 00 00 02 1F 3E
+					39 01 00 00 00 00 02 20 3E
+					39 01 00 00 00 00 02 28 FD
+					39 01 00 00 00 00 02 29 12
+					39 01 00 00 00 00 02 2A E1
+					39 01 00 00 00 00 02 2D 0A
+					39 01 00 00 00 00 02 30 49
+					39 01 00 00 00 00 02 33 96
+					39 01 00 00 00 00 02 34 FF
+					39 01 00 00 00 00 02 35 40
+					39 01 00 00 00 00 02 36 DE
+					39 01 00 00 00 00 02 37 F9
+					39 01 00 00 00 00 02 38 45
+					39 01 00 00 00 00 02 39 D9
+					39 01 00 00 00 00 02 3A 49
+					39 01 00 00 00 00 02 4A F0
+					39 01 00 00 00 00 02 7A 09
+					39 01 00 00 00 00 02 7B 40
+					39 01 00 00 00 00 02 7F F0
+					39 01 00 00 00 00 02 83 0F
+					39 01 00 00 00 00 02 84 A4
+					39 01 00 00 00 00 02 87 0F
+					39 01 00 00 00 00 02 88 78
+					39 01 00 00 00 00 02 89 23
+					39 01 00 00 00 00 02 8B 36
+					39 01 00 00 00 00 02 8C 7D
+					39 01 00 00 00 00 02 8D 7D
+					39 01 00 00 00 00 02 8E 7D
+					39 01 00 00 00 00 02 FF 20
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 11 B0 00 00 00 17 00 49 00 6A 00 89 00 9F 00 B6 00 C8
+					39 01 00 00 00 00 11 B1 00 D9 01 10 01 3A 01 7A 01 A9 01 F2 02 2D 02 2E
+					39 01 00 00 00 00 11 B2 02 64 02 A3 02 CA 03 00 03 1E 03 4A 03 59 03 6A
+					39 01 00 00 00 00 0F B3 03 7D 03 93 03 AB 03 C8 03 EC 03 FE 00 00
+					39 01 00 00 00 00 11 B4 00 00 00 1B 00 51 00 71 00 90 00 A7 00 BF 00 D1
+					39 01 00 00 00 00 11 B5 00 E2 01 1A 01 43 01 83 01 B2 01 FA 02 34 02 36
+					39 01 00 00 00 00 11 B6 02 6B 02 A8 02 D0 03 03 03 21 03 4D 03 5B 03 6B
+					39 01 00 00 00 00 0F B7 03 7E 03 94 03 AC 03 C8 03 EC 03 FE 00 00
+					39 01 00 00 00 00 11 B8 00 00 00 1B 00 51 00 72 00 92 00 A8 00 BF 00 D1
+					39 01 00 00 00 00 11 B9 00 E2 01 18 01 42 01 81 01 AF 01 F5 02 2F 02 31
+					39 01 00 00 00 00 11 BA 02 68 02 A6 02 CD 03 01 03 1F 03 4A 03 59 03 6A
+					39 01 00 00 00 00 0F BB 03 7D 03 93 03 AB 03 C8 03 EC 03 FE 00 00
+					39 01 00 00 00 00 02 FF 21
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 11 B0 00 00 00 17 00 49 00 6A 00 89 00 9F 00 B6 00 C8
+					39 01 00 00 00 00 11 B1 00 D9 01 10 01 3A 01 7A 01 A9 01 F2 02 2D 02 2E
+					39 01 00 00 00 00 11 B2 02 64 02 A3 02 CA 03 00 03 1E 03 4A 03 59 03 6A
+					39 01 00 00 00 00 0F B3 03 7D 03 93 03 AB 03 C8 03 EC 03 FE 00 00
+					39 01 00 00 00 00 11 B4 00 00 00 1B 00 51 00 71 00 90 00 A7 00 BF 00 D1
+					39 01 00 00 00 00 11 B5 00 E2 01 1A 01 43 01 83 01 B2 01 FA 02 34 02 36
+					39 01 00 00 00 00 11 B6 02 6B 02 A8 02 D0 03 03 03 21 03 4D 03 5B 03 6B
+					39 01 00 00 00 00 0F B7 03 7E 03 94 03 AC 03 C8 03 EC 03 FE 00 00
+					39 01 00 00 00 00 11 B8 00 00 00 1B 00 51 00 72 00 92 00 A8 00 BF 00 D1
+					39 01 00 00 00 00 11 B9 00 E2 01 18 01 42 01 81 01 AF 01 F5 02 2F 02 31
+					39 01 00 00 00 00 11 BA 02 68 02 A6 02 CD 03 01 03 1F 03 4A 03 59 03 6A
+					39 01 00 00 00 00 0F BB 03 7D 03 93 03 AB 03 C8 03 EC 03 FE 00 00
+					39 01 00 00 00 00 02 FF 2C
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 61 1F
+					39 01 00 00 00 00 02 62 1F
+					39 01 00 00 00 00 02 7E 03
+					39 01 00 00 00 00 02 6A 14
+					39 01 00 00 00 00 02 6B 36
+					39 01 00 00 00 00 02 6C 36
+					39 01 00 00 00 00 02 6D 36
+					39 01 00 00 00 00 02 53 04
+					39 01 00 00 00 00 02 54 04
+					39 01 00 00 00 00 02 55 04
+					39 01 00 00 00 00 02 56 0F
+					39 01 00 00 00 00 02 58 0F
+					39 01 00 00 00 00 02 59 0F
+					39 01 00 00 00 00 02 FF F0
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 5A 00
+					15 01 00 00 00 00 02 FF 10
+					15 01 00 00 00 00 02 FB 01
+					15 01 00 00 00 00 02 51 FF
+					15 01 00 00 00 00 02 53 24
+					15 01 00 00 00 00 02 55 01
+					05 01 00 00 78 00 01 11
+					05 01 00 00 64 00 01 29
+				];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command = [
+					05 01 00 00 10 00 01 28
+					05 01 00 00 32 00 01 10
+				];
+			};
+		};
+	};
+};
diff --git a/qcom/dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi b/qcom/dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi
new file mode 100644
index 00000000..02f1cee0
--- /dev/null
+++ b/qcom/dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi
@@ -0,0 +1,480 @@
+&mdss_mdp {
+	dsi_nt36672e_fhd_plus_90hz_video: qcom,mdss_dsi_nt36672e_fhd_plus_90hz_video {
+		qcom,mdss-dsi-panel-name =
+			"nt36672e 90Hz fhd plus video mode panel with DSC";
+		qcom,mdss-dsi-panel-type = "dsi_video_mode";
+		qcom,dsi-ctrl-num = <0>;
+		qcom,dsi-phy-num = <0>;
+		qcom,mdss-dsi-virtual-channel-id = <0>;
+		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-bpp = <24>;
+		qcom,mdss-dsi-border-color = <0>;
+		qcom,mdss-dsi-traffic-mode = "burst_mode";
+		qcom,mdss-dsi-bllp-power-mode;
+		qcom,mdss-dsi-bllp-eof-power-mode;
+		qcom,mdss-dsi-lane-0-state;
+		qcom,mdss-dsi-lane-1-state;
+		qcom,mdss-dsi-lane-2-state;
+		qcom,mdss-dsi-lane-3-state;
+		qcom,mdss-dsi-dma-trigger = "trigger_sw";
+		qcom,mdss-dsi-mdp-trigger = "none";
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+		qcom,mdss-dsi-tx-eot-append;
+		qcom,adjust-timer-wakeup-ms = <1>;
+		qcom,mdss-dsi-panel-hdr-enabled;
+		qcom,mdss-dsi-panel-hdr-color-primaries = <39000 16000 33750
+						 39800 13250 34450 7500 3000>;
+		qcom,mdss-dsi-panel-peak-brightness = <6450000>;
+		qcom,mdss-dsi-panel-blackness-level = <4961>;
+
+		qcom,mdss-dsi-display-timings {
+			timing@0 {
+				qcom,mdss-dsi-panel-width = <1080>;
+				qcom,mdss-dsi-panel-height = <2408>;
+				qcom,mdss-dsi-h-front-porch = <76>;
+				qcom,mdss-dsi-h-back-porch = <68>;
+				qcom,mdss-dsi-h-pulse-width = <10>;
+				qcom,mdss-dsi-h-sync-skew = <0>;
+				qcom,mdss-dsi-v-back-porch = <10>;
+				qcom,mdss-dsi-v-front-porch = <46>;
+				qcom,mdss-dsi-v-pulse-width = <10>;
+				qcom,mdss-dsi-panel-framerate = <90>;
+				qcom,mdss-dsi-on-command = [
+					39 01 00 00 00 00 02 FF 10
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 B0 00
+					39 01 00 00 00 00 02 C0 03
+					39 01 00 00 00 00 11 C1 89 28 00 08 00 AA 02 0E 00 2B 00 07 0D B7 0C B7
+					39 01 00 00 00 00 03 C2 1B A0
+
+					39 01 00 00 00 00 02 FF 20
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 01 66
+					39 01 00 00 00 00 02 06 40
+					39 01 00 00 00 00 02 07 38
+					39 01 00 00 00 00 02 18 66
+					39 01 00 00 00 00 02 1B 01
+					39 01 00 00 00 00 02 5C 90
+					39 01 00 00 00 00 02 5E AA
+					39 01 00 00 00 00 02 69 91
+
+					39 01 00 00 00 00 02 89 0D
+					39 01 00 00 00 00 02 8A 0D
+					39 01 00 00 00 00 02 8D 0D
+					39 01 00 00 00 00 02 8E 0D
+					39 01 00 00 00 00 02 8F 0D
+					39 01 00 00 00 00 02 91 0D
+
+					39 01 00 00 00 00 02 95 D1
+					39 01 00 00 00 00 02 96 D1
+					39 01 00 00 00 00 02 F2 65
+					39 01 00 00 00 00 02 F3 64
+					39 01 00 00 00 00 02 F4 65
+					39 01 00 00 00 00 02 F5 64
+					39 01 00 00 00 00 02 F6 65
+					39 01 00 00 00 00 02 F7 64
+					39 01 00 00 00 00 02 F8 65
+					39 01 00 00 00 00 02 F9 64
+
+					39 01 00 00 00 00 02 FF 24
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 01 0F
+					39 01 00 00 00 00 02 03 0C
+					39 01 00 00 00 00 02 05 1D
+					39 01 00 00 00 00 02 08 2F
+					39 01 00 00 00 00 02 09 2E
+					39 01 00 00 00 00 02 0A 2D
+					39 01 00 00 00 00 02 0B 2C
+					39 01 00 00 00 00 02 11 17
+					39 01 00 00 00 00 02 12 13
+					39 01 00 00 00 00 02 13 15
+					39 01 00 00 00 00 02 15 14
+					39 01 00 00 00 00 02 16 16
+					39 01 00 00 00 00 02 17 18
+					39 01 00 00 00 00 02 1B 01
+					39 01 00 00 00 00 02 1D 1D
+					39 01 00 00 00 00 02 20 2F
+					39 01 00 00 00 00 02 21 2E
+					39 01 00 00 00 00 02 22 2D
+					39 01 00 00 00 00 02 23 2C
+					39 01 00 00 00 00 02 29 17
+					39 01 00 00 00 00 02 2A 13
+					39 01 00 00 00 00 02 2B 15
+					39 01 00 00 00 00 02 2F 14
+					39 01 00 00 00 00 02 30 16
+					39 01 00 00 00 00 02 31 18
+					39 01 00 00 00 00 02 32 04
+					39 01 00 00 00 00 02 34 10
+					39 01 00 00 00 00 02 35 1F
+					39 01 00 00 00 00 02 36 1F
+					39 01 00 00 00 00 02 4D 19
+					39 01 00 00 00 00 02 4E 45
+					39 01 00 00 00 00 02 4F 45
+					39 01 00 00 00 00 02 53 45
+					39 01 00 00 00 00 02 71 30
+					39 01 00 00 00 00 02 79 11
+					39 01 00 00 00 00 02 7A 82
+					39 01 00 00 00 00 02 7B 94
+					39 01 00 00 00 00 02 7D 04
+					39 01 00 00 00 00 02 80 04
+					39 01 00 00 00 00 02 81 04
+					39 01 00 00 00 00 02 82 13
+					39 01 00 00 00 00 02 84 31
+					39 01 00 00 00 00 02 85 00
+					39 01 00 00 00 00 02 86 00
+					39 01 00 00 00 00 02 87 00
+					39 01 00 00 00 00 02 90 13
+					39 01 00 00 00 00 02 92 31
+					39 01 00 00 00 00 02 93 00
+					39 01 00 00 00 00 02 94 00
+					39 01 00 00 00 00 02 95 00
+					39 01 00 00 00 00 02 9C F4
+					39 01 00 00 00 00 02 9D 01
+					39 01 00 00 00 00 02 A0 14
+					39 01 00 00 00 00 02 A2 14
+					39 01 00 00 00 00 02 A3 02
+					39 01 00 00 00 00 02 A4 04
+					39 01 00 00 00 00 02 A5 04
+					39 01 00 00 00 00 02 C4 40
+					39 01 00 00 00 00 02 C6 C0
+					39 01 00 00 00 00 02 C9 00
+					39 01 00 00 00 00 02 D9 80
+					39 01 00 00 00 00 02 E9 02
+
+					39 01 00 00 00 00 02 FF 25
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 0F 1B
+					39 01 00 00 00 00 02 19 E4
+					39 01 00 00 00 00 02 21 40
+					39 01 00 00 00 00 02 66 D8
+					39 01 00 00 00 00 02 68 50
+					39 01 00 00 00 00 02 69 10
+					39 01 00 00 00 00 02 6B 00
+					39 01 00 00 00 00 02 6D 0D
+					39 01 00 00 00 00 02 6E 48
+					39 01 00 00 00 00 02 72 41
+					39 01 00 00 00 00 02 73 4A
+					39 01 00 00 00 00 02 74 D0
+					39 01 00 00 00 00 02 77 62
+					39 01 00 00 00 00 02 79 7F
+					39 01 00 00 00 00 02 7D 40
+					39 01 00 00 00 00 02 7F 00
+					39 01 00 00 00 00 02 80 04
+					39 01 00 00 00 00 02 84 0D
+					39 01 00 00 00 00 02 CF 80
+					39 01 00 00 00 00 02 D6 80
+					39 01 00 00 00 00 02 D7 80
+					39 01 00 00 00 00 02 EF 20
+					39 01 00 00 00 00 02 F0 84
+
+					39 01 00 00 00 00 02 FF 26
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 15 04
+					39 01 00 00 00 00 02 81 14
+					39 01 00 00 00 00 02 83 02
+					39 01 00 00 00 00 02 84 03
+					39 01 00 00 00 00 02 85 01
+					39 01 00 00 00 00 02 86 03
+					39 01 00 00 00 00 02 87 01
+					39 01 00 00 00 00 02 88 06
+					39 01 00 00 00 00 02 8A 1A
+					39 01 00 00 00 00 02 8B 11
+					39 01 00 00 00 00 02 8C 24
+					39 01 00 00 00 00 02 8E 42
+					39 01 00 00 00 00 02 8F 11
+					39 01 00 00 00 00 02 90 11
+					39 01 00 00 00 00 02 91 11
+					39 01 00 00 00 00 02 9A 81
+					39 01 00 00 00 00 02 9B 03
+					39 01 00 00 00 00 02 9C 00
+					39 01 00 00 00 00 02 9D 00
+					39 01 00 00 00 00 02 9E 00
+
+					39 01 00 00 00 00 02 FF 27
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 01 68
+					39 01 00 00 00 00 02 20 81
+					39 01 00 00 00 00 02 21 EA
+					39 01 00 00 00 00 02 25 82
+					39 01 00 00 00 00 02 26 1F
+					39 01 00 00 00 00 02 6E 00
+					39 01 00 00 00 00 02 6F 00
+					39 01 00 00 00 00 02 70 00
+					39 01 00 00 00 00 02 71 00
+					39 01 00 00 00 00 02 72 00
+					39 01 00 00 00 00 02 75 00
+					39 01 00 00 00 00 02 76 00
+					39 01 00 00 00 00 02 77 00
+					39 01 00 00 00 00 02 7D 09
+					39 01 00 00 00 00 02 7E 67
+					39 01 00 00 00 00 02 80 23
+					39 01 00 00 00 00 02 82 09
+					39 01 00 00 00 00 02 83 67
+					39 01 00 00 00 00 02 88 01
+					39 01 00 00 00 00 02 89 10
+					39 01 00 00 00 00 02 A5 10
+					39 01 00 00 00 00 02 A6 23
+					39 01 00 00 00 00 02 A7 01
+					39 01 00 00 00 00 02 B6 40
+					39 01 00 00 00 00 02 E3 02
+					39 01 00 00 00 00 02 E4 E0
+					39 01 00 00 00 00 02 E5 01
+					39 01 00 00 00 00 02 E6 70
+					39 01 00 00 00 00 02 E9 03
+					39 01 00 00 00 00 02 EA 2F
+					39 01 00 00 00 00 02 EB 01
+					39 01 00 00 00 00 02 EC 98
+
+					39 01 00 00 00 00 02 FF 2A
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 00 91
+					39 01 00 00 00 00 02 03 20
+					39 01 00 00 00 00 02 07 5A
+					39 01 00 00 00 00 02 0A 70
+					39 01 00 00 00 00 02 0D 40
+					39 01 00 00 00 00 02 0E 02
+					39 01 00 00 00 00 02 11 F0
+					39 01 00 00 00 00 02 15 0F
+					39 01 00 00 00 00 02 16 65
+					39 01 00 00 00 00 02 19 0F
+					39 01 00 00 00 00 02 1A 39
+					39 01 00 00 00 00 02 1B 14
+					39 01 00 00 00 00 02 1D 36
+					39 01 00 00 00 00 02 1E 4F
+					39 01 00 00 00 00 02 1F 4F
+					39 01 00 00 00 00 02 20 4F
+					39 01 00 00 00 00 02 28 E4
+					39 01 00 00 00 00 02 29 17
+					39 01 00 00 00 00 02 2A F5
+					39 01 00 00 00 00 02 2D 06
+					39 01 00 00 00 00 02 2F 04
+					39 01 00 00 00 00 02 30 54
+					39 01 00 00 00 00 02 33 04
+					39 01 00 00 00 00 02 34 E6
+					39 01 00 00 00 00 02 35 32
+					39 01 00 00 00 00 02 36 02
+					39 01 00 00 00 00 02 37 E1
+					39 01 00 00 00 00 02 38 36
+					39 01 00 00 00 00 02 39 FE
+					39 01 00 00 00 00 02 3A 14
+					39 01 00 00 00 00 02 46 40
+					39 01 00 00 00 00 02 47 02
+					39 01 00 00 00 00 02 4A F0
+					39 01 00 00 00 00 02 4E 0F
+					39 01 00 00 00 00 02 4F 65
+					39 01 00 00 00 00 02 52 0F
+					39 01 00 00 00 00 02 53 39
+					39 01 00 00 00 00 02 54 14
+					39 01 00 00 00 00 02 56 36
+					39 01 00 00 00 00 02 57 7E
+					39 01 00 00 00 00 02 58 7E
+					39 01 00 00 00 00 02 59 7E
+					39 01 00 00 00 00 02 60 80
+					39 01 00 00 00 00 02 61 C9
+					39 01 00 00 00 00 02 62 03
+					39 01 00 00 00 00 02 63 FB
+					39 01 00 00 00 00 02 64 03
+					39 01 00 00 00 00 02 65 05
+					39 01 00 00 00 00 02 66 01
+					39 01 00 00 00 00 02 67 04
+					39 01 00 00 00 00 02 68 91
+					39 01 00 00 00 00 02 6A 19
+					39 01 00 00 00 00 02 6B CB
+					39 01 00 00 00 00 02 6C 20
+					39 01 00 00 00 00 02 6D E5
+					39 01 00 00 00 00 02 6E C8
+					39 01 00 00 00 00 02 6F 22
+					39 01 00 00 00 00 02 70 E3
+					39 01 00 00 00 00 02 71 04
+					39 01 00 00 00 00 02 7A 07
+					39 01 00 00 00 00 02 7B 40
+					39 01 00 00 00 00 02 7D 01
+					39 01 00 00 00 00 02 7F 2C
+					39 01 00 00 00 00 02 83 0F
+					39 01 00 00 00 00 02 84 65
+					39 01 00 00 00 00 02 87 0F
+					39 01 00 00 00 00 02 88 39
+					39 01 00 00 00 00 02 89 14
+					39 01 00 00 00 00 02 8B 36
+					39 01 00 00 00 00 02 8C 39
+					39 01 00 00 00 00 02 8D 39
+					39 01 00 00 00 00 02 8E 39
+					39 01 00 00 00 00 02 95 80
+					39 01 00 00 00 00 02 96 FD
+					39 01 00 00 00 00 02 97 14
+					39 01 00 00 00 00 02 98 B3
+					39 01 00 00 00 00 02 99 01
+					39 01 00 00 00 00 02 9A 08
+					39 01 00 00 00 00 02 9B 02
+					39 01 00 00 00 00 02 9C 4C
+					39 01 00 00 00 00 02 9D BC
+					39 01 00 00 00 00 02 9F AC
+					39 01 00 00 00 00 02 A0 FF
+					39 01 00 00 00 00 02 A2 44
+					39 01 00 00 00 00 02 A3 78
+					39 01 00 00 00 00 02 A4 F8
+					39 01 00 00 00 00 02 A5 4A
+					39 01 00 00 00 00 02 A6 72
+					39 01 00 00 00 00 02 A7 4C
+
+					39 01 00 00 00 00 02 FF 2C
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 00 02
+					39 01 00 00 00 00 02 01 02
+					39 01 00 00 00 00 02 02 02
+					39 01 00 00 00 00 02 03 16
+					39 01 00 00 00 00 02 04 16
+					39 01 00 00 00 00 02 05 16
+					39 01 00 00 00 00 02 0D 1F
+					39 01 00 00 00 00 02 0E 1F
+					39 01 00 00 00 00 02 16 1B
+					39 01 00 00 00 00 02 17 4B
+					39 01 00 00 00 00 02 18 4B
+					39 01 00 00 00 00 02 19 4B
+					39 01 00 00 00 00 02 2A 03
+					39 01 00 00 00 00 02 4D 16
+					39 01 00 00 00 00 02 4E 02
+					39 01 00 00 00 00 02 4F 2F
+					39 01 00 00 00 00 02 53 02
+					39 01 00 00 00 00 02 54 02
+					39 01 00 00 00 00 02 55 02
+					39 01 00 00 00 00 02 56 0E
+					39 01 00 00 00 00 02 58 0E
+					39 01 00 00 00 00 02 59 0E
+					39 01 00 00 00 00 02 61 1F
+					39 01 00 00 00 00 02 62 1F
+					39 01 00 00 00 00 02 6A 14
+					39 01 00 00 00 00 02 6B 34
+					39 01 00 00 00 00 02 6C 34
+					39 01 00 00 00 00 02 6D 34
+					39 01 00 00 00 00 02 7E 03
+					39 01 00 00 00 00 02 9D 0E
+					39 01 00 00 00 00 02 9E 02
+					39 01 00 00 00 00 02 9F 02
+
+					39 01 00 00 00 00 02 FF 20
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 11 B0 00 00 00 15 00 3F 00 5F 00 7E 00 97 00 AF 00 C3
+					39 01 00 00 00 00 11 B1 00 D7 01 0A 01 32 01 6F 01 9E 01 E5 02 1D 02 1E
+					39 01 00 00 00 00 11 B2 02 56 02 94 02 BC 02 F1 03 13 03 41 03 4F 03 5F
+					39 01 00 00 00 00 0F B3 03 71 03 84 03 99 03 B0 03 CA 03 D7 00 00
+					39 01 00 00 00 00 11 B4 00 00 00 17 00 46 00 69 00 8C 00 A5 00 BE 00 D1
+					39 01 00 00 00 00 11 B5 00 E4 01 18 01 40 01 7C 01 AA 01 F0 02 27 02 28
+					39 01 00 00 00 00 11 B6 02 5E 02 9B 02 C3 02 F6 03 18 03 45 03 54 03 63
+					39 01 00 00 00 00 0F B7 03 75 03 87 03 9C 03 B2 03 CA 03 D7 00 00
+					39 01 00 00 00 00 11 B8 00 00 00 18 00 49 00 6B 00 8E 00 A8 00 C1 00 D3
+					39 01 00 00 00 00 11 B9 00 E5 01 18 01 3F 01 7B 01 A8 01 EC 02 24 02 26
+					39 01 00 00 00 00 11 BA 02 5A 02 97 02 C0 02 F4 03 15 03 43 03 51 03 61
+					39 01 00 00 00 00 0F BB 03 72 03 85 03 9A 03 B1 03 CA 03 D7 00 00
+
+					39 01 00 00 00 00 02 C6 00
+					39 01 00 00 00 00 02 C7 00
+					39 01 00 00 00 00 02 C8 00
+					39 01 00 00 00 00 02 C9 00
+					39 01 00 00 00 00 02 CA 00
+
+					39 01 00 00 00 00 02 CB 00
+					39 01 00 00 00 00 02 CC 00
+					39 01 00 00 00 00 02 CD 00
+					39 01 00 00 00 00 02 CE 00
+					39 01 00 00 00 00 02 CF 00
+
+					39 01 00 00 00 00 02 D0 00
+					39 01 00 00 00 00 02 D1 00
+					39 01 00 00 00 00 02 D2 00
+					39 01 00 00 00 00 02 D3 00
+					39 01 00 00 00 00 02 D4 00
+
+					39 01 00 00 00 00 02 D5 00
+					39 01 00 00 00 00 02 D6 00
+					39 01 00 00 00 00 02 D7 00
+					39 01 00 00 00 00 02 D8 00
+					39 01 00 00 00 00 02 D9 00
+
+					39 01 00 00 00 00 02 DA 00
+					39 01 00 00 00 00 02 DB 00
+					39 01 00 00 00 00 02 DC 00
+					39 01 00 00 00 00 02 DD 00
+					39 01 00 00 00 00 02 DE 00
+
+					39 01 00 00 00 00 02 DF 00
+					39 01 00 00 00 00 02 E0 00
+					39 01 00 00 00 00 02 E1 00
+					39 01 00 00 00 00 02 E2 00
+					39 01 00 00 00 00 02 E3 00
+
+					39 01 00 00 00 00 02 E4 00
+					39 01 00 00 00 00 02 E5 00
+					39 01 00 00 00 00 02 E6 00
+					39 01 00 00 00 00 02 E7 00
+					39 01 00 00 00 00 02 E8 00
+					39 01 00 00 00 00 02 E9 00
+
+
+					39 01 00 00 00 00 02 FF 21
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 11 B0 00 00 00 15 00 3F 00 5F 00 7E 00 97 00 AF 00 C3
+					39 01 00 00 00 00 11 B1 00 D7 01 0A 01 32 01 6F 01 9E 01 E5 02 1D 02 1E
+					39 01 00 00 00 00 11 B2 02 56 02 94 02 BC 02 F1 03 13 03 41 03 4F 03 5F
+					39 01 00 00 00 00 0F B3 03 71 03 84 03 99 03 B0 03 CA 03 D7 00 00
+					39 01 00 00 00 00 11 B4 00 00 00 17 00 46 00 69 00 8C 00 A5 00 BE 00 D1
+					39 01 00 00 00 00 11 B5 00 E4 01 18 01 40 01 7C 01 AA 01 F0 02 27 02 28
+					39 01 00 00 00 00 11 B6 02 5E 02 9B 02 C3 02 F6 03 18 03 45 03 54 03 63
+					39 01 00 00 00 00 0F B7 03 75 03 87 03 9C 03 B2 03 CA 03 D7 00 00
+					39 01 00 00 00 00 11 B8 00 00 00 18 00 49 00 6B 00 8E 00 A8 00 C1 00 D3
+					39 01 00 00 00 00 11 B9 00 E5 01 18 01 3F 01 7B 01 A8 01 EC 02 24 02 26
+					39 01 00 00 00 00 11 BA 02 5A 02 97 02 C0 02 F4 03 15 03 43 03 51 03 61
+					39 01 00 00 00 00 0F BB 03 72 03 85 03 9A 03 B1 03 CA 03 D7 00 00
+
+					39 01 00 00 00 00 02 FF E0
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 35 82
+					39 01 00 00 00 00 02 85 32
+
+					39 01 00 00 00 00 02 FF F0
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 1C 01
+					39 01 00 00 00 00 02 33 01
+					39 01 00 00 00 00 02 5A 00
+
+					39 01 00 00 00 00 02 FF D0
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 53 22
+					39 01 00 00 00 00 02 54 02
+
+					39 01 00 00 00 00 02 FF C0
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 9C 11
+					39 01 00 00 00 00 02 9D 11
+
+					39 01 00 00 00 00 02 FF 2B
+					39 01 00 00 00 00 02 FB 01
+					39 01 00 00 00 00 02 B7 0A
+					39 01 00 00 00 00 02 B8 1C
+					39 01 00 00 00 00 02 C0 01
+
+					39 01 00 00 00 00 02 FF 10
+					39 01 00 00 00 00 02 35 01
+					39 01 00 00 00 00 02 51 FF
+					39 01 00 00 00 00 02 53 0C
+					39 01 00 00 00 00 02 55 00
+					05 01 00 00 78 00 01 11
+					05 01 00 00 28 00 01 29
+				];
+				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+				qcom,mdss-dsi-off-command = [
+					05 01 00 00 10 00 01 28
+					05 01 00 00 32 00 01 10
+				];
+				qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+				qcom,compression-mode = "dsc";
+				qcom,mdss-dsc-slice-height = <8>;
+				qcom,mdss-dsc-slice-width = <540>;
+				qcom,mdss-dsc-slice-per-pkt = <1>;
+				qcom,mdss-dsc-bit-per-component = <8>;
+				qcom,mdss-dsc-bit-per-pixel = <8>;
+				qcom,mdss-dsc-block-prediction-enable;
+			};
+		};
+	};
+};
diff --git a/qcom/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi b/qcom/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi
index d066925a..f1f5e541 100644
--- a/qcom/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi
+++ b/qcom/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi
@@ -3,23 +3,382 @@
 		qcom,mdss-dsi-panel-name =
 			"Dual nt36850 cmd mode dsi truly panel without DSC";
 		qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
-
-		qcom,dsi-ctrl-num = <0 1>;
-		qcom,dsi-phy-num = <0 1>;
-		qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
-
+		qcom,mdss-dsi-panel-framerate = <60>;
 		qcom,mdss-dsi-virtual-channel-id = <0>;
 		qcom,mdss-dsi-stream = <0>;
+		qcom,mdss-dsi-panel-width = <720>;
+		qcom,mdss-dsi-panel-height = <2560>;
+		qcom,mdss-dsi-h-front-porch = <120>;
+		qcom,mdss-dsi-h-back-porch = <140>;
+		qcom,mdss-dsi-h-pulse-width = <20>;
+		qcom,mdss-dsi-h-sync-skew = <0>;
+		qcom,mdss-dsi-v-back-porch = <20>;
+		qcom,mdss-dsi-v-front-porch = <8>;
+		qcom,mdss-dsi-v-pulse-width = <4>;
+		qcom,mdss-dsi-h-left-border = <0>;
+		qcom,mdss-dsi-h-right-border = <0>;
+		qcom,mdss-dsi-v-top-border = <0>;
+		qcom,mdss-dsi-v-bottom-border = <0>;
 		qcom,mdss-dsi-bpp = <24>;
 		qcom,mdss-dsi-color-order = "rgb_swap_rgb";
 		qcom,mdss-dsi-underflow-color = <0xff>;
 		qcom,mdss-dsi-border-color = <0>;
-
+		qcom,mdss-dsi-on-command = [
+				15 01 00 00 00 00 02 ff 24
+				15 01 00 00 00 00 02 fb 01
+				15 01 00 00 00 00 02 00 19
+				15 01 00 00 00 00 02 01 03
+				15 01 00 00 00 00 02 02 04
+				15 01 00 00 00 00 02 03 1b
+				15 01 00 00 00 00 02 04 1d
+				15 01 00 00 00 00 02 05 01
+				15 01 00 00 00 00 02 06 0c
+				15 01 00 00 00 00 02 07 0f
+				15 01 00 00 00 00 02 08 1f
+				15 01 00 00 00 00 02 09 00
+				15 01 00 00 00 00 02 0a 00
+				15 01 00 00 00 00 02 0b 13
+				15 01 00 00 00 00 02 0c 16
+				15 01 00 00 00 00 02 0d 14
+				15 01 00 00 00 00 02 0e 15
+				15 01 00 00 00 00 02 0f 00
+				15 01 00 00 00 00 02 10 19
+				15 01 00 00 00 00 02 11 03
+				15 01 00 00 00 00 02 12 04
+				15 01 00 00 00 00 02 13 1b
+				15 01 00 00 00 00 02 14 1d
+				15 01 00 00 00 00 02 15 01
+				15 01 00 00 00 00 02 16 0c
+				15 01 00 00 00 00 02 17 0f
+				15 01 00 00 00 00 02 18 1f
+				15 01 00 00 00 00 02 19 00
+				15 01 00 00 00 00 02 1a 00
+				15 01 00 00 00 00 02 1b 13
+				15 01 00 00 00 00 02 1c 16
+				15 01 00 00 00 00 02 1d 14
+				15 01 00 00 00 00 02 1e 15
+				15 01 00 00 00 00 02 1f 00
+				15 01 00 00 00 00 02 21 01
+				15 01 00 00 00 00 02 22 10
+				15 01 00 00 00 00 02 23 28
+				15 01 00 00 00 00 02 24 28
+				15 01 00 00 00 00 02 25 5d
+				15 01 00 00 00 00 02 26 28
+				15 01 00 00 00 00 02 27 28
+				15 01 00 00 00 00 02 29 d8
+				15 01 00 00 00 00 02 2a 15
+				15 01 00 00 00 00 02 2b 00
+				15 01 00 00 00 00 02 2d 00
+				15 01 00 00 00 00 02 2f 02
+				15 01 00 00 00 00 02 30 02
+				15 01 00 00 00 00 02 31 00
+				15 01 00 00 00 00 02 32 23
+				15 01 00 00 00 00 02 33 01
+				15 01 00 00 00 00 02 34 03
+				15 01 00 00 00 00 02 35 49
+				15 01 00 00 00 00 02 36 00
+				15 01 00 00 00 00 02 37 1d
+				15 01 00 00 00 00 02 38 08
+				15 01 00 00 00 00 02 39 03
+				15 01 00 00 00 00 02 3a 49
+				15 01 00 00 00 00 02 42 01
+				15 01 00 00 00 00 02 43 8c
+				15 01 00 00 00 00 02 44 a3
+				15 01 00 00 00 00 02 48 8c
+				15 01 00 00 00 00 02 49 a3
+				15 01 00 00 00 00 02 5b 00
+				15 01 00 00 00 00 02 5f 4d
+				15 01 00 00 00 00 02 63 00
+				15 01 00 00 00 00 02 67 04
+				15 01 00 00 00 00 02 6e 10
+				15 01 00 00 00 00 02 72 02
+				15 01 00 00 00 00 02 73 00
+				15 01 00 00 00 00 02 74 04
+				15 01 00 00 00 00 02 75 1b
+				15 01 00 00 00 00 02 76 05
+				15 01 00 00 00 00 02 77 01
+				15 01 00 00 00 00 02 78 00
+				15 01 00 00 00 00 02 79 00
+				15 01 00 00 00 00 02 7a 00
+				15 01 00 00 00 00 02 7b 91
+				15 01 00 00 00 00 02 7c da
+				15 01 00 00 00 00 02 7d 10
+				15 01 00 00 00 00 02 7e 04
+				15 01 00 00 00 00 02 7f 1b
+				15 01 00 00 00 00 02 80 00
+				15 01 00 00 00 00 02 81 05
+				15 01 00 00 00 00 02 82 01
+				15 01 00 00 00 00 02 83 00
+				15 01 00 00 00 00 02 84 05
+				15 01 00 00 00 00 02 85 05
+				15 01 00 00 00 00 02 86 1b
+				15 01 00 00 00 00 02 87 1b
+				15 01 00 00 00 00 02 88 1b
+				15 01 00 00 00 00 02 89 1b
+				15 01 00 00 00 00 02 8a 00
+				15 01 00 00 00 00 02 8b f0
+				15 01 00 00 00 00 02 8c 00
+				15 01 00 00 00 00 02 8f 63
+				15 01 00 00 00 00 02 90 51
+				15 01 00 00 00 00 02 91 40
+				15 01 00 00 00 00 02 92 51
+				15 01 00 00 00 00 02 93 08
+				15 01 00 00 00 00 02 94 08
+				15 01 00 00 00 00 02 95 51
+				15 01 00 00 00 00 02 96 51
+				15 01 00 00 00 00 02 97 00
+				15 01 00 00 00 00 02 98 00
+				15 01 00 00 00 00 02 99 33
+				15 01 00 00 00 00 02 9b ff
+				15 01 00 00 00 00 02 9c 01
+				15 01 00 00 00 00 02 9d 30
+				15 01 00 00 00 00 02 a5 10
+				15 01 00 00 00 00 02 a6 01
+				15 01 00 00 00 00 02 a9 21
+				15 01 00 00 00 00 02 b3 2a
+				15 01 00 00 00 00 02 b4 da
+				15 01 00 00 00 00 02 ba 83
+				15 01 00 00 00 00 02 c4 24
+				15 01 00 00 00 00 02 c5 aa
+				15 01 00 00 00 00 02 c6 09
+				15 01 00 00 00 00 02 c7 00
+				15 01 00 00 00 00 02 c9 c0
+				15 01 00 00 00 00 02 ca 04
+				15 01 00 00 00 00 02 d5 3f
+				15 01 00 00 00 00 02 d6 10
+				15 01 00 00 00 00 02 d7 3f
+				15 01 00 00 00 00 02 d8 10
+				15 01 00 00 00 00 02 d9 ee
+				15 01 00 00 00 00 02 da 49
+				15 01 00 00 00 00 02 db 94
+				15 01 00 00 00 00 02 e9 33
+				15 01 00 00 00 00 02 eb 28
+				15 01 00 00 00 00 02 ec 00
+				15 01 00 00 00 00 02 ee 00
+				15 01 00 00 00 00 02 ef 06
+				15 01 00 00 00 00 02 f0 01
+				15 01 00 00 00 00 02 f1 01
+				15 01 00 00 00 00 02 f2 0d
+				15 01 00 00 00 00 02 f3 48
+				15 01 00 00 00 00 02 f6 00
+				15 01 00 00 00 00 02 f7 00
+				15 01 00 00 00 00 02 f8 00
+				15 01 00 00 00 00 02 f9 00
+				15 01 00 00 00 00 02 ff 26
+				15 01 00 00 00 00 02 fb 01
+				15 01 00 00 00 00 02 00 ab
+				15 01 00 00 00 00 02 01 00
+				15 01 00 00 00 00 02 02 80
+				15 01 00 00 00 00 02 03 08
+				15 01 00 00 00 00 02 04 01
+				15 01 00 00 00 00 02 05 32
+				15 01 00 00 00 00 02 06 4c
+				15 01 00 00 00 00 02 07 26
+				15 01 00 00 00 00 02 08 09
+				15 01 00 00 00 00 02 09 02
+				15 01 00 00 00 00 02 0a 32
+				15 01 00 00 00 00 02 0b 55
+				15 01 00 00 00 00 02 0c 14
+				15 01 00 00 00 00 02 0d 28
+				15 01 00 00 00 00 02 0e 40
+				15 01 00 00 00 00 02 0f 80
+				15 01 00 00 00 00 02 10 00
+				15 01 00 00 00 00 02 11 22
+				15 01 00 00 00 00 02 12 0a
+				15 01 00 00 00 00 02 13 20
+				15 01 00 00 00 00 02 14 06
+				15 01 00 00 00 00 02 15 00
+				15 01 00 00 00 00 02 16 40
+				15 01 00 00 00 00 02 19 43
+				15 01 00 00 00 00 02 1a 03
+				15 01 00 00 00 00 02 1b 25
+				15 01 00 00 00 00 02 1c 11
+				15 01 00 00 00 00 02 1d 00
+				15 01 00 00 00 00 02 1e 80
+				15 01 00 00 00 00 02 1f 00
+				15 01 00 00 00 00 02 20 03
+				15 01 00 00 00 00 02 21 03
+				15 01 00 00 00 00 02 22 25
+				15 01 00 00 00 00 02 23 25
+				15 01 00 00 00 00 02 24 00
+				15 01 00 00 00 00 02 25 a7
+				15 01 00 00 00 00 02 26 80
+				15 01 00 00 00 00 02 27 a5
+				15 01 00 00 00 00 02 28 06
+				15 01 00 00 00 00 02 29 85
+				15 01 00 00 00 00 02 2a 30
+				15 01 00 00 00 00 02 2b 97
+				15 01 00 00 00 00 02 2f 25
+				15 01 00 00 00 00 02 30 26
+				15 01 00 00 00 00 02 31 41
+				15 01 00 00 00 00 02 32 04
+				15 01 00 00 00 00 02 33 04
+				15 01 00 00 00 00 02 34 2b
+				15 01 00 00 00 00 02 35 00
+				15 01 00 00 00 00 02 36 00
+				15 01 00 00 00 00 02 37 c8
+				15 01 00 00 00 00 02 38 26
+				15 01 00 00 00 00 02 39 25
+				15 01 00 00 00 00 02 3a 26
+				15 01 00 00 00 00 02 3f eb
+				15 01 00 00 00 00 02 41 21
+				15 01 00 00 00 00 02 42 03
+				15 01 00 00 00 00 02 43 00
+				15 01 00 00 00 00 02 44 11
+				15 01 00 00 00 00 02 45 00
+				15 01 00 00 00 00 02 46 00
+				15 01 00 00 00 00 02 47 00
+				15 01 00 00 00 00 02 48 03
+				15 01 00 00 00 00 02 49 03
+				15 01 00 00 00 00 02 4a 00
+				15 01 00 00 00 00 02 4b 00
+				15 01 00 00 00 00 02 4c 01
+				15 01 00 00 00 00 02 4d 4e
+				15 01 00 00 00 00 02 4e 01
+				15 01 00 00 00 00 02 4f 4c
+				15 01 00 00 00 00 02 50 0d
+				15 01 00 00 00 00 02 51 0e
+				15 01 00 00 00 00 02 52 20
+				15 01 00 00 00 00 02 53 97
+				15 01 00 00 00 00 02 54 4b
+				15 01 00 00 00 00 02 55 4c
+				15 01 00 00 00 00 02 56 20
+				15 01 00 00 00 00 02 58 04
+				15 01 00 00 00 00 02 59 04
+				15 01 00 00 00 00 02 5a 09
+				15 01 00 00 00 00 02 5b 00
+				15 01 00 00 00 00 02 5c 00
+				15 01 00 00 00 00 02 5d c8
+				15 01 00 00 00 00 02 5e 4c
+				15 01 00 00 00 00 02 5f 4b
+				15 01 00 00 00 00 02 60 00
+				15 01 00 00 00 00 02 80 2b
+				15 01 00 00 00 00 02 81 43
+				15 01 00 00 00 00 02 82 03
+				15 01 00 00 00 00 02 83 25
+				15 01 00 00 00 00 02 84 11
+				15 01 00 00 00 00 02 85 00
+				15 01 00 00 00 00 02 86 80
+				15 01 00 00 00 00 02 87 00
+				15 01 00 00 00 00 02 88 00
+				15 01 00 00 00 00 02 89 03
+				15 01 00 00 00 00 02 8a 22
+				15 01 00 00 00 00 02 8b 25
+				15 01 00 00 00 00 02 8c 00
+				15 01 00 00 00 00 02 8d a4
+				15 01 00 00 00 00 02 8e 00
+				15 01 00 00 00 00 02 8f a2
+				15 01 00 00 00 00 02 90 06
+				15 01 00 00 00 00 02 91 63
+				15 01 00 00 00 00 02 92 30
+				15 01 00 00 00 00 02 93 97
+				15 01 00 00 00 00 02 94 25
+				15 01 00 00 00 00 02 95 26
+				15 01 00 00 00 00 02 96 41
+				15 01 00 00 00 00 02 97 04
+				15 01 00 00 00 00 02 98 04
+				15 01 00 00 00 00 02 99 f0
+				15 01 00 00 00 00 02 9a 00
+				15 01 00 00 00 00 02 9b 00
+				15 01 00 00 00 00 02 9c c8
+				15 01 00 00 00 00 02 9d 50
+				15 01 00 00 00 00 02 9e 26
+				15 01 00 00 00 00 02 9f 25
+				15 01 00 00 00 00 02 a0 26
+				15 01 00 00 00 00 02 a2 00
+				15 01 00 00 00 00 02 a3 33
+				15 01 00 00 00 00 02 a5 40
+				15 01 00 00 00 00 02 a6 40
+				15 01 00 00 00 00 02 ac 91
+				15 01 00 00 00 00 02 ad 66
+				15 01 00 00 00 00 02 ae 66
+				15 01 00 00 00 00 02 b1 40
+				15 01 00 00 00 00 02 b2 40
+				15 01 00 00 00 00 02 b4 40
+				15 01 00 00 00 00 02 b5 40
+				15 01 00 00 00 00 02 b7 40
+				15 01 00 00 00 00 02 b8 40
+				15 01 00 00 00 00 02 ba 22
+				15 01 00 00 00 00 02 bb 00
+				15 01 00 00 00 00 02 c2 01
+				15 01 00 00 00 00 02 c3 01
+				15 01 00 00 00 00 02 c4 01
+				15 01 00 00 00 00 02 c5 01
+				15 01 00 00 00 00 02 c6 01
+				15 01 00 00 00 00 02 c8 00
+				15 01 00 00 00 00 02 c9 00
+				15 01 00 00 00 00 02 ca 00
+				15 01 00 00 00 00 02 cd 00
+				15 01 00 00 00 00 02 ce 00
+				15 01 00 00 00 00 02 d6 04
+				15 01 00 00 00 00 02 d7 00
+				15 01 00 00 00 00 02 d8 0d
+				15 01 00 00 00 00 02 d9 00
+				15 01 00 00 00 00 02 da 00
+				15 01 00 00 00 00 02 db 00
+				15 01 00 00 00 00 02 dc 00
+				15 01 00 00 00 00 02 dd 00
+				15 01 00 00 00 00 02 de 00
+				15 01 00 00 00 00 02 df 01
+				15 01 00 00 00 00 02 e0 00
+				15 01 00 00 00 00 02 e1 00
+				15 01 00 00 00 00 02 e2 19
+				15 01 00 00 00 00 02 e3 04
+				15 01 00 00 00 00 02 e4 00
+				15 01 00 00 00 00 02 e5 04
+				15 01 00 00 00 00 02 e6 00
+				15 01 00 00 00 00 02 e7 12
+				15 01 00 00 00 00 02 e8 00
+				15 01 00 00 00 00 02 e9 50
+				15 01 00 00 00 00 02 ea 10
+				15 01 00 00 00 00 02 eb 02
+				15 01 00 00 00 00 02 ff 27
+				15 01 00 00 00 00 02 fb 01
+				15 01 00 00 00 00 02 ff 28
+				15 01 00 00 00 00 02 fb 01
+				15 01 00 00 00 00 02 60 0a
+				15 01 00 00 00 00 02 63 32
+				15 01 00 00 00 00 02 64 01
+				15 01 00 00 00 00 02 68 da
+				15 01 00 00 00 00 02 69 00
+				15 01 00 00 00 00 02 ff 29
+				15 01 00 00 00 00 02 fb 01
+				15 01 00 00 00 00 02 60 0a
+				15 01 00 00 00 00 02 63 32
+				15 01 00 00 00 00 02 64 01
+				15 01 00 00 00 00 02 68 da
+				15 01 00 00 00 00 02 69 00
+				15 01 00 00 00 00 02 ff e0
+				15 01 00 00 00 00 02 fb 01
+				15 01 00 00 00 00 02 35 40
+				15 01 00 00 00 00 02 36 40
+				15 01 00 00 00 00 02 37 00
+				15 01 00 00 00 00 02 89 c6
+				15 01 00 00 00 00 02 ff f0
+				15 01 00 00 00 00 02 fb 01
+				15 01 00 00 00 00 02 ea 40
+				15 01 00 00 00 00 02 ff 10
+				15 01 00 00 00 00 02 36 00
+				15 01 00 00 00 00 02 35 00
+				39 01 00 00 00 00 03 44 03 e8
+				15 01 00 00 00 00 02 51 ff
+				15 01 00 00 00 00 02 53 2c
+				15 01 00 00 00 00 02 55 01
+				05 01 00 00 0a 00 02 20 00
+				15 01 00 00 00 00 02 bb 10
+				05 01 00 00 78 00 02 11 00
+				05 01 00 00 14 00 02 29 00];
+		qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00
+				05 01 00 00 78 00 02 10 00];
+		qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+		qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+		qcom,mdss-dsi-h-sync-pulse = <0>;
 		qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
 		qcom,mdss-dsi-lane-map = "lane_map_0123";
 		qcom,mdss-dsi-bllp-eof-power-mode;
 		qcom,mdss-dsi-bllp-power-mode;
 		qcom,mdss-dsi-tx-eot-append;
+		qcom,cmd-sync-wait-broadcast;
 		qcom,mdss-dsi-lane-0-state;
 		qcom,mdss-dsi-lane-1-state;
 		qcom,mdss-dsi-lane-2-state;
@@ -30,51 +389,16 @@
 		qcom,mdss-dsi-te-dcs-command = <1>;
 		qcom,mdss-dsi-te-check-enable;
 		qcom,mdss-dsi-te-using-te-pin;
+		qcom,mdss-dsi-panel-timings =
+			[da 34 24 00 64 68 28 38 2a 03 04 00];
+		qcom,mdss-dsi-t-clk-pre = <0x29>;
+		qcom,mdss-dsi-t-clk-post = <0x03>;
 		qcom,mdss-dsi-dma-trigger = "trigger_sw";
 		qcom,mdss-dsi-mdp-trigger = "none";
 		qcom,mdss-dsi-lp11-init;
 		qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
 		qcom,mdss-dsi-bl-min-level = <1>;
 		qcom,mdss-dsi-bl-max-level = <4095>;
-		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 50>;
-		qcom,mdss-dsi-display-timings {
-			timing@0 {
-				qcom,mdss-dsi-panel-framerate = <60>;
-				qcom,mdss-dsi-panel-width = <720>;
-				qcom,mdss-dsi-panel-height = <2560>;
-				qcom,mdss-dsi-h-front-porch = <120>;
-				qcom,mdss-dsi-h-back-porch = <140>;
-				qcom,mdss-dsi-h-pulse-width = <20>;
-				qcom,mdss-dsi-h-sync-skew = <0>;
-				qcom,mdss-dsi-v-back-porch = <20>;
-				qcom,mdss-dsi-v-front-porch = <8>;
-				qcom,mdss-dsi-v-pulse-width = <4>;
-				qcom,mdss-dsi-h-left-border = <0>;
-				qcom,mdss-dsi-h-right-border = <0>;
-				qcom,mdss-dsi-v-top-border = <0>;
-				qcom,mdss-dsi-v-bottom-border = <0>;
-				qcom,mdss-dsi-on-command = [
-					15 01 00 00 00 00 02 ff 10
-					15 01 00 00 00 00 02 fb 01
-					15 01 00 00 00 00 02 36 00
-					15 01 00 00 00 00 02 35 00
-					39 01 00 00 00 00 03 44 03 e8
-					15 01 00 00 00 00 02 51 ff
-					15 01 00 00 00 00 02 53 2c
-					15 01 00 00 00 00 02 55 01
-					05 01 00 00 0a 00 02 20 00
-					15 01 00 00 00 00 02 bb 10
-					05 01 00 00 78 00 02 11 00
-					05 01 00 00 78 00 02 29 00
-				];
-				qcom,mdss-dsi-off-command = [
-					05 01 00 00 78 00 02 28 00
-					05 01 00 00 78 00 02 10 00
-				];
-				qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
-				qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
-				qcom,mdss-dsi-h-sync-pulse = <0>;
-			};
-		};
+		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
 	};
 };
diff --git a/qcom/fg-gen4-batterydata-goertek-650mah.dtsi b/qcom/fg-gen4-batterydata-goertek-650mah.dtsi
new file mode 100644
index 00000000..f85b7aa3
--- /dev/null
+++ b/qcom/fg-gen4-batterydata-goertek-650mah.dtsi
@@ -0,0 +1,123 @@
+qcom,5376013_goertek_oracle_650mah_pm8150b_sept23rd2021 {
+	/* #5376013_Goertek_Oracle_650mAH_averaged_MasterSlave_Sept23rd2021*/
+	qcom,max-voltage-uv = <4480000>;
+	qcom,fg-cc-cv-threshold-mv = <4470>;
+	qcom,nom-batt-capacity-mah = <650>;
+	qcom,batt-id-kohm = <100>;
+	qcom,battery-beta = <4250>;
+	qcom,therm-room-temp = <100000>;
+	qcom,battery-type = "goertek_oracle_650mah_pm8150b_sept23rd2021";
+	qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>;
+	qcom,therm-center-offset = <0x70>;
+	qcom,therm-pull-up = <100>;
+	qcom,rslow-normal-coeffs = <0x3b 0xf2 0x34 0x0b>;
+	qcom,rslow-low-coeffs = <0x3f 0x0d 0x0c 0xea>;
+	qcom,checksum = <0x4B53>;
+	qcom,gui-version = "PM855GUI - 1.0.0.14";
+	qcom,fg-profile-data = [
+		 09 00 2F 01
+		 F8 05 9C 03
+		 0F FC 00 00
+		 3D CC 0D A2
+		 CC 87 E0 C2
+		 F1 C5 80 87
+		 52 00 3B F2
+		 34 0B FE D5
+		 9A E2 CE 07
+		 32 00 6E F2
+		 15 E2 4A E2
+		 62 13 97 F2
+		 FA C5 F1 1A
+		 15 07 DE CD
+		 60 00 42 00
+		 40 00 3E 00
+		 39 00 3D 00
+		 3C 00 41 00
+		 51 00 54 00
+		 4C 00 60 00
+		 34 00 3F 00
+		 40 00 38 00
+		 44 00 36 00
+		 61 64 4A 00
+		 3B E8 3E 00
+		 60 F0 21 00
+		 28 08 23 18
+		 30 18 3D 00
+		 2A 18 53 40
+		 30 58 2A 07
+		 33 00 D8 00
+		 6F 1C 14 0B
+		 1C 02 59 0D
+		 6E 19 D9 13
+		 4E 0D 1E 1B
+		 B6 18 43 33
+		 78 3D 80 03
+		 4F 1B 3C 1F
+		 2A 05 63 0B
+		 30 05 C3 19
+		 85 0A EC 0D
+		 6B 0B C4 17
+		 68 1A C5 2D
+		 60 3B 85 20
+		 ED 1E 75 F5
+		 3E F3 40 F5
+		 FE 19 3D EA
+		 97 04 D5 CA
+		 E3 17 1E A2
+		 BA 84 0E CA
+		 87 C0 09 80
+		 B6 03 29 FD
+		 B7 03 1C 05
+		 00 F8 87 E4
+		 04 D2 CB DF
+		 50 E2 8D CC
+		 E4 25 30 00
+		 E8 E6 85 02
+		 EF 06 7E 00
+		 CE 07 32 00
+		 15 03 56 02
+		 C3 05 C9 05
+		 62 04 42 02
+		 C4 02 49 01
+		 EB 05 60 00
+		 39 00 46 00
+		 47 64 4B 00
+		 52 08 53 10
+		 52 08 51 00
+		 50 00 3F 08
+		 60 08 54 00
+		 5B 20 5B 38
+		 58 48 6B 15
+		 74 00 5E 08
+		 6B 10 60 00
+		 6C 00 60 00
+		 77 08 69 08
+		 70 00 5F 20
+		 73 38 7E 48
+		 60 18 6F 00
+		 72 08 8B 10
+		 D8 08 7F 23
+		 9F 04 F1 02
+		 83 05 E1 1C
+		 27 22 DF 3D
+		 4E 4A C7 18
+		 7B 02 65 04
+		 A4 03 8E 17
+		 3F 0A 8C 21
+		 99 05 4E 02
+		 25 04 9A 1C
+		 3B 02 F0 05
+		 4A 02 C4 18
+		 0F 02 69 05
+		 49 02 87 00
+		 38 22 36 05
+		 9E 02 C3 05
+		 65 1C 21 02
+		 D7 04 89 03
+		 B0 18 07 02
+		 67 05 59 02
+		 91 00 10 03
+		 C0 00 FA 00
+		 93 02 00 00
+	];
+};
diff --git a/qcom/khaje-atp-overlay.dts b/qcom/khaje-atp-overlay.dts
new file mode 100644
index 00000000..bc5789fc
--- /dev/null
+++ b/qcom/khaje-atp-overlay.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-atp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Khaje ATP";
+	compatible = "qcom,khaje-atp", "qcom,khaje", "qcom,atp";
+	qcom,msm-id = <518 0x10000>;
+	qcom,board-id = <33 0>;
+	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
+
diff --git a/qcom/khaje-atp.dts b/qcom/khaje-atp.dts
new file mode 100644
index 00000000..fc94ce2e
--- /dev/null
+++ b/qcom/khaje-atp.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-atp.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Khaje ATP";
+	compatible = "qcom,khaje-atp", "qcom,khaje", "qcom,atp";
+	qcom,board-id = <33 0>;
+	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
+
diff --git a/qcom/khaje-atp.dtsi b/qcom/khaje-atp.dtsi
new file mode 100644
index 00000000..50b6b9a1
--- /dev/null
+++ b/qcom/khaje-atp.dtsi
@@ -0,0 +1,309 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/input.h>
+#include "bengal-audio-overlay.dtsi"
+#include "khaje-sde-display.dtsi"
+#include "khaje-pm7250b.dtsi"
+
+&pm6125_gpios {
+	eldo9_pin {
+		usb_eldo9:gpio@c000 {
+			pins = "gpio1";
+			function = "normal";
+			qcom,drive-strength = <2>;
+			power-source = <0>;
+			bias-disable;
+			output-high;
+		};
+	};
+};
+
+&soc {
+	vdda_usb_ss_dp_core: vdda_usb_ss_dp_core {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_supply";
+		regulator-min-microvolt = <880000>;
+		regulator-max-microvolt = <880000>;
+		enable-active-high;
+		gpio = <&pm6125_gpios 1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb_eldo9>;
+	};
+};
+
+&sdhc_1 {
+	vdd-supply = <&L24A>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 570000>;
+
+	vdd-io-supply = <&L11A>;
+	qcom,vdd-io-always-on;
+	qcom,vdd-io-lpm-sup;
+	qcom,vdd-io-voltage-level = <1800000 1800000>;
+	qcom,vdd-io-current-level = <0 325000>;
+
+	pinctrl-names = "active", "sleep";
+	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+					&sdc1_rclk_on>;
+	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+					&sdc1_rclk_off>;
+
+	status = "ok";
+};
+
+&sdhc_2 {
+	vdd-supply = <&L22A>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 800000>;
+
+	vdd-io-supply = <&L5A>;
+	qcom,vdd-io-voltage-level = <1800000 2960000>;
+	qcom,vdd-io-current-level = <0 22000>;
+
+	vdd-io-bias-supply = <&L7A>;
+	qcom,vdd-io-bias-voltage-level = <1256000 1256000>;
+	qcom,vdd-io-bias-current-level = <0 6000>;
+
+	pinctrl-names = "active", "sleep";
+	pinctrl-0 = <&sdc2_clk_on  &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+	cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>;
+
+	status = "ok";
+};
+
+&ufsphy_mem {
+	compatible = "qcom,ufs-phy-qmp-v4";
+
+	vdda-phy-supply = <&L4A>; /* 0.9v */
+	vdda-pll-supply = <&L18A>; /* 1.8v */
+	vdda-phy-max-microamp = <85700>;
+	vdda-pll-max-microamp = <18300>;
+
+	status = "ok";
+};
+
+&ufshc_mem {
+	vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+	vdd-hba-fixed-regulator;
+	vcc-supply = <&L24A>;
+	vcc-voltage-level = <2950000 2960000>;
+	vccq2-supply = <&L11A>;
+	vccq2-voltage-level = <1800000 1800000>;
+	vcc-max-microamp = <800000>;
+	vccq2-max-microamp = <800000>;
+	vccq2-pwr-collapse-sup;
+
+	qcom,vddp-ref-clk-supply = <&L18A>;
+	qcom,vddp-ref-clk-max-microamp = <100>;
+	qcom,vddp-ref-clk-min-uV = <1232000>;
+	qcom,vddp-ref-clk-max-uV = <1232000>;
+
+	status = "ok";
+};
+
+&usb_qmp_dp_phy {
+	vdd-supply = <&vdda_usb_ss_dp_core>;
+};
+
+&pm6125_vadc {
+	pinctrl-0 = <&camera_therm_default &emmc_therm_default &rf_pa1_therm_default>;
+
+	rf_pa1_therm {
+		reg = <ADC_GPIO4_PU2>;
+		label = "rf_pa1_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+};
+
+&pm6125_adc_tm {
+	io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>,
+			<&pm6125_vadc ADC_AMUX_THM2_PU2>,
+			<&pm6125_vadc ADC_XO_THERM_PU2>,
+			<&pm6125_vadc ADC_GPIO4_PU2>;
+
+	rf_pa1_therm {
+		reg = <ADC_GPIO4_PU2>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+};
+
+&thermal_zones {
+	rf-pa1-therm-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm6125_adc_tm ADC_GPIO4_PU2>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+};
+
+&pm6125_gpios {
+
+	rf_pa1_therm {
+		rf_pa1_therm_default: rf_pa1_therm_default {
+			pins = "gpio7";
+			 bias-high-impedance;
+		};
+	};
+
+	key_vol_up {
+		key_vol_up_default: key_vol_up_default {
+			pins = "gpio5";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+			power-source = <0>;
+		};
+	};
+};
+
+&soc {
+	gpio_keys {
+		compatible = "gpio-keys";
+		label = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_vol_up_default>;
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_VOLUMEUP>;
+			linux,can-disable;
+			debounce-interval = <15>;
+			gpio-key,wakeup;
+		};
+	};
+};
+
+&pm7250b_charger {
+	status = "ok";
+	io-channels = <&pm7250b_vadc ADC_USB_IN_V_16>,
+		      <&pm7250b_vadc ADC_USB_IN_I>,
+		      <&pm7250b_vadc ADC_CHG_TEMP>,
+		      <&pm7250b_vadc ADC_DIE_TEMP>,
+		      <&pm7250b_vadc ADC_AMUX_THM3_PU2>,
+		      <&pm7250b_vadc ADC_SBUx>,
+		      <&pm7250b_vadc ADC_VPH_PWR>;
+	io-channel-names = "usb_in_voltage",
+			   "usb_in_current",
+			   "chg_temp",
+			   "die_temp",
+			   "conn_temp",
+			   "sbux_res",
+			   "vph_voltage";
+	qcom,batteryless-platform;
+	qcom,sec-charger-config = <0>;
+	qcom,auto-recharge-soc = <98>;
+	qcom,step-charging-enable;
+	qcom,sw-jeita-enable;
+	qcom,charger-temp-max = <800>;
+	qcom,suspend-input-on-debug-batt;
+};
+
+&pm7250b_qg {
+	status = "ok";
+	io-channels = <&pm7250b_vadc ADC_BAT_THERM_PU2>,
+		      <&pm7250b_vadc ADC_BAT_ID_PU2>;
+	io-channel-names = "batt-therm",
+			   "batt-id";
+	qcom,qg-iterm-ma = <150>;
+	qcom,hold-soc-while-full;
+	qcom,linearize-soc;
+	qcom,cl-feedback-on;
+};
+
+&pm8008_8 {
+	status = "disabled";
+};
+
+&pm8008_9 {
+	status = "disabled";
+};
+
+&pm6125_pwm {
+	status = "okay";
+};
+
+&dsi_nt36672e_fhd_plus_90hz_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+	pwms = <&pm6125_pwm 0 0>;
+	qcom,bl-pmic-pwm-period-usecs = <100>;
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,platform-reset-gpio = <&tlmm 82 0>;
+	qcom,platform-en-gpio = <&pm7250b_gpios 5 0>;
+	qcom,platform-bklight-en-gpio = <&pm7250b_gpios 1 0>;
+	/delete-property/ qcom,esd-check-enabled;
+};
+
+&dsi_sim_vid {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&sde_dsi {
+	qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_90hz_video>;
+	pinctrl-0 = <&sde_dsi_active &sde_te_active &disp_lcd_bias_en_default>;
+};
+
+&qupv3_se2_i2c {
+	status = "okay";
+	qcom,i2c-touch-active="novatek,NVT-ts";
+
+	novatek@62 {
+		compatible = "novatek,NVT-ts";
+		reg = <0x62>;
+		status = "ok";
+
+		interrupt-parent = <&tlmm>;
+		interrupts = <80 0x2008>;
+		pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+				"pmx_ts_release";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+		pinctrl-2 = <&ts_release>;
+
+		novatek,reset-gpio = <&tlmm 86 0x00>;
+		novatek,irq-gpio = <&tlmm 80 0x2008>;
+
+		panel = <&dsi_nt36672e_fhd_plus_90hz_video>;
+	};
+};
+
+&pm7250b_charger {
+	dpdm-supply = <&usb2_phy0>;
+
+	smb5_vbus: qcom,smb5-vbus {
+		regulator-name = "smb5-vbus";
+	};
+
+	smb5_vconn: qcom,smb5-vconn {
+		regulator-name = "smb5-vconn";
+	};
+};
+
+&pm7250b_pdphy {
+	vdd-pdphy-supply = <&L15A>;
+	vbus-supply = <&smb5_vbus>;
+	vconn-supply = <&smb5_vconn>;
+};
+
+&usb0 {
+	extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>;
+};
diff --git a/qcom/khaje-idp-nopmi-overlay.dts b/qcom/khaje-idp-nopmi-overlay.dts
new file mode 100644
index 00000000..566b24f0
--- /dev/null
+++ b/qcom/khaje-idp-nopmi-overlay.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-idp-nopmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. KHAJE IDP nopmi";
+	compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+	qcom,msm-id = <518 0x10000>;
+	qcom,board-id = <0x10022 0>;
+	qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
+};
diff --git a/qcom/khaje-idp-nopmi.dts b/qcom/khaje-idp-nopmi.dts
new file mode 100644
index 00000000..31d8418b
--- /dev/null
+++ b/qcom/khaje-idp-nopmi.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-idp-nopmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. KHAJE IDP nopmi";
+	compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+	qcom,board-id = <0x10022 0>;
+	qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
+};
diff --git a/qcom/khaje-idp-nopmi.dtsi b/qcom/khaje-idp-nopmi.dtsi
new file mode 100644
index 00000000..ec89efa1
--- /dev/null
+++ b/qcom/khaje-idp-nopmi.dtsi
@@ -0,0 +1,30 @@
+#include "khaje-idp.dtsi"
+
+&dsi_td4330_truly_v2_video {
+	/delete-property/ qcom,esd-check-enabled;
+};
+
+&dsi_td4330_truly_v2_cmd {
+	/delete-property/ qcom,esd-check-enabled;
+};
+
+&dsi_nt36672e_fhd_plus_90hz_video {
+	/delete-property/ qcom,esd-check-enabled;
+};
+
+&qupv3_se2_i2c {
+	synaptics_tcm@20 {
+		status = "disabled";
+	};
+
+	novatek@62 {
+		status = "disabled";
+	};
+};
+
+&usb0 {
+	/delete-property/ extcon;
+	dwc3@4e00000 {
+		dr_mode = "peripheral";
+	};
+};
diff --git a/qcom/khaje-idp-overlay.dts b/qcom/khaje-idp-overlay.dts
new file mode 100644
index 00000000..dea903c5
--- /dev/null
+++ b/qcom/khaje-idp-overlay.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-idp.dtsi"
+#include "khaje-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Khaje IDP";
+	compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+	qcom,msm-id = <518 0x10000>;
+	qcom,board-id = <0x10022 0>;
+	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
diff --git a/qcom/khaje-idp-pm7250b.dtsi b/qcom/khaje-idp-pm7250b.dtsi
new file mode 100644
index 00000000..7008c7e9
--- /dev/null
+++ b/qcom/khaje-idp-pm7250b.dtsi
@@ -0,0 +1,156 @@
+#include "khaje-pm7250b.dtsi"
+#include "khaje-thermal-pm7250b-overlay.dtsi"
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+&soc {
+	mtp_batterydata: qcom,battery-data {
+		qcom,batt-id-range-pct = <15>;
+		#include "qg-batterydata-alium-3600mah.dtsi"
+	};
+};
+
+&pm7250b_gpios {
+	pm7250b_smb_int_default: pm7250b_smb_int_default {
+		pins = "gpio6";
+		function = "gpio";
+		input-enable;
+		bias-pull-up;
+		qcom,pull-up-strength = <PMIC_GPIO_PULL_UP_30>;
+		power-source = <0>;
+	 };
+};
+
+&qupv3_se1_i2c {
+	status = "ok";
+	#include "smb1355.dtsi"
+};
+
+&smb1355 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pm7250b_smb_int_default>;
+	status = "ok";
+};
+
+&smb1355_charger {
+	qcom,parallel-mode = <1>;
+	qcom,hw-die-temp-mitigation;
+	status = "ok";
+};
+
+&pm7250b_charger {
+	status = "ok";
+	io-channels = <&pm7250b_vadc ADC_USB_IN_V_16>,
+		      <&pm7250b_vadc ADC_USB_IN_I>,
+		      <&pm7250b_vadc ADC_CHG_TEMP>,
+		      <&pm7250b_vadc ADC_DIE_TEMP>,
+		      <&pm7250b_vadc ADC_AMUX_THM3_PU2>,
+		      <&pm7250b_vadc ADC_SBUx>,
+		      <&pm7250b_vadc ADC_VPH_PWR>,
+		      <&pm7250b_vadc ADC_AMUX_THM1_PU2>;
+	io-channel-names = "usb_in_voltage",
+			   "usb_in_current",
+			   "chg_temp",
+			   "die_temp",
+			   "conn_temp",
+			   "sbux_res",
+			   "vph_voltage",
+			   "skin_temp";
+	qcom,battery-data = <&mtp_batterydata>;
+	qcom,sec-charger-config = <2>;
+	qcom,auto-recharge-soc = <98>;
+	qcom,step-charging-enable;
+	qcom,sw-jeita-enable;
+	qcom,charger-temp-max = <800>;
+	qcom,smb-temp-max = <800>;
+	qcom,suspend-input-on-debug-batt;
+	qcom,fcc-stepping-enable;
+	qcom,fcc-step-delay-ms = <100>;
+	qcom,fcc-step-size-ua = <100000>;
+	qcom,smb-internal-pull-kohm = <0>;
+	qcom,en-skin-therm-mitigation;
+	qcom,hvdcp3-standalone-config;
+};
+
+&pm7250b_qg {
+	status = "ok";
+	io-channels = <&pm7250b_vadc ADC_BAT_THERM_PU2>,
+		      <&pm7250b_vadc ADC_BAT_ID_PU2>;
+	io-channel-names = "batt-therm",
+			   "batt-id";
+	qcom,battery-data = <&mtp_batterydata>;
+	qcom,qg-iterm-ma = <100>;
+	qcom,hold-soc-while-full;
+	qcom,linearize-soc;
+	qcom,cl-feedback-on;
+	qcom,tcss-enable;
+	qcom,fvss-enable;
+	qcom,fvss-vbatt-mv = <3500>;
+	qcom,bass-enable;
+	qcom,vbatt-cutoff-mv = <3400>;
+	qcom,vbatt-low-mv = <3500>;
+	qcom,vbatt-low-cold-mv = <3800>;
+	qcom,vbatt-empty-mv = <3200>;
+	qcom,vbatt-empty-cold-mv = <3100>;
+};
+
+&sde_dsi {
+	pinctrl-0 = <&sde_dsi_active &sde_te_active &disp_lcd_bias_en_default>;
+};
+
+&dsi_td4330_truly_v2_video {
+	qcom,platform-en-gpio = <&pm7250b_gpios 5 0>;
+	qcom,platform-bklight-en-gpio = <&pm7250b_gpios 1 0>;
+};
+
+&dsi_td4330_truly_v2_cmd {
+	qcom,platform-en-gpio = <&pm7250b_gpios 5 0>;
+	qcom,platform-bklight-en-gpio = <&pm7250b_gpios 1 0>;
+};
+
+&dsi_nt36672e_fhd_plus_90hz_video {
+	qcom,platform-en-gpio = <&pm7250b_gpios 5 0>;
+	qcom,platform-bklight-en-gpio = <&pm7250b_gpios 1 0>;
+};
+
+&dsi_nt36672e_fhd_plus_120hz_video {
+	qcom,platform-en-gpio = <&pm7250b_gpios 5 0>;
+	qcom,platform-bklight-en-gpio = <&pm7250b_gpios 1 0>;
+};
+
+&cam_res_mgr_label {
+	gpios = <&pm7250b_gpios 4 0>;
+};
+
+&led_flash_rear {
+	gpios = <&pm7250b_gpios 4 0>;
+};
+
+&led_flash_rear_aux {
+	gpios = <&pm7250b_gpios 4 0>;
+};
+
+&led_flash_rear_aux2 {
+	gpios = <&pm7250b_gpios 4 0>;
+};
+
+&pm7250b_charger {
+	dpdm-supply = <&usb2_phy0>;
+
+	smb5_vbus: qcom,smb5-vbus {
+		regulator-name = "smb5-vbus";
+	};
+
+	smb5_vconn: qcom,smb5-vconn {
+		regulator-name = "smb5-vconn";
+	};
+};
+
+&pm7250b_pdphy {
+	vdd-pdphy-supply = <&L15A>;
+	vbus-supply = <&smb5_vbus>;
+	vconn-supply = <&smb5_vconn>;
+};
+
+&usb0 {
+	extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>;
+};
diff --git a/qcom/khaje-idp-pm8010-overlay.dts b/qcom/khaje-idp-pm8010-overlay.dts
new file mode 100644
index 00000000..6031d889
--- /dev/null
+++ b/qcom/khaje-idp-pm8010-overlay.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-idp.dtsi"
+#include "khaje-idp-pm8010.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Khaje IDP with PM8010";
+	compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+	qcom,msm-id = <518 0x10000>;
+	qcom,board-id = <0x10222 0>;
+	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
+
diff --git a/qcom/khaje-idp-pm8010.dts b/qcom/khaje-idp-pm8010.dts
new file mode 100644
index 00000000..85b55f04
--- /dev/null
+++ b/qcom/khaje-idp-pm8010.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-idp.dtsi"
+#include "khaje-idp-pm8010.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. KHAJE IDP with PM8010";
+	compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+	qcom,board-id = <0x10222 0>;
+	qcom,pmic-id = <0x02D 0x2E 0x0 0x0>;
+};
+
diff --git a/qcom/khaje-idp-pm8010.dtsi b/qcom/khaje-idp-pm8010.dtsi
new file mode 100644
index 00000000..5979c7c9
--- /dev/null
+++ b/qcom/khaje-idp-pm8010.dtsi
@@ -0,0 +1,34 @@
+&soc {
+};
+
+&pm8008_regulators {
+	compatible = "qcom,pm8010-regulator";
+};
+
+&L1P {
+	qcom,min-dropout-voltage = <40000>;
+};
+
+&L2P {
+	qcom,min-dropout-voltage = <64000>;
+};
+
+&L3P {
+	qcom,min-dropout-voltage = <96000>;
+};
+
+&L4P {
+	qcom,min-dropout-voltage = <136000>;
+};
+
+&L5P {
+	qcom,min-dropout-voltage = <176000>;
+};
+
+&L6P {
+	qcom,min-dropout-voltage = <168000>;
+};
+
+&L7P {
+	qcom,min-dropout-voltage = <80000>;
+};
diff --git a/qcom/khaje-idp-usbc-overlay.dts b/qcom/khaje-idp-usbc-overlay.dts
new file mode 100644
index 00000000..4993cdae
--- /dev/null
+++ b/qcom/khaje-idp-usbc-overlay.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-idp.dtsi"
+#include "khaje-idp-pm7250b.dtsi"
+#include "khaje-idp-usbc.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. KHAJE IDP USBC Audio";
+	compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+	qcom,msm-id = <518 0x10000>;
+	qcom,board-id = <0x1010022 0>;
+	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
+
diff --git a/qcom/khaje-idp-usbc.dts b/qcom/khaje-idp-usbc.dts
new file mode 100644
index 00000000..7a62a6d1
--- /dev/null
+++ b/qcom/khaje-idp-usbc.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-idp.dtsi"
+#include "khaje-idp-pm7250b.dtsi"
+#include "khaje-idp-usbc.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. KHAJE IDP USBC Audio";
+	compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+	qcom,msm-id = <518 0x10000>;
+	qcom,board-id = <0x1010022 0>;
+	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
+
diff --git a/qcom/khaje-idp-usbc.dtsi b/qcom/khaje-idp-usbc.dtsi
new file mode 100644
index 00000000..2a627c57
--- /dev/null
+++ b/qcom/khaje-idp-usbc.dtsi
@@ -0,0 +1,6 @@
+&bengal_snd {
+	qcom,msm-mbhc-usbc-audio-supported = <1>;
+	qcom,msm-mbhc-hphl-swh = <0>;
+	qcom,msm-mbhc-gnd-swh = <0>;
+};
+
diff --git a/qcom/khaje-idp.dts b/qcom/khaje-idp.dts
new file mode 100644
index 00000000..3787ab3d
--- /dev/null
+++ b/qcom/khaje-idp.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-idp.dtsi"
+#include "khaje-idp-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. KHAJE IDP";
+	compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+	qcom,board-id = <0x10022 0>;
+	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
diff --git a/qcom/khaje-idp.dtsi b/qcom/khaje-idp.dtsi
new file mode 100644
index 00000000..e9b0f263
--- /dev/null
+++ b/qcom/khaje-idp.dtsi
@@ -0,0 +1,362 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/input.h>
+#include "bengal-audio-overlay.dtsi"
+#include "camera/khaje-camera-sensor-idp.dtsi"
+#include "bengal-thermal-overlay.dtsi"
+#include "khaje-sde-display.dtsi"
+
+&qupv3_se4_2uart {
+	status = "ok";
+};
+
+&pm6125_vadc {
+	pinctrl-0 = <&camera_therm_default &emmc_therm_default &rf_pa1_therm_default>;
+
+	rf_pa1_therm {
+		reg = <ADC_GPIO4_PU2>;
+		label = "rf_pa1_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+};
+
+&pm6125_adc_tm {
+	io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>,
+			<&pm6125_vadc ADC_AMUX_THM2_PU2>,
+			<&pm6125_vadc ADC_XO_THERM_PU2>,
+			<&pm6125_vadc ADC_GPIO4_PU2>;
+
+	rf_pa1_therm {
+		reg = <ADC_GPIO4_PU2>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+};
+
+&thermal_zones {
+	rf-pa1-therm-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm6125_adc_tm ADC_GPIO4_PU2>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+};
+
+&pm6125_gpios {
+
+	rf_pa1_therm {
+		rf_pa1_therm_default: rf_pa1_therm_default {
+			pins = "gpio7";
+			 bias-high-impedance;
+		};
+	};
+
+	key_vol_up {
+		key_vol_up_default: key_vol_up_default {
+			pins = "gpio5";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+			power-source = <0>;
+		};
+	};
+
+	eldo9_pin {
+		usb_eldo9:gpio@c000 {
+			pins = "gpio1";
+			function = "normal";
+			qcom,drive-strength = <2>;
+			power-source = <0>;
+			bias-disable;
+			output-high;
+		};
+	};
+};
+
+&soc {
+	gpio_keys {
+		compatible = "gpio-keys";
+		label = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_vol_up_default>;
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_VOLUMEUP>;
+			linux,can-disable;
+			debounce-interval = <15>;
+			gpio-key,wakeup;
+		};
+	};
+
+	vdda_usb_ss_dp_core: vdda_usb_ss_dp_core {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_supply";
+		regulator-min-microvolt = <880000>;
+		regulator-max-microvolt = <880000>;
+		enable-active-high;
+		gpio = <&pm6125_gpios 1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb_eldo9>;
+	};
+};
+
+&usb_qmp_dp_phy {
+	vdd-supply = <&vdda_usb_ss_dp_core>;
+};
+
+&qupv3_se1_i2c {
+	awinic@64 {
+		compatible = "awinic,aw2016_led";
+		reg = <0x64>;
+
+		awinic,red {
+			awinic,name = "red";
+			awinic,id = <0>;
+			awinic,imax = <2>;
+			awinic,led-current = <3>;
+			awinic,max-brightness = <255>;
+			awinic,rise-time-ms = <6>;
+			awinic,hold-time-ms = <0>;
+			awinic,fall-time-ms = <6>;
+			awinic,off-time-ms = <4>;
+		};
+
+		awinic,green {
+			awinic,name = "green";
+			awinic,id = <1>;
+			awinic,imax = <2>;
+			awinic,led-current = <3>;
+			awinic,max-brightness = <255>;
+			awinic,rise-time-ms = <6>;
+			awinic,hold-time-ms = <0>;
+			awinic,fall-time-ms = <6>;
+			awinic,off-time-ms = <4>;
+		};
+
+		awinic,blue {
+			awinic,name = "blue";
+			awinic,id = <2>;
+			awinic,imax = <2>;
+			awinic,led-current = <3>;
+			awinic,max-brightness = <255>;
+			awinic,rise-time-ms = <6>;
+			awinic,hold-time-ms = <0>;
+			awinic,fall-time-ms = <6>;
+			awinic,off-time-ms = <4>;
+		};
+
+	};
+};
+
+&qupv3_se1_i2c {
+	status = "ok";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	nq@28 {
+		compatible = "qcom,nq-nci";
+		reg = <0x28>;
+		qcom,nq-irq = <&tlmm 70 0x00>;
+		qcom,nq-ven = <&tlmm 69 0x00>;
+		qcom,nq-firm = <&tlmm 31 0x00>;
+		qcom,nq-clkreq = <&tlmm 71 0x00>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <70 0>;
+		interrupt-names = "nfc_irq";
+		pinctrl-names = "nfc_active", "nfc_suspend";
+		pinctrl-0 = <&nfc_int_active &nfc_enable_active
+				&nfc_clk_req_active>;
+		pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+				&nfc_clk_req_suspend>;
+	};
+};
+
+&sdhc_1 {
+	vdd-supply = <&L24A>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 570000>;
+
+	vdd-io-supply = <&L11A>;
+	qcom,vdd-io-always-on;
+	qcom,vdd-io-lpm-sup;
+	qcom,vdd-io-voltage-level = <1800000 1800000>;
+	qcom,vdd-io-current-level = <0 325000>;
+
+	pinctrl-names = "active", "sleep";
+	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+					&sdc1_rclk_on>;
+	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+					&sdc1_rclk_off>;
+
+	status = "ok";
+};
+
+&sdhc_2 {
+	vdd-supply = <&L22A>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 800000>;
+
+	vdd-io-supply = <&L5A>;
+	qcom,vdd-io-voltage-level = <1800000 2960000>;
+	qcom,vdd-io-current-level = <0 22000>;
+
+	vdd-io-bias-supply = <&L7A>;
+	qcom,vdd-io-bias-voltage-level = <1256000 1256000>;
+	qcom,vdd-io-bias-current-level = <0 6000>;
+
+	pinctrl-names = "active", "sleep";
+	pinctrl-0 = <&sdc2_clk_on  &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+	cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>;
+
+	status = "ok";
+};
+
+&ufsphy_mem {
+	compatible = "qcom,ufs-phy-qmp-v4";
+
+	vdda-phy-supply = <&L4A>; /* 0.9v */
+	vdda-pll-supply = <&L18A>; /* 1.8v */
+	vdda-phy-max-microamp = <85700>;
+	vdda-pll-max-microamp = <18300>;
+
+	status = "ok";
+};
+
+&ufshc_mem {
+	vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+	vdd-hba-fixed-regulator;
+	vcc-supply = <&L24A>;
+	vcc-voltage-level = <2950000 2960000>;
+	vccq2-supply = <&L11A>;
+	vccq2-voltage-level = <1800000 1800000>;
+	vcc-max-microamp = <800000>;
+	vccq2-max-microamp = <800000>;
+	vccq2-pwr-collapse-sup;
+
+	qcom,vddp-ref-clk-supply = <&L18A>;
+	qcom,vddp-ref-clk-max-microamp = <100>;
+	qcom,vddp-ref-clk-min-uV = <1232000>;
+	qcom,vddp-ref-clk-max-uV = <1232000>;
+
+	status = "ok";
+};
+
+&pm6125_pwm {
+	status = "ok";
+};
+
+&dsi_td4330_truly_v2_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+	pwms = <&pm6125_pwm 0 0>;
+	qcom,bl-pmic-pwm-period-usecs = <100>;
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&dsi_td4330_truly_v2_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+	pwms = <&pm6125_pwm 0 0>;
+	qcom,bl-pmic-pwm-period-usecs = <100>;
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,platform-te-gpio = <&tlmm 81 0>;
+	qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&dsi_nt36672e_fhd_plus_90hz_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+	pwms = <&pm6125_pwm 0 0>;
+	qcom,bl-pmic-pwm-period-usecs = <100>;
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&dsi_nt36672e_fhd_plus_120hz_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+	pwms = <&pm6125_pwm 0 0>;
+	qcom,bl-pmic-pwm-period-usecs = <100>;
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&dsi_sim_vid {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&sde_dsi {
+	qcom,dsi-default-panel = <&dsi_td4330_truly_v2_video>;
+};
+
+&qupv3_se2_i2c {
+	status = "okay";
+	qcom,i2c-touch-active="synaptics,tcm-i2c";
+
+	synaptics_tcm@20 {
+		compatible = "synaptics,tcm-i2c";
+		reg = <0x20>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <80 0x2008>;
+		pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+			"pmx_ts_release";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+		pinctrl-2 = <&ts_release>;
+		synaptics,irq-gpio = <&tlmm 80 0x2008>;
+		synaptics,irq-on-state = <0>;
+		synaptics,reset-gpio = <&tlmm 86 0x00>;
+		synaptics,reset-on-state = <0>;
+		synaptics,reset-active-ms = <20>;
+		synaptics,reset-delay-ms = <200>;
+		synaptics,power-delay-ms = <200>;
+		synaptics,ubl-i2c-addr = <0x20>;
+		synaptics,extend_report;
+		synaptics,firmware-name = "synaptics_firmware_k.img";
+
+		panel = <&dsi_td4330_truly_v2_video &dsi_td4330_truly_v2_cmd>;
+	};
+
+	novatek@62 {
+		compatible = "novatek,NVT-ts";
+		reg = <0x62>;
+		status = "ok";
+
+		interrupt-parent = <&tlmm>;
+		interrupts = <80 0x2008>;
+		pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+			"pmx_ts_release";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+		pinctrl-2 = <&ts_release>;
+
+		novatek,reset-gpio = <&tlmm 86 0x00>;
+		novatek,irq-gpio = <&tlmm 80 0x2008>;
+
+		panel = <&dsi_nt36672e_fhd_plus_90hz_video
+			&dsi_nt36672e_fhd_plus_120hz_video>;
+	};
+
+};
diff --git a/qcom/khaje-idps-display-90hz-overlay.dts b/qcom/khaje-idps-display-90hz-overlay.dts
new file mode 100644
index 00000000..02711ed2
--- /dev/null
+++ b/qcom/khaje-idps-display-90hz-overlay.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-idp.dtsi"
+#include "khaje-idp-pm7250b.dtsi"
+#include "khaje-idps-display-90hz.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. KHAJE IDPS + 90Hz";
+	compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+	qcom,msm-id = <518 0x10000>;
+	qcom,board-id = <0x10122 0>;
+	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
diff --git a/qcom/khaje-idps-display-90hz.dts b/qcom/khaje-idps-display-90hz.dts
new file mode 100644
index 00000000..a9fc4d48
--- /dev/null
+++ b/qcom/khaje-idps-display-90hz.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-idp.dtsi"
+#include "khaje-idp-pm7250b.dtsi"
+#include "khaje-idps-display-90hz.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. KHAJE IDPS + 90Hz";
+	compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+	qcom,board-id = <0x10122 0>;
+	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
diff --git a/qcom/khaje-idps-display-90hz.dtsi b/qcom/khaje-idps-display-90hz.dtsi
new file mode 100644
index 00000000..f42bc201
--- /dev/null
+++ b/qcom/khaje-idps-display-90hz.dtsi
@@ -0,0 +1,6 @@
+&soc {
+};
+
+&sde_dsi {
+	qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_90hz_video>;
+};
diff --git a/qcom/khaje-pinctrl.dtsi b/qcom/khaje-pinctrl.dtsi
new file mode 100644
index 00000000..5c85f5f3
--- /dev/null
+++ b/qcom/khaje-pinctrl.dtsi
@@ -0,0 +1,140 @@
+#include "bengal-pinctrl.dtsi"
+
+&tlmm {
+		compatible = "qcom,khaje-pinctrl";
+
+		cam_flash_torch_active: cam_flash_torch_active {
+			/* TORCH */
+			mux {
+				pins = "gpio85";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio85";
+				bias-disable; /* No PULL */
+				drive-strength = <2>; /* 2 MA */
+			};
+		};
+
+		cam_flash_torch_suspend: cam_flash_torch_suspend {
+			/* TORCH */
+			mux {
+				pins = "gpio85";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio85";
+				bias-pull-down; /* PULL DOWN */
+				drive-strength = <2>; /* 2 MA */
+				output-low;
+			};
+		};
+
+		cam_flash_tx_active: cam_flash_tx_active {
+			/* TX */
+			mux {
+				pins = "gpio93";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio93";
+				bias-disable; /* No PULL */
+				drive-strength = <2>; /* 2 MA */
+			};
+		};
+
+		cam_flash_tx_suspend: cam_flash_tx_suspend {
+			/* TX */
+			mux {
+				pins = "gpio93";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio93";
+				bias-pull-down; /* PULL DOWN */
+				drive-strength = <2>; /* 2 MA */
+				output-low;
+			};
+		};
+
+	nfc {
+			nfc_clk_req_active {
+				/* active state */
+				mux {
+					/* GPIO 71: NFC CLOCK REQUEST */
+					pins = "gpio71";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio71";
+					drive-strength = <2>; /* 2 MA */
+					bias-pull-up;
+				};
+			};
+
+			nfc_clk_req_suspend {
+				/* sleep state */
+				mux {
+					/* GPIO 71: NFC CLOCK REQUEST */
+					pins = "gpio71";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio71";
+					drive-strength = <2>; /* 2 MA */
+					bias-disable;
+				};
+			};
+	};
+
+		pmx_ts_reset_active {
+			ts_reset_active: ts_reset_active {
+				mux {
+					pins = "gpio86";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio86";
+					drive-strength = <8>;
+					bias-pull-up;
+				};
+			};
+		};
+
+		pmx_ts_reset_suspend {
+			ts_reset_suspend: ts_reset_suspend {
+				mux {
+					pins = "gpio86";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio86";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+		};
+
+		pmx_ts_release {
+			ts_release: ts_release {
+				mux {
+					pins = "gpio80", "gpio86";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio80", "gpio86";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+		};
+};
diff --git a/qcom/khaje-pm7250b.dtsi b/qcom/khaje-pm7250b.dtsi
new file mode 100644
index 00000000..28f98c5b
--- /dev/null
+++ b/qcom/khaje-pm7250b.dtsi
@@ -0,0 +1,89 @@
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include "pm7250b.dtsi"
+
+&pm7250b_clkdiv {
+	clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+};
+
+&pm7250b_vadc {
+	charger_skin_therm@4d {
+		reg = <ADC_AMUX_THM1_PU2>;
+		label = "charger_skin_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	conn_therm@4f {
+		reg = <ADC_AMUX_THM3_PU2>;
+		label = "conn_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+};
+
+&pm7250b_adc_tm {
+	io-channels = <&pm7250b_vadc ADC_AMUX_THM1_PU2>,
+			<&pm7250b_vadc ADC_AMUX_THM3_PU2>;
+
+	/* Channel nodes */
+	charger_skin_therm@4d {
+		reg = <ADC_AMUX_THM1_PU2>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	conn_therm@4f {
+		reg = <ADC_AMUX_THM3_PU2>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+};
+
+&thermal_zones {
+	charger-therm-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm7250b_adc_tm ADC_AMUX_THM1_PU2>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	conn-therm-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm7250b_adc_tm ADC_AMUX_THM3_PU2>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+};
+
+&pm7250b_gpios {
+	disp_lcd_bias_en {
+		disp_lcd_bias_en_default: disp_lcd_bias_en_default {
+			pins = "gpio5";
+			function = "func1";
+			input-disable;
+			output-enable;
+			bias-disable;
+			power-source = <0>;
+			qcom,drive-strength = <2>;
+		};
+	};
+};
diff --git a/qcom/khaje-qrd-hvdcp3p5-overlay.dts b/qcom/khaje-qrd-hvdcp3p5-overlay.dts
new file mode 100644
index 00000000..a5fb87eb
--- /dev/null
+++ b/qcom/khaje-qrd-hvdcp3p5-overlay.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-qrd.dtsi"
+#include "khaje-qrd-pm7250b.dtsi"
+#include "khaje-qrd-hvdcp3p5.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Khaje QRD HVDCP3P5";
+	compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
+	qcom,msm-id = <518 0x10000>;
+	qcom,board-id = <0x1010B 0>;
+	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
diff --git a/qcom/khaje-qrd-hvdcp3p5.dts b/qcom/khaje-qrd-hvdcp3p5.dts
new file mode 100644
index 00000000..7b4d4935
--- /dev/null
+++ b/qcom/khaje-qrd-hvdcp3p5.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-qrd.dtsi"
+#include "khaje-qrd-pm7250b.dtsi"
+#include "khaje-qrd-hvdcp3p5.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. KHAJE QRD HVDCP3P5";
+	compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
+	qcom,board-id = <0x1010B 0>;
+	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
diff --git a/qcom/khaje-qrd-hvdcp3p5.dtsi b/qcom/khaje-qrd-hvdcp3p5.dtsi
new file mode 100644
index 00000000..f87a199d
--- /dev/null
+++ b/qcom/khaje-qrd-hvdcp3p5.dtsi
@@ -0,0 +1,20 @@
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+&pm7250b_gpios {
+	pm7250b_smb_int_default: pm7250b_smb_int_default {
+		pins = "gpio6";
+		function = "gpio";
+		input-enable;
+		bias-pull-up;
+		qcom,pull-up-strength = <PMIC_GPIO_PULL_UP_30>;
+		power-source = <0>;
+	};
+};
+
+&smb1394 {
+	qcom,enable-toggle-stat;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pm7250b_smb_int_default>;
+	interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>;
+	interrupt-parent = <&spmi_bus>;
+};
diff --git a/qcom/khaje-qrd-nopmi-overlay.dts b/qcom/khaje-qrd-nopmi-overlay.dts
new file mode 100644
index 00000000..eab93663
--- /dev/null
+++ b/qcom/khaje-qrd-nopmi-overlay.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-qrd-nopmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. KHAJE QRD nopmi overlay";
+	compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
+	qcom,msm-id = <518 0x10000>;
+	qcom,board-id = <0x1000B 0>;
+	qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
+};
diff --git a/qcom/khaje-qrd-nopmi.dts b/qcom/khaje-qrd-nopmi.dts
new file mode 100644
index 00000000..f36f81e8
--- /dev/null
+++ b/qcom/khaje-qrd-nopmi.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-qrd-nopmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. KHAJE QRD nopmi";
+	compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
+	qcom,board-id = <0x1000B 0>;
+	qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
+};
diff --git a/qcom/khaje-qrd-nopmi.dtsi b/qcom/khaje-qrd-nopmi.dtsi
new file mode 100644
index 00000000..0aff33e9
--- /dev/null
+++ b/qcom/khaje-qrd-nopmi.dtsi
@@ -0,0 +1,35 @@
+#include "khaje-qrd.dtsi"
+
+&sde_dsi {
+	/delete-property/ lab-supply;
+	/delete-property/ ibb-supply;
+};
+
+&dsi_td4330_truly_v2_video {
+	/delete-property/ qcom,esd-check-enabled;
+};
+
+&dsi_td4330_truly_v2_cmd {
+	/delete-property/ qcom,esd-check-enabled;
+};
+
+&qupv3_se2_i2c {
+	synaptics_tcm@20 {
+		status = "disabled";
+	};
+
+	novatek@62 {
+		status = "disabled";
+	};
+
+	focaltech@38 {
+		status = "disabled";
+	};
+};
+
+&usb0 {
+	/delete-property/ extcon;
+	dwc3@4e00000 {
+		dr_mode = "peripheral";
+	};
+};
diff --git a/qcom/khaje-qrd-nowcd9375-overlay.dts b/qcom/khaje-qrd-nowcd9375-overlay.dts
new file mode 100644
index 00000000..17dcc66b
--- /dev/null
+++ b/qcom/khaje-qrd-nowcd9375-overlay.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-qrd.dtsi"
+#include "khaje-qrd-pm7250b.dtsi"
+#include "khaje-qrd-nowcd9375.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Khaje QRD NOWCD9375";
+	compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
+	qcom,msm-id = <518 0x10000>;
+	qcom,board-id = <0x2010B 0>;
+	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
diff --git a/qcom/khaje-qrd-nowcd9375.dts b/qcom/khaje-qrd-nowcd9375.dts
new file mode 100644
index 00000000..891a0705
--- /dev/null
+++ b/qcom/khaje-qrd-nowcd9375.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-qrd.dtsi"
+#include "khaje-qrd-pm7250b.dtsi"
+#include "khaje-qrd-nowcd9375.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. KHAJE QRD NOWCD9375";
+	compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
+	qcom,board-id = <0x2010B 0>;
+	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
diff --git a/qcom/khaje-qrd-nowcd9375.dtsi b/qcom/khaje-qrd-nowcd9375.dtsi
new file mode 100644
index 00000000..05fd5493
--- /dev/null
+++ b/qcom/khaje-qrd-nowcd9375.dtsi
@@ -0,0 +1,17 @@
+#include "khaje-qrd-hvdcp3p5.dtsi"
+
+&wcd937x_codec {
+	status = "disabled";
+};
+
+&wcd937x_rx_slave {
+	status = "disabled";
+};
+
+&wcd937x_tx_slave {
+	status = "disabled";
+};
+
+&bengal_snd {
+	qcom,codec-max-aux-devs = <0>;
+};
diff --git a/qcom/khaje-qrd-overlay.dts b/qcom/khaje-qrd-overlay.dts
new file mode 100644
index 00000000..7c8960f3
--- /dev/null
+++ b/qcom/khaje-qrd-overlay.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-qrd.dtsi"
+#include "khaje-qrd-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Khaje QRD";
+	compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
+	qcom,msm-id = <518 0x10000>;
+	qcom,board-id = <0x1000B 0>;
+	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
+
+&bengal_snd {
+	qcom,wcd-datalane-mismatch = <1>;
+};
diff --git a/qcom/khaje-qrd-pm7250b.dtsi b/qcom/khaje-qrd-pm7250b.dtsi
new file mode 100644
index 00000000..db33ce04
--- /dev/null
+++ b/qcom/khaje-qrd-pm7250b.dtsi
@@ -0,0 +1,192 @@
+#include "khaje-pm7250b.dtsi"
+#include "khaje-thermal-pm7250b-overlay.dtsi"
+
+&sde_dsi {
+	pinctrl-0 = <&sde_dsi_active &sde_te_active &disp_lcd_bias_en_default>;
+};
+
+&dsi_td4330_truly_v2_video {
+	qcom,platform-en-gpio = <&pm7250b_gpios 5 0>;
+	qcom,platform-bklight-en-gpio = <&pm7250b_gpios 1 0>;
+};
+
+&dsi_td4330_truly_v2_cmd {
+	qcom,platform-en-gpio = <&pm7250b_gpios 5 0>;
+	qcom,platform-bklight-en-gpio = <&pm7250b_gpios 1 0>;
+};
+
+&soc {
+	qrd_batterydata: qcom,battery-data {
+		qcom,batt-id-range-pct = <15>;
+		#include "qg-batterydata-atl466271_3300mAh.dtsi"
+	};
+};
+
+&tlmm {
+	smb_int_default: smb_int_default {
+		mux {
+			pins = "gpio105";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio105";
+			bias-pull-up;
+			input-enable;
+		};
+	};
+};
+
+&qupv3_se1_i2c {
+	status = "ok";
+	#include "smb1394.dtsi"
+};
+
+&smb1394 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&smb_int_default>;
+	interrupt-parent = <&tlmm>;
+	interrupt-names = "smb1394";
+	interrupts = <105 IRQ_TYPE_LEVEL_LOW>;
+	status = "ok";
+};
+
+&smb1394_div2_cp_primary {
+	io-channels = <&pm7250b_vadc ADC_AMUX_THM2>;
+	io-channel-names = "die_temp";
+	qcom,parallel-input-mode = <1>;
+	qcom,parallel-output-mode = <2>;
+	status = "ok";
+};
+
+&pm7250b_vadc {
+	smb1390_therm@e {
+		qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_SMB1398_TEMP>;
+	};
+};
+
+&pm7250b_charger {
+	status = "ok";
+	io-channels = <&pm7250b_vadc ADC_USB_IN_V_16>,
+		      <&pm7250b_vadc ADC_USB_IN_I>,
+		      <&pm7250b_vadc ADC_CHG_TEMP>,
+		      <&pm7250b_vadc ADC_DIE_TEMP>,
+		      <&pm7250b_vadc ADC_AMUX_THM3_PU2>,
+		      <&pm7250b_vadc ADC_SBUx>,
+		      <&pm7250b_vadc ADC_VPH_PWR>,
+		      <&pm7250b_vadc ADC_AMUX_THM1_PU2>;
+	io-channel-names = "usb_in_voltage",
+			   "usb_in_current",
+			   "chg_temp",
+			   "die_temp",
+			   "conn_temp",
+			   "sbux_res",
+			   "vph_voltage",
+			   "skin_temp";
+	qcom,battery-data = <&qrd_batterydata>;
+	qcom,sec-charger-config = <1>;
+	qcom,auto-recharge-soc = <98>;
+	qcom,step-charging-enable;
+	qcom,sw-jeita-enable;
+	qcom,charger-temp-max = <800>;
+	qcom,smb-temp-max = <800>;
+	qcom,suspend-input-on-debug-batt;
+	qcom,fcc-stepping-enable;
+	qcom,fcc-step-delay-ms = <100>;
+	qcom,fcc-step-size-ua = <100000>;
+	qcom,smb-internal-pull-kohm = <0>;
+	qcom,thermal-mitigation = <8000000 7500000 7000000 6500000 6000000 5500000
+			5000000 4500000 4000000 3500000 3000000 2500000 2000000 1500000
+			1000000 500000>;
+};
+
+&pm7250b_qg {
+	status = "ok";
+	io-channels = <&pm7250b_vadc ADC_BAT_THERM_PU2>,
+		      <&pm7250b_vadc ADC_BAT_ID_PU2>;
+	io-channel-names = "batt-therm",
+			   "batt-id";
+	qcom,qg-iterm-ma = <150>;
+	qcom,hold-soc-while-full;
+	qcom,linearize-soc;
+	qcom,cl-feedback-on;
+	qcom,tcss-enable;
+	qcom,fvss-enable;
+	qcom,fvss-vbatt-mv = <3500>;
+	qcom,bass-enable;
+	qcom,vbatt-cutoff-mv = <3400>;
+	qcom,vbatt-low-mv = <3500>;
+	qcom,vbatt-low-cold-mv = <3800>;
+	qcom,vbatt-empty-mv = <3200>;
+	qcom,vbatt-empty-cold-mv = <3100>;
+	qcom,use-cp-iin-sns;
+};
+
+&cam_res_mgr_label {
+	gpios = <&pm7250b_gpios 4 0>;
+};
+
+&led_flash_rear {
+	gpios = <&pm7250b_gpios 4 0>;
+};
+
+&led_flash_rear_aux {
+	gpios = <&pm7250b_gpios 4 0>;
+};
+
+&led_flash_rear_aux2 {
+	gpios = <&pm7250b_gpios 4 0>;
+};
+
+&pm7250b_charger {
+	dpdm-supply = <&usb2_phy0>;
+
+	smb5_vbus: qcom,smb5-vbus {
+		regulator-name = "smb5-vbus";
+	};
+
+	smb5_vconn: qcom,smb5-vconn {
+		regulator-name = "smb5-vconn";
+	};
+};
+
+&pm7250b_pdphy {
+	vdd-pdphy-supply = <&L15A>;
+	vbus-supply = <&smb5_vbus>;
+	vconn-supply = <&smb5_vconn>;
+};
+
+&usb0 {
+	extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>;
+};
+
+&thermal_zones {
+	quiet-thermal-step {
+		cooling-maps {
+			quiet_batt_cdev1 {
+				trip = <&quiet_batt_trip0>;
+				cooling-device = <&pm7250b_charger 8 8>;
+			};
+
+			quiet_batt_cdev2 {
+				trip = <&quiet_batt_trip1>;
+				cooling-device = <&pm7250b_charger 12 12>;
+			};
+
+			quiet_batt_cdev3 {
+				trip = <&quiet_batt_trip2>;
+				cooling-device = <&pm7250b_charger 14 14>;
+			};
+
+			quiet_batt_cdev4 {
+				trip = <&quiet_batt_trip3>;
+				cooling-device = <&pm7250b_charger 16 16>;
+			};
+
+			quiet_batt_cdev5 {
+				trip = <&quiet_batt_trip4>;
+				cooling-device = <&pm7250b_charger 18 18>;
+			};
+		};
+	};
+};
diff --git a/qcom/khaje-qrd.dts b/qcom/khaje-qrd.dts
new file mode 100644
index 00000000..df4c7c15
--- /dev/null
+++ b/qcom/khaje-qrd.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-qrd.dtsi"
+#include "khaje-qrd-pm7250b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. KHAJE QRD";
+	compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
+	qcom,board-id = <0x1000B 0>;
+	qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
diff --git a/qcom/khaje-qrd.dtsi b/qcom/khaje-qrd.dtsi
new file mode 100644
index 00000000..8ac99391
--- /dev/null
+++ b/qcom/khaje-qrd.dtsi
@@ -0,0 +1,547 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/input.h>
+#include "bengal-thermal-overlay.dtsi"
+#include "camera/khaje-camera-sensor-qrd.dtsi"
+#include "bengal-audio-overlay.dtsi"
+#include "khaje-sde-display.dtsi"
+
+&pm6125_gpios {
+	key_vol_up {
+		key_vol_up_default: key_vol_up_default {
+			pins = "gpio5";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+			power-source = <0>;
+		};
+	};
+
+	eldo9_pin {
+		usb_eldo9:gpio@c000 {
+			pins = "gpio1";
+			function = "normal";
+			qcom,drive-strength = <2>;
+			power-source = <0>;
+			bias-disable;
+			output-high;
+		};
+	};
+};
+
+&soc {
+	gpio_keys {
+		compatible = "gpio-keys";
+		label = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_vol_up_default>;
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_VOLUMEUP>;
+			linux,can-disable;
+			debounce-interval = <15>;
+			gpio-key,wakeup;
+		};
+	};
+
+	vdda_usb_ss_dp_core: vdda_usb_ss_dp_core {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_supply";
+		regulator-min-microvolt = <880000>;
+		regulator-max-microvolt = <880000>;
+		enable-active-high;
+		gpio = <&pm6125_gpios 1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb_eldo9>;
+	};
+};
+
+&usb_qmp_dp_phy {
+	vdd-supply = <&vdda_usb_ss_dp_core>;
+};
+
+&qupv3_se1_i2c {
+	awinic@64 {
+		compatible = "awinic,aw2016_led";
+		reg = <0x64>;
+
+		awinic,red {
+			awinic,name = "red";
+			awinic,id = <0>;
+			awinic,imax = <2>;
+			awinic,led-current = <3>;
+			awinic,max-brightness = <255>;
+			awinic,rise-time-ms = <6>;
+			awinic,hold-time-ms = <0>;
+			awinic,fall-time-ms = <6>;
+			awinic,off-time-ms = <4>;
+		};
+
+		awinic,green {
+			awinic,name = "green";
+			awinic,id = <1>;
+			awinic,imax = <2>;
+			awinic,led-current = <3>;
+			awinic,max-brightness = <255>;
+			awinic,rise-time-ms = <6>;
+			awinic,hold-time-ms = <0>;
+			awinic,fall-time-ms = <6>;
+			awinic,off-time-ms = <4>;
+		};
+
+		awinic,blue {
+			awinic,name = "blue";
+			awinic,id = <2>;
+			awinic,imax = <2>;
+			awinic,led-current = <3>;
+			awinic,max-brightness = <255>;
+			awinic,rise-time-ms = <6>;
+			awinic,hold-time-ms = <0>;
+			awinic,fall-time-ms = <6>;
+			awinic,off-time-ms = <4>;
+		};
+
+	};
+};
+
+&bengal_snd {
+	qcom,model = "bengal-qrd-snd-card";
+	qcom,msm-mi2s-master = <1>, <1>, <1>, <1>;
+	qcom,wcn-btfm = <1>;
+	qcom,ext-disp-audio-rx = <0>;
+	qcom,audio-routing =
+		"AMIC1", "MIC BIAS1",
+		"MIC BIAS1", "Analog Mic1",
+		"AMIC2", "MIC BIAS2",
+		"MIC BIAS2", "Analog Mic2",
+		"AMIC3", "MIC BIAS3",
+		"MIC BIAS3", "Analog Mic3",
+		"AMIC4", "MIC BIAS3",
+		"MIC BIAS3", "Analog Mic4",
+		"IN1_HPHL", "HPHL_OUT",
+		"IN2_HPHR", "HPHR_OUT",
+		"IN3_AUX", "AUX_OUT",
+		"SpkrMono WSA_IN", "AUX",
+		"TX SWR_MIC0", "ADC1_OUTPUT",
+		"TX SWR_MIC4", "ADC2_OUTPUT",
+		"TX SWR_MIC5", "ADC3_OUTPUT",
+		"TX SWR_MIC0", "VA_TX_SWR_CLK",
+		"TX SWR_MIC1", "VA_TX_SWR_CLK",
+		"TX SWR_MIC2", "VA_TX_SWR_CLK",
+		"TX SWR_MIC3", "VA_TX_SWR_CLK",
+		"TX SWR_MIC4", "VA_TX_SWR_CLK",
+		"TX SWR_MIC5", "VA_TX_SWR_CLK",
+		"TX SWR_MIC6", "VA_TX_SWR_CLK",
+		"TX SWR_MIC7", "VA_TX_SWR_CLK",
+		"TX SWR_MIC8", "VA_TX_SWR_CLK",
+		"TX SWR_MIC9", "VA_TX_SWR_CLK",
+		"TX SWR_MIC10", "VA_TX_SWR_CLK",
+		"TX SWR_MIC11", "VA_TX_SWR_CLK",
+		"RX_TX DEC0_INP", "TX DEC0 MUX",
+		"RX_TX DEC1_INP", "TX DEC1 MUX",
+		"RX_TX DEC2_INP", "TX DEC2 MUX",
+		"RX_TX DEC3_INP", "TX DEC3 MUX",
+		"TX_AIF1 CAP", "VA_TX_SWR_CLK",
+		"TX_AIF2 CAP", "VA_TX_SWR_CLK",
+		"TX_AIF3 CAP", "VA_TX_SWR_CLK",
+		"VA SWR_MIC0", "ADC1_OUTPUT",
+		"VA SWR_MIC4", "ADC2_OUTPUT",
+		"VA SWR_MIC5", "ADC3_OUTPUT";
+	qcom,msm-mbhc-hphl-swh = <1>;
+	qcom,msm-mbhc-gnd-swh = <1>;
+	asoc-codec  = <&stub_codec>, <&bolero>;
+	asoc-codec-names = "msm-stub-codec.1", "bolero_codec";
+	qcom,wsa-max-devs = <1>;
+	qcom,wsa-devs = <&wsa881x_i2c_e>;
+	qcom,wsa-aux-dev-prefix = "SpkrMono";
+	qcom,codec-max-aux-devs = <1>;
+	qcom,codec-aux-devs = <&wcd937x_codec>;
+	qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&bolero>,
+				<&lpi_tlmm>;
+};
+
+&qupv3_se1_i2c {
+	status = "ok";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	nq@28 {
+		compatible = "qcom,nq-nci";
+		reg = <0x28>;
+		qcom,nq-irq = <&tlmm 70 0x00>;
+		qcom,nq-ven = <&tlmm 69 0x00>;
+		qcom,nq-firm = <&tlmm 31 0x00>;
+		qcom,nq-clkreq = <&tlmm 71 0x00>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <70 0>;
+		interrupt-names = "nfc_irq";
+		pinctrl-names = "nfc_active", "nfc_suspend";
+		pinctrl-0 = <&nfc_int_active &nfc_enable_active
+				&nfc_clk_req_active>;
+		pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+				&nfc_clk_req_suspend>;
+	};
+};
+
+&sdhc_1 {
+	vdd-supply = <&L24A>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 570000>;
+
+	vdd-io-supply = <&L11A>;
+	qcom,vdd-io-always-on;
+	qcom,vdd-io-lpm-sup;
+	qcom,vdd-io-voltage-level = <1800000 1800000>;
+	qcom,vdd-io-current-level = <0 325000>;
+
+	pinctrl-names = "active", "sleep";
+	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+					&sdc1_rclk_on>;
+	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+					&sdc1_rclk_off>;
+
+	status = "ok";
+};
+
+&sdhc_2 {
+	vdd-supply = <&L22A>;
+	qcom,vdd-voltage-level = <2960000 2960000>;
+	qcom,vdd-current-level = <0 800000>;
+
+	vdd-io-supply = <&L5A>;
+	qcom,vdd-io-voltage-level = <1800000 2960000>;
+	qcom,vdd-io-current-level = <0 22000>;
+
+	vdd-io-bias-supply = <&L7A>;
+	qcom,vdd-io-bias-voltage-level = <1256000 1256000>;
+	qcom,vdd-io-bias-current-level = <0 6000>;
+
+	pinctrl-names = "active", "sleep";
+	pinctrl-0 = <&sdc2_clk_on  &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+	cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>;
+
+	status = "ok";
+};
+
+&ufsphy_mem {
+	compatible = "qcom,ufs-phy-qmp-v4";
+
+	vdda-phy-supply = <&L4A>; /* 0.9v */
+	vdda-pll-supply = <&L18A>; /* 1.8v */
+	vdda-phy-max-microamp = <85700>;
+	vdda-pll-max-microamp = <18300>;
+
+	status = "ok";
+};
+
+&ufshc_mem {
+	vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+	vdd-hba-fixed-regulator;
+	vcc-supply = <&L24A>;
+	vcc-voltage-level = <2950000 2960000>;
+	vccq2-supply = <&L11A>;
+	vccq2-voltage-level = <1800000 1800000>;
+	vcc-max-microamp = <800000>;
+	vccq2-max-microamp = <800000>;
+	vccq2-pwr-collapse-sup;
+
+	qcom,vddp-ref-clk-supply = <&L18A>;
+	qcom,vddp-ref-clk-max-microamp = <100>;
+	qcom,vddp-ref-clk-min-uV = <1232000>;
+	qcom,vddp-ref-clk-max-uV = <1232000>;
+
+	status = "ok";
+};
+
+&pm6125_pwm {
+	status = "ok";
+};
+
+&dsi_td4330_truly_v2_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+	pwms = <&pm6125_pwm 0 0>;
+	qcom,bl-pmic-pwm-period-usecs = <100>;
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&dsi_td4330_truly_v2_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+	pwms = <&pm6125_pwm 0 0>;
+	qcom,bl-pmic-pwm-period-usecs = <100>;
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,platform-te-gpio = <&tlmm 81 0>;
+	qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&dsi_sim_vid {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&sde_dsi {
+	qcom,dsi-default-panel = <&dsi_td4330_truly_v2_video>;
+};
+
+&qupv3_se2_i2c {
+	status = "okay";
+	qcom,i2c-touch-active="synaptics,tcm-i2c";
+
+	synaptics_tcm@20 {
+		compatible = "synaptics,tcm-i2c";
+		reg = <0x20>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <80 0x2008>;
+		pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+			"pmx_ts_release";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+		pinctrl-2 = <&ts_release>;
+		synaptics,irq-gpio = <&tlmm 80 0x2008>;
+		synaptics,irq-on-state = <0>;
+		synaptics,reset-gpio = <&tlmm 86 0x00>;
+		synaptics,reset-on-state = <0>;
+		synaptics,reset-active-ms = <20>;
+		synaptics,reset-delay-ms = <200>;
+		synaptics,power-delay-ms = <200>;
+		synaptics,ubl-i2c-addr = <0x20>;
+		synaptics,extend_report;
+		synaptics,firmware-name = "synaptics_firmware_k.img";
+
+		panel = <&dsi_td4330_truly_v2_video &dsi_td4330_truly_v2_cmd>;
+	};
+};
+
+&thermal_zones {
+	quiet-thermal-step {
+		polling-delay-passive = <2000>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm6125_adc_tm ADC_AMUX_THM2_PU2>;
+		wake-capable-sensor;
+
+		trips {
+			quiet_batt_trip0: batt-trip0 {
+				temperature = <41000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+
+			quiet_modem_trip0: modem-trip0 {
+				temperature = <42000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+
+			quiet_batt_trip1: batt-trip1 {
+				temperature = <43000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+
+			quiet_batt_trip2: batt-trip2 {
+				temperature = <45000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+
+			quiet_gold_trip: gold-trip {
+				temperature = <47000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			quiet_batt_trip3: batt-trip3 {
+				temperature = <47000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+
+			quiet_batt_trip4: batt-trip4 {
+				temperature = <48000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			quiet_gpu_trip: gpu-trip {
+				temperature = <48000>;
+				hysteresis = <4000>;
+				type = "passive";
+			};
+
+			quiet_silver_trip: silver-trip {
+				temperature = <50000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			quiet_hvx_trip: hvx-trip {
+				temperature = <52000>;
+				hysteresis = <4000>;
+				type = "passive";
+			};
+
+			quiet_modem_trip1: modem-trip1 {
+				temperature = <60000>;
+				hysteresis = <4000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			gold_cdev {
+				trip = <&quiet_gold_trip>;
+				/* limit to 1766400khz */
+				cooling-device = <&CPU4 THERMAL_NO_LIMIT
+							(THERMAL_MAX_LIMIT-4)>;
+			};
+
+			silver_cdev {
+				trip = <&quiet_silver_trip>;
+				/* limit to 1516800khz */
+				cooling-device = <&CPU0 THERMAL_NO_LIMIT
+							(THERMAL_MAX_LIMIT-4)>;
+			};
+
+			gpu_cdev {
+				trip = <&quiet_gpu_trip>;
+				/* limit 785000000hz */
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							(THERMAL_MAX_LIMIT-3)>;
+			};
+
+			hvx_cdev {
+				trip = <&quiet_hvx_trip>;
+				cooling-device = <&cdsp_sw 4 4>;
+			};
+
+			mdm_cdev0 {
+				trip = <&quiet_modem_trip0>;
+				cooling-device = <&modem_proc 1 1>;
+			};
+
+			mdm_cdev1 {
+				trip = <&quiet_modem_trip1>;
+				cooling-device = <&modem_proc 3 3>;
+			};
+		};
+	};
+
+	pa-therm0-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm6125_adc_tm ADC_AMUX_THM1_PU2>;
+		wake-capable-sensor;
+
+		trips {
+			pa_therm0_trip0: pa-therm0-trip0 {
+				temperature = <52000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+
+			pa_therm0_trip1: pa-therm0-trip1 {
+				temperature = <54000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+
+			pa_therm0_trip2: pa-therm0-trip2 {
+				temperature = <60000>;
+				hysteresis = <4000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			modem_cdev0 {
+				trip = <&pa_therm0_trip0>;
+				cooling-device = <&modem_pa 1 1>;
+			};
+
+			modem_cdev1 {
+				trip = <&pa_therm0_trip1>;
+				cooling-device = <&modem_pa 2 2>;
+			};
+
+			modem_cdev2 {
+				trip = <&pa_therm0_trip2>;
+				cooling-device = <&modem_pa 3 3>;
+			};
+		};
+	};
+};
+
+&tlmm {
+	fpc_reset_int: fpc_reset_int {
+		fpc_reset_low: reset_low {
+			mux {
+				pins = "gpio104";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio104";
+				drive-strength = <2>;
+				bias-disable;
+				output-low;
+			};
+		};
+
+		fpc_reset_high: reset_high {
+			mux {
+				pins = "gpio104";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio104";
+				drive-strength = <2>;
+				bias-disable;
+				output-high;
+			};
+		};
+
+		fpc_int_low: int_low {
+			mux {
+				pins = "gpio97";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio97";
+				drive-strength = <2>;
+				bias-pull-down;
+				input-enable;
+			};
+		};
+	};
+};
+
+&soc {
+	fingerprint: fpc1020 {
+		compatible = "fpc,fpc1020";
+		interrupt-parent = <&tlmm>;
+		interrupts = <97 0>;
+		fpc,gpio_rst = <&tlmm 104 0>;
+		fpc,gpio_irq = <&tlmm 97 0>;
+		fpc,enable-on-boot;
+		pinctrl-names = "fpc1020_reset_reset",
+				"fpc1020_reset_active",
+				"fpc1020_irq_active";
+		pinctrl-0 = <&fpc_reset_low>;
+		pinctrl-1 = <&fpc_reset_high>;
+		pinctrl-2 = <&fpc_int_low>;
+	};
+};
diff --git a/qcom/khaje-regulator.dtsi b/qcom/khaje-regulator.dtsi
new file mode 100644
index 00000000..51508ac7
--- /dev/null
+++ b/qcom/khaje-regulator.dtsi
@@ -0,0 +1,152 @@
+#include "bengal-regulator.dtsi"
+
+&S6A {
+	regulator-min-microvolt = <400000>;
+	regulator-max-microvolt = <1419000>;
+	qcom,init-voltage = <1352000>;
+};
+
+&S7A {
+	regulator-min-microvolt = <1569000>;
+	regulator-max-microvolt = <2040000>;
+	qcom,init-voltage = <2040000>;
+};
+
+&S8A {
+	regulator-min-microvolt = <1060000>;
+	regulator-max-microvolt = <1170000>;
+	qcom,init-voltage = <1128000>;
+};
+
+&L1A {
+	regulator-min-microvolt = <950000>;
+	regulator-max-microvolt = <1150000>;
+	qcom,init-voltage = <1000000>;
+};
+
+&L4A {
+	regulator-min-microvolt = <720000>;
+	regulator-max-microvolt = <1050000>;
+	qcom,init-voltage = <880000>;
+};
+
+&L5A {
+	regulator-min-microvolt = <1650000>;
+	regulator-max-microvolt = <3050000>;
+	qcom,init-voltage = <2960000>;
+};
+
+&L6A {
+	regulator-min-microvolt = <570000>;
+	regulator-max-microvolt = <650000>;
+	qcom,init-voltage = <624000>;
+};
+
+&L7A {
+	regulator-max-microvolt = <1300000>;
+	qcom,init-voltage = <1256000>;
+};
+
+&L8A {
+	qcom,init-voltage = <704000>;
+};
+
+&L9A {
+	regulator-min-microvolt = <1504000>;
+	qcom,init-voltage = <1800000>;
+};
+
+&L10A {
+	regulator-min-microvolt = <1700000>;
+	regulator-max-microvolt = <1900000>;
+	qcom,init-voltage = <1800000>;
+};
+
+&L11A {
+	regulator-min-microvolt = <1700000>;
+	regulator-max-microvolt = <1950000>;
+	qcom,init-voltage = <1800000>;
+};
+
+&L12A {
+	regulator-min-microvolt = <1620000>;
+	regulator-max-microvolt = <1980000>;
+	qcom,init-voltage = <1800000>;
+};
+
+&L13A {
+	regulator-min-microvolt = <1504000>;
+	regulator-max-microvolt = <2000000>;
+	qcom,init-voltage = <1800000>;
+};
+
+&L14A {
+	regulator-min-microvolt = <1700000>;
+	regulator-max-microvolt = <1900000>;
+	qcom,init-voltage = <1700000>;
+};
+
+&L15A {
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3544000>;
+	qcom,init-voltage = <3080000>;
+};
+
+&L16A {
+	regulator-min-microvolt = <1700000>;
+	regulator-max-microvolt = <1900000>;
+	qcom,init-voltage = <1700000>;
+};
+
+&L17A {
+	regulator-min-microvolt = <1220000>;
+	regulator-max-microvolt = <1304000>;
+	qcom,init-voltage = <1220000>;
+};
+
+&L18A {
+	regulator-min-microvolt = <1100000>;
+	regulator-max-microvolt = <1300000>;
+	qcom,init-voltage = <1232000>;
+};
+
+&L19A {
+	regulator-min-microvolt = <1620000>;
+	regulator-max-microvolt = <3300000>;
+	qcom,init-voltage = <1620000>;
+};
+
+&L20A {
+	regulator-min-microvolt = <1620000>;
+	regulator-max-microvolt = <3300000>;
+	qcom,init-voltage = <1620000>;
+};
+
+&L21A {
+	regulator-min-microvolt = <1600000>;
+	regulator-max-microvolt = <3544000>;
+	qcom,init-voltage = <1600000>;
+};
+
+&L22A {
+	regulator-min-microvolt = <2950000>;
+	regulator-max-microvolt = <3300000>;
+	qcom,init-voltage = <2960000>;
+};
+
+&L24A {
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <3544000>;
+	qcom,init-voltage = <2960000>;
+};
+
+&soc {
+	refgen: refgen-regulator@1600000 {
+		compatible = "qcom,refgen-kona-regulator";
+		reg = <0x1600000 0x84>;
+		regulator-name = "refgen";
+		regulator-enable-ramp-delay = <5>;
+		proxy-supply = <&refgen>;
+		qcom,proxy-consumer-enable;
+	};
+};
diff --git a/qcom/khaje-sde-display.dtsi b/qcom/khaje-sde-display.dtsi
new file mode 100644
index 00000000..e3c3b4bf
--- /dev/null
+++ b/qcom/khaje-sde-display.dtsi
@@ -0,0 +1,185 @@
+#include "dsi-panel-td4330-truly-v2-singlemipi-fhd-cmd.dtsi"
+#include "dsi-panel-td4330-truly-v2-singlemipi-fhd-vid.dtsi"
+#include "dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi"
+#include "dsi-panel-nt36672e-fhd-plus-120hz-video.dtsi"
+#include "dsi-panel-sim-video.dtsi"
+#include <dt-bindings/clock/mdss-7nm-pll-clk.h>
+
+&soc {
+	dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,panel-supply-entry@0 {
+			reg = <0>;
+			qcom,supply-name = "vddio";
+			qcom,supply-min-voltage = <1800000>;
+			qcom,supply-max-voltage = <1800000>;
+			qcom,supply-enable-load = <62000>;
+			qcom,supply-disable-load = <80>;
+			qcom,supply-post-on-sleep = <20>;
+		};
+	};
+
+	sde_dsi: qcom,dsi-display-primary {
+		compatible = "qcom,dsi-display";
+		label = "primary";
+		qcom,dsi-ctrl = <&mdss_dsi0>;
+		qcom,dsi-phy = <&mdss_dsi_phy0>;
+
+		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
+			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,
+			 <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,
+			 <&mdss_dsi0_pll PCLK_SRC_0_CLK>,
+			 <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>,
+			 <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>;
+		clock-names = "mux_byte_clk0", "mux_pixel_clk0",
+			"src_byte_clk0", "src_pixel_clk0",
+			"shadow_byte_clk0", "shadow_pixel_clk0";
+		pinctrl-names = "panel_active", "panel_suspend";
+		pinctrl-0 = <&sde_dsi_active &sde_te_active>;
+		pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
+
+		qcom,platform-te-gpio = <&tlmm 81 0>;
+		qcom,panel-te-source = <0>;
+
+		vddio-supply = <&L9A>;
+		qcom,mdp = <&mdss_mdp>;
+
+		qcom,dsi-default-panel =
+			<&dsi_td4330_truly_v2_video>;
+	};
+
+	sde_wb: qcom,wb-display@0 {
+		status = "disabled";
+		compatible = "qcom,wb-display";
+		cell-index = <0>;
+		label = "wb_display";
+	};
+
+	msm_notifier: qcom,msm_notifier@0 {
+		compatible = "qcom,msm-notifier";
+		panel = <&dsi_nt36672e_fhd_plus_90hz_video
+			&dsi_nt36672e_fhd_plus_120hz_video>;
+	};
+};
+
+&mdss_mdp {
+	connectors = <&sde_dsi>;
+};
+
+&dsi_td4330_truly_v2_video {
+	qcom,esd-check-enabled;
+	qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+	qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+	qcom,mdss-dsi-panel-status-value = <0x1c>;
+	qcom,mdss-dsi-panel-on-check-value = <0x1c>;
+	qcom,mdss-dsi-panel-status-read-length = <1>;
+	qcom,dsi-supported-dfps-list = <60 55 48>;
+	qcom,mdss-dsi-pan-enable-dynamic-fps;
+	qcom,mdss-dsi-pan-fps-update =
+			"dfps_immediate_porch_mode_vfp";
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+				"src_byte_clk0", "src_pixel_clk0",
+				"shadow_byte_clk0", "shadow_pixel_clk0";
+	qcom,dsi-dyn-clk-enable;
+	qcom,dsi-dyn-clk-list =
+		<976190400 988392784 984325320 980257864>;
+	qcom,dsi-dyn-clk-type = "constant-fps-adjust-vfp";
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-phy-timings = [00 21 08 08 25 22 09
+					08 09 02 04 00 1D 18];
+			qcom,display-topology = <1 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+
+		timing@1 {
+			qcom,mdss-dsi-panel-phy-timings = [00 23 09 09 26 24 09
+					09 09 02 04 00 1E 19];
+			qcom,display-topology = <1 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
+
+&dsi_td4330_truly_v2_cmd {
+	qcom,esd-check-enabled;
+	qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+	qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+	qcom,mdss-dsi-panel-status-value = <0x1c>;
+	qcom,mdss-dsi-panel-on-check-value = <0x1c>;
+	qcom,mdss-dsi-panel-status-read-length = <1>;
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+	qcom,ulps-enabled;
+	qcom,dsi-dyn-clk-enable;
+	qcom,dsi-dyn-clk-list =
+		<944315056 928576464 932511112 936445760 940380400>;
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-phy-timings = [00 23 09 09 26 24 09
+					09 09 02 04 00 1E 19];
+			qcom,display-topology = <1 0 1>;
+			qcom,default-topology-index = <0>;
+			qcom,partial-update-enabled = "single_roi";
+			qcom,panel-roi-alignment = <40 40 40 40 40 40>;
+		};
+
+		timing@1 {
+			qcom,mdss-dsi-panel-phy-timings = [00 21 08 08 25 22 09
+					08 09 02 04 00 1D 18];
+			qcom,display-topology = <1 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
+
+&dsi_nt36672e_fhd_plus_90hz_video {
+	qcom,esd-check-enabled;
+	qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+	qcom,mdss-dsi-panel-status-value = <0x9c>;
+	qcom,mdss-dsi-panel-status-read-length = <1>;
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06
+					06 07 02 04 00 16 16];
+			qcom,display-topology = <1 1 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
+
+&dsi_nt36672e_fhd_plus_120hz_video {
+	qcom,esd-check-enabled;
+	qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+	qcom,mdss-dsi-panel-status-value = <0x9c>;
+	qcom,mdss-dsi-panel-status-read-length = <1>;
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08
+					08 08 02 04 00 1b 18];
+			qcom,display-topology = <1 1 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
+
+&dsi_sim_vid {
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1B 1B 01
+					01 02 02 04 00 0A 11];
+			qcom,display-topology = <1 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
diff --git a/qcom/khaje-sde-pll.dtsi b/qcom/khaje-sde-pll.dtsi
new file mode 100644
index 00000000..5ea95879
--- /dev/null
+++ b/qcom/khaje-sde-pll.dtsi
@@ -0,0 +1,20 @@
+&soc {
+	mdss_dsi0_pll: qcom,mdss_dsi0_pll {
+		compatible = "qcom,mdss_dsi_pll_7nm_v4_1";
+		label = "MDSS DSI 0 PLL";
+		cell-index = <0>;
+		#clock-cells = <1>;
+		reg = <0x5e94900 0x264>,
+		      <0x5e94400 0x800>,
+		      <0x5f01004 0x8>,
+		      <0x5e94200 0x100>;
+		reg-names = "pll_base", "phy_base",
+			"gdsc_base", "dynamic_pll_base";
+		clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
+		clock-names = "iface_clk";
+		clock-rate = <0>;
+		memory-region = <&dfps_data_memory>;
+		qcom,dsi-pll-ssc-en;
+		qcom,dsi-pll-ssc-mode = "down-spread";
+	};
+};
diff --git a/qcom/khaje-sde.dtsi b/qcom/khaje-sde.dtsi
new file mode 100644
index 00000000..20724c41
--- /dev/null
+++ b/qcom/khaje-sde.dtsi
@@ -0,0 +1,418 @@
+#include <dt-bindings/clock/mdss-7nm-pll-clk.h>
+
+&soc {
+	mdss_mdp: qcom,mdss_mdp {
+		compatible = "qcom,sde-kms";
+		reg = <0x5e00000 0x8f030>,
+		      <0x5eb0000 0x2008>,
+		      <0x5e8f000 0x030>;
+
+		reg-names = "mdp_phys",
+			   "vbif_phys",
+			   "sid_phys";
+
+		clocks =
+			<&gcc GCC_DISP_AHB_CLK>,
+			<&gcc GCC_DISP_HF_AXI_CLK>,
+			<&gcc GCC_DISP_THROTTLE_CORE_CLK>,
+			<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
+			<&dispcc DISP_CC_MDSS_AHB_CLK>,
+			<&dispcc DISP_CC_MDSS_MDP_CLK>,
+			<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+			<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+			<&dispcc DISP_CC_MDSS_ROT_CLK>;
+		clock-names = "gcc_iface", "gcc_bus", "throttle_clk",
+				 "div_clk",
+				"iface_clk", "core_clk", "vsync_clk",
+				"lut_clk", "rot_clk";
+		clock-rate = <0 0 0 0 0 300000000 19200000 300000000 200000000>;
+		clock-max-rate = <0 0 0 0 0 560000000 19200000 560000000
+							 560000000>;
+
+		sde-vdd-supply = <&mdss_core_gdsc>;
+
+		/* interrupt config */
+		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		#power-domain-cells = <0>;
+		#list-cells = <1>;
+
+		/* hw blocks */
+		qcom,sde-off = <0x1000>;
+		qcom,sde-len = <0x494>;
+
+		qcom,sde-ctl-off = <0x2000>;
+		qcom,sde-ctl-size = <0x1dc>;
+		qcom,sde-ctl-display-pref = "primary";
+
+		qcom,sde-mixer-off = <0x45000>;
+		qcom,sde-mixer-size = <0x320>;
+		qcom,sde-mixer-display-pref = "primary";
+
+		qcom,sde-dspp-top-off = <0x1300>;
+		qcom,sde-dspp-top-size = <0x80>;
+		qcom,sde-dspp-off = <0x55000>;
+		qcom,sde-dspp-size = <0x1800>;
+
+		qcom,sde-dspp-rc-version = <0x00010000>;
+		qcom,sde-dspp-rc-off = <0x15800>;
+		qcom,sde-dspp-rc-size = <0x100>;
+		qcom,sde-dspp-rc-mem-size = <2720>;
+
+		qcom,sde-intf-off = <0x0 0x6b800>;
+		qcom,sde-intf-size = <0x2c0>;
+		qcom,sde-intf-type = "none", "dsi";
+
+		qcom,sde-pp-off = <0x71000>;
+		qcom,sde-pp-size = <0xd4>;
+
+		qcom,sde-dsc-off = <0x81000>;
+		qcom,sde-dsc-size = <0x140>;
+
+		qcom,sde-dither-off = <0x30e0>;
+		qcom,sde-dither-version = <0x00010000>;
+		qcom,sde-dither-size = <0x20>;
+
+		qcom,sde-sspp-type = "vig", "dma";
+
+		qcom,sde-sspp-off = <0x5000 0x25000>;
+		qcom,sde-sspp-src-size = <0x1f8>;
+
+		qcom,sde-sspp-xin-id = <0 1>;
+		qcom,sde-sspp-excl-rect = <1 1>;
+		qcom,sde-sspp-smart-dma-priority = <2 1>;
+		qcom,sde-smart-dma-rev = "smart_dma_v2p5";
+
+		qcom,sde-mixer-pair-mask = <0>;
+
+		qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
+						0xb0 0xc8 0xe0 0xf8 0x110>;
+
+		qcom,sde-mixer-stage-base-layer;
+
+		qcom,sde-max-per-pipe-bw-kbps = <3200000 3200000>;
+
+		qcom,sde-max-per-pipe-bw-high-kbps = <3200000 3200000>;
+
+		/* offsets are relative to "mdp_phys + qcom,sde-off */
+		qcom,sde-sspp-clk-ctrl =
+				<0x2ac 0>, <0x2ac 8>;
+		qcom,sde-sspp-csc-off = <0x1a00>;
+		qcom,sde-csc-type = "csc-10bit";
+		qcom,sde-qseed-type = "qseedv3lite";
+		qcom,sde-sspp-qseed-off = <0xa00>;
+		qcom,sde-mixer-linewidth = <2048>;
+		qcom,sde-sspp-linewidth = <2160>;
+		qcom,sde-mixer-blendstages = <0x4>;
+		qcom,sde-highest-bank-bit = <0x1>;
+		qcom,sde-ubwc-version = <0x100>;
+		qcom,sde-ubwc-swizzle = <0x7>;
+		qcom,sde-ubwc-static = <0x11F>;
+		qcom,sde-panic-per-pipe;
+		qcom,sde-has-cdp;
+
+		qcom,sde-has-dim-layer;
+		qcom,sde-has-idle-pc;
+
+		qcom,sde-max-bw-low-kbps = <3200000>;
+		qcom,sde-max-bw-high-kbps = <4300000>;
+		qcom,sde-min-core-ib-kbps = <2400000>;
+		qcom,sde-min-llcc-ib-kbps = <0>;
+		qcom,sde-min-dram-ib-kbps = <1600000>;
+		qcom,sde-dram-channels = <1>;
+		qcom,sde-num-nrt-paths = <0>;
+
+		qcom,sde-vbif-off = <0>;
+		qcom,sde-vbif-size = <0x2008>;
+		qcom,sde-vbif-id = <0>;
+		qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
+		qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
+
+		qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
+		qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
+
+		/*Pending macrotile & macrotile-qseed has the same configs */
+
+		qcom,sde-danger-lut = <0x000000ff 0x0000ffff
+			0x00000000 0x00000000 0x0000ffff>;
+
+		qcom,sde-safe-lut-linear = <0 0xfff0>;
+		qcom,sde-safe-lut-macrotile = <0 0xff00>;
+		/* same as safe-lut-macrotile */
+		qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>;
+		qcom,sde-safe-lut-nrt = <0 0xffff>;
+
+		qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>;
+		qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>;
+		qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>;
+		qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>;
+
+		qcom,sde-cdp-setting = <1 1>, <1 0>;
+
+		qcom,sde-qos-cpu-mask = <0x3>;
+		qcom,sde-qos-cpu-dma-latency = <300>;
+
+		qcom,sde-secure-sid-mask = <0x0000421>;
+		qcom,sde-num-mnoc-ports = <1>;
+		qcom,sde-axi-bus-width = <16>;
+
+		qcom,sde-sspp-vig-blocks {
+			qcom,sde-vig-csc-off = <0x1a00>;
+			qcom,sde-vig-qseed-off = <0xa00>;
+			qcom,sde-vig-qseed-size = <0xa0>;
+			qcom,sde-vig-inverse-pma;
+		};
+
+		qcom,sde-dspp-blocks {
+			qcom,sde-dspp-igc = <0x0 0x00030001>;
+			qcom,sde-dspp-hsic = <0x800 0x00010007>;
+			qcom,sde-dspp-memcolor = <0x880 0x00010007>;
+			qcom,sde-dspp-hist = <0x800 0x00010007>;
+			qcom,sde-dspp-sixzone= <0x900 0x00010007>;
+			qcom,sde-dspp-vlut = <0xa00 0x00010008>;
+			qcom,sde-dspp-pcc = <0x1700 0x00040000>;
+			qcom,sde-dspp-gc = <0x17c0 0x00010008>;
+			qcom,sde-dspp-dither = <0x82c 0x00010007>;
+		};
+
+		qcom,platform-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,platform-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "sde-vdd";
+				qcom,supply-min-voltage = <0>;
+				qcom,supply-max-voltage = <0>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+
+		smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
+			compatible = "qcom,smmu_sde_unsec";
+			iommus = <&apps_smmu 0x420 0x2>;
+			qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+			qcom,iommu-faults = "non-fatal";
+			qcom,iommu-earlymap; /* for cont-splash */
+		};
+
+		smmu_sde_sec: qcom,smmu_sde_sec_cb {
+			compatible = "qcom,smmu_sde_sec";
+			iommus = <&apps_smmu 0x421 0x0>;
+			qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+			qcom,iommu-faults = "non-fatal";
+			qcom,iommu-vmid = <0xa>;
+		};
+
+		/* data and reg bus scale settings */
+		qcom,sde-data-bus {
+			qcom,msm-bus,name = "mdss_sde";
+			qcom,msm-bus,num-cases = <3>;
+			qcom,msm-bus,num-paths = <1>;
+			qcom,msm-bus,vectors-KBps =
+				<22 512 0 0>,
+				<22 512 0 4800000>,
+				<22 512 0 4800000>;
+		};
+
+		qcom,sde-reg-bus {
+			qcom,msm-bus,name = "mdss_reg";
+			qcom,msm-bus,num-cases = <4>;
+			qcom,msm-bus,num-paths = <1>;
+			qcom,msm-bus,vectors-KBps =
+				<1 590 0 0>,
+				<1 590 0 76800>,
+				<1 590 0 150000>,
+				<1 590 0 300000>;
+		};
+
+		qcom,sde-limits {
+			qcom,sde-linewidth-limits {
+				qcom,sde-limit-name = "sspp_linewidth_usecases";
+				qcom,sde-limit-cases = "vig", "dma", "scale";
+				qcom,sde-limit-ids= <0x1 0x2 0x4>;
+				qcom,sde-limit-values = <0x1 4096>,
+							<0x5 2560>,
+							<0x2 2160>;
+			};
+
+			qcom,sde-bw-limits {
+				qcom,sde-limit-name = "sde_bwlimit_usecases";
+				qcom,sde-limit-cases = "per_vig_pipe",
+							"per_dma_pipe",
+							"total_max_bw",
+							"camera_concurrency";
+				qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>;
+				qcom,sde-limit-values = <0x1 3200000>,
+							<0x9 3200000>,
+							<0x2 3200000>,
+							<0xa 3200000>,
+							<0x4 4300000>,
+							<0xc 3200000>;
+			};
+		};
+	};
+
+	mdss_rotator: qcom,mdss_rotator {
+		compatible = "qcom,sde_rotator";
+		reg = <0x5e00000 0xac000>,
+		      <0x5eb0000 0x2008>;
+		reg-names = "mdp_phys",
+			    "rot_vbif_phys";
+
+		#list-cells = <1>;
+
+		qcom,mdss-rot-mode = <1>;
+
+		/* Bus Scale Settings */
+		qcom,msm-bus,name = "mdss_rotator";
+		qcom,msm-bus,num-cases = <3>;
+		qcom,msm-bus,num-paths = <1>;
+		qcom,msm-bus,vectors-KBps =
+			<22 512 0 0>,
+			<22 512 0 6400000>,
+			<22 512 0 6400000>;
+
+		rot-vdd-supply = <&mdss_core_gdsc>;
+		qcom,supply-names = "rot-vdd";
+
+		clocks =
+			<&gcc GCC_DISP_AHB_CLK>,
+			<&dispcc DISP_CC_MDSS_AHB_CLK>,
+			<&dispcc DISP_CC_MDSS_ROT_CLK>;
+		clock-names = "gcc_iface",
+			"iface_clk", "rot_clk";
+
+		interrupt-parent = <&mdss_mdp>;
+		interrupts = <2 0>;
+
+		power-domains = <&mdss_mdp>;
+		/*Offline rotator RT setting */
+		qcom,mdss-rot-parent = <&mdss_mdp 0>;
+		qcom,mdss-rot-xin-id = <10 11>;
+
+		/* Offline rotator QoS setting */
+		qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
+		qcom,mdss-rot-cdp-setting = <1 1>;
+		qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
+		qcom,mdss-rot-danger-lut = <0x0 0x0>;
+		qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;
+
+		qcom,mdss-default-ot-rd-limit = <32>;
+		qcom,mdss-default-ot-wr-limit = <32>;
+
+		qcom,mdss-sbuf-headroom = <20>;
+
+		/* reg bus scale settings */
+		rot_reg: qcom,rot-reg-bus {
+			qcom,msm-bus,name = "mdss_rot_reg";
+			qcom,msm-bus,num-cases = <2>;
+			qcom,msm-bus,num-paths = <1>;
+			qcom,msm-bus,vectors-KBps =
+				<1 590 0 0>,
+				<1 590 0 76800>;
+		};
+
+		smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
+			compatible = "qcom,smmu_sde_rot_unsec";
+			iommus = <&apps_smmu 0x43C 0x0>;
+			qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+			qcom,iommu-faults = "non-fatal";
+		};
+
+		smmu_rot_sec: qcom,smmu_rot_sec_cb {
+			compatible = "qcom,smmu_sde_rot_sec";
+			iommus = <&apps_smmu 0x43D 0x0>;
+			qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+			qcom,iommu-faults = "non-fatal";
+			qcom,iommu-vmid = <0xa>;
+		};
+	};
+
+	mdss_dsi0: qcom,mdss_dsi0_ctrl {
+		compatible = "qcom,dsi-ctrl-hw-v2.4";
+		label = "dsi-ctrl-0";
+		cell-index = <0>;
+		frame-threshold-time-us = <1000>;
+		reg =   <0x5e94000 0x400>,
+			<0x5f08000 0x4>;
+		reg-names = "dsi_ctrl", "disp_cc_base";
+		interrupt-parent = <&mdss_mdp>;
+		interrupts = <4 0>;
+		vdda-1p2-supply = <&L18A>;
+		refgen-supply = <&refgen>;
+		clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+			<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+			<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+			<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+			<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
+			<&dispcc DISP_CC_MDSS_ESC0_CLK>;
+		clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+					"pixel_clk", "pixel_clk_rcg",
+					"esc_clk";
+
+		qcom,ctrl-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,ctrl-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vdda-1p2";
+				qcom,supply-min-voltage = <1232000>;
+				qcom,supply-max-voltage = <1232000>;
+				qcom,supply-enable-load = <21800>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+
+		qcom,core-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,core-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "refgen";
+				qcom,supply-min-voltage = <0>;
+				qcom,supply-max-voltage = <0>;
+				qcom,supply-enable-load = <0>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+	};
+
+	mdss_dsi_phy0: qcom,mdss_dsi_phy0 {
+		compatible = "qcom,dsi-phy-v4.1";
+		label = "dsi-phy-0";
+		cell-index = <0>;
+		reg = <0x5e94400 0x800>,
+			<0x5e94200 0x100>;
+		reg-names = "dsi_phy", "dyn_refresh_base";
+		vdda-0p9-supply = <&L4A>;
+		qcom,platform-strength-ctrl = [55 03
+						55 03
+						55 03
+						55 03
+						55 00];
+		qcom,platform-lane-config = [00 00 0a 0a
+						00 00 0a 0a
+						00 00 0a 0a
+						00 00 0a 0a
+						00 00 8a 8a];
+		qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
+		qcom,phy-supply-entries {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			qcom,phy-supply-entry@0 {
+				reg = <0>;
+				qcom,supply-name = "vdda-0p9";
+				qcom,supply-min-voltage = <880000>;
+				qcom,supply-max-voltage = <880000>;
+				qcom,supply-enable-load = <36000>;
+				qcom,supply-disable-load = <0>;
+			};
+		};
+	};
+};
diff --git a/qcom/khaje-thermal-pm7250b-overlay.dtsi b/qcom/khaje-thermal-pm7250b-overlay.dtsi
new file mode 100644
index 00000000..da513941
--- /dev/null
+++ b/qcom/khaje-thermal-pm7250b-overlay.dtsi
@@ -0,0 +1,116 @@
+#include <dt-bindings/thermal/thermal.h>
+
+&thermal_zones {
+	pm7250b-tz {
+		cooling-maps {
+			trip0_bat {
+				trip = <&pm7250b_trip0>;
+				cooling-device =
+					<&pm7250b_charger (THERMAL_MAX_LIMIT-1)
+						(THERMAL_MAX_LIMIT-1)>;
+			};
+
+			trip1_bat {
+				trip = <&pm7250b_trip1>;
+				cooling-device =
+					<&pm7250b_charger THERMAL_MAX_LIMIT
+						THERMAL_MAX_LIMIT>;
+			};
+		};
+	};
+
+	soc {
+		cooling-maps {
+			soc_cpu4 {
+				trip = <&soc_trip>;
+				cooling-device = <&cpu4_isolate 1 1>;
+			};
+
+			soc_cpu5 {
+				trip = <&soc_trip>;
+				cooling-device = <&cpu5_isolate 1 1>;
+			};
+
+			soc_cpu6 {
+				trip = <&soc_trip>;
+				cooling-device = <&cpu6_isolate 1 1>;
+			};
+
+			soc_cpu7 {
+				trip = <&soc_trip>;
+				cooling-device = <&cpu7_isolate 1 1>;
+			};
+		};
+	};
+
+	pm7250b-bcl-lvl0 {
+		cooling-maps {
+			lbat0_cpufreq4 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device =
+					<&CPU4 (THERMAL_MAX_LIMIT-4)
+						(THERMAL_MAX_LIMIT-4)>;
+			};
+
+			lbat0_cpu6 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&cpu6_isolate 1 1>;
+			};
+
+			lbat0_cpu7 {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&cpu7_isolate 1 1>;
+			};
+
+			lbat0_gpu {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&msm_gpu 2 2>;
+			};
+
+			lbat0_cdsp {
+				trip = <&b_bcl_lvl0>;
+				cooling-device = <&cdsp_sw 2 2>;
+			};
+		};
+	};
+
+	pm7250b-bcl-lvl1 {
+		cooling-maps {
+			lbat1_cpu4 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&cpu4_isolate 1 1>;
+			};
+
+			lbat1_cpu5 {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&cpu5_isolate 1 1>;
+			};
+
+			lbat1_gpu {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&msm_gpu 4 4>;
+			};
+
+			lbat1_cdsp {
+				trip = <&b_bcl_lvl1>;
+				cooling-device = <&cdsp_sw 4 4>;
+			};
+		};
+	};
+
+	pm7250b-bcl-lvl2 {
+		cooling-maps {
+			lbat2_gpu {
+				trip = <&b_bcl_lvl2>;
+				cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+
+			lbat2_cdsp {
+				trip = <&b_bcl_lvl2>;
+				cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+		};
+	};
+};
diff --git a/qcom/khaje-usb.dtsi b/qcom/khaje-usb.dtsi
new file mode 100644
index 00000000..849cdf38
--- /dev/null
+++ b/qcom/khaje-usb.dtsi
@@ -0,0 +1,355 @@
+#include <dt-bindings/clock/qcom,gcc-khaje.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/phy/qcom,khaje-qmp-usb3.h>
+&soc {
+	/* Primary USB port related controller */
+	usb0: ssusb@4e00000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0x4e00000 0x100000>;
+		reg-names = "core_base";
+
+		iommus = <&apps_smmu 0x120 0x0>;
+		qcom,iommu-dma = "atomic";
+		qcom,iommu-dma-addr-pool = <0x50000000 0x60000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "pwr_event_irq", "ss_phy_irq",
+				  "dp_hs_phy_irq", "dm_hs_phy_irq";
+
+		clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+			<&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
+			<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+			<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+			<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+			<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+				"xo", "sleep_clk", "utmi_clk";
+
+		resets = <&gcc GCC_USB30_PRIM_BCR>;
+		reset-names = "core_reset";
+
+		USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
+		dpdm-supply = <&usb2_phy0>;
+
+		qcom,core-clk-rate = <133333333>;
+		qcom,core-clk-rate-hs = <66666667>;
+		qcom,num-gsi-evt-buffs = <0x3>;
+		qcom,gsi-reg-offset =
+			<0x0fc /* GSI_GENERAL_CFG */
+			 0x110 /* GSI_DBL_ADDR_L */
+			 0x120 /* GSI_DBL_ADDR_H */
+			 0x130 /* GSI_RING_BASE_ADDR_L */
+			 0x144 /* GSI_RING_BASE_ADDR_H */
+			 0x1a4>; /* GSI_IF_STS */
+		qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
+		qcom,gsi-disable-io-coherency;
+
+		qcom,msm-bus,name = "usb0";
+		qcom,msm-bus,num-cases = <4>;
+		qcom,msm-bus,num-paths = <3>;
+		qcom,msm-bus,vectors-KBps =
+			/*  suspend vote */
+			<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 0 0>,
+			<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 0>,
+			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 0>,
+
+			/*  nominal vote */
+			<MSM_BUS_MASTER_USB3
+				MSM_BUS_SLAVE_EBI_CH0 240000 700000>,
+			<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
+			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
+
+			/*  svs vote */
+			<MSM_BUS_MASTER_USB3
+				MSM_BUS_SLAVE_EBI_CH0 240000 700000>,
+			<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
+			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
+
+			/*  min vote */
+			<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 1 1>,
+			<MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 1 1>,
+			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 1 1>;
+
+		dwc3@4e00000 {
+			compatible = "snps,dwc3";
+			reg = <0x4e00000 0xe000>;
+			interrupt-parent = <&intc>;
+			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+			usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>;
+			tx-fifo-resize;
+			linux,sysdev_is_parent;
+			snps,disable-clk-gating;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x10>;
+			snps,usb3-u1u2-disable;
+			snps,usb3_lpm_capable;
+			usb-core-id = <0>;
+			maximum-speed = "super-speed";
+			dr_mode = "otg";
+		};
+
+		qcom,usbbam@0x04f04000 {
+			compatible = "qcom,usb-bam-msm";
+			reg = <0x04f04000 0x17000>;
+			interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
+
+			qcom,usb-bam-fifo-baseaddr = <0xc121000>;
+			qcom,usb-bam-num-pipes = <4>;
+			qcom,disable-clk-gating;
+			qcom,usb-bam-override-threshold = <0x4001>;
+			qcom,usb-bam-max-mbps-highspeed = <400>;
+			qcom,usb-bam-max-mbps-superspeed = <3600>;
+			qcom,reset-bam-on-connect;
+
+			qcom,pipe0 {
+				label = "ssusb-qdss-in-0";
+				qcom,usb-bam-mem-type = <2>;
+				qcom,dir = <1>;
+				qcom,pipe-num = <0>;
+				qcom,peer-bam = <0>;
+				qcom,peer-bam-physical-address = <0x08064000>;
+				qcom,src-bam-pipe-index = <0>;
+				qcom,dst-bam-pipe-index = <0>;
+				qcom,data-fifo-offset = <0x0>;
+				qcom,data-fifo-size = <0x1800>;
+				qcom,descriptor-fifo-offset = <0x1800>;
+				qcom,descriptor-fifo-size = <0x800>;
+			};
+		};
+	};
+
+	/* Primary USB port related High Speed PHY */
+	usb2_phy0: hsphy@1613000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x1613000 0x110>,
+			<0x1612000 0x4>;
+		reg-names = "hsusb_phy_base",
+			"eud_enable_reg";
+
+		vdd-supply = <&L4A>;
+		vdda18-supply = <&L12A>;
+		vdda33-supply = <&L15A>;
+		qcom,vdd-voltage-level = <0 880000 880000>;
+
+		clocks = <&rpmcc CXO_SMD_OTG_CLK>,
+			<&gcc GCC_AHB2PHY_USB_CLK>;
+		clock-names =  "ref_clk_src", "cfg_ahb_clk";
+
+		resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+		reset-names = "phy_reset";
+		qcom,param-override-seq =
+			<0xa6 0x6c>,  /* override_x0 */
+			<0x85 0x70>,  /* override_x1 */
+			<0x16 0x74>;  /* override_x2 */
+	};
+
+	/* Primary USB port related QMP USB PHY */
+	usb_qmp_dp_phy: ssphy@1615000 {
+		compatible = "qcom,usb-ssphy-qmp-dp-combo";
+		reg = <0x01615000 0x3000>;
+		reg-names = "qmp_phy_base";
+
+		core-supply = <&L18A>;
+		qcom,vdd-voltage-level = <0 880000 880000>;
+		qcom,core-voltage-level = <0 1232000 1260000>;
+
+		clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+			 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+			 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
+			 <&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
+			 <&rpmcc CXO_SMD_OTG_CLK>,
+			 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+			 <&gcc GCC_AHB2PHY_USB_CLK>;
+
+		clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
+				"pipe_clk_ext_src", "ref_clk_src",
+				"com_aux_clk","cfg_ahb_clk";
+
+		resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+			 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
+		reset-names = "global_phy_reset", "phy_reset";
+
+		qcom,qmp-phy-reg-offset =
+			<USB3_DP_PCS_PCS_STATUS1
+			 USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL
+			 USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
+			 USB3_DP_PCS_POWER_DOWN_CONTROL
+			 USB3_DP_PCS_SW_RESET
+			 USB3_DP_PCS_START_CONTROL
+			 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
+			 0x2a18 /* USB3_DP_DP_PHY_PD_CTL */
+			 USB3_DP_COM_POWER_DOWN_CTRL
+			 USB3_DP_COM_SW_RESET
+			 USB3_DP_COM_RESET_OVRD_CTRL
+			 USB3_DP_COM_PHY_MODE_CTRL
+			 USB3_DP_COM_TYPEC_CTRL
+			 USB3_DP_COM_SWI_CTRL
+			 USB3_DP_PCS_CLAMP_ENABLE>;
+
+		qcom,qmp-phy-init-seq =
+			/* <reg_offset, value, delay> */
+			<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0
+			USB3_DP_QSERDES_COM_SSC_PER1 0x31 0
+			USB3_DP_QSERDES_COM_SSC_PER2 0x01 0
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
+			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0
+			USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
+			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0
+			USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
+			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0
+			USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82 0
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
+			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
+			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
+			USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0
+			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x60 0
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x60 0
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x11 0
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x02 0
+			USB3_DP_QSERDES_TXA_LANE_MODE_1 0xD5 0
+			USB3_DP_QSERDES_TXA_LANE_MODE_2 0x00 0
+			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
+			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x40 0
+			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x09 0
+			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0
+			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
+			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08 0
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00 0
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04 0
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0C 0
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0 0
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0
+			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
+			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0
+			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0
+			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xFF 0
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7F 0
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x7F 0
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x7F 0
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x97 0
+			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC 0
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xDC 0
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x5C 0
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x7B 0
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xB4 0
+			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0
+			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0
+			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0
+			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0
+			USB3_DP_QSERDES_RXA_GM_CAL 0x1F 0
+			USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x60 0
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x60 0
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x11 0
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x02 0
+			USB3_DP_QSERDES_TXB_LANE_MODE_1 0xD5 0
+			USB3_DP_QSERDES_TXB_LANE_MODE_2 0x00 0
+			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
+			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x54 0
+			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x09 0
+			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0
+			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
+			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08 0
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00 0
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04 0
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0C 0
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0 0
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0
+			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
+			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0
+			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0
+			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x7F 0
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xFF 0
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x3F 0
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x7F 0
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xA6 0
+			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC 0
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xDC 0
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x5C 0
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x7B 0
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xB4 0
+			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0
+			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0
+			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0
+			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0
+			USB3_DP_QSERDES_RXB_GM_CAL 0x1F 0
+			USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0
+			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0 0
+			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0
+			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0
+			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0
+			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0
+			USB3_DP_PCS_RX_SIGDET_LVL 0xA9 0
+			USB3_DP_PCS_CDR_RESET_TIME 0x0A 0
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0
+			USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0
+			USB3_DP_PCS_EQ_CONFIG1 0x4B 0
+			USB3_DP_PCS_EQ_CONFIG5 0x10 0
+			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0
+			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
+			0xffffffff 0xffffffff 0x00>;
+	};
+
+	usb_nop_phy: usb_nop_phy {
+		compatible = "usb-nop-xceiv";
+	};
+
+	usb_audio_qmi_dev {
+		compatible = "qcom,usb-audio-qmi-dev";
+		iommus = <&apps_smmu 0x1cf 0x0>;
+		qcom,iommu-dma = "disabled";
+		qcom,usb-audio-stream-id = <0xf>;
+		qcom,usb-audio-intr-num = <2>;
+	};
+};
diff --git a/qcom/khaje.dts b/qcom/khaje.dts
new file mode 100644
index 00000000..b522b78f
--- /dev/null
+++ b/qcom/khaje.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Khaje SoC";
+	compatible = "qcom,khaje";
+	qcom,board-id = <0 0>;
+};
diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi
new file mode 100644
index 00000000..28c4c58d
--- /dev/null
+++ b/qcom/khaje.dtsi
@@ -0,0 +1,4398 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,dispcc-khaje.h>
+#include <dt-bindings/clock/qcom,gcc-khaje.h>
+#include <dt-bindings/clock/qcom,gpucc-khaje.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/soc/qcom,dcc_v2.h>
+
+#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
+#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
+
+#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\
+				opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\
+				opp-supported-hw = <ddrtype>;}
+
+#define DDR_TYPE_LPDDR3		5
+#define DDR_TYPE_LPDDR4X	7
+
+/ {
+	model = "Qualcomm Technologies, Inc. Khaje SoC";
+	compatible = "qcom,khaje";
+	qcom,msm-id = <518 0x10000>;
+	interrupt-parent = <&wakegic>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+	memory { device_type = "memory"; reg = <0 0 0 0>; };
+
+	mem-offline {
+		compatible = "qcom,mem-offline";
+		offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
+				<0x1 0xc0000000 0x0 0x80000000>,
+				<0x2 0xc0000000 0x1 0x40000000>;
+		granule = <512>;
+	};
+
+	aliases {
+		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
+		sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
+		swr0 = &swr0;
+		swr1 = &swr1;
+		ufshc1 = &ufshc_mem; /* Embedded UFS slot */
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+			qcom,freq-domain = <&cpufreq_hw 0 7>;
+			qcom,lmh-dcvs = <&lmh_dcvs0>;
+			#cooling-cells = <2>;
+			L2_0: l2-cache {
+				compatible = "arm,arch-cache";
+				cache-level = <2>;
+			};
+
+			L1_I_0: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L1_D_0: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x1>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+			qcom,freq-domain = <&cpufreq_hw 0 7>;
+			qcom,lmh-dcvs = <&lmh_dcvs0>;
+
+			L1_I_1: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L1_D_1: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x2>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+			qcom,freq-domain = <&cpufreq_hw 0 7>;
+			qcom,lmh-dcvs = <&lmh_dcvs0>;
+
+			L1_I_2: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L1_D_2: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x3>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+			qcom,freq-domain = <&cpufreq_hw 0 7>;
+			qcom,lmh-dcvs = <&lmh_dcvs0>;
+
+			L1_I_3: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L1_D_3: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU4: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			capacity-dmips-mhz = <1638>;
+			dynamic-power-coefficient = <282>;
+			next-level-cache = <&L2_1>;
+			qcom,freq-domain = <&cpufreq_hw 1 7>;
+			qcom,lmh-dcvs = <&lmh_dcvs1>;
+			#cooling-cells = <2>;
+			L2_1: l2-cache {
+				compatible = "arm,arch-cache";
+				cache-level = <2>;
+			};
+
+			L1_I_100: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L1_D_100: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU5: cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x101>;
+			capacity-dmips-mhz = <1638>;
+			dynamic-power-coefficient = <282>;
+			enable-method = "psci";
+			next-level-cache = <&L2_1>;
+			qcom,freq-domain = <&cpufreq_hw 1 7>;
+			qcom,lmh-dcvs = <&lmh_dcvs1>;
+
+			L1_I_101: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L1_D_101: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU6: cpu@102 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x102>;
+			capacity-dmips-mhz = <1638>;
+			dynamic-power-coefficient = <282>;
+			enable-method = "psci";
+			next-level-cache = <&L2_1>;
+			qcom,freq-domain = <&cpufreq_hw 1 7>;
+			qcom,lmh-dcvs = <&lmh_dcvs1>;
+
+			L1_I_102: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L1_D_102: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU7: cpu@103 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x103>;
+			capacity-dmips-mhz = <1638>;
+			dynamic-power-coefficient = <282>;
+			enable-method = "psci";
+			next-level-cache = <&L2_1>;
+			qcom,freq-domain = <&cpufreq_hw 1 7>;
+			qcom,lmh-dcvs = <&lmh_dcvs1>;
+
+			L1_I_103: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L1_D_103: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+
+				core3 {
+					cpu = <&CPU3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&CPU4>;
+				};
+
+				core1 {
+					cpu = <&CPU5>;
+				};
+
+				core2 {
+					cpu = <&CPU6>;
+				};
+
+				core3 {
+					cpu = <&CPU7>;
+				};
+			};
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	firmware: firmware {
+		android {
+			compatible = "android,firmware";
+			vbmeta {
+				compatible="android,vbmeta";
+				parts = "vbmeta,boot,system,vendor,dtbo,recovery";
+			};
+
+			fstab {
+				compatible = "android,fstab";
+				vendor {
+					compatible = "android,vendor";
+					dev = "/dev/block/platform/soc/4744000.sdhci/by-name/vendor";
+					type = "ext4";
+					mnt_flags = "ro,barrier=1,discard";
+					fsmgr_flags = "wait,slotselect,avb";
+					status = "ok";
+				};
+			};
+		};
+	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		hyp_mem: hyp_region@45700000 {
+			compatible = "removed-dma-pool";
+			no-map;
+			reg = <0x0 0x45700000 0x0 0x600000>;
+		};
+
+		xbl_aop_mem: xbl_aop_region@45e00000 {
+			compatible = "removed-dma-pool";
+			no-map;
+			reg = <0x0 0x45e00000 0x0 0x140000>;
+		};
+
+		sec_apps_mem: sec_apps_region@45fff000 {
+			compatible = "removed-dma-pool";
+			no-map;
+			reg = <0x0 0x45fff000 0x0 0x1000>;
+		};
+
+		smem_mem: smem_region@46000000 {
+			compatible = "removed-dma-pool";
+			no-map;
+			reg = <0x0 0x46000000 0x0 0x200000>;
+		};
+
+		removed_mem: removed_region@60000000 {
+			compatible = "removed-dma-pool";
+			no-map;
+			reg = <0x0 0x60000000 0x0 0x3900000>;
+		};
+
+		pil_modem_mem: modem_region@4ab00000 {
+			compatible = "removed-dma-pool";
+			no-map;
+			reg = <0x0 0x4ab00000 0x0 0x6900000>;
+		};
+
+		pil_video_mem: pil_video_region@51400000 {
+			compatible = "removed-dma-pool";
+			no-map;
+			reg = <0x0 0x51400000 0x0 0x500000>;
+		};
+
+		wlan_msa_mem: wlan_msa_region@51900000 {
+			compatible = "removed-dma-pool";
+			no-map;
+			reg = <0x0 0x51900000 0x0 0x100000>;
+		};
+
+		pil_cdsp_mem: cdsp_regions@51a00000 {
+			compatible = "removed-dma-pool";
+			no-map;
+			reg = <0x0 0x51a00000 0x0 0x1e00000>;
+		};
+
+		pil_adsp_mem: pil_adsp_region@53800000 {
+			compatible = "removed-dma-pool";
+			no-map;
+			reg = <0x0 0x53800000 0x0 0x1e00000>;
+		};
+
+		pil_ipa_fw_mem: ipa_fw_region@55600000 {
+			compatible = "removed-dma-pool";
+			no-map;
+			reg = <0x0 0x55600000 0x0 0x10000>;
+		};
+
+		pil_ipa_gsi_mem: ipa_gsi_region@55610000 {
+			compatible = "removed-dma-pool";
+			no-map;
+			reg = <0x0 0x55610000 0x0 0x5000>;
+		};
+
+		pil_gpu_mem: gpu_region@55615000 {
+			compatible = "removed-dma-pool";
+			no-map;
+			reg = <0x0 0x55615000 0x0 0x2000>;
+		};
+
+		user_contig_mem: user_contig_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x1000000>;
+		};
+
+		qseecom_mem: qseecom_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x1400000>;
+		};
+
+		qseecom_ta_mem: qseecom_ta_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x1000000>;
+		};
+
+		cdsp_sec_mem: cdsp_sec_regions@46200000 {
+			compatible = "removed-dma-pool";
+			no-map;
+			reg = <0x0 0x46200000 0x0 0x1e00000>;
+		};
+
+		secure_display_memory: secure_display_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0 0x00000000 0 0xffffffff>;
+			reusable;
+			alignment = <0 0x400000>;
+			size = <0 0x5c00000>;
+		};
+
+		cont_splash_memory: cont_splash_region@5c000000 {
+			reg = <0x0 0x5c000000 0x0 0x00f00000>;
+			label = "cont_splash_region";
+		};
+
+		disp_rdump_memory: disp_rdump_region@5c000000 {
+			reg = <0x0 0x5c000000 0x0 0x00f00000>;
+			label = "disp_rdump_region";
+		};
+
+		dfps_data_memory: dfps_data_region@5cf00000 {
+			reg = <0x0 0x5cf00000 0x0 0x0100000>;
+			label = "dfps_data_region";
+		};
+
+		adsp_mem: adsp_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0 0x00000000 0 0xffffffff>;
+			reusable;
+			alignment = <0 0x400000>;
+			size = <0 0x800000>;
+		};
+
+		dump_mem: mem_dump_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			size = <0 0x800000>;
+		};
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x2000000>;
+			linux,cma-default;
+		};
+	};
+
+	chosen {
+		bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off";
+	};
+
+	soc: soc { };
+};
+
+#include "bengal-coresight.dtsi"
+
+&soc {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0 0 0 0xffffffff>;
+	compatible = "simple-bus";
+
+	intc: interrupt-controller@f200000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupt-parent = <&intc>;
+		#redistributor-regions = <1>;
+		redistributor-stride = <0x0 0x20000>;
+		reg = <0xf200000 0x10000>,     /* GICD */
+		      <0xf300000 0x100000>;    /* GICR * 8 */
+		interrupts = <1 9 4>;
+	};
+
+	jtag_mm0: jtagmm@9040000 {
+		compatible = "qcom,jtagv8-mm";
+		reg = <0x9040000 0x1000>;
+		reg-names = "etm-base";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "core_clk";
+
+		qcom,coresight-jtagmm-cpu = <&CPU0>;
+	};
+
+	jtag_mm1: jtagmm@9140000 {
+		compatible = "qcom,jtagv8-mm";
+		reg = <0x9140000 0x1000>;
+		reg-names = "etm-base";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "core_clk";
+
+		qcom,coresight-jtagmm-cpu = <&CPU1>;
+	};
+
+	jtag_mm2: jtagmm@9240000 {
+		compatible = "qcom,jtagv8-mm";
+		reg = <0x9240000 0x1000>;
+		reg-names = "etm-base";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "core_clk";
+
+		qcom,coresight-jtagmm-cpu = <&CPU2>;
+	};
+
+	jtag_mm3: jtagmm@9340000 {
+		compatible = "qcom,jtagv8-mm";
+		reg = <0x9340000 0x1000>;
+		reg-names = "etm-base";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "core_clk";
+
+		qcom,coresight-jtagmm-cpu = <&CPU3>;
+	};
+
+	jtag_mm4: jtagmm@9440000 {
+		compatible = "qcom,jtagv8-mm";
+		reg = <0x9440000 0x1000>;
+		reg-names = "etm-base";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "core_clk";
+
+		qcom,coresight-jtagmm-cpu = <&CPU4>;
+	};
+
+	jtag_mm5: jtagmm@9540000 {
+		compatible = "qcom,jtagv8-mm";
+		reg = <0x9540000 0x1000>;
+		reg-names = "etm-base";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "core_clk";
+
+		qcom,coresight-jtagmm-cpu = <&CPU5>;
+	};
+
+	jtag_mm6: jtagmm@9640000 {
+		compatible = "qcom,jtagv8-mm";
+		reg = <0x9640000 0x1000>;
+		reg-names = "etm-base";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "core_clk";
+
+		qcom,coresight-jtagmm-cpu = <&CPU6>;
+	};
+
+	jtag_mm7: jtagmm@9740000 {
+		compatible = "qcom,jtagv8-mm";
+		reg = <0x9740000 0x1000>;
+		reg-names = "etm-base";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "core_clk";
+
+		qcom,coresight-jtagmm-cpu = <&CPU7>;
+	};
+
+	qcom,memshare {
+		compatible = "qcom,memshare";
+
+		qcom,client_1 {
+			compatible = "qcom,memshare-peripheral";
+			qcom,peripheral-size = <0x0>;
+			qcom,client-id = <0>;
+			qcom,allocate-boot-time;
+			label = "modem";
+		};
+
+		qcom,client_2 {
+			compatible = "qcom,memshare-peripheral";
+			qcom,peripheral-size = <0x0>;
+			qcom,client-id = <2>;
+			label = "modem";
+		};
+
+		mem_client_3_size: qcom,client_3 {
+			compatible = "qcom,memshare-peripheral";
+			qcom,peripheral-size = <0x500000>;
+			qcom,client-id = <1>;
+			qcom,allocate-on-request;
+			label = "modem";
+		};
+	};
+
+	slim_aud: slim@a5c0000 {
+		cell-index = <1>;
+		compatible = "qcom,slim-ngd";
+		reg = <0xa5c0000 0x2c000>,
+			<0xa584000 0x20000>, <0xa66e000 0x2000>;
+		reg-names = "slimbus_physical",
+			"slimbus_bam_physical", "slimbus_lpass_mem";
+		interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "slimbus_irq", "slimbus_bam_irq";
+		qcom,apps-ch-pipes = <0x0>;
+		qcom,ea-pc = <0x3b0>;
+		status = "ok";
+
+		/* Slimbus Slave DT for WCN3990 */
+		btfmslim_codec: wcn3990 {
+			compatible = "qcom,btfmslim_slave";
+			elemental-addr = [00 01 20 02 17 02];
+			qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
+			qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
+		};
+	};
+
+	wakegic: wake-gic {
+		compatible = "qcom,mpm-gic-khaje", "qcom,mpm-gic";
+		interrupts-extended = <&wakegic GIC_SPI 197
+						IRQ_TYPE_EDGE_RISING>;
+		reg = <0x45f01b8 0x1000>,
+			<0xf011008 0x4>;  /* MSM_APCS_GCC_BASE 4K */
+		reg-names = "vmpm", "ipc";
+		qcom,num-mpm-irqs = <96>;
+		interrupt-controller;
+		interrupt-parent = <&intc>;
+		#interrupt-cells = <3>;
+	};
+
+	wakegpio: wake-gpio {
+		compatible = "qcom,mpm-gpio";
+		interrupt-controller;
+		interrupt-parent = <&intc>;
+		#interrupt-cells = <2>;
+	};
+
+	bluetooth: bt_wcn3990 {
+		compatible = "qca,wcn3990";
+		qca,bt-sw-ctrl-gpio = <&tlmm 87 0>; /* SW_CTRL */
+		qca,bt-vdd-io-supply =   <&L9A>;  /* IO */
+		qca,bt-vdd-core-supply = <&L17A>; /* RFA */
+		qca,bt-vdd-pa-supply =   <&L23A>; /* CH0 */
+		qca,bt-vdd-xtal-supply = <&L16A>; /* XO */
+
+		qca,bt-vdd-io-voltage-level = <1700000 1900000>;
+		qca,bt-vdd-core-voltage-level = <1304000 1304000>;
+		qca,bt-vdd-pa-voltage-level = <3000000 3312000>;
+		qca,bt-vdd-xtal-voltage-level = <1700000 1900000>;
+
+		qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */
+		qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */
+		qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */
+		qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <1 1 0xf08>,
+			     <1 2 0xf08>,
+			     <1 3 0xf08>,
+			     <1 0 0xf08>;
+		clock-frequency = <19200000>;
+	};
+
+	dcc: dcc_v2@1be2000 {
+		compatible = "qcom,dcc-v2";
+		reg = <0x1be2000 0x1000>,
+			<0x1bee000 0x2000>;
+		reg-names = "dcc-base", "dcc-ram-base";
+		dcc-ram-offset = <0x2000>;
+
+		link_list1 {
+			qcom,curr-link-list = <3>;
+			qcom,data-sink = "sram";
+			qcom,link-list = <DCC_READ 0x0F1880B4 1 0>,
+				<DCC_READ 0x0F1980B4 1 0>,
+				<DCC_READ 0x0F1A80B4 1 0>,
+				<DCC_READ 0x0F1B80B4 1 0>,
+				<DCC_READ 0x0F0880B4 1 0>,
+				<DCC_READ 0x0F0980B4 1 0>,
+				<DCC_READ 0x0F0A80B4 1 0>,
+				<DCC_READ 0x0F0B80B4 1 0>,
+				<DCC_READ 0x0F1D1228 1 0>,
+				<DCC_READ 0x0F1880B0 1 0>,
+				<DCC_READ 0x0F1980B0 1 0>,
+				<DCC_READ 0x0F1A80B0 1 0>,
+				<DCC_READ 0x0F1B80B0 1 0>,
+				<DCC_READ 0x0F0880B0 1 0>,
+				<DCC_READ 0x0F0980B0 1 0>,
+				<DCC_READ 0x0F0A80B0 1 0>,
+				<DCC_READ 0x0F0B80B0 1 0>,
+				<DCC_READ 0x0F1880B8 1 0>,
+				<DCC_READ 0x0F1980B8 1 0>,
+				<DCC_READ 0x0F1A80B8 1 0>,
+				<DCC_READ 0x0F1B80B8 1 0>,
+				<DCC_READ 0x0F0880B8 1 0>,
+				<DCC_READ 0x0F0980B8 1 0>,
+				<DCC_READ 0x0F0A80B8 1 0>,
+				<DCC_READ 0x0F0B80B8 1 0>,
+				<DCC_READ 0x0F1D160C 1 0>,
+				<DCC_READ 0x0F1D120C 1 0>,
+				<DCC_READ 0x0F1D1434 1 0>,
+				<DCC_READ 0x0F1D141C 5 0>,
+				<DCC_READ 0x0F1D1448 1 0>,
+				<DCC_READ 0x0F1D144C 1 0>,
+				<DCC_READ 0xA754520 1 0>,
+				<DCC_READ 0xA751020 1 0>,
+				<DCC_READ 0xA751024 1 0>,
+				<DCC_READ 0xA751030 1 0>,
+				<DCC_READ 0xA751200 1 0>,
+				<DCC_READ 0xA751214 1 0>,
+				<DCC_READ 0xA751228 1 0>,
+				<DCC_READ 0xA75123C 1 0>,
+				<DCC_READ 0xA751250 1 0>,
+				<DCC_READ 0xA751204 1 0>,
+				<DCC_READ 0xA751218 1 0>,
+				<DCC_READ 0xA75122C 1 0>,
+				<DCC_READ 0xA751240 1 0>,
+				<DCC_READ 0xA751254 1 0>,
+				<DCC_READ 0xA751208 1 0>,
+				<DCC_READ 0xA75121C 1 0>,
+				<DCC_READ 0xA751230 1 0>,
+				<DCC_READ 0xA751244 1 0>,
+				<DCC_READ 0xA751258 1 0>,
+				<DCC_READ 0xA754510 1 0>,
+				<DCC_READ 0xA754514 1 0>,
+				<DCC_READ 0xA750010 1 0>,
+				<DCC_READ 0xA750014 1 0>,
+				<DCC_READ 0xA750900 1 0>,
+				<DCC_READ 0xA750904 1 0>,
+				<DCC_READ 0x0A402028 1 0>,
+				<DCC_READ 0x0A900010 1 0>,
+				<DCC_READ 0x0A900014 1 0>,
+				<DCC_READ 0x0A900018 1 0>,
+				<DCC_READ 0x0A900030 1 0>,
+				<DCC_READ 0x0A900038 1 0>,
+				<DCC_READ 0x0A900040 1 0>,
+				<DCC_READ 0x0A900048 1 0>,
+				<DCC_READ 0x0A9000D0 1 0>,
+				<DCC_READ 0x0A900210 1 0>,
+				<DCC_READ 0x0A900230 1 0>,
+				<DCC_READ 0x0A900250 1 0>,
+				<DCC_READ 0x0A900270 1 0>,
+				<DCC_READ 0x0A900290 1 0>,
+				<DCC_READ 0x0A9002B0 1 0>,
+				<DCC_READ 0x0A900208 1 0>,
+				<DCC_READ 0x0A900228 1 0>,
+				<DCC_READ 0x0A900248 1 0>,
+				<DCC_READ 0x0A900268 1 0>,
+				<DCC_READ 0x0A900288 1 0>,
+				<DCC_READ 0x0A9002A8 1 0>,
+				<DCC_READ 0x0A90020C 1 0>,
+				<DCC_READ 0x0A90022C 1 0>,
+				<DCC_READ 0x0A90024C 1 0>,
+				<DCC_READ 0x0A90026C 1 0>,
+				<DCC_READ 0x0A90028C 1 0>,
+				<DCC_READ 0x0A9002AC 1 0>,
+				<DCC_READ 0x0A900404 1 0>,
+				<DCC_READ 0x0A900408 1 0>,
+				<DCC_READ 0x0A900400 1 0>,
+				<DCC_READ 0x0A900D04 1 0>,
+				<DCC_READ 0x0A4B0010 1 0>,
+				<DCC_READ 0x0A4B0014 1 0>,
+				<DCC_READ 0x0A4B0018 1 0>,
+				<DCC_READ 0x0A4B0210 1 0>,
+				<DCC_READ 0x0A4B0230 1 0>,
+				<DCC_READ 0x0A4B0250 1 0>,
+				<DCC_READ 0x0A4B0270 1 0>,
+				<DCC_READ 0x0A4B0290 1 0>,
+				<DCC_READ 0x0A4B02B0 1 0>,
+				<DCC_READ 0x0A4B0208 1 0>,
+				<DCC_READ 0x0A4B0228 1 0>,
+				<DCC_READ 0x0A4B0248 1 0>,
+				<DCC_READ 0x0A4B0268 1 0>,
+				<DCC_READ 0x0A4B0288 1 0>,
+				<DCC_READ 0x0A4B02A8 1 0>,
+				<DCC_READ 0x0A4B020C 1 0>,
+				<DCC_READ 0x0A4B022C 1 0>,
+				<DCC_READ 0x0A4B024C 1 0>,
+				<DCC_READ 0x0A4B026C 1 0>,
+				<DCC_READ 0x0A4B028C 1 0>,
+				<DCC_READ 0x0A4B02AC 1 0>,
+				<DCC_READ 0x0A4B0400 1 0>,
+				<DCC_READ 0x0A4B0404 1 0>,
+				<DCC_READ 0x0A4B0408 1 0>,
+				<DCC_READ 0x4488100 1 0>,
+				<DCC_READ 0x4488400 2 0>,
+				<DCC_READ 0x4488410 1 0>,
+				<DCC_READ 0x4488420 2 0>,
+				<DCC_READ 0x4488430 2 0>,
+				<DCC_READ 0x448c100 1 0>,
+				<DCC_READ 0x448c400 2 0>,
+				<DCC_READ 0x448c410 1 0>,
+				<DCC_READ 0x448c420 2 0>,
+				<DCC_READ 0x448c430 2 0>,
+				<DCC_READ 0x4490100 1 0>,
+				<DCC_READ 0x4490400 2 0>,
+				<DCC_READ 0x4490410 1 0>,
+				<DCC_READ 0x4490420 2 0>,
+				<DCC_READ 0x4490430 2 0>,
+				<DCC_READ 0x4494100 1 0>,
+				<DCC_READ 0x4494400 2 0>,
+				<DCC_READ 0x4494410 1 0>,
+				<DCC_READ 0x4494420 2 0>,
+				<DCC_READ 0x4494430 2 0>,
+				<DCC_READ 0x449810c 1 0>,
+				<DCC_READ 0x4498400 2 0>,
+				<DCC_READ 0x4498410 1 0>,
+				<DCC_READ 0x4498420 2 0>,
+				<DCC_READ 0x4498430 2 0>,
+				<DCC_READ 0x44a0100 1 0>,
+				<DCC_READ 0x44a0400 2 0>,
+				<DCC_READ 0x44a0410 1 0>,
+				<DCC_READ 0x44a0420 2 0>,
+				<DCC_READ 0x44a0430 2 0>,
+				<DCC_READ 0x44b0560 1 0>,
+				<DCC_READ 0x44b05a0 1 0>,
+				<DCC_READ 0x44b1800 1 0>,
+				<DCC_READ 0x44b408c 1 0>,
+				<DCC_READ 0x44b409c 1 0>,
+				<DCC_READ 0x44b0520 1 0>,
+				<DCC_READ 0x44b5070 2 0>,
+				<DCC_READ 0x44bc220 1 0>,
+				<DCC_READ 0x44bc400 7 0>,
+				<DCC_READ 0x44bc420 9 0>,
+				<DCC_READ 0x44bd800 1 0>,
+				<DCC_READ 0x44c5800 1 0>,
+				<DCC_READ 0x4480040 2 0>,
+				<DCC_READ 0x4480810 2 0>,
+				<DCC_READ 0x44b0a40 1 0>,
+				<DCC_READ 0x4506044 1 0>,
+				<DCC_READ 0x45061dc 1 0>,
+				<DCC_READ 0x45061ec 1 0>,
+				<DCC_READ 0x4506028 2 0>,
+				<DCC_READ 0x4506094 1 0>,
+				<DCC_READ 0x4506608 1 0>,
+				<DCC_READ 0x447d02c 4 0>,
+				<DCC_READ 0x447d040 1 0>,
+				<DCC_READ 0x450002c 2 0>,
+				<DCC_READ 0x4500094 1 0>,
+				<DCC_READ 0x450009c 1 0>,
+				<DCC_READ 0x45000c4 2 0>,
+				<DCC_READ 0x45003dc 1 0>,
+				<DCC_READ 0x45005d8 1 0>,
+				<DCC_READ 0x450102c 2 0>,
+				<DCC_READ 0x4501094 1 0>,
+				<DCC_READ 0x450109c 1 0>,
+				<DCC_READ 0x45010c4 2 0>,
+				<DCC_READ 0x45013dc 1 0>,
+				<DCC_READ 0x45015d8 1 0>,
+				<DCC_READ 0x450202c 2 0>,
+				<DCC_READ 0x4502094 1 0>,
+				<DCC_READ 0x450209c 1 0>,
+				<DCC_READ 0x45020c4 2 0>,
+				<DCC_READ 0x45023dc 1 0>,
+				<DCC_READ 0x45025d8 1 0>,
+				<DCC_READ 0x450302c 2 0>,
+				<DCC_READ 0x4503094 1 0>,
+				<DCC_READ 0x450309c 1 0>,
+				<DCC_READ 0x45030c4 2 0>,
+				<DCC_READ 0x45033dc 1 0>,
+				<DCC_READ 0x45035d8 1 0>,
+				<DCC_READ 0x450402c 2 0>,
+				<DCC_READ 0x4504094 1 0>,
+				<DCC_READ 0x450409c 1 0>,
+				<DCC_READ 0x45040c8 2 0>,
+				<DCC_READ 0x45043dc 1 0>,
+				<DCC_READ 0x45045d8 1 0>,
+				<DCC_READ 0x450502c 2 0>,
+				<DCC_READ 0x4505094 1 0>,
+				<DCC_READ 0x450509c 1 0>,
+				<DCC_READ 0x45050c4 2 0>,
+				<DCC_READ 0x45053dc 1 0>,
+				<DCC_READ 0x45055d8 1 0>,
+				<DCC_READ 0x141102C 1 0>,
+				<DCC_READ 0x1436004 1 0>,
+				<DCC_READ 0x1471154 1 0>,
+				<DCC_READ 0x141050C 1 0>,
+				<DCC_READ 0x143600C 1 0>,
+				<DCC_READ 0x1436018 1 0>,
+				<DCC_READ 0x147C000 1 0>,
+				<DCC_READ 0x147D000 1 0>,
+				<DCC_READ 0x1436048 1 0>,
+				<DCC_READ 0x1436040 1 0>,
+				<DCC_READ 0x5991004 1 0>,
+				<DCC_READ 0x599100c 1 0>,
+				<DCC_READ 0x5991010 1 0>,
+				<DCC_READ 0x5991014 1 0>,
+				<DCC_READ 0x5991054 1 0>,
+				<DCC_READ 0x5991060 1 0>,
+				<DCC_READ 0x599106c 1 0>,
+				<DCC_READ 0x5991070 1 0>,
+				<DCC_READ 0x5991074 1 0>,
+				<DCC_READ 0x5991078 1 0>,
+				<DCC_READ 0x599107c 1 0>,
+				<DCC_READ 0x599108c 1 0>,
+				<DCC_READ 0x5991098 1 0>,
+				<DCC_READ 0x599109c 1 0>,
+				<DCC_READ 0x5991540 1 0>,
+				<DCC_READ 0x5995000 1 0>,
+				<DCC_READ 0x5995004 1 0>,
+				<DCC_READ 0x599101C 1 0>,
+				<DCC_READ 0x5991020 1 0>,
+				<DCC_READ 0x5990000 1 0>,
+				<DCC_READ 0x5990100 1 0>,
+				<DCC_READ 0x5991508 1 0>,
+				<DCC_READ 0x59910A4 1 0>,
+				<DCC_READ 0x5991578 1 0>,
+				<DCC_READ 0x5990010 1 0>,
+				<DCC_READ 0x5990110 1 0>,
+				<DCC_READ 0xf189000 1 0>,
+				<DCC_READ 0xf18900c 1 0>,
+				<DCC_READ 0xf189c0c 1 0>,
+				<DCC_READ 0xf189c10 1 0>,
+				<DCC_READ 0xf189c20 1 0>,
+				<DCC_READ 0xf199000 1 0>,
+				<DCC_READ 0xf19900c 1 0>,
+				<DCC_READ 0xf199c0c 1 0>,
+				<DCC_READ 0xf199c10 1 0>,
+				<DCC_READ 0xf199c20 1 0>,
+				<DCC_READ 0xf1a9000 1 0>,
+				<DCC_READ 0xf1a900c 1 0>,
+				<DCC_READ 0xf1a9c0c 1 0>,
+				<DCC_READ 0xf1a9c10 1 0>,
+				<DCC_READ 0xf1a9c20 1 0>,
+				<DCC_READ 0xf1b9000 1 0>,
+				<DCC_READ 0xf1b900c 1 0>,
+				<DCC_READ 0xf1b9c0c 1 0>,
+				<DCC_READ 0xf1b9c10 1 0>,
+				<DCC_READ 0xf1b9c18 1 0>,
+				<DCC_READ 0xf089000 1 0>,
+				<DCC_READ 0xf08900c 1 0>,
+				<DCC_READ 0xf089c0c 1 0>,
+				<DCC_READ 0xf089c10 1 0>,
+				<DCC_READ 0xf089c20 1 0>,
+				<DCC_READ 0xf099000 1 0>,
+				<DCC_READ 0xf09900c 1 0>,
+				<DCC_READ 0xf099c0c 1 0>,
+				<DCC_READ 0xf099c10 1 0>,
+				<DCC_READ 0xf099c20 1 0>,
+				<DCC_READ 0xf0a9000 1 0>,
+				<DCC_READ 0xf0a900c 1 0>,
+				<DCC_READ 0xf0a9c0c 1 0>,
+				<DCC_READ 0xf0a9c10 1 0>,
+				<DCC_READ 0xf0a9c20 1 0>,
+				<DCC_READ 0xf0b9000 1 0>,
+				<DCC_READ 0xf0b900c 1 0>,
+				<DCC_READ 0xf0b9c0c 1 0>,
+				<DCC_READ 0xf0b9c10 1 0>,
+				<DCC_READ 0xf0b9c20 1 0>,
+				<DCC_READ 0xf112000 1 0>,
+				<DCC_READ 0xf11200c 1 0>,
+				<DCC_READ 0xf112c0c 1 0>,
+				<DCC_READ 0xf112c10 1 0>,
+				<DCC_READ 0xf112c20 1 0>,
+				<DCC_READ 0xf012000 1 0>,
+				<DCC_READ 0xf01200c 1 0>,
+				<DCC_READ 0xf012c0c 1 0>,
+				<DCC_READ 0xf012c10 1 0>,
+				<DCC_READ 0xf012c20 1 0>,
+				<DCC_READ 0xf1d2000 1 0>,
+				<DCC_READ 0xf1d200c 1 0>,
+				<DCC_READ 0xf1d2c0c 1 0>,
+				<DCC_READ 0xf1d2c10 1 0>,
+				<DCC_READ 0xf1d2c20 1 0>,
+				<DCC_READ 0xf011014 1 0>,
+				<DCC_READ 0xf011018 1 0>,
+				<DCC_READ 0xf011218 1 0>,
+				<DCC_READ 0xf011234 1 0>,
+				<DCC_READ 0xf011220 1 0>,
+				<DCC_READ 0xf011264 1 0>,
+				<DCC_READ 0xf011290 1 0>,
+				<DCC_READ 0xf111014 1 0>,
+				<DCC_READ 0xf111018 1 0>,
+				<DCC_READ 0xf111218 1 0>,
+				<DCC_READ 0xf111234 1 0>,
+				<DCC_READ 0xf111264 1 0>,
+				<DCC_READ 0xf111290 1 0>,
+				<DCC_READ 0x0F521700 1 0>,
+				<DCC_READ 0x0F523700 1 0>,
+				<DCC_READ 0x0F112C18 1 0>,
+				<DCC_READ 0x0F012C18 1 0>,
+				<DCC_READ 0x0F513A84 1 0>,
+				<DCC_READ 0x0F513A88 1 0>,
+				<DCC_READ 0x01B60110 1 0>,
+				<DCC_READ 0x1900010 1 0>,
+				<DCC_READ 0x1900020 1 0>,
+				<DCC_READ 0x1900024 1 0>,
+				<DCC_READ 0x1900028 1 0>,
+				<DCC_READ 0x190002C 1 0>,
+				<DCC_READ 0x1900030 1 0>,
+				<DCC_READ 0x1900034 1 0>,
+				<DCC_READ 0x1900038 1 0>,
+				<DCC_READ 0x190003C 1 0>,
+				<DCC_READ 0x1900300 1 0>,
+				<DCC_READ 0x1900304 1 0>,
+				<DCC_READ 0x1900308 1 0>,
+				<DCC_READ 0x190030C 1 0>,
+				<DCC_READ 0x1900310 1 0>,
+				<DCC_READ 0x1900314 1 0>,
+				<DCC_READ 0x1900900 1 0>,
+				<DCC_READ 0x1900904 1 0>,
+				<DCC_READ 0x1900B00 1 0>,
+				<DCC_READ 0x1900D00 1 0>,
+				<DCC_READ 0x1909100 1 0>,
+				<DCC_READ 0x1909104 1 0>,
+				<DCC_READ 0x1480140 1 0>,
+				<DCC_READ 0x1481140 1 0>,
+				<DCC_READ 0x1415008 1 0>,
+				<DCC_READ 0x1416008 1 0>,
+				<DCC_READ 0x44B0120 1 0>,
+				<DCC_READ 0x44B0124 1 0>,
+				<DCC_READ 0x44B0128 1 0>,
+				<DCC_READ 0x44B012C 1 0>,
+				<DCC_READ 0x44B0130 1 0>,
+				<DCC_READ 0x44B0100 1 0>,
+				<DCC_READ 0x44B0020 1 0>,
+				<DCC_READ 0x44C4000 1 0>,
+				<DCC_READ 0x44C4020 1 0>,
+				<DCC_READ 0x44C4030 1 0>,
+				<DCC_READ 0x44C4100 1 0>,
+				<DCC_READ 0x44C410C 1 0>,
+				<DCC_READ 0x44C4400 1 0>,
+				<DCC_READ 0x44C4410 1 0>,
+				<DCC_READ 0x44C4420 1 0>,
+				<DCC_READ 0x1900240 1 0>,
+				<DCC_READ 0x1900244 1 0>,
+				<DCC_READ 0x1900248 1 0>,
+				<DCC_READ 0x190024C 1 0>,
+				<DCC_READ 0x1900250 1 0>,
+				<DCC_READ 0x1900258 1 0>,
+				<DCC_READ 0x1411004 1 0>,
+				<DCC_READ 0x1411028 1 0>,
+				<DCC_READ 0x1458004 1 0>,
+				<DCC_READ 0x1880108 1 0>,
+				<DCC_READ 0x1880110 1 0>,
+				<DCC_READ 0x1880120 1 0>,
+				<DCC_READ 0x1880124 1 0>,
+				<DCC_READ 0x1880128 1 0>,
+				<DCC_READ 0x188012C 1 0>,
+				<DCC_READ 0x1880130 1 0>,
+				<DCC_READ 0x1880134 1 0>,
+				<DCC_READ 0x1880138 1 0>,
+				<DCC_READ 0x188013C 1 0>,
+				<DCC_READ 0x1880300 1 0>,
+				<DCC_READ 0x1880304 1 0>,
+				<DCC_READ 0x1880308 1 0>,
+				<DCC_READ 0x188030C 1 0>,
+				<DCC_READ 0x1880310 1 0>,
+				<DCC_READ 0x1880314 1 0>,
+				<DCC_READ 0x1880318 1 0>,
+				<DCC_READ 0x188031C 1 0>,
+				<DCC_READ 0x1880700 1 0>,
+				<DCC_READ 0x1880704 1 0>,
+				<DCC_READ 0x1880708 1 0>,
+				<DCC_READ 0x188070C 1 0>,
+				<DCC_READ 0x1880710 1 0>,
+				<DCC_READ 0x1880714 1 0>,
+				<DCC_READ 0x1880718 1 0>,
+				<DCC_READ 0x188071C 1 0>,
+				<DCC_READ 0x1881100 1 0>,
+				<DCC_READ 0x1880240 1 0>,
+				<DCC_READ 0x1880248 1 0>,
+				<DCC_READ 0xF017000 1 0>,
+				<DCC_READ 0xF01700C 1 0>,
+				<DCC_READ 0xF017010 1 0>,
+				<DCC_READ 0xF017014 1 0>,
+				<DCC_READ 0xF017018 1 0>,
+				<DCC_READ 0xF017020 1 0>,
+				<DCC_READ 0x1414008 1 0>,
+				<DCC_READ 0x1414004 1 0>,
+				<DCC_READ 0x5991554 1 0>,
+				<DCC_READ 0x5991544 1 0>,
+				<DCC_READ 0x599155C 1 0>,
+				<DCC_READ 0x440B00C 1 0>,
+				<DCC_READ 0x440B014 1 0>,
+				<DCC_READ 0x0F522C14 1 0>,
+				<DCC_READ 0x0F522C1C 1 0>,
+				<DCC_READ 0x0F522C10 1 0>,
+				<DCC_READ 0x0F524C10 1 0>,
+				<DCC_READ 0x0F524C14 1 0>,
+				<DCC_READ 0x0F524C18 1 0>,
+				<DCC_READ 0x0F524C1C 1 0>,
+				<DCC_READ 0x0F521920 1 0>,
+				<DCC_READ 0x0F52102C 1 0>,
+				<DCC_READ 0x0F521044 1 0>,
+				<DCC_READ 0x0F521710 1 0>,
+				<DCC_READ 0x0F52176C 1 0>,
+				<DCC_READ 0x0F523920 1 0>,
+				<DCC_READ 0x0F52302C 1 0>,
+				<DCC_READ 0x0F523044 1 0>,
+				<DCC_READ 0x0F523710 1 0>,
+				<DCC_READ 0x0F52376C 1 0>,
+				<DCC_READ 0x0F116000 1 0>,
+				<DCC_READ 0x0F116004 1 0>,
+				<DCC_READ 0x0F11602C 1 0>,
+				<DCC_READ 0x0F016000 1 0>,
+				<DCC_READ 0x0F016004 1 0>,
+				<DCC_READ 0x0F01602C 1 0>,
+				<DCC_READ 0x0F111250 1 0>,
+				<DCC_READ 0x0F111254 1 0>,
+				<DCC_READ 0x0F111258 1 0>,
+				<DCC_READ 0x0F11125C 1 0>,
+				<DCC_READ 0x0F111260 1 0>,
+				<DCC_READ 0x0F188078 1 0>,
+				<DCC_READ 0x0F188084 1 0>,
+				<DCC_READ 0x0F198078 1 0>,
+				<DCC_READ 0x0F198084 1 0>,
+				<DCC_READ 0x0F1A8078 1 0>,
+				<DCC_READ 0x0F1A8084 1 0>,
+				<DCC_READ 0x0F1B8078 1 0>,
+				<DCC_READ 0x0F1B8084 1 0>,
+				<DCC_READ 0x0F521818 1 0>,
+				<DCC_READ 0x0F52181C 1 0>,
+				<DCC_READ 0x0F521828 1 0>,
+				<DCC_READ 0x0F523818 1 0>,
+				<DCC_READ 0x0F52381C 1 0>,
+				<DCC_READ 0x0F523828 1 0>,
+				<DCC_READ 0x0F522C18 1 0>,
+				<DCC_READ 0x0F111310 1 0>,
+				<DCC_READ 0x0F111314 1 0>,
+				<DCC_READ 0x0F111318 1 0>,
+				<DCC_READ 0x0F01125C 1 0>,
+				<DCC_READ 0x0F011258 1 0>,
+				<DCC_READ 0x0F011310 1 0>,
+				<DCC_READ 0x0F011314 1 0>,
+				<DCC_READ 0x0F011318 1 0>,
+				<DCC_WRITE 0x9870010 0x14000 0>,
+				<DCC_READ 0xF011600 1 0>,
+				<DCC_READ 0xF011608 1 0>,
+				<DCC_READ 0xF01160C 1 0>,
+				<DCC_READ 0xF011610 1 0>,
+				<DCC_READ 0xF011614 1 0>,
+				<DCC_READ 0xF011618 1 0>,
+				<DCC_READ 0xF01161C 1 0>,
+				<DCC_READ 0xF011620 1 0>,
+				<DCC_READ 0xF011624 1 0>,
+				<DCC_READ 0xF011628 1 0>,
+				<DCC_READ 0xF01162C 1 0>,
+				<DCC_READ 0xF011630 1 0>,
+				<DCC_READ 0xF011634 1 0>,
+				<DCC_READ 0xF011638 1 0>,
+				<DCC_READ 0xF01163C 1 0>,
+				<DCC_READ 0xF011640 1 0>,
+				<DCC_READ 0xF011644 1 0>,
+				<DCC_READ 0xF011648 1 0>,
+				<DCC_READ 0xF01164C 1 0>,
+				<DCC_READ 0xF011650 1 0>,
+				<DCC_READ 0xF011654 1 0>,
+				<DCC_READ 0xF011658 1 0>,
+				<DCC_READ 0xF01165C 1 0>,
+				<DCC_READ 0xF011664 1 0>,
+				<DCC_READ 0xF111600 1 0>,
+				<DCC_READ 0xF111608 1 0>,
+				<DCC_READ 0xF11160C 1 0>,
+				<DCC_READ 0xF111610 1 0>,
+				<DCC_READ 0xF111614 1 0>,
+				<DCC_READ 0xF111618 1 0>,
+				<DCC_READ 0xF11161C 1 0>,
+				<DCC_READ 0xF111620 1 0>,
+				<DCC_READ 0xF111624 1 0>,
+				<DCC_READ 0xF111628 1 0>,
+				<DCC_READ 0xF11162C 1 0>,
+				<DCC_READ 0xF111630 1 0>,
+				<DCC_READ 0xF111634 1 0>,
+				<DCC_READ 0xF111638 1 0>,
+				<DCC_READ 0xF11163C 1 0>,
+				<DCC_READ 0xF111640 1 0>,
+				<DCC_READ 0xF111644 1 0>,
+				<DCC_READ 0xF111648 1 0>,
+				<DCC_READ 0xF111650 1 0>,
+				<DCC_READ 0xF111654 1 0>,
+				<DCC_READ 0xF111658 1 0>,
+				<DCC_READ 0xF11165C 1 0>,
+				<DCC_READ 0xF111664 1 0>,
+				<DCC_READ 0xF011400 1 0>,
+				<DCC_READ 0xF111400 1 0>,
+				<DCC_WRITE 0x9870010 0x0 0>,
+				<DCC_READ 0x06130010 1 0>,
+				<DCC_READ 0x06130014 1 0>,
+				<DCC_READ 0x06130018 1 0>,
+				<DCC_READ 0x06130210 1 0>,
+				<DCC_READ 0x06130230 1 0>,
+				<DCC_READ 0x06130250 1 0>,
+				<DCC_READ 0x06130270 1 0>,
+				<DCC_READ 0x06130290 1 0>,
+				<DCC_READ 0x061302B0 1 0>,
+				<DCC_READ 0x06130208 1 0>,
+				<DCC_READ 0x06130228 1 0>,
+				<DCC_READ 0x06130248 1 0>,
+				<DCC_READ 0x06130268 1 0>,
+				<DCC_READ 0x06130288 1 0>,
+				<DCC_READ 0x061302A8 1 0>,
+				<DCC_READ 0x0613020C 1 0>,
+				<DCC_READ 0x0613022C 1 0>,
+				<DCC_READ 0x0613024C 1 0>,
+				<DCC_READ 0x0613026C 1 0>,
+				<DCC_READ 0x0613028C 1 0>,
+				<DCC_READ 0x061302AC 1 0>,
+				<DCC_READ 0x06130400 1 0>,
+				<DCC_READ 0x06130404 1 0>,
+				<DCC_READ 0x06130408 1 0>,
+				<DCC_READ 0x6082028  1 0>,
+				<DCC_READ 0x0143300C 1 0>,
+				<DCC_READ 0x0B3B0010 1 0>,
+				<DCC_READ 0x0B3B0014 1 0>,
+				<DCC_READ 0x0B3B0018 1 0>,
+				<DCC_READ 0x0B3B0210 1 0>,
+				<DCC_READ 0x0B3B0230 1 0>,
+				<DCC_READ 0x0B3B0250 1 0>,
+				<DCC_READ 0x0B3B0270 1 0>,
+				<DCC_READ 0x0B3B0290 1 0>,
+				<DCC_READ 0x0B3B02B0 1 0>,
+				<DCC_READ 0x0B3B0208 1 0>,
+				<DCC_READ 0x0B3B0228 1 0>,
+				<DCC_READ 0x0B3B0248 1 0>,
+				<DCC_READ 0x0B3B0268 1 0>,
+				<DCC_READ 0x0B3B0288 1 0>,
+				<DCC_READ 0x0B3B02A8 1 0>,
+				<DCC_READ 0x0B3B020C 1 0>,
+				<DCC_READ 0x0B3B022C 1 0>,
+				<DCC_READ 0x0B3B024C 1 0>,
+				<DCC_READ 0x0B3B026C 1 0>,
+				<DCC_READ 0x0B3B028C 1 0>,
+				<DCC_READ 0x0B3B02AC 1 0>,
+				<DCC_READ 0x0B3B0400 1 0>,
+				<DCC_READ 0x0B3B0404 1 0>,
+				<DCC_READ 0x0B3B0408 1 0>,
+				<DCC_READ 0x0B302028 1 0>,
+				<DCC_READ 0x0B300044 1 0>,
+				<DCC_READ 0x0B300304 1 0>,
+				<DCC_READ 0x5C6F000 1 0>,
+				<DCC_READ 0x5C42000 1 0>,
+				<DCC_READ 0x5C42400 1 0>,
+				<DCC_READ 0x5C23000 1 0>;
+		};
+
+		link_list2 {
+			qcom,curr-link-list = <2>;
+			qcom,data-sink = "sram";
+			qcom,link-list = <DCC_READ 0x01480140 1 0>,
+				<DCC_READ 0x01481140 1 0>,
+				<DCC_READ 0x0148014C 1 0>,
+				<DCC_READ 0x0148114C 1 0>,
+				<DCC_READ 0x01477008 1 0>,
+				<DCC_READ 0x01439000 1 0>,
+				<DCC_READ 0x01415010 1 0>,
+				<DCC_READ 0x01416010 1 0>,
+				<DCC_READ 0x0142A00C 1 0>,
+				<DCC_READ 0x1400000 1 0>,
+				<DCC_READ 0x1400004 1 0>,
+				<DCC_READ 0x1400008 1 0>,
+				<DCC_READ 0x140000C 1 0>,
+				<DCC_READ 0x1400010 1 0>,
+				<DCC_READ 0x1400014 1 0>,
+				<DCC_READ 0x1400018 1 0>,
+				<DCC_READ 0x140001C 1 0>,
+				<DCC_READ 0x1400020 1 0>,
+				<DCC_READ 0x1400024 1 0>,
+				<DCC_READ 0x1401000 1 0>,
+				<DCC_READ 0x1401004 1 0>,
+				<DCC_READ 0x1401008 1 0>,
+				<DCC_READ 0x140100C 1 0>,
+				<DCC_READ 0x1401010 1 0>,
+				<DCC_READ 0x1401014 1 0>,
+				<DCC_READ 0x1401018 1 0>,
+				<DCC_READ 0x140101C 1 0>,
+				<DCC_READ 0x1401020 1 0>,
+				<DCC_READ 0x1401024 1 0>,
+				<DCC_READ 0x1402000 1 0>,
+				<DCC_READ 0x1402004 1 0>,
+				<DCC_READ 0x1402008 1 0>,
+				<DCC_READ 0x140200C 1 0>,
+				<DCC_READ 0x1402010 1 0>,
+				<DCC_READ 0x1402014 1 0>,
+				<DCC_READ 0x1402018 1 0>,
+				<DCC_READ 0x140201C 1 0>,
+				<DCC_READ 0x1402020 1 0>,
+				<DCC_READ 0x1402024 1 0>,
+				<DCC_READ 0x1403000 1 0>,
+				<DCC_READ 0x1403004 1 0>,
+				<DCC_READ 0x1403008 1 0>,
+				<DCC_READ 0x140300C 1 0>,
+				<DCC_READ 0x1403010 1 0>,
+				<DCC_READ 0x1403014 1 0>,
+				<DCC_READ 0x1403018 1 0>,
+				<DCC_READ 0x140301C 1 0>,
+				<DCC_READ 0x1403020 1 0>,
+				<DCC_READ 0x1403024 1 0>,
+				<DCC_READ 0x1404000 1 0>,
+				<DCC_READ 0x1404004 1 0>,
+				<DCC_READ 0x1404008 1 0>,
+				<DCC_READ 0x140400C 1 0>,
+				<DCC_READ 0x1404010 1 0>,
+				<DCC_READ 0x1404014 1 0>,
+				<DCC_READ 0x1404018 1 0>,
+				<DCC_READ 0x140401C 1 0>,
+				<DCC_READ 0x1404020 1 0>,
+				<DCC_READ 0x1404024 1 0>,
+				<DCC_READ 0x1405000 1 0>,
+				<DCC_READ 0x1405004 1 0>,
+				<DCC_READ 0x1405008 1 0>,
+				<DCC_READ 0x140500C 1 0>,
+				<DCC_READ 0x1405010 1 0>,
+				<DCC_READ 0x1405014 1 0>,
+				<DCC_READ 0x1405018 1 0>,
+				<DCC_READ 0x140501C 1 0>,
+				<DCC_READ 0x1405020 1 0>,
+				<DCC_READ 0x1405024 1 0>,
+				<DCC_READ 0x1406000 1 0>,
+				<DCC_READ 0x1406004 1 0>,
+				<DCC_READ 0x1406008 1 0>,
+				<DCC_READ 0x140600C 1 0>,
+				<DCC_READ 0x1406010 1 0>,
+				<DCC_READ 0x1406014 1 0>,
+				<DCC_READ 0x1406018 1 0>,
+				<DCC_READ 0x140601C 1 0>,
+				<DCC_READ 0x1406020 1 0>,
+				<DCC_READ 0x1406024 1 0>,
+				<DCC_READ 0x1407000 1 0>,
+				<DCC_READ 0x1407004 1 0>,
+				<DCC_READ 0x1407008 1 0>,
+				<DCC_READ 0x140700C 1 0>,
+				<DCC_READ 0x1407010 1 0>,
+				<DCC_READ 0x1407014 1 0>,
+				<DCC_READ 0x1407018 1 0>,
+				<DCC_READ 0x140701C 1 0>,
+				<DCC_READ 0x1407020 1 0>,
+				<DCC_READ 0x1407024 1 0>,
+				<DCC_READ 0x1407028 1 0>,
+				<DCC_READ 0x140702C 1 0>,
+				<DCC_READ 0x1407030 1 0>,
+				<DCC_READ 0x1407034 1 0>,
+				<DCC_READ 0x1408000 1 0>,
+				<DCC_READ 0x1408004 1 0>,
+				<DCC_READ 0x1408008 1 0>,
+				<DCC_READ 0x140800C 1 0>,
+				<DCC_READ 0x1408010 1 0>,
+				<DCC_READ 0x1408014 1 0>,
+				<DCC_READ 0x1408018 1 0>,
+				<DCC_READ 0x140801C 1 0>,
+				<DCC_READ 0x1408020 1 0>,
+				<DCC_READ 0x1408024 1 0>,
+				<DCC_READ 0x1409000 1 0>,
+				<DCC_READ 0x1409004 1 0>,
+				<DCC_READ 0x1409008 1 0>,
+				<DCC_READ 0x140900C 1 0>,
+				<DCC_READ 0x1409010 1 0>,
+				<DCC_READ 0x1409014 1 0>,
+				<DCC_READ 0x1409018 1 0>,
+				<DCC_READ 0x140901C 1 0>,
+				<DCC_READ 0x1409020 1 0>,
+				<DCC_READ 0x1409024 1 0>,
+				<DCC_READ 0x141001C 1 0>,
+				<DCC_READ 0x14103EC 1 0>,
+				<DCC_READ 0x1414024 1 0>,
+				<DCC_READ 0x1415004 1 0>,
+				<DCC_READ 0x1415008 1 0>,
+				<DCC_READ 0x141500C 1 0>,
+				<DCC_READ 0x1415034 1 0>,
+				<DCC_READ 0x1416004 1 0>,
+				<DCC_READ 0x1416008 1 0>,
+				<DCC_READ 0x141600C 1 0>,
+				<DCC_READ 0x1416038 1 0>,
+				<DCC_READ 0x141703C 1 0>,
+				<DCC_READ 0x1417040 1 0>,
+				<DCC_READ 0x141A004 1 0>,
+				<DCC_READ 0x141A008 1 0>,
+				<DCC_READ 0x141A00C 1 0>,
+				<DCC_READ 0x141A01C 1 0>,
+				<DCC_READ 0x141A020 1 0>,
+				<DCC_READ 0x141A034 1 0>,
+				<DCC_READ 0x141A038 1 0>,
+				<DCC_READ 0x141A060 1 0>,
+				<DCC_READ 0x141A064 1 0>,
+				<DCC_READ 0x141E00C 1 0>,
+				<DCC_READ 0x141E010 1 0>,
+				<DCC_READ 0x141F02C 1 0>,
+				<DCC_READ 0x141F148 1 0>,
+				<DCC_READ 0x141F14C 1 0>,
+				<DCC_READ 0x141F15C 1 0>,
+				<DCC_READ 0x141F278 1 0>,
+				<DCC_READ 0x141F27C 1 0>,
+				<DCC_READ 0x141F28C 1 0>,
+				<DCC_READ 0x141F3A8 1 0>,
+				<DCC_READ 0x141F3AC 1 0>,
+				<DCC_READ 0x141F3BC 1 0>,
+				<DCC_READ 0x141F4D8 1 0>,
+				<DCC_READ 0x141F4DC 1 0>,
+				<DCC_READ 0x141F4EC 1 0>,
+				<DCC_READ 0x141F608 1 0>,
+				<DCC_READ 0x141F60C 1 0>,
+				<DCC_READ 0x141F61C 1 0>,
+				<DCC_READ 0x141F738 1 0>,
+				<DCC_READ 0x141F73C 1 0>,
+				<DCC_READ 0x141F74C 1 0>,
+				<DCC_READ 0x1420010 1 0>,
+				<DCC_READ 0x1420014 1 0>,
+				<DCC_READ 0x1426018 1 0>,
+				<DCC_READ 0x142601C 1 0>,
+				<DCC_READ 0x1426030 1 0>,
+				<DCC_READ 0x1426034 1 0>,
+				<DCC_READ 0x1427024 1 0>,
+				<DCC_READ 0x1428014 1 0>,
+				<DCC_READ 0x1428018 1 0>,
+				<DCC_READ 0x142802C 1 0>,
+				<DCC_READ 0x1428030 1 0>,
+				<DCC_READ 0x1429004 1 0>,
+				<DCC_READ 0x1429008 1 0>,
+				<DCC_READ 0x142900C 1 0>,
+				<DCC_READ 0x1429040 1 0>,
+				<DCC_READ 0x1429044 1 0>,
+				<DCC_READ 0x142A000 1 0>,
+				<DCC_READ 0x142A004 1 0>,
+				<DCC_READ 0x142A008 1 0>,
+				<DCC_READ 0x142A154 1 0>,
+				<DCC_READ 0x142A158 1 0>,
+				<DCC_READ 0x142B13C 1 0>,
+				<DCC_READ 0x142B140 1 0>,
+				<DCC_READ 0x142B158 1 0>,
+				<DCC_READ 0x142B15C 1 0>,
+				<DCC_READ 0x142E00C 1 0>,
+				<DCC_READ 0x142E010 1 0>,
+				<DCC_READ 0x142F00C 1 0>,
+				<DCC_READ 0x142F010 1 0>,
+				<DCC_READ 0x1432004 1 0>,
+				<DCC_READ 0x1432008 1 0>,
+				<DCC_READ 0x143200C 1 0>,
+				<DCC_READ 0x1432034 1 0>,
+				<DCC_READ 0x1432080 1 0>,
+				<DCC_READ 0x1438010 1 0>,
+				<DCC_READ 0x1438014 1 0>,
+				<DCC_READ 0x1438028 1 0>,
+				<DCC_READ 0x143802C 1 0>,
+				<DCC_READ 0x143B000 1 0>,
+				<DCC_READ 0x143B004 1 0>,
+				<DCC_READ 0x143B008 1 0>,
+				<DCC_READ 0x143B00C 1 0>,
+				<DCC_READ 0x143B010 1 0>,
+				<DCC_READ 0x143B014 1 0>,
+				<DCC_READ 0x143B018 1 0>,
+				<DCC_READ 0x143B01C 1 0>,
+				<DCC_READ 0x143B020 1 0>,
+				<DCC_READ 0x143B024 1 0>,
+				<DCC_READ 0x143D01C 1 0>,
+				<DCC_READ 0x143D020 1 0>,
+				<DCC_READ 0x143E000 1 0>,
+				<DCC_READ 0x143E004 1 0>,
+				<DCC_READ 0x143E008 1 0>,
+				<DCC_READ 0x143E00C 1 0>,
+				<DCC_READ 0x143E010 1 0>,
+				<DCC_READ 0x143E014 1 0>,
+				<DCC_READ 0x143E018 1 0>,
+				<DCC_READ 0x143E01C 1 0>,
+				<DCC_READ 0x143E020 1 0>,
+				<DCC_READ 0x143E024 1 0>,
+				<DCC_READ 0x143E060 1 0>,
+				<DCC_READ 0x143F000 1 0>,
+				<DCC_READ 0x143F004 1 0>,
+				<DCC_READ 0x143F008 1 0>,
+				<DCC_READ 0x143F00C 1 0>,
+				<DCC_READ 0x143F010 1 0>,
+				<DCC_READ 0x143F014 1 0>,
+				<DCC_READ 0x143F018 1 0>,
+				<DCC_READ 0x143F01C 1 0>,
+				<DCC_READ 0x143F020 1 0>,
+				<DCC_READ 0x143F024 1 0>,
+				<DCC_READ 0x1442018 1 0>,
+				<DCC_READ 0x144201C 1 0>,
+				<DCC_READ 0x1442030 1 0>,
+				<DCC_READ 0x1442034 1 0>,
+				<DCC_READ 0x1445004 1 0>,
+				<DCC_READ 0x1445008 1 0>,
+				<DCC_READ 0x144500C 1 0>,
+				<DCC_READ 0x1445020 1 0>,
+				<DCC_READ 0x1445024 1 0>,
+				<DCC_READ 0x1445048 1 0>,
+				<DCC_READ 0x144504C 1 0>,
+				<DCC_READ 0x1445060 1 0>,
+				<DCC_READ 0x1445064 1 0>,
+				<DCC_READ 0x144507C 1 0>,
+				<DCC_READ 0x1445080 1 0>,
+				<DCC_READ 0x1446004 1 0>,
+				<DCC_READ 0x1446008 1 0>,
+				<DCC_READ 0x1446024 1 0>,
+				<DCC_READ 0x1446150 1 0>,
+				<DCC_READ 0x1448024 1 0>,
+				<DCC_READ 0x144D004 1 0>,
+				<DCC_READ 0x144D008 1 0>,
+				<DCC_READ 0x144E004 1 0>,
+				<DCC_READ 0x144E008 1 0>,
+				<DCC_READ 0x144F004 1 0>,
+				<DCC_READ 0x144F008 1 0>,
+				<DCC_READ 0x1451000 1 0>,
+				<DCC_READ 0x1451004 1 0>,
+				<DCC_READ 0x145101C 1 0>,
+				<DCC_READ 0x1451020 1 0>,
+				<DCC_READ 0x1451038 1 0>,
+				<DCC_READ 0x145103C 1 0>,
+				<DCC_READ 0x1451054 1 0>,
+				<DCC_READ 0x1451058 1 0>,
+				<DCC_READ 0x1452004 1 0>,
+				<DCC_READ 0x1452008 1 0>,
+				<DCC_READ 0x1452028 1 0>,
+				<DCC_READ 0x145202C 1 0>,
+				<DCC_READ 0x1454004 1 0>,
+				<DCC_READ 0x1455000 1 0>,
+				<DCC_READ 0x1455004 1 0>,
+				<DCC_READ 0x1457000 1 0>,
+				<DCC_READ 0x1457004 1 0>,
+				<DCC_READ 0x1457008 1 0>,
+				<DCC_READ 0x145700C 1 0>,
+				<DCC_READ 0x1457010 1 0>,
+				<DCC_READ 0x145A000 1 0>,
+				<DCC_READ 0x145A004 1 0>,
+				<DCC_READ 0x145A008 1 0>,
+				<DCC_READ 0x145A00C 1 0>,
+				<DCC_READ 0x145A010 1 0>,
+				<DCC_READ 0x145B000 1 0>,
+				<DCC_READ 0x145B004 1 0>,
+				<DCC_READ 0x145B00C 1 0>,
+				<DCC_READ 0x1463020 1 0>,
+				<DCC_READ 0x1469000 1 0>,
+				<DCC_READ 0x1469004 1 0>,
+				<DCC_READ 0x1469008 1 0>,
+				<DCC_READ 0x146900C 1 0>,
+				<DCC_READ 0x1469010 1 0>,
+				<DCC_READ 0x146B000 1 0>,
+				<DCC_READ 0x146B004 1 0>,
+				<DCC_READ 0x146B008 1 0>,
+				<DCC_READ 0x146B00C 1 0>,
+				<DCC_READ 0x146B010 1 0>,
+				<DCC_READ 0x146B014 1 0>,
+				<DCC_READ 0x146B018 1 0>,
+				<DCC_READ 0x146B01C 1 0>,
+				<DCC_READ 0x146B020 1 0>,
+				<DCC_READ 0x146C000 1 0>,
+				<DCC_READ 0x146C004 1 0>,
+				<DCC_READ 0x146C00C 1 0>,
+				<DCC_READ 0x1475000 1 0>,
+				<DCC_READ 0x1475004 1 0>,
+				<DCC_READ 0x147500C 1 0>,
+				<DCC_READ 0x1477000 1 0>,
+				<DCC_READ 0x1477004 1 0>,
+				<DCC_READ 0x147700C 1 0>,
+				<DCC_READ 0x1478030 1 0>,
+				<DCC_READ 0x1479000 1 0>,
+				<DCC_READ 0x1479004 1 0>,
+				<DCC_READ 0x147900C 1 0>,
+				<DCC_READ 0x147A000 1 0>,
+				<DCC_READ 0x147A004 1 0>,
+				<DCC_READ 0x147A00C 1 0>,
+				<DCC_READ 0x1480018 1 0>,
+				<DCC_READ 0x1480144 1 0>,
+				<DCC_READ 0x1481144 1 0>,
+				<DCC_READ 0x148B004 1 0>,
+				<DCC_READ 0x1490004 1 0>,
+				<DCC_READ 0x1490008 1 0>,
+				<DCC_READ 0x1490024 1 0>,
+				<DCC_READ 0x1490028 1 0>,
+				<DCC_READ 0x149002C 1 0>,
+				<DCC_READ 0x1490034 1 0>,
+				<DCC_READ 0x1495000 1 0>,
+				<DCC_READ 0x1495004 1 0>,
+				<DCC_READ 0x149500C 1 0>,
+				<DCC_READ 0x14B5000 1 0>,
+				<DCC_READ 0x14C4000 1 0>,
+				<DCC_READ 0x14C5000 1 0>,
+				<DCC_READ 0x14C6000 1 0>,
+				<DCC_READ 0x14C7000 1 0>,
+				<DCC_READ 0x440C000 1 0>,
+				<DCC_READ 0x440C004 1 0>,
+				<DCC_READ 0x440C008 1 0>,
+				<DCC_READ 0x440C040 1 0>,
+				<DCC_READ 0x440C044 1 0>,
+				<DCC_READ 0x440C048 1 0>,
+				<DCC_READ 0x440C04C 1 0>,
+				<DCC_READ 0x440C050 1 0>,
+				<DCC_READ 0x440C054 1 0>,
+				<DCC_READ 0x440C058 1 0>,
+				<DCC_READ 0x440C05C 1 0>,
+				<DCC_READ 0x440C060 1 0>,
+				<DCC_READ 0x440C068 1 0>,
+				<DCC_READ 0x440C06C 1 0>,
+				<DCC_READ 0x440E050 1 0>,
+				<DCC_READ 0x440E054 1 0>,
+				<DCC_READ 0x440E0A0 1 0>,
+				<DCC_READ 0x440E0A4 1 0>,
+				<DCC_READ 0x440F010 1 0>;
+		};
+	};
+
+	timer@f120000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		compatible = "arm,armv7-timer-mem";
+		reg = <0xf120000 0x1000>;
+		clock-frequency = <19200000>;
+
+		frame@f121000 {
+			frame-number = <0>;
+			interrupts = <0 8 0x4>,
+				     <0 7 0x4>;
+			reg = <0xf121000 0x1000>,
+			      <0xf122000 0x1000>;
+		};
+
+		frame@f123000 {
+			frame-number = <1>;
+			interrupts = <0 9 0x4>;
+			reg = <0xf123000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@f124000 {
+			frame-number = <2>;
+			interrupts = <0 10 0x4>;
+			reg = <0xf124000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@f125000 {
+			frame-number = <3>;
+			interrupts = <0 11 0x4>;
+			reg = <0xf125000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@f126000 {
+			frame-number = <4>;
+			interrupts = <0 12 0x4>;
+			reg = <0xf126000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@f127000 {
+			frame-number = <5>;
+			interrupts = <0 13 0x4>;
+			reg = <0xf127000 0x1000>;
+			status = "disabled";
+		};
+
+		frame@f128000 {
+			frame-number = <6>;
+			interrupts = <0 14 0x4>;
+			reg = <0xf128000 0x1000>;
+			status = "disabled";
+		};
+	};
+
+	arm64_cpu_erp {
+		compatible = "arm,arm64-cpu-erp";
+		interrupt-names = "pri-dbe-irq",
+				  "sec-dbe-irq",
+				  "pri-ext-irq",
+				  "sec-ext-irq";
+		interrupts = <0 43 4>,
+			     <0 44 4>,
+			     <0 41 4>,
+			     <0 42 4>;
+		poll-delay-ms = <5000>;
+	};
+
+	l2cache_pmu {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "qcom,l2cache-pmu";
+		ranges;
+
+		cluster0@f111000 {
+			cluster-id = <0>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0xf111000 0x1000>;
+		};
+
+		cluster1@f011000 {
+			cluster-id = <1>;
+			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0xf011000 0x1000>;
+		};
+	};
+
+	qcom,msm-imem@c125000 {
+		compatible = "qcom,msm-imem";
+		reg = <0xc125000 0x1000>;
+		ranges = <0x0 0xc125000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		mem_dump_table@10 {
+			compatible = "qcom,msm-imem-mem_dump_table";
+			reg = <0x10 0x8>;
+		};
+
+		restart_reason@65c {
+			compatible = "qcom,msm-imem-restart_reason";
+			reg = <0x65c 0x4>;
+		};
+
+		dload_type@1c {
+			compatible = "qcom,msm-imem-dload-type";
+			reg = <0x1c 0x4>;
+		};
+
+		boot_stats@6b0 {
+			compatible = "qcom,msm-imem-boot_stats";
+			reg = <0x6b0 0x20>;
+		};
+
+		kaslr_offset@6d0 {
+			compatible = "qcom,msm-imem-kaslr_offset";
+			reg = <0x6d0 0xc>;
+		};
+
+		pil@94c {
+			compatible = "qcom,msm-imem-pil";
+			reg = <0x94c 0xc8>;
+		};
+
+		diag_dload@c8 {
+			compatible = "qcom,msm-imem-diag-dload";
+			reg = <0xc8 0xc8>;
+		};
+	};
+
+	restart@440b000 {
+		compatible = "qcom,pshold";
+		reg = <0x440b000 0x4>,
+		      <0x03d3000 0x4>;
+		reg-names = "pshold-base", "tcsr-boot-misc-detect";
+	};
+
+	qcom_seecom: qseecom@61800000 {
+		compatible = "qcom,qseecom";
+		reg = <0x61800000 0x2100000>;
+		reg-names = "secapp-region";
+		memory-region = <&qseecom_mem>;
+		qcom,hlos-num-ce-hw-instances = <1>;
+		qcom,hlos-ce-hw-instance = <0>;
+		qcom,qsee-ce-hw-instance = <0>;
+		qcom,disk-encrypt-pipe-pair = <2>;
+		qcom,support-fde;
+		qcom,fde-key-size;
+		qcom,appsbl-qseecom-support;
+		qcom,commonlib64-loaded-by-uefi;
+		qcom,msm-bus,name = "qseecom-noc";
+		qcom,msm-bus,num-cases = <4>;
+		qcom,msm-bus,num-paths = <1>;
+		qcom,msm-bus,vectors-KBps =
+			<MSM_BUS_MASTER_CRYPTO_CORE0
+			MSM_BUS_SLAVE_FIRST 0 0>,
+			<MSM_BUS_MASTER_CRYPTO_CORE0
+			MSM_BUS_SLAVE_FIRST 200000 400000>,
+			<MSM_BUS_MASTER_CRYPTO_CORE0
+			MSM_BUS_SLAVE_FIRST 300000 800000>,
+			<MSM_BUS_MASTER_CRYPTO_CORE0
+			MSM_BUS_SLAVE_FIRST 400000 1000000>;
+		clock-names =
+			"core_clk_src", "core_clk",
+			"iface_clk", "bus_clk";
+		clocks =
+			<&rpmcc QSEECOM_CE1_CLK>,
+			<&rpmcc QSEECOM_CE1_CLK>,
+			<&rpmcc QSEECOM_CE1_CLK>,
+			<&rpmcc QSEECOM_CE1_CLK>;
+		qcom,ce-opp-freq = <192000000>;
+		qcom,qsee-reentrancy-support = <2>;
+	};
+
+	qcom_smcinvoke: smcinvoke@61800000 {
+		compatible = "qcom,smcinvoke";
+		reg = <0x61800000 0x2100000>;
+		reg-names = "secapp-region";
+	};
+
+	qcom_rng: qrng@1b53000 {
+		compatible = "qcom,msm-rng";
+		reg = <0x1b53000 0x1000>;
+		qcom,msm-rng-iface-clk;
+		qcom,no-qrng-config;
+		qcom,msm-bus,name = "msm-rng-noc";
+		qcom,msm-bus,num-cases = <2>;
+		qcom,msm-bus,num-paths = <1>;
+		qcom,msm-bus,vectors-KBps =
+			<MSM_BUS_MASTER_AMPSS_M0
+			MSM_BUS_SLAVE_PRNG 0 0>,    /* No vote */
+			<MSM_BUS_MASTER_AMPSS_M0
+			MSM_BUS_SLAVE_PRNG 0 300000>;  /* 75 MHz */
+		clocks = <&gcc GCC_PRNG_AHB_CLK>;
+		clock-names = "iface_clk";
+	};
+
+	qcom_tzlog: tz-log@c125720 {
+		compatible = "qcom,tz-log";
+		reg = <0xc125720 0x3000>;
+		qcom,hyplog-enabled;
+		hyplog-address-offset = <0x410>;
+		hyplog-size-offset = <0x414>;
+	};
+
+	qcom_cedev: qcedev@1b20000 {
+		compatible = "qcom,qcedev";
+		reg = <0x1b20000 0x20000>,
+			<0x1b04000 0x24000>;
+		reg-names = "crypto-base","crypto-bam-base";
+		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,bam-pipe-pair = <3>;
+		qcom,ce-hw-instance = <0>;
+		qcom,ce-device = <0>;
+		qcom,ce-hw-shared;
+		qcom,bam-ee = <0>;
+		qcom,msm-bus,name = "qcedev-noc";
+		qcom,msm-bus,num-cases = <2>;
+		qcom,msm-bus,num-paths = <1>;
+		qcom,msm-bus,vectors-KBps =
+				<MSM_BUS_MASTER_CRYPTO_CORE0
+				MSM_BUS_SLAVE_FIRST 0 0>,
+				<MSM_BUS_MASTER_CRYPTO_CORE0
+				MSM_BUS_SLAVE_FIRST 393600 393600>;
+		clock-names =
+			"core_clk_src", "core_clk",
+			"iface_clk", "bus_clk";
+		clocks =
+			<&rpmcc QCEDEV_CE1_CLK>,
+			<&rpmcc QCEDEV_CE1_CLK>,
+			<&rpmcc QCEDEV_CE1_CLK>,
+			<&rpmcc QCEDEV_CE1_CLK>;
+		qcom,ce-opp-freq = <192000000>;
+		qcom,smmu-s1-enable;
+		iommus = <&apps_smmu 0x0086 0x0011>,
+			 <&apps_smmu 0x0096 0x0011>;
+		qcom,iommu-dma = "atomic";
+
+		qcom_cedev_ns_cb {
+			compatible = "qcom,qcedev,context-bank";
+			label = "ns_context";
+			iommus = <&apps_smmu 0x92 0>,
+				<&apps_smmu 0x98 0x1>,
+				<&apps_smmu 0x9F 0>;
+			qcom,iommu-dma-addr-pool = <0x70000000 0X10000000>;
+		};
+
+		qcom_cedev_s_cb {
+			compatible = "qcom,qcedev,context-bank";
+			label = "secure_context";
+			iommus = <&apps_smmu 0x93 0>,
+				<&apps_smmu 0x9C 0x1>,
+				<&apps_smmu 0x9E 0>;
+			qcom,iommu-dma-addr-pool = <0x70000000 0X10000000>;
+			qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
+			qcom,secure-context-bank;
+		};
+	};
+
+	qcom_crypto: qcrypto@1b20000 {
+		compatible = "qcom,qcrypto";
+		reg = <0x1b20000 0x20000>,
+			<0x1b04000 0x24000>;
+		reg-names = "crypto-base","crypto-bam-base";
+		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,bam-pipe-pair = <2>;
+		qcom,ce-hw-instance = <0>;
+		qcom,ce-device = <0>;
+		qcom,bam-ee = <0>;
+		qcom,ce-hw-shared;
+		qcom,clk-mgmt-sus-res;
+		qcom,msm-bus,name = "qcrypto-noc";
+		qcom,msm-bus,num-cases = <2>;
+		qcom,msm-bus,num-paths = <1>;
+		qcom,msm-bus,vectors-KBps =
+			<MSM_BUS_MASTER_CRYPTO_CORE0
+			MSM_BUS_SLAVE_FIRST
+			0 0>,
+			<MSM_BUS_MASTER_CRYPTO_CORE0
+			MSM_BUS_SLAVE_FIRST
+			393600 393600>;
+		clock-names =
+			"core_clk_src", "core_clk",
+			"iface_clk", "bus_clk";
+		clocks =
+			<&rpmcc QCRYPTO_CE1_CLK>,
+			<&rpmcc QCRYPTO_CE1_CLK>,
+			<&rpmcc QCRYPTO_CE1_CLK>,
+			<&rpmcc QCRYPTO_CE1_CLK>;
+		qcom,use-sw-aes-cbc-ecb-ctr-algo;
+		qcom,use-sw-aes-xts-algo;
+		qcom,use-sw-aes-ccm-algo;
+		qcom,use-sw-ahash-algo;
+		qcom,use-sw-aead-algo;
+		qcom,use-sw-hmac-algo;
+		qcom,smmu-s1-enable;
+		iommus = <&apps_smmu 0x0084 0x0011>,
+			<&apps_smmu 0x0094 0x0011>;
+		qcom,iommu-dma = "atomic";
+	};
+
+	qcom,mpm2-sleep-counter@4403000 {
+		compatible = "qcom,mpm2-sleep-counter";
+		reg = <0x4403000 0x1000>;
+		clock-frequency = <32768>;
+	};
+
+	qcom,msm-rtb {
+		compatible = "qcom,msm-rtb";
+		qcom,rtb-size = <0x100000>;
+	};
+
+	cpu_pmu: cpu-pmu {
+		compatible = "arm,armv8-pmuv3";
+		qcom,irq-is-percpu;
+		interrupts = <1 6 4>;
+	};
+
+	eud: qcom,msm-eud@1610000 {
+		compatible = "qcom,msm-eud";
+		interrupt-names = "eud_irq";
+		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x1610000 0x2000>,
+		      <0x1612000 0x1000>,
+		      <0x3E5018 0x4>;
+		reg-names = "eud_base", "eud_mode_mgr2",
+				"eud_tcsr_check_reg";
+		qcom,secure-eud-en;
+		qcom,eud-tcsr-check-enable;
+		qcom,eud-clock-vote-req;
+		clocks = <&gcc GCC_AHB2PHY_USB_CLK>;
+		clock-names = "eud_ahb2phy_clk";
+		status = "ok";
+	};
+
+	qcom,msm-gladiator-v2@f100000 {
+		compatible = "qcom,msm-gladiator-v2";
+		reg = <0xf100000 0xdc00>;
+		reg-names = "gladiator_base";
+		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "atb_clk";
+		clocks = <&rpmcc RPM_QDSS_CLK>;
+	};
+
+	wdog: qcom,wdt@f017000 {
+		compatible = "qcom,msm-watchdog";
+		reg = <0xf017000 0x1000>;
+		reg-names = "wdt-base";
+		interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,bark-time = <11000>;
+		qcom,pet-time = <9360>;
+		qcom,ipi-ping;
+		qcom,wakeup-enable;
+	};
+
+	rpm_bus: qcom,rpm-smd {
+		compatible = "qcom,rpm-smd";
+		rpm-channel-name = "rpm_requests";
+		interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
+		rpm-channel-type = <15>; /* SMD_APPS_RPM */
+	};
+
+	qcom,chd_silver {
+		compatible = "qcom,core-hang-detect";
+		label = "silver";
+		qcom,threshold-arr = <0x0f1880b0 0x0f1980b0
+				      0x0f1a80b0 0x0f1b80b0>;
+		qcom,config-arr = <0x0f1880b8 0x0f1980b8
+				   0x0f1a80b8 0x0f1b80b8>;
+	};
+
+	qcom,chd_gold {
+		compatible = "qcom,core-hang-detect";
+		label = "gold";
+		qcom,threshold-arr = <0x0f0880b0 0x0f0980b0
+				      0x0f0a80b0 0x0f0b80b0>;
+		qcom,config-arr = <0x0f0880b8 0x0f0980b8
+				   0x0f0a80b8 0x0f0b80b8>;
+	};
+
+	qcom,ghd {
+		compatible = "qcom,gladiator-hang-detect";
+		qcom,threshold-arr = <0x0f1d141c 0x0f1d1420
+				      0x0f1d1424 0x0f1d1428
+				      0x0f1d142c 0x0f1d1430>;
+		qcom,config-reg = <0x0f1d1434>;
+	};
+
+	qcom,lpass@ab00000 {
+		compatible = "qcom,pil-tz-generic";
+		reg = <0xab00000 0x00100>;
+
+		vdd_lpi_cx-supply = <&L3A_LEVEL>;
+		qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx";
+		qcom,vdd_lpi_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+		vdd_lpi_mx-supply = <&L2A_LEVEL>;
+		qcom,vdd_lpi_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+
+		clocks = <&rpmcc CXO_SMD_PIL_LPASS_CLK>;
+		clock-names = "xo";
+		qcom,proxy-clock-names = "xo";
+		qcom,mas-crypto = <&mas_crypto_c0>;
+
+		qcom,pas-id = <1>;
+		qcom,proxy-timeout-ms = <10000>;
+		qcom,smem-id = <423>;
+		qcom,minidump-id = <5>;
+		qcom,sysmon-id = <1>;
+		qcom,ssctl-instance-id = <0x14>;
+		qcom,firmware-name = "adsp";
+		memory-region = <&pil_adsp_mem>;
+		qcom,complete-ramdump;
+		qcom,minidump-as-elf32;
+
+		/* Inputs from lpass */
+		interrupts-extended = <&intc 0 282 1>,
+				      <&adsp_smp2p_in 0 0>,
+				      <&adsp_smp2p_in 2 0>,
+				      <&adsp_smp2p_in 1 0>,
+				      <&adsp_smp2p_in 3 0>;
+
+		interrupt-names = "qcom,wdog",
+				  "qcom,err-fatal",
+				  "qcom,proxy-unvote",
+				  "qcom,err-ready",
+				  "qcom,stop-ack";
+
+		/* Outputs to lpass */
+		qcom,smem-states = <&adsp_smp2p_out 0>;
+		qcom,smem-state-names = "qcom,force-stop";
+	};
+
+	qcom,turing@b300000 {
+		compatible = "qcom,pil-tz-generic";
+		reg = <0xb300000 0x100000>;
+
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		qcom,proxy-reg-names = "vdd_cx";
+		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+
+		clocks = <&rpmcc CXO_SMD_PIL_CDSP_CLK>;
+		clock-names = "xo";
+		qcom,proxy-clock-names = "xo";
+		qcom,mas-crypto = <&mas_crypto_c0>;
+
+		qcom,pas-id = <18>;
+		qcom,proxy-timeout-ms = <10000>;
+		qcom,smem-id = <601>;
+		qcom,minidump-id = <7>;
+		qcom,sysmon-id = <7>;
+		qcom,ssctl-instance-id = <0x17>;
+		qcom,firmware-name = "cdsp";
+		memory-region = <&pil_cdsp_mem>;
+		qcom,complete-ramdump;
+		qcom,minidump-as-elf32;
+
+		/* Inputs from turing */
+		interrupts-extended = <&intc 0 265 1>,
+				      <&cdsp_smp2p_in 0 0>,
+				      <&cdsp_smp2p_in 2 0>,
+				      <&cdsp_smp2p_in 1 0>,
+				      <&cdsp_smp2p_in 3 0>;
+
+		interrupt-names = "qcom,wdog",
+				  "qcom,err-fatal",
+				  "qcom,proxy-unvote",
+				  "qcom,err-ready",
+				  "qcom,stop-ack";
+
+		/* Outputs to turing */
+		qcom,smem-states = <&cdsp_smp2p_out 0>;
+		qcom,smem-state-names = "qcom,force-stop";
+	};
+
+	mem_dump {
+		compatible = "qcom,mem-dump";
+		memory-region = <&dump_mem>;
+
+		c0_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x0>;
+		};
+
+		c1_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x1>;
+		};
+
+		c2_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x2>;
+		};
+
+		c3_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x3>;
+		};
+
+		c100_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x4>;
+		};
+
+		c101_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x5>;
+		};
+
+		c102_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x6>;
+		};
+
+		c103_context {
+			qcom,dump-size = <0x800>;
+			qcom,dump-id = <0x7>;
+		};
+
+		c_scandump {
+			qcom,dump-size = <0x40000>;
+			qcom,dump-id = <0xeb>;
+		};
+
+		l1_icache0 {
+			qcom,dump-size = <0x8900>;
+			qcom,dump-id = <0x60>;
+		};
+
+		l1_icache1 {
+			qcom,dump-size = <0x8900>;
+			qcom,dump-id = <0x61>;
+		};
+
+		l1_icache2 {
+			qcom,dump-size = <0x8900>;
+			qcom,dump-id = <0x62>;
+		};
+
+		l1_icache3 {
+			qcom,dump-size = <0x8900>;
+			qcom,dump-id = <0x63>;
+		};
+
+		l1_icache100 {
+			qcom,dump-size = <0x11100>;
+			qcom,dump-id = <0x64>;
+		};
+
+		l1_icache101 {
+			qcom,dump-size = <0x11100>;
+			qcom,dump-id = <0x65>;
+		};
+
+		l1_icache102 {
+			qcom,dump-size = <0x11100>;
+			qcom,dump-id = <0x66>;
+		};
+
+		l1_icache103 {
+			qcom,dump-size = <0x11100>;
+			qcom,dump-id = <0x67>;
+		};
+
+		l1_dcache0 {
+			qcom,dump-size = <0x9100>;
+			qcom,dump-id = <0x80>;
+		};
+
+		l1_dcache1 {
+			qcom,dump-size = <0x9100>;
+			qcom,dump-id = <0x81>;
+		};
+
+		l1_dcache2 {
+			qcom,dump-size = <0x9100>;
+			qcom,dump-id = <0x82>;
+		};
+
+		l1_dcache3 {
+			qcom,dump-size = <0x9100>;
+			qcom,dump-id = <0x83>;
+		};
+
+		l1_dcache100 {
+			qcom,dump-size = <0x12100>;
+			qcom,dump-id = <0x84>;
+		};
+
+		l1_dcache101 {
+			qcom,dump-size = <0x12100>;
+			qcom,dump-id = <0x85>;
+		};
+
+		l1_dcache102 {
+			qcom,dump-size = <0x12100>;
+			qcom,dump-id = <0x86>;
+		};
+
+		l1_dcache103 {
+			qcom,dump-size = <0x12100>;
+			qcom,dump-id = <0x87>;
+		};
+
+		l2_tlb0 {
+			qcom,dump-size = <0x2100>;
+			qcom,dump-id = <0x120>;
+		};
+
+		l2_tlb1 {
+			qcom,dump-size = <0x2100>;
+			qcom,dump-id = <0x121>;
+		};
+
+		l2_tlb2 {
+			qcom,dump-size = <0x2100>;
+			qcom,dump-id = <0x122>;
+		};
+
+		l2_tlb3 {
+			qcom,dump-size = <0x2100>;
+			qcom,dump-id = <0x123>;
+		};
+
+		l2_tlb100 {
+			qcom,dump-size = <0x4900>;
+			qcom,dump-id = <0x124>;
+		};
+
+		l2_tlb101 {
+			qcom,dump-size = <0x4900>;
+			qcom,dump-id = <0x125>;
+		};
+
+		l2_tlb102 {
+			qcom,dump-size = <0x4900>;
+			qcom,dump-id = <0x126>;
+		};
+
+		l2_tlb103 {
+			qcom,dump-size = <0x4900>;
+			qcom,dump-id = <0x127>;
+		};
+
+		rpm_sw {
+			qcom,dump-size = <0x28000>;
+			qcom,dump-id = <0xea>;
+		};
+
+		pmic {
+			qcom,dump-size = <0x40000>;
+			qcom,dump-id = <0xe4>;
+		};
+
+		fcm {
+			qcom,dump-size = <0x8400>;
+			qcom,dump-id = <0xee>;
+		};
+
+		tmc_etf {
+			qcom,dump-size = <0x8000>;
+			qcom,dump-id = <0xf0>;
+		};
+
+		etr_reg {
+			qcom,dump-size = <0x1000>;
+			qcom,dump-id = <0x100>;
+		};
+
+		etf_reg {
+			qcom,dump-size = <0x1000>;
+			qcom,dump-id = <0x101>;
+		};
+
+		misc_data {
+			qcom,dump-size = <0x1000>;
+			qcom,dump-id = <0xe8>;
+		};
+	};
+
+	sdhc_1: sdhci@4744000 {
+		compatible = "qcom,sdhci-msm-v5", "qcom,sdhci-msm-cqe";
+		reg = <0x4744000 0x1000>, <0x4745000 0x1000>,
+		      <0x4748000 0x8000>;
+		reg-names = "hc_mem", "cqhci_mem", "cqhci_ice";
+
+		interrupts-extended = <&intc GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+				<&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+				<&tlmm 19 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "hc_irq", "pwr_irq", "tb_trig_irq";
+
+		qcom,bus-width = <8>;
+		qcom,large-address-bus;
+
+		qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
+						192000000 384000000>;
+		qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
+
+		qcom,devfreq,freq-table = <50000000 200000000>;
+
+		qcom,scaling-lower-bus-speed-mode = "DDR52";
+
+		qcom,msm-bus,name = "sdhc1";
+		qcom,msm-bus,num-cases = <9>;
+		qcom,msm-bus,num-paths = <2>;
+		qcom,msm-bus,vectors-KBps =
+			/* No vote */
+			<78 512 0 0>, <1 606 0 0>,
+			/* 400 KB/s*/
+			<78 512 1046 1600>,
+			<1 606 1600 1600>,
+			/* 20 MB/s */
+			<78 512 20480 80000>,
+			<1 606 80000 80000>,
+			/* 25 MB/s */
+			<78 512 25600 250000>,
+			<1 606 50000 133320>,
+			/* 50 MB/s */
+			<78 512 51200 250000>,
+			<1 606 65000 133320>,
+			/* 100 MB/s */
+			<78 512 102400 250000>,
+			<1 606 65000 133320>,
+			/* 200 MB/s */
+			<78 512 204800 800000>,
+			<1 606 200000 300000>,
+			/* 400 MB/s */
+			<78 512 204800 800000>,
+			<1 606 200000 300000>,
+			/* Max. bandwidth */
+			<78 512 1338562 4096000>,
+			<1 606 1338562 4096000>;
+		qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+			100750000 200000000 400000000 4294967295>;
+
+		/* PM QoS */
+		qcom,pm-qos-irq-type = "affine_irq";
+		qcom,pm-qos-irq-latency = <26 26>;
+		qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
+		qcom,pm-qos-cmdq-latency-us = <26 26>, <26 26>;
+		qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>;
+
+		clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+			<&gcc GCC_SDCC1_APPS_CLK>,
+			<&gcc GCC_SDCC1_ICE_CORE_CLK>;
+		clock-names = "iface_clk", "core_clk", "ice_core_clk";
+
+		qcom,ice-clk-rates = <300000000 100000000>;
+
+		/* Add support for gcc hw reset */
+		resets = <&gcc GCC_SDCC1_BCR>;
+		reset-names = "core_reset";
+
+		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+		qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x2C010800 0x80040868>;
+		qcom,nonremovable;
+		status = "disabled";
+	};
+
+	sdhc_2: sdhci@4784000 {
+		compatible = "qcom,sdhci-msm-v5";
+		reg = <0x4784000 0x1000>;
+		reg-names = "hc_mem";
+
+		interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hc_irq", "pwr_irq";
+
+		qcom,bus-width = <4>;
+		qcom,large-address-bus;
+
+		qcom,clk-rates = <400000 20000000 25000000
+				50000000 100000000 202000000>;
+		qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
+				      "SDR104";
+
+		qcom,devfreq,freq-table = <50000000 202000000>;
+
+		qcom,msm-bus,name = "sdhc2";
+		qcom,msm-bus,num-cases = <8>;
+		qcom,msm-bus,num-paths = <2>;
+		qcom,msm-bus,vectors-KBps =
+			/* No vote */
+			<81 512 0 0>, <1 608 0 0>,
+			/* 400 KB/s*/
+			<81 512 1046 3200>,
+			<1 608 1600 1600>,
+			/* 20 MB/s */
+			<81 512 52286 250000>,
+			<1 608 80000 133320>,
+			/* 25 MB/s */
+			<81 512 65360 250000>,
+			<1 608 100000 133320>,
+			/* 50 MB/s */
+			<81 512 130718 250000>,
+			<1 608 133320 133320>,
+			/* 100 MB/s */
+			<81 512 261438 250000>,
+			<1 608 150000 133320>,
+			/* 200 MB/s */
+			<81 512 261438 800000>,
+			<1 608 300000 300000>,
+			/* Max. bandwidth */
+			<81 512 1338562 4096000>,
+			<1 608 1338562 4096000>;
+		qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+			100750000 200000000 4294967295>;
+
+		/* PM QoS */
+		qcom,pm-qos-irq-type = "affine_irq";
+		qcom,pm-qos-irq-latency = <26 26>;
+		qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
+		qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>;
+
+
+		clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+			<&gcc GCC_SDCC2_APPS_CLK>;
+		clock-names = "iface_clk", "core_clk";
+
+		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+		qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
+		qcom,vbias-skip-wa;
+
+		status = "disabled";
+	};
+
+	ufsphy_mem: ufsphy_mem@4807000 {
+		reg = <0x4807000 0xe00>; /* PHY regs */
+		reg-names = "phy_mem";
+		#phy-cells = <0>;
+
+		lanes-per-direction = <2>;
+
+		clock-names = "ref_clk_src",
+			"ref_clk",
+			"ref_aux_clk";
+		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+			<&gcc GCC_UFS_CLKREF_CLK>,
+			<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+
+		status = "disabled";
+	};
+
+	ufshc_mem: ufshc@4804000 {
+		compatible = "qcom,ufshc";
+		reg = <0x4804000 0x3000>, <0x4810000 0x8000>;
+		reg-names = "ufs_mem", "ufs_ice";
+		interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+		phys = <&ufsphy_mem>;
+		phy-names = "ufsphy";
+
+		lanes-per-direction = <2>;
+		dev-ref-clk-freq = <0>; /* 19.2 MHz */
+		spm-level = <5>;
+
+		clock-names =
+			"core_clk",
+			"bus_aggr_clk",
+			"iface_clk",
+			"core_clk_unipro",
+			"core_clk_ice",
+			"ref_clk",
+			"tx_lane0_sync_clk",
+			"rx_lane0_sync_clk",
+			"rx_lane1_sync_clk";
+		clocks =
+			<&gcc GCC_UFS_PHY_AXI_CLK>,
+			<&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
+			<&gcc GCC_UFS_PHY_AHB_CLK>,
+			<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+			<&rpmcc RPM_SMD_XO_CLK_SRC>,
+			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+			<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+		freq-table-hz =
+			<50000000 200000000>,
+			<0 0>,
+			<0 0>,
+			<37500000 150000000>,
+			<75000000 300000000>,
+			<0 0>,
+			<0 0>,
+			<0 0>,
+			<0 0>;
+
+		qcom,msm-bus,name = "ufshc_mem";
+		qcom,msm-bus,num-cases = <22>;
+		qcom,msm-bus,num-paths = <2>;
+		qcom,msm-bus,vectors-KBps =
+		/*
+		 * During HS G3 UFS runs at nominal voltage corner, vote
+		 * higher bandwidth to push other buses in the data path
+		 * to run at nominal to achieve max throughput.
+		 * 4GBps pushes BIMC to run at nominal.
+		 * 200MBps pushes CNOC to run at nominal.
+		 * Vote for half of this bandwidth for HS G3 1-lane.
+		 * For max bandwidth, vote high enough to push the buses
+		 * to run in turbo voltage corner.
+		 */
+		<123 512 0 0>, <1 757 0 0>,          /* No vote */
+		<123 512 922 0>, <1 757 1000 0>,     /* PWM G1 */
+		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G2 */
+		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G3 */
+		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G4 */
+		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G1 L2 */
+		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G2 L2 */
+		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G3 L2 */
+		<123 512 14752 0>, <1 757 1000 0>,   /* PWM G4 L2 */
+		<123 512 127796 0>, <1 757 1000 0>,  /* HS G1 RA */
+		<123 512 255591 0>, <1 757 1000 0>,  /* HS G2 RA */
+		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RA */
+		<123 512 255591 0>, <1 757 1000 0>,  /* HS G1 RA L2 */
+		<123 512 511181 0>, <1 757 1000 0>,  /* HS G2 RA L2 */
+		<123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */
+		<123 512 149422 0>, <1 757 1000 0>,  /* HS G1 RB */
+		<123 512 298189 0>, <1 757 1000 0>,  /* HS G2 RB */
+		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RB */
+		<123 512 298189 0>, <1 757 1000 0>,  /* HS G1 RB L2 */
+		<123 512 596378 0>, <1 757 1000 0>,  /* HS G2 RB L2 */
+		/* As UFS working in HS G3 RB L2 mode, aggregated
+		 * bandwidth (AB) should take care of providing
+		 * optimum throughput requested. However, as tested,
+		 * in order to scale up CNOC clock, instantaneous
+		 * bindwidth (IB) needs to be given a proper value too.
+		 */
+		<123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */
+		<123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */
+
+		qcom,bus-vector-names = "MIN",
+		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
+		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
+		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
+		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2",
+		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
+		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2",
+		"MAX";
+
+		/* PM QoS */
+		qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
+		qcom,pm-qos-cpu-group-latency-us = <26 26>;
+		qcom,pm-qos-default-cpu = <0>;
+
+		pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
+		pinctrl-0 = <&ufs_dev_reset_assert>;
+		pinctrl-1 = <&ufs_dev_reset_deassert>;
+
+		resets = <&gcc GCC_UFS_PHY_BCR>;
+		reset-names = "core_reset";
+		non-removable;
+
+		status = "disabled";
+	};
+
+	thermal_zones: thermal-zones {};
+
+	tsens0:tsens@c222000 {
+		compatible = "qcom,tsens24xx";
+		reg = <0x04410000  0x8>,
+			<0x04411000  0x1ff>;
+		reg-names = "tsens_srot_physical",
+			"tsens_tm_physical";
+		interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "tsens-upper-lower", "tsens-critical";
+		tsens-reinit-wa;
+		#thermal-sensor-cells = <1>;
+	};
+
+	clocks {
+		xo_board: xo_board {
+			compatible = "fixed-clock";
+			clock-frequency = <19200000>;
+			clock-output-names = "xo_board";
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32764>;
+			clock-output-names = "sleep_clk";
+			#clock-cells = <0>;
+		};
+
+		usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
+			#clock-cells = <0>;
+		};
+	};
+
+	rpmcc: clock-controller {
+		compatible = "qcom,rpmcc-bengal";
+		#clock-cells = <1>;
+	};
+
+	qcom,rmtfs_sharedmem@0 {
+		compatible = "qcom,sharedmem-uio";
+		reg = <0x0 0x200000>;
+		reg-names = "rmtfs";
+		qcom,client-id = <0x00000001>;
+		qcom,guard-memory;
+		qcom,vm-nav-path;
+	};
+
+	gcc: clock-controller@1400000 {
+		compatible = "qcom,khaje-gcc", "syscon";
+		reg = <0x1400000 0x1f0000>;
+		reg-names = "cc_base";
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		vdd_mx-supply = <&VDD_MX_LEVEL>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	dispcc: clock-controller@5f00000 {
+		compatible = "qcom,khaje-dispcc", "syscon";
+		reg = <0x05f00000 0x20000>;
+		reg-names = "cc_base";
+		clock-names = "cfg_ahb_clk";
+		clocks = <&gcc GCC_DISP_AHB_CLK>;
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	gpucc: clock-controller@5990000 {
+		compatible = "qcom,khaje-gpucc", "syscon";
+		reg = <0x5990000 0x9000>;
+		reg-names = "cc_base";
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		vdd_mx-supply = <&VDD_MX_LEVEL>;
+		qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	mccc_debug: syscon@447d200 {
+		compatible = "syscon";
+		reg = <0x447d200 0x100>;
+	};
+
+	cpucc_debug: syscon@f11101c {
+		compatible = "syscon";
+		reg = <0xf11101c 0x4>;
+	};
+
+	debugcc: clock-controller@0 {
+		compatible = "qcom,khaje-debugcc";
+		qcom,gcc = <&gcc>;
+		qcom,dispcc = <&dispcc>;
+		qcom,gpucc = <&gpucc>;
+		qcom,mccc = <&mccc_debug>;
+		qcom,cpucc = <&cpucc_debug>;
+		clock-names = "xo_clk_src";
+		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+		#clock-cells = <1>;
+	};
+
+	cpufreq_hw: qcom,cpufreq-hw {
+		compatible = "qcom,cpufreq-hw";
+		reg = <0xf521000 0x1000>, <0xf523000 0x1000>;
+		reg-names = "freq-domain0", "freq-domain1";
+		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+		clock-names = "xo", "alternate";
+		qcom,no-accumulative-counter;
+		qcom,max-lut-entries = <12>;
+		#freq-domain-cells = <2>;
+	};
+
+	qcom,cpufreq-hw-debug@0f521000 {
+		compatible = "qcom,cpufreq-hw-debug";
+		reg = <0x0f521000 0x800>;
+		reg-names = "domain-top";
+		qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>;
+	};
+
+	tcsr_mutex_block: syscon@00340000 {
+		compatible = "syscon";
+		reg = <0x340000 0x20000>;
+	};
+
+	tcsr_mutex: hwlock {
+		compatible = "qcom,tcsr-mutex";
+		syscon = <&tcsr_mutex_block 0 0x1000>;
+		#hwlock-cells = <1>;
+	};
+
+	smem: qcom,smem {
+		compatible = "qcom,smem";
+		memory-region = <&smem_mem>;
+		hwlocks = <&tcsr_mutex 3>;
+	};
+
+	rpm_msg_ram: memory@045f0000 {
+			compatible = "qcom,rpm-msg-ram";
+			reg = <0x45f0000 0x7000>;
+	};
+
+	apcs_glb: mailbox@0f111000 {
+		compatible = "qcom,bengal-apcs-hmss-global";
+		reg = <0xF111000 0x1000>;
+
+		#mbox-cells = <1>;
+	};
+
+	qcom,msm-cdsp-loader {
+		compatible = "qcom,cdsp-loader";
+		qcom,proc-img-to-load = "cdsp";
+	};
+
+	qcom,msm-adsprpc-mem {
+		compatible = "qcom,msm-adsprpc-mem-region";
+		memory-region = <&adsp_mem>;
+		restrict-access;
+	};
+
+	qcom,msm_fastrpc {
+		compatible = "qcom,msm-fastrpc-compute";
+		qcom,rpc-latency-us = <611>;
+		qcom,adsp-remoteheap-vmid = <22 37>;
+		qcom,fastrpc-adsp-audio-pdr;
+		qcom,fastrpc-adsp-sensors-pdr;
+
+		qcom,msm_fastrpc_compute_cb1 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x0C01 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+		};
+
+		qcom,msm_fastrpc_compute_cb2 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x0C02 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+		};
+
+		qcom,msm_fastrpc_compute_cb3 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x0C03 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+		};
+
+		qcom,msm_fastrpc_compute_cb4 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x0C04 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+		};
+
+		qcom,msm_fastrpc_compute_cb5 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x0C05 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+		};
+
+		qcom,msm_fastrpc_compute_cb6 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x0C06 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+		};
+
+		qcom,msm_fastrpc_compute_cb9 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			qcom,secure-context-bank;
+			iommus = <&apps_smmu 0x0C09 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+		};
+
+		qcom,msm_fastrpc_compute_cb10 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x01C3 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+		};
+
+		qcom,msm_fastrpc_compute_cb11 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x01C4 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+		};
+
+		qcom,msm_fastrpc_compute_cb12 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x01C5 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+		};
+
+		qcom,msm_fastrpc_compute_cb13 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x01C6 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+		};
+
+		qcom,msm_fastrpc_compute_cb14 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x01C7 0x0>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+		};
+
+	};
+
+	rpm-glink {
+		compatible = "qcom,glink-rpm";
+		interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
+		qcom,rpm-msg-ram = <&rpm_msg_ram>;
+		mboxes = <&apcs_glb 0>;
+
+		qcom,rpm_glink_ssr {
+			qcom,glink-channels = "glink_ssr";
+			qcom,notify-edges = <&glink_modem>,
+					    <&glink_adsp>,
+					    <&glink_cdsp>;
+		};
+
+	};
+
+	qcom,glink {
+		compatible = "qcom,glink";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		glink_modem: modem {
+			qcom,remote-pid = <1>;
+			transport = "smem";
+			mboxes = <&apcs_glb 12>;
+			mbox-names = "mpss_smem";
+			interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
+
+			label = "modem";
+			qcom,glink-label = "mpss";
+
+			qcom,modem_qrtr {
+				qcom,glink-channels = "IPCRTR";
+				qcom,low-latency;
+				qcom,intents = <0x800  5
+						0x2000 3
+						0x4400 2>;
+			};
+
+			qcom,msm_fastrpc_rpmsg {
+				compatible = "qcom,msm-fastrpc-rpmsg";
+				qcom,glink-channels = "fastrpcglink-apps-dsp";
+				qcom,intents = <0x64 64>;
+			};
+
+			qcom,modem_ds {
+				qcom,glink-channels = "DS";
+				qcom,intents = <0x4000 2>;
+			};
+
+			qcom,modem_glink_ssr {
+				qcom,glink-channels = "glink_ssr";
+				qcom,notify-edges = <&glink_adsp>,
+						    <&glink_cdsp>;
+			};
+		};
+
+		glink_adsp: adsp {
+			qcom,remote-pid = <2>;
+			transport = "smem";
+			mboxes = <&apcs_glb 8>;
+			mbox-names = "adsp_smem";
+			interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
+
+			label = "adsp";
+			qcom,glink-label = "lpass";
+
+			qcom,adsp_qrtr {
+				qcom,glink-channels = "IPCRTR";
+				qcom,low-latency;
+				qcom,intents = <0x800  5
+						0x2000 3
+						0x4400 2>;
+			};
+
+			qcom,apr_tal_rpmsg {
+				qcom,glink-channels = "apr_audio_svc";
+				qcom,intents = <0x200 20>;
+			};
+
+			qcom,msm_fastrpc_rpmsg {
+				compatible = "qcom,msm-fastrpc-rpmsg";
+				qcom,glink-channels = "fastrpcglink-apps-dsp";
+				qcom,intents = <0x64 64>;
+			};
+
+			qcom,adsp_glink_ssr {
+				qcom,glink-channels = "glink_ssr";
+				qcom,notify-edges = <&glink_modem>,
+						    <&glink_cdsp>;
+			};
+		};
+
+		glink_cdsp: cdsp {
+			qcom,remote-pid = <5>;
+			transport = "smem";
+			mboxes = <&apcs_glb 28>;
+			mbox-names = "cdsp_smem";
+			interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>;
+
+			label = "cdsp";
+			qcom,glink-label = "cdsp";
+
+			qcom,cdsp_qrtr {
+				qcom,glink-channels = "IPCRTR";
+				qcom,intents = <0x800  5
+						0x2000 3
+						0x4400 2>;
+			};
+
+			qcom,msm_fastrpc_rpmsg {
+				compatible = "qcom,msm-fastrpc-rpmsg";
+				qcom,glink-channels = "fastrpcglink-apps-dsp";
+				qcom,intents = <0x64 64>;
+			};
+
+			qcom,msm_cdsprm_rpmsg {
+				compatible = "qcom,msm-cdsprm-rpmsg";
+				qcom,glink-channels = "cdsprmglink-apps-dsp";
+				qcom,intents = <0x20 12>;
+
+				msm_cdsp_rm: qcom,msm_cdsp_rm {
+					compatible = "qcom,msm-cdsp-rm";
+					qcom,qos-latency-us = <100>;
+					qcom,qos-maxhold-ms = <20>;
+				};
+			};
+
+			qcom,cdsp_glink_ssr {
+				qcom,glink-channels = "glink_ssr";
+				qcom,notify-edges = <&glink_modem>,
+						    <&glink_adsp>;
+			};
+		};
+	};
+
+	qcom,glinkpkt {
+		compatible = "qcom,glinkpkt";
+
+		qcom,glinkpkt-at-mdm0 {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DS";
+			qcom,glinkpkt-dev-name = "at_mdm0";
+		};
+
+		qcom,glinkpkt-apr-apps2 {
+			qcom,glinkpkt-edge = "adsp";
+			qcom,glinkpkt-ch-name = "apr_apps2";
+			qcom,glinkpkt-dev-name = "apr_apps2";
+		};
+
+		qcom,glinkpkt-data40-cntl {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DATA40_CNTL";
+			qcom,glinkpkt-dev-name = "smdcntl8";
+		};
+
+		qcom,glinkpkt-data1 {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DATA1";
+			qcom,glinkpkt-dev-name = "smd7";
+		};
+
+		qcom,glinkpkt-data4 {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DATA4";
+			qcom,glinkpkt-dev-name = "smd8";
+		};
+
+		qcom,glinkpkt-data11 {
+			qcom,glinkpkt-edge = "mpss";
+			qcom,glinkpkt-ch-name = "DATA11";
+			qcom,glinkpkt-dev-name = "smd11";
+		};
+	};
+
+	qcom,smp2p_sleepstate {
+		compatible = "qcom,smp2p-sleepstate";
+		qcom,smem-states = <&sleepstate_smp2p_out 0>;
+		interrupt-parent = <&sleepstate_smp2p_in>;
+		interrupts = <0 0>;
+		interrupt-names = "smp2p-sleepstate-in";
+	};
+
+	qcom,smp2p-modem {
+		compatible = "qcom,smp2p";
+		qcom,smem = <435>, <428>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&apcs_glb 14>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <1>;
+
+		modem_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		modem_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
+			qcom,entry-name = "ipa";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		/* ipa - inbound entry from mss */
+		smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
+			qcom,entry-name = "ipa";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
+			qcom,entry-name = "wlan";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+	};
+
+	qcom,smp2p-adsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <443>, <429>;
+		interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&apcs_glb 10>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <2>;
+
+		adsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		adsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
+			qcom,entry-name = "rdbg";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
+			qcom,entry-name = "rdbg";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		sleepstate_smp2p_out: sleepstate-out {
+			qcom,entry-name = "sleepstate";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		sleepstate_smp2p_in: qcom,sleepstate-in {
+			qcom,entry-name = "sleepstate_see";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	qcom,smp2p-cdsp {
+		compatible = "qcom,smp2p";
+		qcom,smem = <94>, <432>;
+		interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&apcs_glb 30>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <5>;
+
+		cdsp_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		cdsp_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
+			qcom,entry-name = "rdbg";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
+			qcom,entry-name = "rdbg";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	qcom,sps {
+		compatible = "qcom,msm-sps-4k";
+		qcom,pipe-attr-ee;
+	};
+
+	qfprom: qfprom@1b40000 {
+		compatible = "qcom,qfprom";
+		reg = <0x1b40000 0x7000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		read-only;
+		ranges;
+
+		stm_debug_fuse: stm@20f0 {
+			reg = <0x20f0 0x4>;
+		};
+
+		feat_conf5: feat_conf5@6018 {
+			reg = <0x6018 0x4>;
+		};
+
+		feat_conf10: feat_conf10@602c {
+			reg = <0x602c 0x4>;
+		};
+
+		adsp_variant: adsp_variant@6011 {
+			reg = <0x6011 0x1>;
+			bits = <3 1>;
+		};
+
+		gpu_speed_bin: gpu_speed_bin@6006 {
+			reg = <0x6006 0x2>;
+			bits = <5 8>;
+		};
+
+		gpu_gaming_bin: gpu_gaming_bin@602d {
+			reg = <0x602d 0x1>;
+			bits = <5 1>;
+		};
+
+		feat_conf11: feat_conf11@6030 {
+			reg = <0x6030 0x1>;
+			bits = <0 8>;
+		};
+	};
+
+	spmi_bus: qcom,spmi@1c40000 {
+		compatible = "qcom,spmi-pmic-arb";
+		reg = <0x1c40000 0x1100>,
+			<0x1e00000 0x2000000>,
+			<0x3e00000 0x100000>,
+			<0x3f00000 0xa0000>,
+			<0x1c0a000 0x26000>;
+		reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+		interrupt-names = "periph_irq";
+		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,ee = <0>;
+		qcom,channel = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-controller;
+		#interrupt-cells = <4>;
+		cell-index = <0>;
+	};
+
+	icnss: qcom,icnss@C800000 {
+		compatible = "qcom,icnss";
+		reg = <0xC800000 0x800000>,
+		      <0xb0000000 0x10000>;
+		reg-names = "membase", "smmu_iova_ipa";
+		iommus = <&apps_smmu 0x1A0 0x1>;
+		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
+			     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
+			     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
+			     <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
+			     <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
+			     <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
+			     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
+			     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
+			     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
+			     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
+			     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH /* CE10 */ >,
+			     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH /* CE11 */ >;
+		qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
+		qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		qcom,iommu-faults = "stall-disable", "HUPCF";
+		qcom,iommu-geometry = <0xa0000000 0x10010000>;
+		vdd-cx-mx-supply = <&L8A>;
+		vdd-1.8-xo-supply = <&L16A>;
+		vdd-1.3-rfa-supply = <&L17A>;
+		vdd-3.3-ch0-supply = <&L23A>;
+		qcom,vdd-cx-mx-config = <640000 640000>;
+		qcom,vdd-3.3-ch0-config = <3000000 3312000>;
+		qcom,smp2p_map_wlan_1_in {
+			interrupts-extended = <&smp2p_wlan_1_in 0 0>,
+					      <&smp2p_wlan_1_in 1 0>;
+			interrupt-names = "qcom,smp2p-force-fatal-error",
+					  "qcom,smp2p-early-crash-ind";
+		};
+	};
+
+	qcom,venus@5ab0000 {
+		compatible = "qcom,pil-tz-generic";
+		reg = <0x5ab0000 0x20000>;
+
+		vdd-supply = <&gcc_venus_gdsc>;
+		qcom,proxy-reg-names = "vdd";
+
+		clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>,
+			<&gcc GCC_VENUS_CTL_AXI_CLK>,
+			<&gcc GCC_VIDEO_AHB_CLK>,
+			<&gcc GCC_VIDEO_THROTTLE_CORE_CLK>;
+		clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk";
+		qcom,proxy-clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk";
+		qcom,mas-crypto = <&mas_crypto_c0>;
+
+		qcom,core-freq = <240000000>;
+		qcom,ahb-freq = <240000000>;
+
+		qcom,pas-id = <9>;
+		qcom,msm-bus,name = "pil-venus";
+		qcom,msm-bus,num-cases = <2>;
+		qcom,msm-bus,num-paths = <1>;
+		qcom,msm-bus,vectors-KBps =
+			<63 512 0 0>,
+			<63 512 0 304000>;
+		qcom,proxy-timeout-ms = <100>;
+		qcom,firmware-name = "venus";
+		memory-region = <&pil_video_mem>;
+	};
+
+	cx_ipeak_lm: cx_ipeak@3ed000 {
+		compatible = "qcom,cx-ipeak-v2";
+		reg = <0x3ed000 0xe008>;
+	};
+
+	pil_modem: qcom,mss@6080000 {
+		compatible = "qcom,pil-tz-generic";
+		reg = <0x6080000 0x100>;
+
+		clocks = <&rpmcc CXO_SMD_PIL_MSS_CLK>;
+		clock-names = "xo";
+		qcom,proxy-clock-names = "xo";
+		qcom,mas-crypto = <&mas_crypto_c0>;
+
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		qcom,proxy-reg-names = "vdd_cx";
+
+		qcom,firmware-name = "modem";
+		memory-region = <&pil_modem_mem>;
+		qcom,proxy-timeout-ms = <10000>;
+		qcom,sysmon-id = <0>;
+		qcom,ssctl-instance-id = <0x12>;
+		qcom,pas-id = <4>;
+		qcom,smem-id = <421>;
+		qcom,minidump-id = <3>;
+		qcom,aux-minidump-ids = <4>;
+		qcom,complete-ramdump;
+		qcom,sequential-fw-load;
+
+		qcom,msm-bus,name = "pil-modem";
+		qcom,msm-bus,num-cases = <2>;
+		qcom,msm-bus,num-paths = <1>;
+		qcom,msm-bus,vectors-KBps =
+			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0 0 0>,
+			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0 0 8171520>;
+
+		/* Inputs from mss */
+		interrupts-extended = <&intc 0 307 1>,
+				<&modem_smp2p_in 0 0>,
+				<&modem_smp2p_in 2 0>,
+				<&modem_smp2p_in 1 0>,
+				<&modem_smp2p_in 3 0>,
+				<&modem_smp2p_in 7 0>;
+
+		interrupt-names = "qcom,wdog",
+				"qcom,err-fatal",
+				"qcom,proxy-unvote",
+				"qcom,err-ready",
+				"qcom,stop-ack",
+				"qcom,shutdown-ack";
+
+		/* Outputs to mss */
+		qcom,smem-states = <&modem_smp2p_out 0>;
+		qcom,smem-state-names = "qcom,force-stop";
+	};
+
+	ddr_bw_opp_table: ddr-bw-opp-table {
+		compatible = "operating-points-v2";
+		BW_OPP_ENTRY_DDR( 200, 8, 0x80); /* 1525 MB/s */
+		BW_OPP_ENTRY_DDR( 547, 8, 0x80); /* 4173 MB/s */
+		BW_OPP_ENTRY_DDR( 768, 8, 0x80); /* 5859 MB/s */
+		BW_OPP_ENTRY_DDR(1017, 8, 0x80); /* 7759 MB/s */
+		BW_OPP_ENTRY_DDR(1555, 8, 0x80); /*11863 MB/s */
+		BW_OPP_ENTRY_DDR(1804, 8, 0x80); /*13763 MB/s */
+		BW_OPP_ENTRY_DDR(2092, 8, 0x80); /*15960 MB/s */
+	};
+
+	suspendable_ddr4_bw_opp_table: suspendable-ddr4-bw-opp-table {
+		compatible = "operating-points-v2";
+		BW_OPP_ENTRY_DDR(   0, 8, 0x80); /*    0 MB/s */
+		BW_OPP_ENTRY_DDR( 200, 8, 0x80); /* 1525 MB/s */
+		BW_OPP_ENTRY_DDR( 547, 8, 0x80); /* 4173 MB/s */
+		BW_OPP_ENTRY_DDR( 768, 8, 0x80); /* 5859 MB/s */
+		BW_OPP_ENTRY_DDR(1017, 8, 0x80); /* 7759 MB/s */
+		BW_OPP_ENTRY_DDR(1555, 8, 0x80); /*11863 MB/s */
+		BW_OPP_ENTRY_DDR(1804, 8, 0x80); /*13763 MB/s */
+		BW_OPP_ENTRY_DDR(2092, 8, 0x80); /*15960 MB/s */
+	};
+
+	cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw {
+		compatible = "qcom,devbw-ddr";
+		governor = "performance";
+		qcom,src-dst-ports =
+			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+		qcom,active-only;
+		operating-points-v2 = <&ddr_bw_opp_table>;
+	};
+
+	cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@01b8e200 {
+		compatible = "qcom,bimc-bwmon4";
+		reg = <0x01b8e300 0x100>, <0x01b8e200 0x100>;
+		reg-names = "base", "global_base";
+		interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,mport = <0>;
+		qcom,hw-timer-hz = <19200000>;
+		qcom,target-dev = <&cpu_cpu_ddr_bw>;
+		qcom,count-unit = <0x10000>;
+	};
+
+	cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
+		compatible = "qcom,devbw-ddr";
+		governor = "performance";
+		qcom,src-dst-ports =
+			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+		qcom,active-only;
+		operating-points-v2 = <&ddr_bw_opp_table>;
+	};
+
+	cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat {
+		compatible = "qcom,devbw-ddr";
+		governor = "performance";
+		qcom,src-dst-ports =
+			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+		qcom,active-only;
+		operating-points-v2 = <&ddr_bw_opp_table>;
+	};
+
+	cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
+		compatible = "qcom,arm-memlat-cpugrp";
+		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+
+		cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon {
+			compatible = "qcom,arm-memlat-mon";
+			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+			qcom,target-dev = <&cpu0_cpu_ddr_lat>;
+			qcom,cachemiss-ev = <0x17>;
+			qcom,stall-cycle-ev = <0xE7>;
+			qcom,core-dev-table =
+				< 1190400 MHZ_TO_MBPS( 547, 8) >,
+				< 1516800 MHZ_TO_MBPS( 768, 8) >,
+				< 1804800 MHZ_TO_MBPS(1017, 8) >;
+		};
+
+		cpu0_computemon: qcom,cpu0-computemon {
+			compatible = "qcom,arm-compute-mon";
+			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+			qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
+			qcom,core-dev-table =
+				< 1190400 MHZ_TO_MBPS( 547, 8) >,
+				< 1516800 MHZ_TO_MBPS( 768, 8) >,
+				< 1804800 MHZ_TO_MBPS(1017, 8) >;
+		};
+	};
+
+	cpu4_cpu_ddr_lat: qcom,cpu4-cpu-ddr-lat {
+		compatible = "qcom,devbw-ddr";
+		governor = "performance";
+		qcom,src-dst-ports =
+			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+		qcom,active-only;
+		operating-points-v2 = <&ddr_bw_opp_table>;
+	};
+
+	cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {
+		compatible = "qcom,devbw-ddr";
+		governor = "performance";
+		qcom,src-dst-ports =
+			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+		qcom,active-only;
+		operating-points-v2 = <&ddr_bw_opp_table>;
+	};
+
+	cpu4_memlat_cpugrp: qcom,cpu4-cpugrp {
+		compatible = "qcom,arm-memlat-cpugrp";
+		qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+
+		cpu4_cpu_ddr_latmon: qcom,cpu4-cpu-ddr-latmon {
+			compatible = "qcom,arm-memlat-mon";
+			qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+			qcom,target-dev = <&cpu4_cpu_ddr_lat>;
+			qcom,cachemiss-ev = <0x17>;
+			qcom,stall-cycle-ev = <0x24>;
+			qcom,core-dev-table =
+				< 1056000 MHZ_TO_MBPS( 547, 8) >,
+				< 1344000 MHZ_TO_MBPS(1017, 8) >,
+				< 1766400 MHZ_TO_MBPS(1555, 8) >,
+				< 2208000 MHZ_TO_MBPS(1804, 8) >,
+				< 2803200 MHZ_TO_MBPS(2092, 8) >;
+		};
+
+		cpu4_computemon: qcom,cpu4-computemon {
+			compatible = "qcom,arm-compute-mon";
+			qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+			qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
+			qcom,core-dev-table =
+				< 1056000 MHZ_TO_MBPS( 547, 8) >,
+				< 1344000 MHZ_TO_MBPS( 768, 8) >,
+				< 1766400 MHZ_TO_MBPS(1017, 8) >,
+				< 2208000 MHZ_TO_MBPS(1804, 8) >,
+				< 2803200 MHZ_TO_MBPS(2092, 8) >;
+		};
+	};
+
+	qcom,msm_gsi {
+		compatible = "qcom,msm_gsi";
+	};
+
+	qcom,rmnet-ipa {
+		compatible = "qcom,rmnet-ipa3";
+		qcom,rmnet-ipa-ssr;
+		qcom,ipa-platform-type-msm;
+		qcom,ipa-advertise-sg-support;
+		qcom,ipa-napi-enable;
+	};
+
+	ipa_hw: qcom,ipa@0x5800000 {
+		compatible = "qcom,ipa";
+		reg = <0x5800000 0x34000>,
+			<0x5804000 0x28000>;
+		reg-names = "ipa-base", "gsi-base";
+		interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "ipa-irq", "gsi-irq";
+		qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */
+		qcom,ipa-hw-mode = <0>;
+		qcom,platform-type = <1>; /* MSM platform */
+		qcom,ee = <0>;
+		qcom,use-ipa-tethering-bridge;
+		qcom,modem-cfg-emb-pipe-flt;
+		qcom,ipa-wdi2;
+		qcom,ipa-wdi2_over_gsi;
+		qcom,ipa-endp-delay-wa;
+		qcom,ipa-fltrt-not-hashable;
+		qcom,use-64-bit-dma-mask;
+		qcom,arm-smmu;
+		qcom,smmu-fast-map;
+		qcom,use-ipa-pm;
+		qcom,skip-ieob-mask-wa;
+		clocks = <&rpmcc RPM_SMD_IPA_CLK>;
+		clock-names = "core_clk";
+		qcom,msm-bus,name = "ipa";
+		qcom,msm-bus,num-cases = <5>;
+		qcom,msm-bus,num-paths = <3>;
+		qcom,msm-bus,vectors-KBps =
+		/* No vote */
+		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 0 0>,
+		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 0 0>,
+		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 0>,
+		/* SVS2 */
+		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 465000>,
+		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 68570>,
+		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 80000 30>,
+		/* SVS */
+		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 2000000>,
+		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 267461>,
+		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 80000 109890>,
+		/* NOMINAL */
+		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0  206000 4000000>,
+		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 712961>,
+		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 491520>,
+		/* TURBO */
+		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 206000 5598900>,
+		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 1436481>,
+		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 491520>;
+		qcom,bus-vector-names =
+				"MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
+		qcom,throughput-threshold = <310 600 1000>;
+		qcom,scaling-exceptions = <>;
+
+		/* smp2p information */
+		qcom,smp2p_map_ipa_1_out {
+			compatible = "qcom,smp2p-map-ipa-1-out";
+		qcom,smem-states = <&smp2p_ipa_1_out 0>;
+			qcom,smem-state-names = "ipa-smp2p-out";
+		};
+
+		qcom,smp2p_map_ipa_1_in {
+			compatible = "qcom,smp2p-map-ipa-1-in";
+			interrupts-extended = <&smp2p_ipa_1_in 0 0>;
+			interrupt-names = "ipa-smp2p-in";
+		};
+	};
+
+	ipa_smmu_ap: ipa_smmu_ap {
+		compatible = "qcom,ipa-smmu-ap-cb";
+		iommus = <&apps_smmu 0x0140 0x0>;
+		qcom,iommu-dma-addr-pool = <0x10000000 0x30000000>;
+		/* modem tables in IMEM */
+		qcom,iommu-dma = "fastmap";
+		qcom,additional-mapping = <0x0c123000 0x0c123000 0x2000>;
+		qcom,iommu-geometry = <0 0xB0000000>;
+	};
+
+	ipa_smmu_wlan: ipa_smmu_wlan {
+		compatible = "qcom,ipa-smmu-wlan-cb";
+		iommus = <&apps_smmu 0x0141 0x0>;
+		/* ipa-uc ram */
+		qcom,iommu-dma = "atomic";
+	};
+
+	ipa_smmu_uc: ipa_smmu_uc {
+		compatible = "qcom,ipa-smmu-uc-cb";
+		iommus = <&apps_smmu 0x0142 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40400000 0x1fc00000>;
+	};
+
+	qcom,ipa_fws {
+		compatible = "qcom,pil-tz-generic";
+		qcom,pas-id = <0xf>;
+		qcom,firmware-name = "ipa_fws";
+		qcom,pil-force-shutdown;
+		memory-region = <&pil_ipa_fw_mem>;
+	};
+
+	qcom,demux {
+		compatible = "qcom,demux";
+	};
+
+tpdm_turing_llm: tpdm@8861000 {
+		compatible = "qcom,coresight-dummy";
+
+		coresight-name = "coresight-tpdm-turing_llm";
+		qcom,dummy-source;
+
+		port {
+			tpdm_turing_llm_out_funnel_turing: endpoint {
+				remote-endpoint =
+				<&funnel_turing_in_tpdm_turing_llm>;
+			};
+		};
+	};
+
+	/delete-node/ tpdm@8a58000;
+	tpdm_west: tpdm@8a58000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x8a58000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-west";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+		port {
+			tpdm_west_out_tpda11: endpoint {
+				remote-endpoint =
+				<&tpda11_in_tpdm_west>;
+			};
+		};
+	};
+
+	tpdm_spdm: tpdm@800f000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x0800f000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-spdm";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+		port {
+			tpdm_spdm_out_tpda13: endpoint {
+				remote-endpoint =
+				<&tpda13_in_tpdm_spdm>;
+			};
+		};
+	};
+
+	/delete-node/ funnel@8861000;
+	funnel_turing: funnel@8863000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x8863000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-turing";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_turing_out_funnel_qatb: endpoint {
+					remote-endpoint =
+					<&funnel_qatb_in_funnel_turing>;
+					source = <&turing_etm0>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_turing_out_tpda5: endpoint {
+					remote-endpoint =
+					<&tpda5_in_funnel_turing>;
+				};
+			};
+
+			port@2 {
+				reg = <0>;
+				funnel_turing_in_tpdm_turing: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&tpdm_turing_out_funnel_turing>;
+				};
+			};
+
+			port@3 {
+				reg = <1>;
+				funnel_turing_in_tpdm_turing_llm: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&tpdm_turing_llm_out_funnel_turing>;
+				};
+			};
+
+			port@4 {
+				reg = <2>;
+				funnel_turing_in_turing_etm0: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&turing_etm0_out_funnel_turing>;
+				};
+			};
+		};
+	};
+
+	/delete-node/ tpda@8004000;
+	tpda: tpda@8004000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+		reg = <0x8004000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda";
+
+		qcom,tpda-atid = <65>;
+		qcom,dsb-elem-size = <0 32>,
+						<1 32>,
+						<5 32>,
+						<11 32>,
+						<12 32>,
+						<15 32>;
+		qcom,cmb-elem-size = <7 32>,
+						<8 32>,
+						<10 32>,
+						<15 64>;
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				tpda_out_funnel_qatb: endpoint {
+					remote-endpoint =
+					<&funnel_qatb_in_tpda>;
+				};
+			};
+
+			port@1 {
+				reg = <0>;
+				tpda0_in_tpdm_dl_ct: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&tpdm_dl_ct_out_tpda0>;
+				};
+			};
+
+			port@2 {
+				reg = <1>;
+				tpda1_in_funnel_gpu: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&funnel_gpu_out_tpda1>;
+				};
+			};
+
+			port@3 {
+				reg = <5>;
+				tpda5_in_funnel_turing: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&funnel_turing_out_tpda5>;
+				};
+			};
+
+			port@4 {
+				reg = <7>;
+				tpda7_in_tpdm_vsense: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&tpdm_vsense_out_tpda7>;
+				};
+			};
+
+			port@5 {
+				reg = <8>;
+				tpda8_in_tpdm_dcc: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&tpdm_dcc_out_tpda8>;
+				};
+			};
+
+			port@6 {
+				reg = <10>;
+				tpda10_in_tpdm_prng: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&tpdm_prng_out_tpda10>;
+				};
+			};
+
+			port@7 {
+				reg = <11>;
+				tpda11_in_tpdm_west: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&tpdm_west_out_tpda11>;
+				};
+			};
+
+			port@8 {
+				reg = <12>;
+				tpda12_in_tpdm_qm: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&tpdm_qm_out_tpda12>;
+				};
+			};
+
+			port@9 {
+				reg = <13>;
+				tpda13_in_tpdm_spdm: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&tpdm_spdm_out_tpda13>;
+				};
+			};
+
+			port@10 {
+				reg = <15>;
+				tpda15_in_tpdm_pimem: endpoint {
+					slave-mode;
+					remote-endpoint =
+					<&tpdm_pimem_out_tpda15>;
+				};
+			};
+
+		};
+	};
+
+	/delete-node/ cti@8867000;
+	cti_turing_q6: cti@8862000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x8862000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-turing-q6";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
+};
+
+#include "bengal-gdsc.dtsi"
+#include "khaje-usb.dtsi"
+#include "bengal-ion.dtsi"
+#include "bengal-bus.dtsi"
+#include "bengal-vidc.dtsi"
+#include "pm6125.dtsi"
+
+&gcc_camss_top_gdsc {
+	status = "ok";
+};
+
+&gcc_ufs_phy_gdsc {
+	status = "ok";
+};
+
+&gcc_usb30_prim_gdsc {
+	status = "ok";
+};
+
+&gcc_vcodec0_gdsc {
+	qcom,support-hw-trigger;
+	status = "ok";
+};
+
+&gcc_venus_gdsc {
+	status = "ok";
+};
+
+&hlos1_vote_turing_mmu_tbu1_gdsc {
+	status = "ok";
+};
+
+&hlos1_vote_turing_mmu_tbu0_gdsc {
+	status = "ok";
+};
+
+&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc {
+	status = "ok";
+};
+
+&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc {
+	status = "ok";
+};
+
+&mdss_core_gdsc {
+	reg = <0x5f01004 0x4>;
+	qcom,support-hw-trigger;
+	status = "ok";
+};
+
+&gpu_cx_gdsc {
+	parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+&gpu_gx_gdsc {
+	parent-supply = <&VDD_CX_LEVEL>;
+	status = "ok";
+};
+
+#include "msm-arm-smmu-bengal.dtsi"
+#include "pm6125-rpm-regulator.dtsi"
+#include "khaje-regulator.dtsi"
+#include "bengal-pm.dtsi"
+#include "khaje-pinctrl.dtsi"
+#include "bengal-qupv3.dtsi"
+#include "bengal-gpu.dtsi"
+#include "bengal-audio.dtsi"
+#include "khaje-sde-pll.dtsi"
+#include "khaje-sde.dtsi"
+
+&soc {
+	/delete-node/ gpu_bw_tbl;
+	/delete-node/ gpubw;
+	/delete-node/ gpu_opp_table;
+
+	gpu_bw_tbl: gpu-bw-tbl {
+		compatible = "operating-points-v2";
+		BW_OPP_ENTRY( 0, 8); /* 0 MB/s */
+		BW_OPP_ENTRY( 200, 8); /* 1525 MB/s */
+		BW_OPP_ENTRY( 547, 8); /* 4173 MB/s */
+		BW_OPP_ENTRY( 768, 8); /* 5859 MB/s */
+		BW_OPP_ENTRY(1017, 8); /* 7759 MB/s */
+		BW_OPP_ENTRY(1555, 8); /*11863 MB/s */
+		BW_OPP_ENTRY(1804, 8); /*13763 MB/s */
+		BW_OPP_ENTRY(2092, 8); /*15960 MB/s */
+	};
+
+	gpubw: qcom,gpubw {
+			compatible = "qcom,devbw";
+			governor = "bw_vbif";
+			qcom,src-dst-ports = <26 512>;
+			operating-points-v2 = <&gpu_bw_tbl>;
+	};
+
+	gpu_opp_table: gpu-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-1114800000 {
+			opp-hz = /bits/ 64 <1114800000>;
+			opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+		};
+
+		opp-1025000000 {
+			opp-hz = /bits/ 64 <1025000000>;
+			opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>;
+		};
+
+		opp-785000000 {
+			opp-hz = /bits/ 64 <785000000>;
+			opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;
+		};
+
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+		};
+
+		opp-465000000 {
+			opp-hz = /bits/ 64 <465000000>;
+			opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;
+		};
+
+		opp-320000000 {
+			opp-hz = /bits/ 64 <320000000>;
+			opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+		};
+	};
+};
+
+&msm_gpu {
+	qcom,chipid = <0x06010001>;
+	qcom,msm-bus,num-cases = <8>;
+	qcom,msm-bus,vectors-KBps =
+		<26 512 0 0>,
+		<26 512 0 1600000>,   /*  1 bus=200  (LOW SVS) */
+		<26 512 0 4376000>,   /*  2 bus=547  (LOW SVS) */
+		<26 512 0 6144000>,   /*  3 bus=768  (SVS)     */
+		<26 512 0 8136000>,   /*  4 bus=1017 (SVS_L1)  */
+		<26 512 0 12440000>,  /*  5 bus=1555 (NOM)     */
+		<26 512 0 14432000>,  /*  6 bus=1804 (TURBO)   */
+		<26 512 0 16736000>;  /*  7 bus=2092 (TURBO_L1)   */
+
+	/delete-node/ qcom,gpu-pwrlevel-bins;
+	/*
+	 * Speed-bin zero is default speed bin.
+	 * For rest of the speed bins, speed-bin value
+	 * is calculated as FMAX/4.8 MHz round up to zero
+	 * decimal places plus two margin to account for
+	 * clock jitters.
+	 */
+	qcom,gpu-pwrlevel-bins {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		compatible = "qcom,gpu-pwrlevel-bins";
+
+		qcom,gpu-pwrlevels-0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,speed-bin = <0>;
+
+			qcom,initial-pwrlevel = <5>;
+			qcom,ca-target-pwrlevel = <4>;
+
+			/* TURBO_L1 */
+			qcom,gpu-pwrlevel@0 {
+				reg = <0>;
+				qcom,gpu-freq = <1114800000>;
+				qcom,bus-freq = <7>;
+				qcom,bus-min = <7>;
+				qcom,bus-max = <7>;
+			};
+
+			/* TURBO */
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
+				qcom,gpu-freq = <1025000000>;
+				qcom,bus-freq = <6>;
+				qcom,bus-min = <5>;
+				qcom,bus-max = <7>;
+			};
+
+			/* NOM */
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
+				qcom,gpu-freq = <785000000>;
+				qcom,bus-freq = <5>;
+				qcom,bus-min = <4>;
+				qcom,bus-max = <5>;
+			};
+
+			/* SVS_L1 */
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
+				qcom,gpu-freq = <600000000>;
+				qcom,bus-freq = <4>;
+				qcom,bus-min = <3>;
+				qcom,bus-max = <5>;
+			};
+
+			/* SVS */
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
+				qcom,gpu-freq = <465000000>;
+				qcom,bus-freq = <3>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <4>;
+			};
+
+			/* LOW SVS */
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
+				qcom,gpu-freq = <320000000>;
+				qcom,bus-freq = <2>;
+				qcom,bus-min = <1>;
+				qcom,bus-max = <2>;
+			};
+
+			/* XO */
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
+				qcom,gpu-freq = <0>;
+				qcom,bus-freq = <0>;
+				qcom,bus-min = <0>;
+				qcom,bus-max = <0>;
+			};
+		};
+
+		qcom,gpu-pwrlevels-1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,speed-bin = <235>;
+
+			qcom,initial-pwrlevel = <5>;
+			qcom,ca-target-pwrlevel = <4>;
+
+			/* TURBO_L1 */
+			qcom,gpu-pwrlevel@0 {
+				reg = <0>;
+				qcom,gpu-freq = <1114800000>;
+				qcom,bus-freq = <7>;
+				qcom,bus-min = <7>;
+				qcom,bus-max = <7>;
+			};
+
+			/* TURBO */
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
+				qcom,gpu-freq = <1025000000>;
+				qcom,bus-freq = <6>;
+				qcom,bus-min = <5>;
+				qcom,bus-max = <7>;
+			};
+
+			/* NOM */
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
+				qcom,gpu-freq = <785000000>;
+				qcom,bus-freq = <5>;
+				qcom,bus-min = <4>;
+				qcom,bus-max = <5>;
+			};
+
+			/* SVS_L1 */
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
+				qcom,gpu-freq = <600000000>;
+				qcom,bus-freq = <4>;
+				qcom,bus-min = <3>;
+				qcom,bus-max = <5>;
+			};
+
+			/* SVS */
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
+				qcom,gpu-freq = <465000000>;
+				qcom,bus-freq = <3>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <4>;
+			};
+
+			/* LOW SVS */
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
+				qcom,gpu-freq = <320000000>;
+				qcom,bus-freq = <2>;
+				qcom,bus-min = <1>;
+				qcom,bus-max = <2>;
+			};
+
+			/* XO */
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
+				qcom,gpu-freq = <0>;
+				qcom,bus-freq = <0>;
+				qcom,bus-min = <0>;
+				qcom,bus-max = <0>;
+			};
+		};
+
+		qcom,gpu-pwrlevels-2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			qcom,speed-bin = <216>;
+
+			qcom,initial-pwrlevel = <4>;
+			qcom,ca-target-pwrlevel = <3>;
+
+			/* TURBO */
+			qcom,gpu-pwrlevel@0 {
+				reg = <0>;
+				qcom,gpu-freq = <1025000000>;
+				qcom,bus-freq = <6>;
+				qcom,bus-min = <5>;
+				qcom,bus-max = <7>;
+			};
+
+			/* NOM */
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
+				qcom,gpu-freq = <785000000>;
+				qcom,bus-freq = <5>;
+				qcom,bus-min = <4>;
+				qcom,bus-max = <5>;
+			};
+
+			/* SVS_L1 */
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
+				qcom,gpu-freq = <600000000>;
+				qcom,bus-freq = <4>;
+				qcom,bus-min = <3>;
+				qcom,bus-max = <5>;
+			};
+
+			/* SVS */
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
+				qcom,gpu-freq = <465000000>;
+				qcom,bus-freq = <3>;
+				qcom,bus-min = <2>;
+				qcom,bus-max = <4>;
+			};
+
+			/* LOW SVS */
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
+				qcom,gpu-freq = <320000000>;
+				qcom,bus-freq = <2>;
+				qcom,bus-min = <1>;
+				qcom,bus-max = <2>;
+			};
+
+			/* XO */
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
+				qcom,gpu-freq = <0>;
+				qcom,bus-freq = <0>;
+				qcom,bus-min = <0>;
+				qcom,bus-max = <0>;
+			};
+		};
+	};
+};
+
+&qupv3_se1_i2c {
+	status = "ok";
+	#include "pm8008.dtsi"
+};
+
+&pm8008_regulators {
+	/delete-property/ qcom,enable-ocp-broadcast;
+};
+
+&pm8008_8 {
+	/* PM8008 IRQ STAT */
+	interrupt-parent = <&tlmm>;
+	interrupts = <25 IRQ_TYPE_EDGE_RISING>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pm8008_active &pm8008_interrupt>;
+};
+
+&pm8008_regulators {
+	vdd_l1_l2-supply = <&S6A>;
+	vdd_l7-supply = <&S7A>;
+};
+
+&L1P {
+	regulator-min-microvolt = <1100000>;
+	regulator-max-microvolt = <1300000>;
+	qcom,min-dropout-voltage = <56000>;
+};
+
+&L2P {
+	regulator-min-microvolt = <950000>;
+	regulator-max-microvolt = <1150000>;
+	qcom,min-dropout-voltage = <88000>;
+};
+
+&L3P {
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <2900000>;
+	qcom,min-dropout-voltage = <96000>;
+};
+
+&L4P {
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <2900000>;
+	qcom,min-dropout-voltage = <136000>;
+};
+
+&L5P {
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <2900000>;
+	qcom,min-dropout-voltage = <240000>;
+};
+
+&L6P {
+	regulator-min-microvolt = <2700000>;
+	regulator-max-microvolt = <2900000>;
+	qcom,min-dropout-voltage = <168000>;
+};
+
+&L7P {
+	regulator-min-microvolt = <1650000>;
+	regulator-max-microvolt = <1800000>;
+	qcom,min-dropout-voltage = <112000>;
+};
+
+&qupv3_se4_2uart {
+	status = "ok";
+};
+
+&qupv3_se3_4uart {
+	status = "ok";
+};
+
+&pm6125_vadc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&camera_therm_default &emmc_therm_default>;
+
+	pa_therm0 {
+		reg = <ADC_AMUX_THM1_PU2>;
+		label = "pa_therm0";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	quiet_therm {
+		reg = <ADC_AMUX_THM2_PU2>;
+		label = "quiet_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	camera_flash_therm {
+		reg = <ADC_GPIO1_PU2>;
+		label = "camera_flash_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	emmc_ufs_therm {
+		reg = <ADC_GPIO2_PU2>;
+		label = "emmc_ufs_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+};
+
+&pm6125_gpios {
+	camera_therm {
+		camera_therm_default: camera_therm_default {
+			pins = "gpio3";
+			bias-high-impedance;
+		};
+	};
+
+	emmc_therm {
+		emmc_therm_default: emmc_therm_default {
+			pins = "gpio4";
+			bias-high-impedance;
+		};
+	};
+
+};
+
+&spmi_bus {
+	qcom,pm6125@0 {
+		pm6125_adc_tm_iio: adc_tm@3400 {
+			compatible = "qcom,adc-tm5-iio";
+			reg = <0x3400 0x100>;
+			#thermal-sensor-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			io-channels = <&pm6125_vadc ADC_GPIO1_PU2>,
+					<&pm6125_vadc ADC_GPIO2_PU2>;
+
+			camera_flash_therm {
+				reg = <ADC_GPIO1_PU2>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+			};
+
+			emmc_ufs_therm {
+				reg = <ADC_GPIO2_PU2>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+			};
+		};
+	};
+};
+
+&pm6125_adc_tm {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>,
+			<&pm6125_vadc ADC_AMUX_THM2_PU2>,
+			<&pm6125_vadc ADC_XO_THERM_PU2>;
+
+	/* Channel nodes */
+	pa_therm0 {
+		reg = <ADC_AMUX_THM1_PU2>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	quiet_therm {
+		reg = <ADC_AMUX_THM2_PU2>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	xo_therm {
+		reg = <ADC_XO_THERM_PU2>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+};
+
+&msm_vidc {
+	qcom,cx-ipeak-data = <&cx_ipeak_lm 6>;
+	qcom,clock-freq-threshold = <300000000>;
+};
+
+#include "bengal-thermal.dtsi"
+#include "camera/khaje-camera.dtsi"
+#include "msm-rdbg.dtsi"
+
+&cxip_cdev {
+	status = "disabled";
+};
+
+&rpm_bus {
+	rpm_smd_cdev: rpm-smd-cdev {
+		compatible = "qcom,rpm-smd-cooling-device";
+		#cooling-cells = <2>;
+	};
+};
+
+&thermal_zones {
+	mapss-lowc {
+		cooling-maps {
+			rpm_smd_vdd_cdev {
+				trip = <&mapss_cap_trip>;
+				cooling-device = <&rpm_smd_cdev 2 2>;
+			};
+		};
+	};
+
+	camera-lowc {
+		cooling-maps {
+			rpm_smd_vdd_cdev {
+				trip = <&camera_cap_trip>;
+				cooling-device = <&rpm_smd_cdev 2 2>;
+			};
+		};
+	};
+};
diff --git a/qcom/kona-arglass-overlay.dts b/qcom/kona-arglass-overlay.dts
new file mode 100644
index 00000000..71a42515
--- /dev/null
+++ b/qcom/kona-arglass-overlay.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-kona.h>
+#include <dt-bindings/clock/qcom,camcc-kona.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "kona-arglass.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. kona AR Glass";
+	compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+	qcom,board-id = <0x1040008 0>;
+};
diff --git a/qcom/kona-arglass.dts b/qcom/kona-arglass.dts
new file mode 100644
index 00000000..417f4c9e
--- /dev/null
+++ b/qcom/kona-arglass.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona.dtsi"
+#include "kona-arglass.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. kona AR Glass";
+	compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+	qcom,board-id = <0x1040008 0>;
+};
diff --git a/qcom/kona-arglass.dtsi b/qcom/kona-arglass.dtsi
new file mode 100644
index 00000000..f892b1ee
--- /dev/null
+++ b/qcom/kona-arglass.dtsi
@@ -0,0 +1,1067 @@
+#include <dt-bindings/gpio/gpio.h>
+#include "kona-pmic-overlay.dtsi"
+#include "kona-sde-display.dtsi"
+#include "kona-audio-overlay.dtsi"
+#include "kona-audio-overlay-ar.dtsi"
+#include "kona-thermal-overlay.dtsi"
+#include "kona-xr-pinctrl-overlay.dtsi"
+#include "camera/kona-camera-sensor-arglass.dtsi"
+
+&tlmm {
+	mag_rst_gpio_default: mag_rst_gpio_default {
+		mux {
+			pins = "gpio125";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio125";
+			drive-strength = <8>;
+			bias-disable = <0>;
+			output-high;
+		};
+	};
+
+	mag_rst_gpio_sleep: mag_rst_gpio_sleep {
+		mux {
+			pins = "gpio125";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio125";
+			drive-strength = <8>;
+			bias-pull-down;
+			input-enable;
+		};
+	};
+
+	spkr_1_sd_n {
+		spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
+			mux {
+				pins = "gpio127";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio127";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;
+				input-enable;
+			};
+		};
+
+		spkr_1_sd_n_active: spkr_1_sd_n_active {
+			mux {
+				pins = "gpio127";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio127";
+				drive-strength = <16>;   /* 16 mA */
+				bias-disable;
+				output-high;
+			};
+		};
+	};
+
+	spkr_2_sd_n {
+		spkr_2_sd_n_sleep: spkr_2_sd_n_sleep {
+			mux {
+				pins = "gpio129";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio129";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;
+				input-enable;
+			};
+		};
+
+		spkr_2_sd_n_active: spkr_2_sd_n_active {
+			mux {
+				pins = "gpio129";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio129";
+				drive-strength = <16>;   /* 16 mA */
+				bias-disable;
+				output-high;
+			};
+		};
+	};
+
+	cam_sensor_6dof_vio_active: cam_sensor_6dof_vio_active {
+		/*  VIO LDO */
+		mux {
+			pins = "gpio41";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio41";
+			bias-disable; /* No PULL */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cam_sensor_6dof_vio_suspend: cam_sensor_6dof_vio_suspend {
+		/*  VIO LDO */
+		mux {
+			pins = "gpio41";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio41";
+			bias-pull-down; /* PULL DOWN */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+};
+
+&vendor {
+	kona_arglass_batterydata: qcom,battery-data {
+		qcom,batt-id-range-pct = <15>;
+		#include "fg-gen4-batterydata-goertek-650mah.dtsi"
+	};
+};
+
+&qupv3_se12_2uart {
+	status = "okay";
+};
+
+&pm8150a_amoled {
+	status = "disabled";
+};
+
+&qupv3_se6_4uart {
+	status = "ok";
+};
+
+&dai_mi2s2 {
+	status = "disabled";
+	qcom,msm-mi2s-tx-lines = <1>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active
+			&tert_mi2s_sd0_active>;
+	pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
+			&tert_mi2s_sd0_sleep>;
+};
+
+&pm8150_l10 {
+	regulator-max-microvolt = <3304000>;
+	qcom,init-voltage = <3304000>;
+};
+
+&qupv3_se1_i2c {
+	status = "disabled";
+	qcom,clk-freq-out = <1000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	xrfancontroller: xrfancontroller@50 {
+		compatible = "maxim,xrfancontroller";
+		reg = <0x50>;
+		/* Manetometer gpio */
+		mag_rst_gpio = <&tlmm 125 0>;
+		enable-active-high;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&mag_rst_gpio_default>;
+		pinctrl-1 = <&mag_rst_gpio_sleep>;
+		qcom,fan-pwr-en = <&tlmm 38 0x00>;
+		qcom,fan-pwr-bp = <&tlmm 39 0x00>;
+	};
+};
+
+&qupv3_se13_i2c {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	status = "disabled";
+};
+
+&ufsphy_mem {
+	compatible = "qcom,ufs-phy-qmp-v4";
+
+	vdda-phy-supply = <&pm8150_l5>;
+	vdda-phy-always-on;
+	vdda-pll-supply = <&pm8150_l9>;
+	vdda-phy-max-microamp = <89900>;
+	vdda-pll-max-microamp = <18800>;
+
+	status = "ok";
+};
+
+&ufshc_mem {
+	vdd-hba-supply = <&ufs_phy_gdsc>;
+	vdd-hba-fixed-regulator;
+	vcc-supply = <&pm8150_l17>;
+	vcc-voltage-level = <2504000 2950000>;
+	vcc-low-voltage-sup;
+	vccq-supply = <&pm8150_l6>;
+	vccq2-supply = <&pm8150_s4>;
+	vcc-max-microamp = <800000>;
+	vccq-max-microamp = <800000>;
+	vccq2-max-microamp = <800000>;
+
+	qcom,vddp-ref-clk-supply = <&pm8150_l6>;
+	qcom,vddp-ref-clk-max-microamp = <100>;
+	qcom,vccq-parent-supply = <&pm8150a_s8>;
+	qcom,vccq-parent-max-microamp = <210000>;
+
+	status = "ok";
+};
+
+&soc {
+	qcom,qbt_handler {
+		status = "disabled";
+	};
+
+	qcom,xr-stdalonevwr-misc {
+		compatible = "qcom,xr-stdalonevwr-misc";
+		/* IMU CLK Enable PM8150 GPIO 3 & MAG_RST_GPIO */
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&imu_clkin_default &mag_rst_gpio_default>;
+		pinctrl-1 = <&imu_clkin_sleep &mag_rst_gpio_sleep>;
+	};
+};
+
+&vreg_hap_boost {
+	status = "ok";
+};
+
+&pm8150b_haptics {
+	qcom,vmax-mv = <1697>;
+	qcom,play-rate-us = <5882>;
+	vdd-supply = <&vreg_hap_boost>;
+
+	wf_0 {
+		/* CLICK */
+		qcom,wf-play-rate-us = <5882>;
+		qcom,wf-vmax-mv = <1697>;
+	};
+
+	wf_1 {
+		/* DOUBLE CLICK */
+		qcom,wf-play-rate-us = <5882>;
+		qcom,wf-vmax-mv = <1697>;
+	};
+
+	wf_2 {
+		/* TICK */
+		qcom,wf-play-rate-us = <5882>;
+		qcom,wf-vmax-mv = <1697>;
+	};
+
+	wf_3 {
+		/* THUD */
+		qcom,wf-play-rate-us = <5882>;
+		qcom,wf-vmax-mv = <1697>;
+	};
+
+	wf_4 {
+		/* POP */
+		qcom,wf-play-rate-us = <5882>;
+		qcom,wf-vmax-mv = <1697>;
+	};
+
+	wf_5 {
+		/* HEAVY CLICK */
+		qcom,wf-play-rate-us = <5882>;
+		qcom,wf-vmax-mv = <1697>;
+	};
+};
+
+&pm8150b_vadc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	vph_pwr@83 {
+		reg = <ADC_VPH_PWR>;
+		label = "vph_pwr";
+		qcom,pre-scaling = <1 3>;
+	};
+
+	conn_therm@4f {
+		reg = <ADC_AMUX_THM3_PU2>;
+		label = "conn_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	chg_sbux@99 {
+		reg = <ADC_SBUx>;
+		label = "chg_sbux";
+		qcom,pre-scaling = <1 3>;
+	};
+
+	mid_chg_div6@1e {
+		reg = <ADC_MID_CHG_DIV6>;
+		label = "chg_mid";
+		qcom,pre-scaling = <1 6>;
+	};
+
+	usb_in_i_uv@7 {
+		reg = <ADC_USB_IN_I>;
+		label = "usb_in_i_uv";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	usb_in_v_div_16@8 {
+		reg = <ADC_USB_IN_V_16>;
+		label = "usb_in_v_div_16";
+		qcom,pre-scaling = <1 16>;
+	};
+};
+
+&qupv3_se15_i2c {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "disabled";
+	redriver: redriver@1c {
+		compatible = "onnn,redriver";
+		reg = <0x1c>;
+		extcon = <&pm8150b_pdphy>, <&pm8150b_pdphy>;
+		eq = /bits/ 8 <
+				/* Parameters for USB */
+				0x4 0x4 0x4 0x4
+				/* Parameters for DP */
+				0x6 0x4 0x4 0x6>;
+		flat-gain = /bits/ 8 <
+				/* Parameters for USB */
+				0x3 0x1 0x1 0x3
+				/* Parameters for DP */
+				0x2 0x1 0x1 0x2>;
+		output-comp = /bits/ 8 <
+				/* Parameters for USB */
+				0x3 0x3 0x3 0x3
+				/* Parameters for DP */
+				0x3 0x3 0x3 0x3>;
+		loss-match = /bits/ 8 <
+				/* Parameters for USB */
+				0x1 0x3 0x3 0x1
+				/* Parameters for DP */
+				0x3 0x3 0x3 0x3>;
+	};
+
+	#include "smb1390.dtsi"
+};
+
+&smb1390 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&smb_stat_default>;
+	status = "ok";
+};
+
+&smb1390_charger {
+	io-channels = <&pm8150b_vadc ADC_AMUX_THM2>;
+	io-channel-names = "cp_die_temp";
+	qcom,parallel-output-mode = <2>;
+	status = "ok";
+};
+
+&smb1390_slave {
+	status = "ok";
+};
+
+&smb1390_slave_charger {
+	status = "ok";
+};
+
+&pm8150b_charger {
+	status = "ok";
+	qcom,sec-charger-config = <1>;
+	qcom,auto-recharge-soc = <98>;
+	io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>,
+		      <&pm8150b_vadc ADC_USB_IN_I>,
+		      <&pm8150b_vadc ADC_SBUx>,
+		      <&pm8150b_vadc ADC_VPH_PWR>,
+		      <&pm8150b_vadc ADC_CHG_TEMP>;
+	io-channel-names = "mid_voltage",
+			   "usb_in_current",
+			   "sbux_res",
+			   "vph_voltage",
+			   "chg_temp";
+	qcom,battery-data = <&kona_arglass_batterydata>;
+	qcom,sw-jeita-enable;
+	qcom,wd-bark-time-secs = <16>;
+	qcom,suspend-input-on-debug-batt;
+	qcom,hvdcp-disable;
+	qcom,thermal-mitigation = <5325000 4500000 4000000 3500000 3000000
+				2500000 2000000 1500000 1000000 500000>;
+};
+
+&pm8150b_fg {
+	status = "ok";
+	qcom,battery-data = <&kona_arglass_batterydata>;
+	qcom,hold-soc-while-full;
+	qcom,linearize-soc;
+	qcom,five-pin-battery;
+	qcom,cl-wt-enable;
+	qcom,soc-scale-mode-en;
+	qcom,fg-force-load-profile;
+	/* ESR fast calibration */
+	qcom,fg-esr-timer-chg-fast = <0 7>;
+	qcom,fg-esr-timer-dischg-fast = <0 7>;
+	qcom,fg-esr-timer-chg-slow = <0 96>;
+	qcom,fg-esr-timer-dischg-slow = <0 96>;
+	qcom,fg-esr-cal-soc-thresh = <26 230>;
+	qcom,fg-esr-cal-temp-thresh = <10 40>;
+};
+
+&pm8150_vadc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	vph_pwr@83 {
+		reg = <ADC_VPH_PWR>;
+		label = "vph_pwr";
+		qcom,pre-scaling = <1 3>;
+	};
+
+	vcoin@85 {
+		reg = <ADC_VCOIN>;
+		label = "vcoin";
+		qcom,pre-scaling = <1 3>;
+	};
+
+	xo_therm@4c {
+		reg = <ADC_XO_THERM_PU2>;
+		label = "xo_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	skin_therm@4d {
+		reg = <ADC_AMUX_THM1_PU2>;
+		label = "skin_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pa_therm1@4e {
+		reg = <ADC_AMUX_THM2_PU2>;
+		label = "pa_therm1";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+};
+
+&pm8150l_vadc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	vph_pwr@83 {
+		reg = <ADC_VPH_PWR>;
+		label = "vph_pwr";
+		qcom,pre-scaling = <1 3>;
+	};
+
+	camera_flash_therm@4d {
+		reg = <ADC_AMUX_THM1_PU2>;
+		label = "camera_flash_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	skin_msm_therm@4e {
+		reg = <ADC_AMUX_THM2_PU2>;
+		label = "skin_msm_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pa_therm2@4f {
+		reg = <ADC_AMUX_THM3_PU2>;
+		label = "pa_therm2";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+};
+
+&pm8150b_adc_tm {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	io-channels = <&pm8150b_vadc ADC_AMUX_THM3_PU2>;
+
+	conn_therm@4f {
+		reg = <ADC_AMUX_THM3_PU2>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+};
+
+&pm8150_adc_tm {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	io-channels = <&pm8150_vadc ADC_XO_THERM_PU2>,
+			<&pm8150_vadc ADC_AMUX_THM1_PU2>,
+			<&pm8150_vadc ADC_AMUX_THM2_PU2>;
+
+	xo_therm@4c {
+		reg = <ADC_XO_THERM_PU2>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	skin_therm@4d {
+		reg = <ADC_AMUX_THM1_PU2>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	pa_therm1@4e {
+		reg = <ADC_AMUX_THM2_PU2>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+};
+
+&pm8150l_adc_tm {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	camera_flash_therm@4d {
+		reg = <ADC_AMUX_THM1_PU2>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	skin_msm_therm@4e {
+		reg = <ADC_AMUX_THM2_PU2>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	pa_therm2@4f {
+		reg = <ADC_AMUX_THM3_PU2>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+};
+
+&spmi_debug_bus {
+	status = "ok";
+};
+
+&sde_dsi {
+	/delete-property/ avdd-supply;
+	lab-supply = <&lcdb_ldo_vreg>;
+	ibb-supply = <&lcdb_ncp_vreg>;
+	qcom,dsi-default-panel = <&dsi_dual_arglass_seeya_video>;
+};
+
+&display_panel_avdd {
+	status = "disabled";
+};
+
+&pm8150l_lcdb {
+	status = "ok";
+};
+
+&pm8150l_wled {
+	status = "ok";
+};
+
+&dsi_dual_arglass_seeya_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-ctrl-dcs-subtype = <0xc2>;
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <1023>;
+	qcom,mdss-brightness-max-level = <1023>;
+	qcom,platform-reset-gpio = <&tlmm 75 0>;
+	qcom,platform-bklight-en-gpio = <&tlmm 46 0>;
+	qcom,5v-boost-gpio = <&tlmm 61 0>;
+	/delete-property/ qcom,platform-en-gpio;
+};
+
+&dsi_sw43404_amoled_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <1023>;
+	qcom,mdss-brightness-max-level = <255>;
+	qcom,platform-te-gpio = <&tlmm 66 0>;
+	qcom,platform-reset-gpio = <&tlmm 75 0>;
+	qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sw43404_amoled_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <1023>;
+	qcom,mdss-brightness-max-level = <255>;
+	qcom,platform-reset-gpio = <&tlmm 75 0>;
+	qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <1023>;
+	qcom,mdss-brightness-max-level = <255>;
+	qcom,platform-te-gpio = <&tlmm 66 0>;
+	qcom,platform-reset-gpio = <&tlmm 75 0>;
+	qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sim_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_vid {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_375_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_10b_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_vid {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+	qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&thermal_zones {
+	conn-therm-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM3_PU2>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	xo-therm-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	skin-therm-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	mmw-pa1-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	camera-therm-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	skin-msm-therm-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	mmw-pa2-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+};
+
+&sdhc_2 {
+	vdd-supply = <&pm8150a_l9>;
+	qcom,vdd-voltage-level = <2950000 2960000>;
+	qcom,vdd-current-level = <200 800000>;
+
+	vdd-io-supply = <&pm8150a_l6>;
+	qcom,vdd-io-voltage-level = <1808000 2960000>;
+	qcom,vdd-io-current-level = <200 22000>;
+
+	pinctrl-names = "active", "sleep";
+	pinctrl-0 = <&sdc2_clk_on  &sdc2_cmd_on &sdc2_data_on &storage_cd>;
+	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>;
+
+	cd-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>; /* Morpheus has to be HIGH */
+
+	status = "disabled";
+};
+
+&vendor {
+	bluetooth: bt_qca6390 {
+		compatible = "qca,qca6390";
+		pinctrl-names = "default";
+		pinctrl-0 = <&bt_en_sleep>;
+		qca,bt-reset-gpio = <&tlmm 21 0>; /* BT_EN */
+		qca,bt-sw-ctrl-gpio = <&tlmm 124 0>; /* SW_CTRL */
+		qca,bt-vdd-aon-supply = <&pm8150_s6>;
+		qca,bt-vdd-dig-supply = <&pm8150_s6>;
+		qca,bt-vdd-rfa1-supply = <&pm8150_s5>;
+		qca,bt-vdd-rfa2-supply = <&pm8150a_s8>;
+		qca,bt-vdd-asd-supply = <&pm8150_l16>;
+
+		qca,bt-vdd-aon-voltage-level = <950000 950000>;
+		qca,bt-vdd-dig-voltage-level = <950000 952000>;
+		qca,bt-vdd-rfa1-voltage-level = <1900000 1900000>;
+		qca,bt-vdd-rfa2-voltage-level = <1350000 1350000>;
+		qca,bt-vdd-asd-voltage-level = <3024000 3304000>;
+
+		qca,bt-vdd-asd-current-level = <10000>;
+	};
+};
+
+&usb0 {
+	dwc3@a600000 {
+		maximum-speed = "super-speed-plus";
+	};
+};
+
+&usb1 {
+	qcom,default-mode-none;
+};
+
+&wil6210 {
+	status = "disabled";
+};
+
+&usb2_phy0 {
+	qcom,param-override-seq =
+		<0xc7 0x6c
+		0x0f 0x70
+		0x03 0x74>;
+};
+
+&mdss_mdp {
+	qcom,sde-mixer-display-pref = "primary", "primary", "primary",
+					"primary", "none", "none";
+};
+
+&kona_snd {
+	qcom,model = "kona-arglass-snd-card";
+	qcom,mi2s-audio-intf = <0>;
+	qcom,audio-routing =
+		"TX DMIC0", "Digital Mic0",
+		"TX DMIC1", "Digital Mic1",
+		"TX DMIC2", "Digital Mic2",
+		"TX DMIC3", "Digital Mic3",
+		"TX DMIC4", "Digital Mic4",
+		"IN1_HPHL", "HPHL_OUT",
+		"IN2_HPHR", "HPHR_OUT",
+		"IN3_AUX", "AUX_OUT",
+		"TX SWR_ADC0", "ADC1_OUTPUT",
+		"TX SWR_ADC1", "ADC2_OUTPUT",
+		"TX SWR_ADC2", "ADC3_OUTPUT",
+		"TX SWR_ADC3", "ADC4_OUTPUT",
+		"TX SWR_DMIC0", "DMIC1_OUTPUT",
+		"TX SWR_DMIC1", "DMIC2_OUTPUT",
+		"TX SWR_DMIC2", "DMIC3_OUTPUT",
+		"TX SWR_DMIC3", "DMIC4_OUTPUT",
+		"TX SWR_DMIC4", "DMIC5_OUTPUT",
+		"TX SWR_DMIC5", "DMIC6_OUTPUT",
+		"TX SWR_DMIC6", "DMIC7_OUTPUT",
+		"TX SWR_DMIC7", "DMIC8_OUTPUT",
+		"WSA SRC0_INP", "SRC0",
+		"WSA_TX DEC0_INP", "TX DEC0 MUX",
+		"WSA_TX DEC1_INP", "TX DEC1 MUX",
+		"RX_TX DEC0_INP", "TX DEC0 MUX",
+		"RX_TX DEC1_INP", "TX DEC1 MUX",
+		"RX_TX DEC2_INP", "TX DEC2 MUX",
+		"RX_TX DEC3_INP", "TX DEC3 MUX",
+		"SpkrRight IN", "WSA_SPK2 OUT",
+		"VA_AIF1 CAP", "VA_SWR_CLK",
+		"VA_AIF2 CAP", "VA_SWR_CLK",
+		"VA_AIF3 CAP", "VA_SWR_CLK",
+		"VA DMIC0", "Digital Mic0",
+		"VA DMIC1", "Digital Mic1",
+		"VA DMIC2", "Digital Mic2",
+		"VA DMIC3", "Digital Mic3",
+		"VA DMIC4", "Digital Mic4",
+		"VA SWR_ADC1", "VA_SWR_CLK",
+		"VA SWR_MIC0", "VA_SWR_CLK",
+		"VA SWR_MIC1", "VA_SWR_CLK",
+		"VA SWR_MIC2", "VA_SWR_CLK",
+		"VA SWR_MIC3", "VA_SWR_CLK",
+		"VA SWR_MIC4", "VA_SWR_CLK",
+		"VA SWR_MIC5", "VA_SWR_CLK",
+		"VA SWR_MIC6", "VA_SWR_CLK",
+		"VA SWR_MIC7", "VA_SWR_CLK",
+		"VA SWR_MIC0", "DMIC1_OUTPUT",
+		"VA SWR_MIC1", "DMIC2_OUTPUT",
+		"VA SWR_MIC2", "DMIC3_OUTPUT",
+		"VA SWR_MIC3", "DMIC4_OUTPUT",
+		"VA SWR_MIC4", "DMIC5_OUTPUT",
+		"VA SWR_MIC5", "DMIC6_OUTPUT",
+		"VA SWR_MIC6", "DMIC7_OUTPUT",
+		"VA SWR_MIC7", "DMIC8_OUTPUT",
+		"VA SWR_ADC1", "ADC2_OUTPUT";
+	qcom,msm-mbhc-hphl-swh = <0>;
+	qcom,msm-mbhc-gnd-swh = <0>;
+	qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
+	qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
+	qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
+	asoc-codec  = <&stub_codec>, <&bolero>, <&ext_disp_audio_codec>;
+	asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
+		"msm-ext-disp-audio-codec-rx";
+	qcom,wsa-max-devs = <2>;
+	qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>,
+		<&wsa881x_0213>, <&wsa881x_0214>;
+	qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
+		"SpkrLeft", "SpkrRight";
+	qcom,codec-max-aux-devs = <0>;
+	/delete-property/ qcom,codec-aux-devs;
+	qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>,
+		<&bolero>;
+};
+
+&wcd938x_tx_slave {
+	status = "disabled";
+};
+
+&wcd938x_rx_slave {
+	status = "disabled";
+};
+
+&wcd938x_codec {
+	status = "disabled";
+};
+
+&kona_snd_ar {
+	qcom,model = "kona-arglass-snd-card";
+	qcom,mi2s-audio-intf = <0>;
+	qcom,audio-routing =
+		"TX DMIC0", "Digital Mic0",
+		"TX DMIC1", "Digital Mic1",
+		"TX DMIC2", "Digital Mic2",
+		"TX DMIC3", "Digital Mic3",
+		"TX DMIC4", "Digital Mic4",
+		"IN1_HPHL", "HPHL_OUT",
+		"IN2_HPHR", "HPHR_OUT",
+		"IN3_AUX", "AUX_OUT",
+		"TX SWR_ADC0", "ADC1_OUTPUT",
+		"TX SWR_ADC1", "ADC2_OUTPUT",
+		"TX SWR_ADC2", "ADC3_OUTPUT",
+		"TX SWR_ADC3", "ADC4_OUTPUT",
+		"TX SWR_DMIC0", "DMIC1_OUTPUT",
+		"TX SWR_DMIC1", "DMIC2_OUTPUT",
+		"TX SWR_DMIC2", "DMIC3_OUTPUT",
+		"TX SWR_DMIC3", "DMIC4_OUTPUT",
+		"TX SWR_DMIC4", "DMIC5_OUTPUT",
+		"TX SWR_DMIC5", "DMIC6_OUTPUT",
+		"TX SWR_DMIC6", "DMIC7_OUTPUT",
+		"TX SWR_DMIC7", "DMIC8_OUTPUT",
+		"WSA SRC0_INP", "SRC0",
+		"WSA_TX DEC0_INP", "TX DEC0 MUX",
+		"WSA_TX DEC1_INP", "TX DEC1 MUX",
+		"RX_TX DEC0_INP", "TX DEC0 MUX",
+		"RX_TX DEC1_INP", "TX DEC1 MUX",
+		"RX_TX DEC2_INP", "TX DEC2 MUX",
+		"RX_TX DEC3_INP", "TX DEC3 MUX",
+		"SpkrRight IN", "WSA_SPK2 OUT",
+		"VA_AIF1 CAP", "VA_SWR_CLK",
+		"VA_AIF2 CAP", "VA_SWR_CLK",
+		"VA_AIF3 CAP", "VA_SWR_CLK",
+		"VA DMIC0", "Digital Mic0",
+		"VA DMIC1", "Digital Mic1",
+		"VA DMIC2", "Digital Mic2",
+		"VA DMIC3", "Digital Mic3",
+		"VA DMIC4", "Digital Mic4",
+		"VA SWR_ADC1", "VA_SWR_CLK",
+		"VA SWR_MIC0", "VA_SWR_CLK",
+		"VA SWR_MIC1", "VA_SWR_CLK",
+		"VA SWR_MIC2", "VA_SWR_CLK",
+		"VA SWR_MIC3", "VA_SWR_CLK",
+		"VA SWR_MIC4", "VA_SWR_CLK",
+		"VA SWR_MIC5", "VA_SWR_CLK",
+		"VA SWR_MIC6", "VA_SWR_CLK",
+		"VA SWR_MIC7", "VA_SWR_CLK",
+		"VA SWR_MIC0", "DMIC1_OUTPUT",
+		"VA SWR_MIC1", "DMIC2_OUTPUT",
+		"VA SWR_MIC2", "DMIC3_OUTPUT",
+		"VA SWR_MIC3", "DMIC4_OUTPUT",
+		"VA SWR_MIC4", "DMIC5_OUTPUT",
+		"VA SWR_MIC5", "DMIC6_OUTPUT",
+		"VA SWR_MIC6", "DMIC7_OUTPUT",
+		"VA SWR_MIC7", "DMIC8_OUTPUT",
+		"VA SWR_ADC1", "ADC2_OUTPUT";
+	qcom,msm-mbhc-hphl-swh = <0>;
+	qcom,msm-mbhc-gnd-swh = <0>;
+	qcom,codec-max-aux-devs = <0>;
+	/delete-property/ qcom,codec-aux-devs;
+};
+
+&wcd938x_tx_slave_ar {
+	status = "disabled";
+};
+
+&wcd938x_rx_slave_ar {
+	status = "disabled";
+};
+
+&wcd938x_codec_ar {
+	status = "disabled";
+};
+
+&pm8150a_l4 {
+	qcom,init-voltage = <2800000>;
+};
+
+&pm8150a_l3 {
+	qcom,init-voltage = <1200000>;
+};
+
+&pm8150a_l9 {
+	qcom,init-voltage = <2800000>;
+};
+
+&sde_dp {
+	status="disabled";
+};
+
+&mdss_mdp {
+	connectors = <&sde_wb &sde_dsi &sde_dsi1 &sde_rscc>;
+};
+
+&wlan {
+	vdd-wlan-dig-supply = <&pm8150_s6>;
+	qcom,vdd-wlan-dig-config = <950000 950000 0 0 1>;
+	qcom,cmd_db_name = "smpa6";
+};
+
+&flash_led {
+	qcom,hw-strobe-option = <0>;
+	qcom,strobe-sel = <1>;
+	qcom,ramp-up-step = <200>;
+	qcom,ramp-down-step = <200>;
+	status = "okay";
+};
+
+&pm8150l_flash0 {
+	qcom,strobe-sel = <1>;
+	status = "okay";
+};
+
+&pm8150l_flash1 {
+	qcom,strobe-sel = <1>;
+	status = "okay";
+};
+
+&pm8150l_flash2 {
+	qcom,strobe-sel = <1>;
+	status = "okay";
+};
+
+&pm8150l_torch0 {
+	qcom,strobe-sel = <1>;
+	status = "okay";
+};
+
+&pm8150l_torch1 {
+	qcom,strobe-sel = <1>;
+	status = "okay";
+};
+
+&pm8150l_torch2 {
+	qcom,strobe-sel = <1>;
+	status = "okay";
+};
+
+&pm8150b_pdphy {
+	/* Restricting only to 5V@3A */
+	qcom,default-sink-caps = <5000 3000>; /* 5V @ 3A */
+};
+
diff --git a/qcom/kona-audio-ar.dtsi b/qcom/kona-audio-ar.dtsi
new file mode 100644
index 00000000..edefccc3
--- /dev/null
+++ b/qcom/kona-audio-ar.dtsi
@@ -0,0 +1,109 @@
+#include <dt-bindings/sound/qcom,gpr.h>
+
+&glink_adsp {
+	audio_gpr: qcom,gpr {
+		compatible = "qcom,gpr";
+		qcom,glink-channels = "adsp_apps";
+		qcom,intents = <0x200 20>;
+		reg = <GPR_DOMAIN_ADSP>;
+		spf_core {
+			compatible = "qcom,spf_core";
+			reg = <GPR_SVC_ADSP_CORE>;
+		};
+
+		audio-pkt {
+			compatible = "qcom,audio-pkt";
+			qcom,audiopkt-ch-name = "apr_audio_svc";
+			reg = <GPR_SVC_MAX>;
+		};
+
+		audio_prm: q6prm {
+			compatible = "qcom,audio_prm";
+			reg = <GPR_SVC_ASM>;
+		};
+
+		voice-mhi {
+			compatible = "qcom,voice_mhi_gpr";
+			reg = <GPR_SVC_VPM>;
+		};
+	};
+};
+
+&soc {
+	spf_core_platform: spf_core_platform {
+		compatible = "qcom,spf-core-platform";
+	};
+
+	audio_pkt_core_platform: qcom,audio-pkt-core-platform {
+		compatible = "qcom,audio-pkt-core-platform";
+	};
+};
+
+&spf_core_platform {
+	msm_audio_ion_ar: qcom,msm-audio-ion-ar {
+		compatible = "qcom,msm-audio-ion";
+		qcom,smmu-version = <2>;
+		qcom,smmu-enabled;
+		iommus = <&apps_smmu 0x1801 0x0>;
+		qcom,iommu-dma-addr-pool = <0x10000000 0x10000000>;
+		qcom,smmu-sid-mask = /bits/ 64 <0xf>;
+	};
+
+	lpass_core_hw_vote_ar: vote_lpass_core_hw_ar {
+		compatible = "qcom,audio-ref-clk";
+		qcom,codec-ext-clk-src = <AUDIO_LPASS_CORE_HW_VOTE>;
+		#clock-cells = <1>;
+	};
+
+	lpass_audio_hw_vote_ar: vote_lpass_audio_hw_ar {
+		compatible = "qcom,audio-ref-clk";
+		qcom,codec-ext-clk-src = <AUDIO_LPASS_AUDIO_HW_VOTE>;
+		#clock-cells = <1>;
+	};
+
+	bolero_ar: bolero-cdc-ar {
+		compatible = "qcom,bolero-codec";
+		clock-names = "lpass_core_hw_vote",
+				"lpass_audio_hw_vote";
+		clocks = <&lpass_core_hw_vote_ar 0>,
+				<&lpass_audio_hw_vote_ar 0>;
+		bolero-clk-rsc-mngr-ar {
+			compatible = "qcom,bolero-clk-rsc-mngr";
+		};
+
+		tx_macro_ar: tx-macro-ar@3220000 {
+			swr_ar2: tx_swr_master_ar {
+			};
+		};
+
+		rx_macro_ar: rx-macro-ar@3200000 {
+			swr_ar1: rx_swr_master_ar {
+			};
+		};
+
+		wsa_macro_ar: wsa-macro-ar@3240000 {
+			swr_ar0: wsa_swr_master_ar {
+			};
+		};
+	};
+
+	voice_mhi_audio_ar: qcom,voice-mhi-audio-ar {
+		compatible = "qcom,voice-mhi-audio";
+		memory-region = <&mailbox_mem>;
+		voice_mhi_voting;
+	};
+
+	kona_snd_ar: sound_ar {
+		compatible = "qcom,kona-asoc-snd";
+		qcom,mi2s-audio-intf = <1>;
+		qcom,auxpcm-audio-intf = <1>;
+		qcom,tdm-audio-intf = <1>;
+		qcom,wcn-bt = <0>;
+		qcom,ext-disp-audio-rx = <0>;
+		qcom,afe-rxtx-lb = <0>;
+
+		clock-names = "lpass_audio_hw_vote";
+		clocks = <&lpass_audio_hw_vote_ar 0>;
+		fsa4480-i2c-handle = <&fsa4480>;
+	};
+};
diff --git a/qcom/kona-audio-overlay-ar.dtsi b/qcom/kona-audio-overlay-ar.dtsi
new file mode 100644
index 00000000..8cc61d5d
--- /dev/null
+++ b/qcom/kona-audio-overlay-ar.dtsi
@@ -0,0 +1,382 @@
+#include "kona-lpi-ar.dtsi"
+#include "kona-va-bolero-ar.dtsi"
+
+&bolero_ar {
+	qcom,num-macros = <4>;
+	bolero-clk-rsc-mngr-ar {
+		compatible = "qcom,bolero-clk-rsc-mngr";
+		qcom,fs-gen-sequence = <0x3000 0x1>,
+					<0x3004 0x1>, <0x3080 0x2>;
+	qcom,rx_mclk_mode_muxsel = <0x033240D8>;
+	qcom,wsa_mclk_mode_muxsel = <0x033220D8>;
+	qcom,va_mclk_mode_muxsel = <0x033A0000>;
+	clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk",
+		 "wsa_core_clk", "wsa_npl_clk", "va_core_clk", "va_npl_clk";
+	clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
+		<&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
+		<&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>,
+		<&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
+	};
+
+	tx_macro_ar: tx-macro-ar@3220000 {
+		compatible = "qcom,tx-macro";
+		reg = <0x3220000 0x0>;
+		clock-names = "tx_core_clk", "tx_npl_clk";
+		clocks = <&clock_audio_tx_1 0>,
+			 <&clock_audio_tx_2 0>;
+		qcom,tx-swr-gpios = <&tx_swr_gpios_ar>;
+		qcom,tx-dmic-sample-rate = <2400000>;
+		swr_ar2: tx_swr_master_ar {
+			compatible = "qcom,swr-mstr";
+			#address-cells = <2>;
+			#size-cells = <0>;
+			clock-names = "lpass_core_hw_vote",
+					"lpass_audio_hw_vote";
+			clocks = <&lpass_core_hw_vote_ar 0>,
+					<&lpass_audio_hw_vote_ar 0>;
+			qcom,swr-master-version = <0x01050001>;
+			qcom,swr_master_id = <3>;
+			qcom,mipi-sdw-block-packing-mode = <1>;
+			swrm-io-base = <0x3230000 0x0>;
+			interrupts-extended =
+				<&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+				<&pdc 109 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "swr_master_irq", "swr_wake_irq";
+			qcom,swr-wakeup-required = <1>;
+			qcom,swr-num-ports = <5>;
+			qcom,swr-port-mapping = <1 PCM_OUT1 0xF>,
+				<2 ADC1 0x1>, <2 ADC2 0x2>,
+				<3 ADC3 0x1>, <3 ADC4 0x2>,
+				<4 DMIC0 0x1>, <4 DMIC1 0x2>,
+				<4 DMIC2 0x4>, <4 DMIC3 0x8>,
+				<5 DMIC4 0x1>, <5 DMIC5 0x2>,
+				<5 DMIC6 0x4>, <5 DMIC7 0x8>;
+			qcom,swr-num-dev = <1>;
+			qcom,swr-clock-stop-mode0 = <1>;
+			qcom,swr-mstr-irq-wakeup-capable = <1>;
+			wcd938x_tx_slave_ar: wcd938x-tx-slave_ar {
+				compatible = "qcom,wcd938x-slave";
+				reg = <0x0D 0x01170223>;
+			};
+		};
+	};
+
+	rx_macro_ar: rx-macro-ar@3200000 {
+		compatible = "qcom,rx-macro";
+		reg = <0x3200000 0x0>;
+		clock-names = "rx_core_clk", "rx_npl_clk";
+		clocks = <&clock_audio_rx_1 0>,
+			 <&clock_audio_rx_2 0>;
+		qcom,rx-swr-gpios = <&rx_swr_gpios_ar>;
+		qcom,rx_mclk_mode_muxsel = <0x033240D8>;
+		qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
+		qcom,default-clk-id = <TX_CORE_CLK>;
+		swr_ar1: rx_swr_master_ar {
+			compatible = "qcom,swr-mstr";
+			#address-cells = <2>;
+			#size-cells = <0>;
+			clock-names = "lpass_core_hw_vote",
+					"lpass_audio_hw_vote";
+			clocks = <&lpass_core_hw_vote_ar 0>,
+					<&lpass_audio_hw_vote_ar 0>;
+			qcom,swr-master-version = <0x01050001>;
+			qcom,swr_master_id = <2>;
+			qcom,mipi-sdw-block-packing-mode = <1>;
+			swrm-io-base = <0x3210000 0x0>;
+			interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "swr_master_irq";
+			qcom,swr-num-ports = <5>;
+			qcom,disable-div2-clk-switch = <1>;
+			qcom,swr-port-mapping = <1 HPH_L 0x1>,
+				<1 HPH_R 0x2>, <2 CLSH 0x1>,
+				<3 COMP_L 0x1>, <3 COMP_R 0x2>,
+				<4 LO 0x1>, <5 DSD_L 0x1>,
+				<5 DSD_R 0x2>;
+			qcom,swr-num-dev = <1>;
+			qcom,swr-clock-stop-mode0 = <1>;
+			wcd938x_rx_slave_ar: wcd938x-rx-slave-ar {
+				compatible = "qcom,wcd938x-slave";
+				reg = <0x0D 0x01170224>;
+			};
+		};
+	};
+
+	wsa_macro_ar: wsa-macro-ar@3240000 {
+		compatible = "qcom,wsa-macro";
+		reg = <0x3240000 0x0>;
+		clock-names = "wsa_core_clk", "wsa_npl_clk";
+		clocks = <&clock_audio_wsa_1 0>,
+			 <&clock_audio_wsa_2 0>;
+		qcom,wsa-swr-gpios = <&wsa_swr_gpios_ar>;
+		qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
+		qcom,default-clk-id = <TX_CORE_CLK>;
+		swr_ar0: wsa_swr_master_ar {
+			compatible = "qcom,swr-mstr";
+			#address-cells = <2>;
+			#size-cells = <0>;
+			clock-names = "lpass_core_hw_vote",
+					"lpass_audio_hw_vote";
+			clocks = <&lpass_core_hw_vote_ar 0>,
+					<&lpass_audio_hw_vote_ar 0>;
+			qcom,swr-master-version = <0x01050001>;
+			qcom,swr_master_id = <1>;
+			qcom,mipi-sdw-block-packing-mode = <0>;
+			swrm-io-base = <0x3250000 0x0>;
+			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "swr_master_irq";
+			qcom,swr-num-ports = <8>;
+			qcom,swr-port-mapping = <1 SPKR_L 0x1>,
+				<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
+				<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
+				<6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,
+				<8 SPKR_R_VI 0x3>;
+			qcom,swr-num-dev = <2>;
+			wsa881x_0211_ar: wsa881x_ar@20170211 {
+				compatible = "qcom,wsa881x";
+				reg = <0x10 0x20170211>;
+				qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
+				qcom,bolero-handle = <&bolero_ar>;
+			};
+
+			wsa881x_0212_ar: wsa881x_ar@20170212 {
+				compatible = "qcom,wsa881x";
+				reg = <0x10 0x20170212>;
+				qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+				qcom,bolero-handle = <&bolero_ar>;
+			};
+
+			wsa881x_0213_ar: wsa881x_ar@21170213 {
+				compatible = "qcom,wsa881x";
+				reg = <0x10 0x21170213>;
+				qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
+				qcom,bolero-handle = <&bolero_ar>;
+			};
+
+			wsa881x_0214_ar: wsa881x_ar@21170214 {
+				compatible = "qcom,wsa881x";
+				reg = <0x10 0x21170214>;
+				qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+				qcom,bolero-handle = <&bolero_ar>;
+			};
+		};
+
+	};
+
+	wcd938x_codec_ar: wcd938x-codec-ar {
+		compatible = "qcom,wcd938x-codec";
+		qcom,split-codec = <1>;
+		qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
+			<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
+			<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
+			<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
+			<4 DSD_R 0x2 0 DSD_R>;
+		qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
+			<0 ADC2 0x2 0 ADC2>, <1 ADC3 0x1 0 ADC3>,
+			<1 ADC4 0x2 0 ADC4>, <2 DMIC0 0x1 0 DMIC0>,
+			<2 DMIC1 0x2 0 DMIC1>, <2 MBHC 0x4 0 DMIC2>,
+			<2 DMIC2 0x4 0 DMIC2>, <2 DMIC3 0x8 0 DMIC3>,
+			<3 DMIC4 0x1 0 DMIC4>, <3 DMIC5 0x2 0 DMIC5>,
+			<3 DMIC6 0x4 0 DMIC6>, <3 DMIC7 0x8 0 DMIC7>;
+
+		qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>;
+		qcom,rx-slave = <&wcd938x_rx_slave_ar>;
+		qcom,tx-slave = <&wcd938x_tx_slave_ar>;
+
+		cdc-vdd-rxtx-supply = <&S4A>;
+		qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
+		qcom,cdc-vdd-rxtx-current = <30000>;
+
+		cdc-vddio-supply = <&S4A>;
+		qcom,cdc-vddio-voltage = <1800000 1800000>;
+		qcom,cdc-vddio-current = <30000>;
+
+		cdc-vdd-buck-supply = <&S4A>;
+		qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
+		qcom,cdc-vdd-buck-current = <650000>;
+
+		cdc-vdd-mic-bias-supply = <&BOB>;
+		qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
+		qcom,cdc-vdd-mic-bias-current = <30000>;
+
+		qcom,cdc-micbias1-mv = <1800>;
+		qcom,cdc-micbias2-mv = <1800>;
+		qcom,cdc-micbias3-mv = <1800>;
+		qcom,cdc-micbias4-mv = <1800>;
+
+		qcom,cdc-static-supplies = "cdc-vdd-rxtx",
+					   "cdc-vddio",
+					   "cdc-vdd-buck",
+					   "cdc-vdd-mic-bias";
+	};
+
+};
+
+&kona_snd_ar {
+	qcom,model = "kona-mtp-snd-card";
+	qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>;
+	qcom,mi2s-tdm-is-hw-vote-needed = <1>, <0>, <1>, <0>, <0>, <0>;
+	qcom,wcn-bt = <0>;
+	qcom,ext-disp-audio-rx = <1>;
+	qcom,tdm-max-slots = <8>;
+	qcom,tdm-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
+	qcom,mi2s-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
+	qcom,audio-routing =
+		"AMIC1", "MIC BIAS1",
+		"MIC BIAS1", "Analog Mic1",
+		"AMIC2", "MIC BIAS2",
+		"MIC BIAS2", "Analog Mic2",
+		"AMIC3", "MIC BIAS3",
+		"MIC BIAS3", "Analog Mic3",
+		"AMIC4", "MIC BIAS3",
+		"MIC BIAS3", "Analog Mic4",
+		"AMIC5", "MIC BIAS4",
+		"MIC BIAS4", "Analog Mic5",
+		"TX DMIC0", "MIC BIAS3",
+		"MIC BIAS3", "Digital Mic0",
+		"TX DMIC1", "MIC BIAS3",
+		"MIC BIAS3", "Digital Mic1",
+		"TX DMIC2", "MIC BIAS1",
+		"MIC BIAS1", "Digital Mic2",
+		"TX DMIC3", "MIC BIAS1",
+		"MIC BIAS1", "Digital Mic3",
+		"TX DMIC4", "MIC BIAS4",
+		"MIC BIAS4", "Digital Mic4",
+		"TX DMIC5", "MIC BIAS4",
+		"MIC BIAS4", "Digital Mic5",
+		"IN1_HPHL", "HPHL_OUT",
+		"IN2_HPHR", "HPHR_OUT",
+		"IN3_AUX", "AUX_OUT",
+		"TX SWR_ADC0", "ADC1_OUTPUT",
+		"TX SWR_ADC1", "ADC2_OUTPUT",
+		"TX SWR_ADC2", "ADC3_OUTPUT",
+		"TX SWR_ADC3", "ADC4_OUTPUT",
+		"TX SWR_DMIC0", "DMIC1_OUTPUT",
+		"TX SWR_DMIC1", "DMIC2_OUTPUT",
+		"TX SWR_DMIC2", "DMIC3_OUTPUT",
+		"TX SWR_DMIC3", "DMIC4_OUTPUT",
+		"TX SWR_DMIC4", "DMIC5_OUTPUT",
+		"TX SWR_DMIC5", "DMIC6_OUTPUT",
+		"TX SWR_DMIC6", "DMIC7_OUTPUT",
+		"TX SWR_DMIC7", "DMIC8_OUTPUT",
+		"WSA SRC0_INP", "SRC0",
+		"WSA_TX DEC0_INP", "TX DEC0 MUX",
+		"WSA_TX DEC1_INP", "TX DEC1 MUX",
+		"RX_TX DEC0_INP", "TX DEC0 MUX",
+		"RX_TX DEC1_INP", "TX DEC1 MUX",
+		"RX_TX DEC2_INP", "TX DEC2 MUX",
+		"RX_TX DEC3_INP", "TX DEC3 MUX",
+		"SpkrLeft IN", "WSA_SPK1 OUT",
+		"SpkrRight IN", "WSA_SPK2 OUT",
+		"VA_AIF1 CAP", "VA_SWR_CLK",
+		"VA_AIF2 CAP", "VA_SWR_CLK",
+		"VA_AIF3 CAP", "VA_SWR_CLK",
+		"VA MIC BIAS3", "Digital Mic0",
+		"VA MIC BIAS3", "Digital Mic1",
+		"VA MIC BIAS1", "Digital Mic2",
+		"VA MIC BIAS1", "Digital Mic3",
+		"VA MIC BIAS4", "Digital Mic4",
+		"VA MIC BIAS4", "Digital Mic5",
+		"VA DMIC0", "VA MIC BIAS3",
+		"VA DMIC1", "VA MIC BIAS3",
+		"VA DMIC2", "VA MIC BIAS1",
+		"VA DMIC3", "VA MIC BIAS1",
+		"VA DMIC4", "VA MIC BIAS4",
+		"VA DMIC5", "VA MIC BIAS4",
+		"VA SWR_ADC0", "VA_SWR_CLK",
+		"VA SWR_ADC1", "VA_SWR_CLK",
+		"VA SWR_ADC2", "VA_SWR_CLK",
+		"VA SWR_ADC3", "VA_SWR_CLK",
+		"VA SWR_MIC0", "VA_SWR_CLK",
+		"VA SWR_MIC1", "VA_SWR_CLK",
+		"VA SWR_MIC2", "VA_SWR_CLK",
+		"VA SWR_MIC3", "VA_SWR_CLK",
+		"VA SWR_MIC4", "VA_SWR_CLK",
+		"VA SWR_MIC5", "VA_SWR_CLK",
+		"VA SWR_MIC6", "VA_SWR_CLK",
+		"VA SWR_MIC7", "VA_SWR_CLK",
+		"VA SWR_ADC0", "ADC1_OUTPUT",
+		"VA SWR_ADC1", "ADC2_OUTPUT",
+		"VA SWR_ADC2", "ADC3_OUTPUT",
+		"VA SWR_ADC3", "ADC4_OUTPUT",
+		"VA SWR_MIC0", "DMIC1_OUTPUT",
+		"VA SWR_MIC1", "DMIC2_OUTPUT",
+		"VA SWR_MIC2", "DMIC3_OUTPUT",
+		"VA SWR_MIC3", "DMIC4_OUTPUT",
+		"VA SWR_MIC4", "DMIC5_OUTPUT",
+		"VA SWR_MIC5", "DMIC6_OUTPUT",
+		"VA SWR_MIC6", "DMIC7_OUTPUT",
+		"VA SWR_MIC7", "DMIC8_OUTPUT";
+	qcom,msm-mbhc-hphl-swh = <1>;
+	qcom,msm-mbhc-gnd-swh = <1>;
+	qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios_ar>;
+	qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios_ar>;
+	qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios_ar>;
+	asoc-codec  = <&stub_codec>, <&bolero_ar>, <&ext_disp_audio_codec>;
+	asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
+			   "msm-ext-disp-audio-codec-rx";
+	qcom,wsa-max-devs = <2>;
+	qcom,wsa-devs = <&wsa881x_0211_ar>, <&wsa881x_0212_ar>,
+			<&wsa881x_0213_ar>, <&wsa881x_0214_ar>;
+	qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
+				  "SpkrLeft", "SpkrRight";
+	qcom,codec-max-aux-devs = <1>;
+	qcom,codec-aux-devs = <&wcd938x_codec_ar>;
+	qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm_ar>,
+				  <&bolero_ar>;
+};
+
+&spf_core_platform {
+	cdc_dmic01_gpios_ar: cdc_dmic01_pinctrl_ar {
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&cdc_dmic01_clk_active_ar &cdc_dmic01_data_active_ar>;
+		pinctrl-1 = <&cdc_dmic01_clk_sleep_ar &cdc_dmic01_data_sleep_ar>;
+		qcom,lpi-gpios;
+	};
+
+	cdc_dmic23_gpios_ar: cdc_dmic23_pinctrl_ar {
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&cdc_dmic23_clk_active_ar &cdc_dmic23_data_active_ar>;
+		pinctrl-1 = <&cdc_dmic23_clk_sleep_ar &cdc_dmic23_data_sleep_ar>;
+		qcom,lpi-gpios;
+	};
+
+	cdc_dmic45_gpios_ar: cdc_dmic45_pinctrl_ar {
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&cdc_dmic45_clk_active_ar &cdc_dmic45_data_active_ar>;
+		pinctrl-1 = <&cdc_dmic45_clk_sleep_ar &cdc_dmic45_data_sleep_ar>;
+		qcom,lpi-gpios;
+		qcom,tlmm-gpio = <158>;
+	};
+
+	wsa_swr_gpios_ar: wsa_swr_clk_data_pinctrl_ar {
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&wsa_swr_clk_active_ar &wsa_swr_data_active_ar>;
+		pinctrl-1 = <&wsa_swr_clk_sleep_ar &wsa_swr_data_sleep_ar>;
+		qcom,lpi-gpios;
+	};
+
+	rx_swr_gpios_ar: rx_swr_clk_data_pinctrl_ar {
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&rx_swr_clk_active_ar &rx_swr_data_active_ar
+				&rx_swr_data1_active_ar>;
+		pinctrl-1 = <&rx_swr_clk_sleep_ar &rx_swr_data_sleep_ar
+				&rx_swr_data1_sleep_ar>;
+		qcom,lpi-gpios;
+	};
+
+	tx_swr_gpios_ar: tx_swr_clk_data_pinctrl_ar {
+		compatible = "qcom,msm-cdc-pinctrl";
+		pinctrl-names = "aud_active", "aud_sleep";
+		pinctrl-0 = <&tx_swr_clk_active_ar &tx_swr_data1_active_ar
+			    &tx_swr_data2_active_ar>;
+		pinctrl-1 = <&tx_swr_clk_sleep_ar &tx_swr_data1_sleep_ar
+			    &tx_swr_data2_sleep_ar>;
+		qcom,lpi-gpios;
+		qcom,tlmm-gpio = <147>;
+	};
+};
diff --git a/qcom/kona-cdp-lcd-tron-overlay.dts b/qcom/kona-cdp-lcd-tron-overlay.dts
new file mode 100644
index 00000000..efee808e
--- /dev/null
+++ b/qcom/kona-cdp-lcd-tron-overlay.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+#include "kona-cdp-lcd.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. kona CDP (LCD) tron";
+	compatible = "qcom,kona-cdp", "qcom,kona", "qcom,cdp";
+	qcom,board-id = <0x01020001 0>;
+};
+
+&mdm0 {
+	status = "disabled";
+};
diff --git a/qcom/kona-cdp-lcd-tron.dts b/qcom/kona-cdp-lcd-tron.dts
new file mode 100644
index 00000000..b367423c
--- /dev/null
+++ b/qcom/kona-cdp-lcd-tron.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+
+#include "kona.dtsi"
+#include "kona-cdp-lcd.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. kona CDP (LCD) tron";
+	compatible = "qcom,kona-cdp", "qcom,kona", "qcom,cdp";
+	qcom,board-id = <0x01020001 0>;
+};
+
+&mdm0 {
+	status = "disabled";
+};
diff --git a/qcom/kona-cdp-lcd.dtsi b/qcom/kona-cdp-lcd.dtsi
index a73e6a22..c5013f27 100644
--- a/qcom/kona-cdp-lcd.dtsi
+++ b/qcom/kona-cdp-lcd.dtsi
@@ -40,6 +40,19 @@
 	/delete-property/ qcom,platform-en-gpio;
 };
 
+&dsi_nt36672e_fhd_plus_60_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+
+	qcom,esd-check-enabled;
+	qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+	qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+	qcom,mdss-dsi-panel-status-value = <0x9c>;
+	qcom,mdss-dsi-panel-status-read-length = <1>;
+	/delete-property/ qcom,platform-en-gpio;
+};
+
 &dsi_sharp_qsync_wqhd_cmd {
 	qcom,esd-check-enabled;
 	qcom,mdss-dsi-panel-status-check-mode = "reg_read";
diff --git a/qcom/kona-cdp.dtsi b/qcom/kona-cdp.dtsi
index 19e30f64..cb06ea89 100644
--- a/qcom/kona-cdp.dtsi
+++ b/qcom/kona-cdp.dtsi
@@ -202,6 +202,26 @@
 
 		panel = <&dsi_r66451_amoled_144hz_cmd>;
 	};
+
+	novatek@62 {
+		compatible = "novatek,NVT-ts";
+		reg = <0x62>;
+
+		interrupt-parent = <&tlmm>;
+		interrupts = <39 0x2008>;
+
+		pinctrl-names = "pmx_ts_active", "pmx_ts_suspend",
+				"pmx_ts_release";
+		pinctrl-0 = <&ts_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+		pinctrl-2 = <&pmx_ts_release>;
+
+		novatek,reset-gpio = <&tlmm 38 0x00>;
+		novatek,irq-gpio = <&tlmm 39 0x2008>;
+
+		panel = <&dsi_nt36672e_fhd_plus_60_video>;
+
+	};
 };
 
 &vendor {
@@ -309,6 +329,15 @@
 	qcom,platform-en-gpio = <&tlmm 60 0>;
 };
 
+&dsi_nt36672e_fhd_plus_60_video {
+	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+	qcom,mdss-dsi-bl-min-level = <1>;
+	qcom,mdss-dsi-bl-max-level = <4095>;
+	qcom,platform-reset-gpio = <&tlmm 75 0>;
+	qcom,platform-en-gpio = <&tlmm 60 0>;
+};
+
 &dsi_sharp_1080_cmd {
 	qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
 	qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
diff --git a/qcom/kona-lpi-ar.dtsi b/qcom/kona-lpi-ar.dtsi
new file mode 100644
index 00000000..adb00ed4
--- /dev/null
+++ b/qcom/kona-lpi-ar.dtsi
@@ -0,0 +1,1679 @@
+&spf_core_platform {
+	lpi_tlmm_ar: lpi_pinctrl_ar {
+		compatible = "qcom,lpi-pinctrl";
+		reg = <0x33c0000 0x0>;
+		qcom,slew-reg = <0x355a000 0x0>;
+		qcom,num-gpios = <14>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		qcom,lpi-offset-tbl = <0x00000000>, <0x00001000>,
+				      <0x00002000>, <0x00003000>,
+				      <0x00004000>, <0x00005000>,
+				      <0x00006000>, <0x00007000>,
+				      <0x00008000>, <0x00009000>,
+				      <0x0000A000>, <0x0000B000>,
+				      <0x0000C000>, <0x0000D000>;
+		qcom,lpi-slew-offset-tbl = <0x00000000>, <0x00000002>,
+					   <0x00000004>, <0x00000008>,
+					   <0x0000000A>, <0x0000000C>,
+					   <0x00000000>, <0x00000000>,
+					   <0x00000000>, <0x00000000>,
+					   <0x00000010>, <0x00000012>,
+					   <0x00000000>, <0x00000000>;
+
+		clock-names = "lpass_core_hw_vote",
+				"lpass_audio_hw_vote";
+		clocks = <&lpass_core_hw_vote_ar 0>,
+				<&lpass_audio_hw_vote_ar 0>;
+
+		quat_mi2s_sck_ar {
+			quat_mi2s_sck_sleep_ar: quat_mi2s_sck_sleep_ar {
+				mux {
+					pins = "gpio0";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio0";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			quat_mi2s_sck_active_ar: quat_mi2s_sck_active_ar {
+				mux {
+					pins = "gpio0";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio0";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		quat_mi2s_ws_ar {
+			quat_mi2s_ws_sleep_ar: quat_mi2s_ws_sleep_ar {
+				mux {
+					pins = "gpio1";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio1";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			quat_mi2s_ws_active_ar: quat_mi2s_ws_active_ar {
+				mux {
+					pins = "gpio1";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio1";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		quat_mi2s_sd0_ar {
+			quat_mi2s_sd0_sleep_ar: quat_mi2s_sd0_sleep_ar {
+				mux {
+					pins = "gpio2";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio2";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			quat_mi2s_sd0_active_ar: quat_mi2s_sd0_active_ar {
+				mux {
+					pins = "gpio2";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio2";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		quat_mi2s_sd1_ar {
+			quat_mi2s_sd1_sleep_ar: quat_mi2s_sd1_sleep_ar {
+				mux {
+					pins = "gpio3";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio3";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			quat_mi2s_sd1_active_ar: quat_mi2s_sd1_active_ar {
+				mux {
+					pins = "gpio3";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio3";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		quat_mi2s_sd2_ar {
+			quat_mi2s_sd2_sleep_ar: quat_mi2s_sd2_sleep_ar {
+				mux {
+					pins = "gpio4";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio4";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			quat_mi2s_sd2_active_ar: quat_mi2s_sd2_active_ar {
+				mux {
+					pins = "gpio4";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio4";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		quat_mi2s_sd3_ar {
+			quat_mi2s_sd3_sleep_ar: quat_mi2s_sd3_sleep_ar {
+				mux {
+					pins = "gpio5";
+					function = "func4";
+				};
+
+				config {
+					pins = "gpio5";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			quat_mi2s_sd3_active_ar: quat_mi2s_sd3_active_ar {
+				mux {
+					pins = "gpio5";
+					function = "func4";
+				};
+
+				config {
+					pins = "gpio5";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_i2s1_sck_ar {
+			lpi_i2s1_sck_sleep_ar: lpi_i2s1_sck_sleep_ar {
+				mux {
+					pins = "gpio6";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio6";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_i2s1_sck_active_ar: lpi_i2s1_sck_active_ar {
+				mux {
+					pins = "gpio6";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio6";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_i2s1_ws_ar {
+			lpi_i2s1_ws_sleep_ar: lpi_i2s1_ws_sleep_ar {
+				mux {
+					pins = "gpio7";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio7";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_i2s1_ws_active_ar: lpi_i2s1_ws_active_ar {
+				mux {
+					pins = "gpio7";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio7";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_i2s1_sd0_ar {
+			lpi_i2s1_sd0_sleep_ar: lpi_i2s1_sd0_sleep_ar {
+				mux {
+					pins = "gpio8";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio8";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_i2s1_sd0_active_ar: lpi_i2s1_sd0_active_ar {
+				mux {
+					pins = "gpio8";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio8";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_i2s1_sd1_ar {
+			lpi_i2s1_sd1_sleep_ar: lpi_i2s1_sd1_sleep_ar {
+				mux {
+					pins = "gpio9";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio9";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_i2s1_sd1_active_ar: lpi_i2s1_sd1_active_ar {
+				mux {
+					pins = "gpio9";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio9";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_i2s2_sck_ar {
+			lpi_i2s2_sck_sleep_ar: lpi_i2s2_sck_sleep_ar {
+				mux {
+					pins = "gpio10";
+					function = "func1";
+				};
+
+				config {
+					pins = "gpio10";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_i2s2_sck_active_ar: lpi_i2s2_sck_active_ar {
+				mux {
+					pins = "gpio10";
+					function = "func1";
+				};
+
+				config {
+					pins = "gpio10";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_i2s2_ws_ar {
+			lpi_i2s2_ws_sleep_ar: lpi_i2s2_ws_sleep_ar {
+				mux {
+					pins = "gpio11";
+					function = "func1";
+				};
+
+				config {
+					pins = "gpio11";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_i2s2_ws_active_ar: lpi_i2s2_ws_active_ar {
+				mux {
+					pins = "gpio11";
+					function = "func1";
+				};
+
+				config {
+					pins = "gpio11";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_i2s2_sd0_ar {
+			lpi_i2s2_sd0_sleep_ar: lpi_i2s2_sd0_sleep_ar {
+				mux {
+					pins = "gpio12";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio12";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_i2s2_sd0_active_ar: lpi_i2s2_sd0_active_ar {
+				mux {
+					pins = "gpio12";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio12";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_i2s2_sd1_ar {
+			lpi_i2s2_sd1_sleep_ar: lpi_i2s2_sd1_sleep_ar {
+				mux {
+					pins = "gpio13";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio13";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_i2s2_sd1_active_ar: lpi_i2s2_sd1_active_ar {
+				mux {
+					pins = "gpio13";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio13";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		quat_tdm_sck_ar {
+			quat_tdm_sck_sleep_ar: quat_tdm_sck_sleep_ar {
+				mux {
+					pins = "gpio0";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio0";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			quat_tdm_sck_active_ar: quat_tdm_sck_active_ar {
+				mux {
+					pins = "gpio0";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio0";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		quat_tdm_ws_ar {
+			quat_tdm_ws_sleep_ar: quat_tdm_ws_sleep_ar {
+				mux {
+					pins = "gpio1";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio1";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			quat_tdm_ws_active_ar: quat_tdm_ws_active_ar {
+				mux {
+					pins = "gpio1";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio1";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		quat_tdm_sd0_ar {
+			quat_tdm_sd0_sleep_ar: quat_tdm_sd0_sleep_ar {
+				mux {
+					pins = "gpio2";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio2";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			quat_tdm_sd0_active_ar: quat_tdm_sd0_active_ar {
+				mux {
+					pins = "gpio2";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio2";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		quat_tdm_sd1_ar {
+			quat_tdm_sd1_sleep_ar: quat_tdm_sd1_sleep_ar {
+				mux {
+					pins = "gpio3";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio3";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			quat_tdm_sd1_active_ar: quat_tdm_sd1_active_ar {
+				mux {
+					pins = "gpio3";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio3";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		quat_tdm_sd2_ar {
+			quat_tdm_sd2_sleep_ar: quat_tdm_sd2_sleep_ar {
+				mux {
+					pins = "gpio4";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio4";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			quat_tdm_sd2_active_ar: quat_tdm_sd2_active_ar {
+				mux {
+					pins = "gpio4";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio4";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		quat_tdm_sd3_ar {
+			quat_tdm_sd3_sleep_ar: quat_tdm_sd3_sleep_ar {
+				mux {
+					pins = "gpio5";
+					function = "func4";
+				};
+
+				config {
+					pins = "gpio5";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			quat_tdm_sd3_active_ar: quat_tdm_sd3_active_ar {
+				mux {
+					pins = "gpio5";
+					function = "func4";
+				};
+
+				config {
+					pins = "gpio5";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_tdm1_sck_ar {
+			lpi_tdm1_sck_sleep_ar: lpi_tdm1_sck_sleep_ar {
+				mux {
+					pins = "gpio6";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio6";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_tdm1_sck_active_ar: lpi_tdm1_sck_active_ar {
+				mux {
+					pins = "gpio6";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio6";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_tdm1_ws_ar {
+			lpi_tdm1_ws_sleep_ar: lpi_tdm1_ws_sleep_ar {
+				mux {
+					pins = "gpio7";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio7";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_tdm1_ws_active_ar: lpi_tdm1_ws_active_ar {
+				mux {
+					pins = "gpio7";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio7";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_tdm1_sd0_ar {
+			lpi_tdm1_sd0_sleep_ar: lpi_tdm1_sd0_sleep_ar {
+				mux {
+					pins = "gpio8";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio8";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_tdm1_sd0_active_ar: lpi_tdm1_sd0_active_ar {
+				mux {
+					pins = "gpio8";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio8";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_tdm1_sd1_ar {
+			lpi_tdm1_sd1_sleep_ar: lpi_tdm1_sd1_sleep_ar {
+				mux {
+					pins = "gpio9";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio9";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_tdm1_sd1_active_ar: lpi_tdm1_sd1_active_ar {
+				mux {
+					pins = "gpio9";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio9";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_tdm2_sck_ar {
+			lpi_tdm2_sck_sleep_ar: lpi_tdm2_sck_sleep_ar {
+				mux {
+					pins = "gpio10";
+					function = "func1";
+				};
+
+				config {
+					pins = "gpio10";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_tdm2_sck_active_ar: lpi_tdm2_sck_active_ar {
+				mux {
+					pins = "gpio10";
+					function = "func1";
+				};
+
+				config {
+					pins = "gpio10";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_tdm2_ws_ar {
+			lpi_tdm2_ws_sleep_ar: lpi_tdm2_ws_sleep_ar {
+				mux {
+					pins = "gpio11";
+					function = "func1";
+				};
+
+				config {
+					pins = "gpio11";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_tdm2_ws_active_ar: lpi_tdm2_ws_active_ar {
+				mux {
+					pins = "gpio11";
+					function = "func1";
+				};
+
+				config {
+					pins = "gpio11";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_tdm2_sd0_ar {
+			lpi_tdm2_sd0_sleep_ar: lpi_tdm2_sd0_sleep_ar {
+				mux {
+					pins = "gpio12";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio12";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_tdm2_sd0_active_ar: lpi_tdm2_sd0_active_ar {
+				mux {
+					pins = "gpio12";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio12";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_tdm2_sd1_ar {
+			lpi_tdm2_sd1_sleep_ar: lpi_tdm2_sd1_sleep_ar {
+				mux {
+					pins = "gpio13";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio13";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_tdm2_sd1_active_ar: lpi_tdm2_sd1_active_ar {
+				mux {
+					pins = "gpio13";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio13";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		quat_aux_sck_ar {
+			quat_aux_sck_sleep_ar: quat_aux_sck_sleep_ar {
+				mux {
+					pins = "gpio0";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio0";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			quat_aux_sck_active_ar: quat_aux_sck_active_ar {
+				mux {
+					pins = "gpio0";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio0";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		quat_aux_ws_ar {
+			quat_aux_ws_sleep_ar: quat_aux_ws_sleep_ar {
+				mux {
+					pins = "gpio1";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio1";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			quat_aux_ws_active_ar: quat_aux_ws_active_ar {
+				mux {
+					pins = "gpio1";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio1";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		quat_aux_sd0_ar {
+			quat_aux_sd0_sleep_ar: quat_aux_sd0_sleep_ar {
+				mux {
+					pins = "gpio2";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio2";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			quat_aux_sd0_active_ar: quat_aux_sd0_active_ar {
+				mux {
+					pins = "gpio2";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio2";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		quat_aux_sd1_ar {
+			quat_aux_sd1_sleep_ar: quat_aux_sd1_sleep_ar {
+				mux {
+					pins = "gpio3";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio3";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			quat_aux_sd1_active_ar: quat_aux_sd1_active_ar {
+				mux {
+					pins = "gpio3";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio3";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		quat_aux_sd2_ar {
+			quat_aux_sd2_sleep_ar: quat_aux_sd2_sleep_ar {
+				mux {
+					pins = "gpio4";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio4";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			quat_aux_sd2_active_ar: quat_aux_sd2_active_ar {
+				mux {
+					pins = "gpio4";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio4";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		quat_aux_sd3_ar {
+			quat_aux_sd3_sleep_ar: quat_aux_sd3_sleep_ar {
+				mux {
+					pins = "gpio5";
+					function = "func4";
+				};
+
+				config {
+					pins = "gpio5";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			quat_aux_sd3_active_ar: quat_aux_sd3_active_ar {
+				mux {
+					pins = "gpio5";
+					function = "func4";
+				};
+
+				config {
+					pins = "gpio5";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_aux1_sck_ar {
+			lpi_aux1_sck_sleep_ar: lpi_aux1_sck_sleep_ar {
+				mux {
+					pins = "gpio6";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio6";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_aux1_sck_active_ar: lpi_aux1_sck_active_ar {
+				mux {
+					pins = "gpio6";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio6";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_aux1_ws_ar {
+			lpi_aux1_ws_sleep_ar: lpi_aux1_ws_sleep_ar {
+				mux {
+					pins = "gpio7";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio7";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_aux1_ws_active_ar: lpi_aux1_ws_active_ar {
+				mux {
+					pins = "gpio7";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio7";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_aux1_sd0_ar {
+			lpi_aux1_sd0_sleep_ar: lpi_aux1_sd0_sleep_ar {
+				mux {
+					pins = "gpio8";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio8";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_aux1_sd0_active_ar: lpi_aux1_sd0_active_ar {
+				mux {
+					pins = "gpio8";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio8";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_aux1_sd1_ar {
+			lpi_aux1_sd1_sleep_ar: lpi_aux1_sd1_sleep_ar {
+				mux {
+					pins = "gpio9";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio9";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_aux1_sd1_active_ar: lpi_aux1_sd1_active_ar {
+				mux {
+					pins = "gpio9";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio9";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_aux2_sck_ar {
+			lpi_aux2_sck_sleep_ar: lpi_aux2_sck_sleep_ar {
+				mux {
+					pins = "gpio10";
+					function = "func1";
+				};
+
+				config {
+					pins = "gpio10";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_aux2_sck_active_ar: lpi_aux2_sck_active_ar {
+				mux {
+					pins = "gpio10";
+					function = "func1";
+				};
+
+				config {
+					pins = "gpio10";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_aux2_ws_ar {
+			lpi_aux2_ws_sleep_ar: lpi_aux2_ws_sleep_ar {
+				mux {
+					pins = "gpio11";
+					function = "func1";
+				};
+
+				config {
+					pins = "gpio11";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_aux2_ws_active_ar: lpi_aux2_ws_active_ar {
+				mux {
+					pins = "gpio11";
+					function = "func1";
+				};
+
+				config {
+					pins = "gpio11";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_aux2_sd0_ar {
+			lpi_aux2_sd0_sleep_ar: lpi_aux2_sd0_sleep_ar {
+				mux {
+					pins = "gpio12";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio12";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_aux2_sd0_active_ar: lpi_aux2_sd0_active_ar {
+				mux {
+					pins = "gpio12";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio12";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		lpi_aux2_sd1_ar {
+			lpi_aux2_sd1_sleep_ar: lpi_aux2_sd1_sleep_ar {
+				mux {
+					pins = "gpio13";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio13";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;         /* PULL DOWN */
+					input-enable;
+				};
+			};
+
+			lpi_aux2_sd1_active_ar: lpi_aux2_sd1_active_ar {
+				mux {
+					pins = "gpio13";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio13";
+					drive-strength = <8>;   /* 8 mA */
+					bias-disable;           /* NO PULL */
+					output-high;
+				};
+			};
+		};
+
+		wsa_swr_clk_pin_ar {
+			wsa_swr_clk_sleep_ar: wsa_swr_clk_sleep_ar {
+				mux {
+					pins = "gpio10";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio10";
+					drive-strength = <2>;
+					input-enable;
+					bias-pull-down;
+				};
+			};
+
+			wsa_swr_clk_active_ar: wsa_swr_clk_active_ar {
+				mux {
+					pins = "gpio10";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio10";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-disable;
+				};
+			};
+		};
+
+		wsa_swr_data_pin_ar {
+			wsa_swr_data_sleep_ar: wsa_swr_data_sleep_ar {
+				mux {
+					pins = "gpio11";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio11";
+					drive-strength = <2>;
+					input-enable;
+					bias-pull-down;
+				};
+			};
+
+			wsa_swr_data_active_ar: wsa_swr_data_active_ar {
+				mux {
+					pins = "gpio11";
+					function = "func2";
+				};
+
+				config {
+					pins = "gpio11";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-bus-hold;
+				};
+			};
+		};
+
+		tx_swr_clk_sleep_ar: tx_swr_clk_sleep_ar {
+			mux {
+				pins = "gpio0";
+				function = "func1";
+				input-enable;
+				bias-pull-down;
+			};
+
+			config {
+				pins = "gpio0";
+				drive-strength = <2>;
+			};
+		};
+
+		tx_swr_clk_active_ar: tx_swr_clk_active_ar {
+			mux {
+				pins = "gpio0";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio0";
+				drive-strength = <2>;
+				slew-rate = <1>;
+				bias-disable;
+			};
+		};
+
+		tx_swr_data1_sleep_ar: tx_swr_data1_sleep_ar {
+			mux {
+				pins = "gpio1";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio1";
+				drive-strength = <2>;
+				input-enable;
+				bias-bus-hold;
+			};
+		};
+
+		tx_swr_data1_active_ar: tx_swr_data1_active_ar {
+			mux {
+				pins = "gpio1";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio1";
+				drive-strength = <2>;
+				slew-rate = <1>;
+				bias-bus-hold;
+			};
+		};
+
+		tx_swr_data2_sleep_ar: tx_swr_data2_sleep_ar {
+			mux {
+				pins = "gpio2";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio2";
+				drive-strength = <2>;
+				input-enable;
+				bias-pull-down;
+			};
+		};
+
+		tx_swr_data2_active_ar: tx_swr_data2_active_ar {
+			mux {
+				pins = "gpio2";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio2";
+				drive-strength = <2>;
+				slew-rate = <1>;
+				bias-bus-hold;
+			};
+		};
+
+		rx_swr_clk_sleep_ar: rx_swr_clk_sleep_ar {
+			mux {
+				pins = "gpio3";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio3";
+				drive-strength = <2>;
+				input-enable;
+				bias-pull-down;
+			};
+		};
+
+		rx_swr_clk_active_ar: rx_swr_clk_active_ar {
+			mux {
+				pins = "gpio3";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio3";
+				drive-strength = <2>;
+				slew-rate = <1>;
+				bias-disable;
+			};
+		};
+
+		rx_swr_data_sleep_ar: rx_swr_data_sleep_ar {
+			mux {
+				pins = "gpio4";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio4";
+				drive-strength = <2>;
+				input-enable;
+				bias-pull-down;
+			};
+		};
+
+		rx_swr_data_active_ar: rx_swr_data_active_ar {
+			mux {
+				pins = "gpio4";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio4";
+				drive-strength = <2>;
+				slew-rate = <1>;
+				bias-bus-hold;
+			};
+		};
+
+		rx_swr_data1_sleep_ar: rx_swr_data1_sleep_ar {
+			mux {
+				pins = "gpio5";
+				function = "func2";
+			};
+
+			config {
+				pins = "gpio5";
+				drive-strength = <2>;
+				input-enable;
+				bias-pull-down;
+			};
+		};
+
+		rx_swr_data1_active_ar: rx_swr_data1_active_ar {
+			mux {
+				pins = "gpio5";
+				function = "func2";
+			};
+
+			config {
+				pins = "gpio5";
+				drive-strength = <2>;
+				slew-rate = <1>;
+				bias-bus-hold;
+			};
+		};
+
+		cdc_dmic01_clk_active_ar: dmic01_clk_active_ar {
+			mux {
+				pins = "gpio6";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio6";
+				drive-strength = <8>;
+				output-high;
+			};
+		};
+
+		cdc_dmic01_clk_sleep_ar: dmic01_clk_sleep_ar {
+			mux {
+				pins = "gpio6";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio6";
+				drive-strength = <2>;
+				bias-disable;
+				output-low;
+			};
+		};
+
+		cdc_dmic01_data_active_ar: dmic01_data_active_ar {
+			mux {
+				pins = "gpio7";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio7";
+				drive-strength = <8>;
+				input-enable;
+			};
+		};
+
+		cdc_dmic01_data_sleep_ar: dmic01_data_sleep_ar {
+			mux {
+				pins = "gpio7";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio7";
+				drive-strength = <2>;
+				pull-down;
+				input-enable;
+			};
+		};
+
+		cdc_dmic23_clk_active_ar: dmic23_clk_active_ar {
+			mux {
+				pins = "gpio8";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio8";
+				drive-strength = <8>;
+				output-high;
+			};
+		};
+
+		cdc_dmic23_clk_sleep_ar: dmic23_clk_sleep_ar {
+			mux {
+				pins = "gpio8";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio8";
+				drive-strength = <2>;
+				bias-disable;
+				output-low;
+			};
+		};
+
+		cdc_dmic23_data_active_ar: dmic23_data_active_ar {
+			mux {
+				pins = "gpio9";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio9";
+				drive-strength = <8>;
+				input-enable;
+			};
+		};
+
+		cdc_dmic23_data_sleep_ar: dmic23_data_sleep_ar {
+			mux {
+				pins = "gpio9";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio9";
+				drive-strength = <2>;
+				pull-down;
+				input-enable;
+			};
+		};
+
+		cdc_dmic45_clk_active_ar: dmic45_clk_active_ar {
+			mux {
+				pins = "gpio12";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio12";
+				drive-strength = <8>;
+				output-high;
+			};
+		};
+
+		cdc_dmic45_clk_sleep_ar: dmic45_clk_sleep_ar {
+			mux {
+				pins = "gpio12";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio12";
+				drive-strength = <2>;
+				bias-disable;
+				output-low;
+			};
+		};
+
+		cdc_dmic45_data_active_ar: dmic45_data_active_ar {
+			mux {
+				pins = "gpio13";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio13";
+				drive-strength = <8>;
+				input-enable;
+			};
+		};
+
+		cdc_dmic45_data_sleep_ar: dmic45_data_sleep_ar {
+			mux {
+				pins = "gpio13";
+				function = "func1";
+			};
+
+			config {
+				pins = "gpio13";
+				drive-strength = <2>;
+				pull-down;
+				input-enable;
+			};
+		};
+	};
+};
diff --git a/qcom/kona-mtp.dtsi b/qcom/kona-mtp.dtsi
index ec769b0c..476ccf0e 100644
--- a/qcom/kona-mtp.dtsi
+++ b/qcom/kona-mtp.dtsi
@@ -5,6 +5,7 @@
 #include "kona-sde-display.dtsi"
 #include "camera/kona-camera-sensor-mtp.dtsi"
 #include "kona-audio-overlay.dtsi"
+#include "kona-audio-overlay-ar.dtsi"
 #include "kona-thermal-overlay.dtsi"
 
 &qupv3_se12_2uart {
@@ -333,14 +334,6 @@
 		qcom,pre-scaling = <1 3>;
 	};
 
-	xo_therm@4c {
-		reg = <ADC_XO_THERM_PU2>;
-		label = "xo_therm";
-		qcom,ratiometric;
-		qcom,hw-settle-time = <200>;
-		qcom,pre-scaling = <1 1>;
-	};
-
 	skin_therm@4d {
 		reg = <ADC_AMUX_THM1_PU2>;
 		label = "skin_therm";
@@ -410,16 +403,9 @@
 	#address-cells = <1>;
 	#size-cells = <0>;
 
-	io-channels = <&pm8150_vadc ADC_XO_THERM_PU2>,
-			<&pm8150_vadc ADC_AMUX_THM1_PU2>,
+	io-channels = <&pm8150_vadc ADC_AMUX_THM1_PU2>,
 			<&pm8150_vadc ADC_AMUX_THM2_PU2>;
 
-	xo_therm@4c {
-		reg = <ADC_XO_THERM_PU2>;
-		qcom,ratiometric;
-		qcom,hw-settle-time = <200>;
-	};
-
 	skin_therm@4d {
 		reg = <ADC_AMUX_THM1_PU2>;
 		qcom,ratiometric;
@@ -565,21 +551,6 @@
 		};
 	};
 
-	xo-therm-usr {
-		polling-delay-passive = <0>;
-		polling-delay = <0>;
-		thermal-governor = "user_space";
-		thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>;
-		wake-capable-sensor;
-		trips {
-			active-config0 {
-				temperature = <125000>;
-				hysteresis = <1000>;
-				type = "passive";
-			};
-		};
-	};
-
 	skin-therm-usr {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
diff --git a/qcom/kona-sde-display.dtsi b/qcom/kona-sde-display.dtsi
index 89ce8c87..22911ac4 100644
--- a/qcom/kona-sde-display.dtsi
+++ b/qcom/kona-sde-display.dtsi
@@ -22,6 +22,8 @@
 #include "dsi-panel-sim-sec-hd-cmd.dtsi"
 #include "dsi-panel-xrsmrtvwr-jdi-dual-video.dtsi"
 #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi"
+#include "dsi-panel-arglass-seeya-dual-1080p-video.dtsi"
+#include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi"
 #include <dt-bindings/clock/mdss-7nm-pll-clk.h>
 
 &tlmm {
@@ -110,7 +112,7 @@
 		qcom,panel-supply-entry@1 {
 			reg = <1>;
 			qcom,supply-name = "lab";
-			qcom,supply-min-voltage = <4600000>;
+			qcom,supply-min-voltage = <5600000>;
 			qcom,supply-max-voltage = <6000000>;
 			qcom,supply-enable-load = <100000>;
 			qcom,supply-disable-load = <100>;
@@ -119,7 +121,7 @@
 		qcom,panel-supply-entry@2 {
 			reg = <2>;
 			qcom,supply-name = "ibb";
-			qcom,supply-min-voltage = <4600000>;
+			qcom,supply-min-voltage = <5600000>;
 			qcom,supply-max-voltage = <6000000>;
 			qcom,supply-enable-load = <100000>;
 			qcom,supply-disable-load = <100>;
@@ -308,6 +310,25 @@
 	};
 };
 
+&dsi_dual_arglass_seeya_video {
+	qcom,mdss-dsi-min-refresh-rate = <60>;
+	qcom,mdss-dsi-max-refresh-rate = <60>;
+	qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+	qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+	qcom,mdss-dsi-panel-status-value = <0x9c>;
+	qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+	qcom,mdss-dsi-panel-status-read-length = <1>;
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-phy-timings =  [00 11 04 04 12 1E
+				04 04 04 03 02 04 0F 09];
+			qcom,display-topology = <2 0 2>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
+
 &dsi_dual_xrsmrtvwr_jdi_video {
 	qcom,mdss-dsi-min-refresh-rate = <53>;
 	qcom,mdss-dsi-max-refresh-rate = <80>;
@@ -537,6 +558,18 @@
 	};
 };
 
+&dsi_nt36672e_fhd_plus_60_video {
+	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+	qcom,mdss-dsi-display-timings {
+		timing@0 {
+			qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1f 1e 05
+				05 03 02 04 00 12 14];
+			qcom,display-topology = <1 0 1>;
+			qcom,default-topology-index = <0>;
+		};
+	};
+};
+
 &dsi_sharp_1080_cmd {
 	qcom,ulps-enabled;
 	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
diff --git a/qcom/kona-sde.dtsi b/qcom/kona-sde.dtsi
index d7873242..5c0bcff6 100644
--- a/qcom/kona-sde.dtsi
+++ b/qcom/kona-sde.dtsi
@@ -96,6 +96,7 @@
 		qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>;
 		qcom,sde-dsc-size = <0x140>;
 		qcom,sde-dsc-pair-mask = <2 1 4 3>;
+		qcom,sde-dsc-linewidth = <2048>;
 
 		qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0
 							0x30e0 0x30e0 0x30e0>;
@@ -406,8 +407,6 @@
 		qcom,widebus-enable;
 		qcom,dsc-feature-enable;
 		qcom,fec-feature-enable;
-		qcom,max-dp-dsc-blks = <2>;
-		qcom,max-dp-dsc-input-width-pixs = <2048>;
 
 		qcom,ctrl-supply-entries {
 			#address-cells = <1>;
diff --git a/qcom/kona-v2-arglass.dts b/qcom/kona-v2-arglass.dts
new file mode 100644
index 00000000..8d4b0f07
--- /dev/null
+++ b/qcom/kona-v2-arglass.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.dtsi"
+#include "kona-arglass.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. kona AR Glass";
+	compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+	qcom,board-id = <0x1040008 0>;
+};
diff --git a/qcom/kona-v2-gpu.dtsi b/qcom/kona-v2-gpu.dtsi
index 119e296d..d9deb32a 100644
--- a/qcom/kona-v2-gpu.dtsi
+++ b/qcom/kona-v2-gpu.dtsi
@@ -472,5 +472,119 @@
 				qcom,bus-max = <0>;
 			};
 		};
+
+		qcom,gpu-pwrlevels-4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			qcom,speed-bin = <4>;
+			qcom,initial-pwrlevel = <6>;
+			qcom,throttle-pwrlevel = <1>;
+
+			qcom,gpu-pwrlevel@0 {
+				reg = <0>;
+				qcom,gpu-freq = <670000000>;
+				qcom,bus-freq-ddr7 = <11>;
+				qcom,bus-min-ddr7 = <11>;
+				qcom,bus-max-ddr7 = <11>;
+
+				qcom,bus-freq-ddr8 = <11>;
+				qcom,bus-min-ddr8 = <11>;
+				qcom,bus-max-ddr8 = <11>;
+
+				qcom,acd-level = <0x802b5ffd>;
+			};
+
+			qcom,gpu-pwrlevel@1 {
+				reg = <1>;
+				qcom,gpu-freq = <587000000>;
+				qcom,bus-freq-ddr7 = <11>;
+				qcom,bus-min-ddr7 = <11>;
+				qcom,bus-max-ddr7 = <11>;
+
+				qcom,bus-freq-ddr8 = <11>;
+				qcom,bus-min-ddr8 = <11>;
+				qcom,bus-max-ddr8 = <11>;
+
+				qcom,acd-level = <0x802b5ffd>;
+			};
+
+			qcom,gpu-pwrlevel@2 {
+				reg = <2>;
+				qcom,gpu-freq = <525000000>;
+				qcom,bus-freq-ddr7 = <9>;
+				qcom,bus-min-ddr7 = <9>;
+				qcom,bus-max-ddr7 = <11>;
+
+				qcom,bus-freq-ddr8 = <8>;
+				qcom,bus-min-ddr8 = <8>;
+				qcom,bus-max-ddr8 = <11>;
+
+				qcom,acd-level = <0x802b5ffd>;
+			};
+
+			qcom,gpu-pwrlevel@3 {
+				reg = <3>;
+				qcom,gpu-freq = <490000000>;
+				qcom,bus-freq-ddr7 = <9>;
+				qcom,bus-min-ddr7 = <6>;
+				qcom,bus-max-ddr7 = <9>;
+
+				qcom,bus-freq-ddr8 = <8>;
+				qcom,bus-min-ddr8 = <7>;
+				qcom,bus-max-ddr8 = <9>;
+
+				qcom,acd-level = <0xa02b5ffd>;
+				};
+
+			qcom,gpu-pwrlevel@4 {
+				reg = <4>;
+				qcom,gpu-freq = <441600000>;
+				qcom,bus-freq-ddr7 = <9>;
+				qcom,bus-min-ddr7 = <6>;
+				qcom,bus-max-ddr7 = <9>;
+
+				qcom,bus-freq-ddr8 = <8>;
+				qcom,bus-min-ddr8 = <7>;
+				qcom,bus-max-ddr8 = <9>;
+
+				qcom,acd-level = <0xa02b5ffd>;
+			};
+
+			qcom,gpu-pwrlevel@5 {
+				reg = <5>;
+				qcom,gpu-freq = <400000000>;
+				qcom,bus-freq-ddr7 = <7>;
+				qcom,bus-min-ddr7 = <6>;
+				qcom,bus-max-ddr7 = <9>;
+
+				qcom,bus-freq-ddr8 = <8>;
+				qcom,bus-min-ddr8 = <6>;
+				qcom,bus-max-ddr8 = <9>;
+
+				qcom,acd-level = <0xa02b5ffd>;
+			};
+
+			qcom,gpu-pwrlevel@6 {
+				reg = <6>;
+				qcom,gpu-freq = <305000000>;
+				qcom,bus-freq-ddr7 = <3>;
+				qcom,bus-min-ddr7 = <2>;
+				qcom,bus-max-ddr7 = <9>;
+
+				qcom,bus-freq-ddr8 = <3>;
+				qcom,bus-min-ddr8 = <2>;
+				qcom,bus-max-ddr8 = <9>;
+
+				qcom,acd-level = <0xa02b5ffd>;
+			};
+
+			qcom,gpu-pwrlevel@7 {
+				reg = <7>;
+				qcom,gpu-freq = <0>;
+				qcom,bus-freq = <0>;
+				qcom,bus-min = <0>;
+				qcom,bus-max = <0>;
+			};
+		};
 	};
 };
diff --git a/qcom/kona-v2.1-arglass.dts b/qcom/kona-v2.1-arglass.dts
new file mode 100644
index 00000000..3ae49243
--- /dev/null
+++ b/qcom/kona-v2.1-arglass.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.1.dtsi"
+#include "kona-arglass.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. kona v2.1 AR Glass";
+	compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+	qcom,board-id = <0x1040008 0>;
+};
diff --git a/qcom/kona-v2.1-iot-rb5.dtsi b/qcom/kona-v2.1-iot-rb5.dtsi
index 7d325134..4b2aa986 100644
--- a/qcom/kona-v2.1-iot-rb5.dtsi
+++ b/qcom/kona-v2.1-iot-rb5.dtsi
@@ -196,6 +196,10 @@
 };
 
 &soc {
+	msm_vidc: qcom,vidc@aa00000 {
+		compatible = "qcom,msm-vidc", "qcom,qcs8250-vidc";
+	};
+
 	clk40M: can_clock {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -246,7 +250,13 @@
 };
 
 &pcie1 {
-	status = "disabled";
+	status = "okay";
+	qcom,boot-option = <0x0>;
+};
+
+&pcie2 {
+	status = "okay";
+	qcom,boot-option = <0x0>;
 };
 
 &thermal_zones {
diff --git a/qcom/kona-va-bolero-ar.dtsi b/qcom/kona-va-bolero-ar.dtsi
new file mode 100644
index 00000000..b4622311
--- /dev/null
+++ b/qcom/kona-va-bolero-ar.dtsi
@@ -0,0 +1,15 @@
+&bolero_ar {
+	va_macro_ar: va-macro-ar@3370000 {
+		compatible = "qcom,va-macro";
+		reg = <0x3370000 0x0>;
+		clock-names = "lpass_audio_hw_vote";
+		clocks = <&lpass_audio_hw_vote_ar 0>;
+		va-vdd-micb-supply = <&S4A>;
+		qcom,va-vdd-micb-voltage = <1800000 1800000>;
+		qcom,va-vdd-micb-current = <11200>;
+		qcom,va-dmic-sample-rate = <600000>;
+		qcom,va-clk-mux-select = <1>;
+		qcom,va-island-mode-muxsel = <0x033A0000>;
+		qcom,default-clk-id = <TX_CORE_CLK>;
+	};
+};
diff --git a/qcom/kona-xrfusion-ult.dtsi b/qcom/kona-xrfusion-ult.dtsi
index 95437f54..d9c69782 100644
--- a/qcom/kona-xrfusion-ult.dtsi
+++ b/qcom/kona-xrfusion-ult.dtsi
@@ -2,6 +2,7 @@
 #include "kona-pmic-overlay.dtsi"
 #include "kona-sde-display.dtsi"
 #include "kona-audio-overlay.dtsi"
+#include "kona-audio-overlay-ar.dtsi"
 #include "kona-thermal-overlay.dtsi"
 #include "kona-xr-pinctrl-overlay.dtsi"
 #include "camera/kona-camera-sensor-xrfusion.dtsi"
@@ -340,6 +341,92 @@
 				<&bolero>;
 };
 
+&kona_snd_ar {
+	qcom,model = "kona-xrfusionult-snd-card";
+	qcom,mi2s-audio-intf = <0>;
+	qcom,audio-routing =
+		"AMIC1", "MIC BIAS1",
+		"MIC BIAS1", "Analog Mic1",
+		"AMIC2", "MIC BIAS2",
+		"MIC BIAS2", "Analog Mic2",
+		"AMIC3", "MIC BIAS3",
+		"MIC BIAS3", "Analog Mic3",
+		"AMIC4", "MIC BIAS4",
+		"MIC BIAS4", "Analog Mic4",
+		"AMIC5", "MIC BIAS4",
+		"MIC BIAS4", "Analog Mic5",
+		"DMIC1", "MIC BIAS1",
+		"MIC BIAS1", "Digital Mic0",
+		"DMIC2", "MIC BIAS1",
+		"MIC BIAS1", "Digital Mic1",
+		"DMIC3", "MIC BIAS1",
+		"MIC BIAS1", "Digital Mic2",
+		"DMIC4", "MIC BIAS1",
+		"MIC BIAS1", "Digital Mic3",
+		"DMIC5", "MIC BIAS3",
+		"MIC BIAS3", "Digital Mic4",
+		"DMIC6", "MIC BIAS3",
+		"MIC BIAS3", "Digital Mic5",
+		"DMIC7", "MIC BIAS4",
+		"MIC BIAS4", "Digital Mic6",
+		"DMIC8", "MIC BIAS4",
+		"MIC BIAS4", "Digital Mic7",
+		"IN1_HPHL", "HPHL_OUT",
+		"IN2_HPHR", "HPHR_OUT",
+		"IN3_AUX", "AUX_OUT",
+		"TX SWR_ADC0", "ADC1_OUTPUT",
+		"TX SWR_ADC1", "ADC2_OUTPUT",
+		"TX SWR_ADC2", "ADC3_OUTPUT",
+		"TX SWR_ADC3", "ADC4_OUTPUT",
+		"TX SWR_DMIC0", "DMIC1_OUTPUT",
+		"TX SWR_DMIC1", "DMIC2_OUTPUT",
+		"TX SWR_DMIC2", "DMIC3_OUTPUT",
+		"TX SWR_DMIC3", "DMIC4_OUTPUT",
+		"TX SWR_DMIC4", "DMIC5_OUTPUT",
+		"TX SWR_DMIC5", "DMIC6_OUTPUT",
+		"TX SWR_DMIC6", "DMIC7_OUTPUT",
+		"TX SWR_DMIC7", "DMIC8_OUTPUT",
+		"WSA SRC0_INP", "SRC0",
+		"WSA_TX DEC0_INP", "TX DEC0 MUX",
+		"WSA_TX DEC1_INP", "TX DEC1 MUX",
+		"RX_TX DEC0_INP", "TX DEC0 MUX",
+		"RX_TX DEC1_INP", "TX DEC1 MUX",
+		"RX_TX DEC2_INP", "TX DEC2 MUX",
+		"RX_TX DEC3_INP", "TX DEC3 MUX",
+		"SpkrRight IN", "WSA_SPK2 OUT",
+		"VA_AIF1 CAP", "VA_SWR_CLK",
+		"VA_AIF2 CAP", "VA_SWR_CLK",
+		"VA_AIF3 CAP", "VA_SWR_CLK",
+		"VA MIC BIAS3", "Digital Mic0",
+		"VA MIC BIAS3", "Digital Mic1",
+		"VA MIC BIAS1", "Digital Mic2",
+		"VA MIC BIAS1", "Digital Mic3",
+		"VA MIC BIAS4", "Digital Mic5",
+		"VA DMIC0", "VA MIC BIAS3",
+		"VA DMIC1", "VA MIC BIAS3",
+		"VA DMIC2", "VA MIC BIAS1",
+		"VA DMIC3", "VA MIC BIAS1",
+		"VA DMIC5", "VA MIC BIAS4",
+		"VA SWR_ADC1", "VA_SWR_CLK",
+		"VA SWR_MIC0", "VA_SWR_CLK",
+		"VA SWR_MIC1", "VA_SWR_CLK",
+		"VA SWR_MIC2", "VA_SWR_CLK",
+		"VA SWR_MIC3", "VA_SWR_CLK",
+		"VA SWR_MIC4", "VA_SWR_CLK",
+		"VA SWR_MIC5", "VA_SWR_CLK",
+		"VA SWR_MIC6", "VA_SWR_CLK",
+		"VA SWR_MIC7", "VA_SWR_CLK",
+		"VA SWR_MIC0", "DMIC1_OUTPUT",
+		"VA SWR_MIC1", "DMIC2_OUTPUT",
+		"VA SWR_MIC2", "DMIC3_OUTPUT",
+		"VA SWR_MIC3", "DMIC4_OUTPUT",
+		"VA SWR_MIC4", "DMIC5_OUTPUT",
+		"VA SWR_MIC5", "DMIC6_OUTPUT",
+		"VA SWR_MIC6", "DMIC7_OUTPUT",
+		"VA SWR_MIC7", "DMIC8_OUTPUT",
+		"VA SWR_ADC1", "ADC2_OUTPUT";
+};
+
 &pm8150_l10 {
 	regulator-max-microvolt = <3304000>;
 	qcom,init-voltage = <3304000>;
diff --git a/qcom/kona-xrfusion.dtsi b/qcom/kona-xrfusion.dtsi
index 2992e347..5d27eb9c 100644
--- a/qcom/kona-xrfusion.dtsi
+++ b/qcom/kona-xrfusion.dtsi
@@ -2,6 +2,7 @@
 #include "kona-pmic-overlay.dtsi"
 #include "kona-sde-display.dtsi"
 #include "kona-audio-overlay.dtsi"
+#include "kona-audio-overlay-ar.dtsi"
 #include "kona-thermal-overlay.dtsi"
 #include "kona-xr-pinctrl-overlay.dtsi"
 #include "camera/kona-camera-sensor-xrfusion.dtsi"
@@ -298,6 +299,78 @@
 				<&bolero>;
 };
 
+&kona_snd_ar {
+	qcom,model = "kona-xrfusion-snd-card";
+	qcom,mi2s-audio-intf = <0>;
+	qcom,audio-routing =
+		"AMIC2", "MIC BIAS2",
+		"MIC BIAS2", "Analog Mic2",
+		"TX DMIC0", "MIC BIAS1",
+		"MIC BIAS1", "Digital Mic0",
+		"TX DMIC1", "MIC BIAS1",
+		"MIC BIAS1", "Digital Mic1",
+		"TX DMIC2", "MIC BIAS4",
+		"MIC BIAS4", "Digital Mic2",
+		"TX DMIC3", "MIC BIAS4",
+		"MIC BIAS4", "Digital Mic3",
+		"TX DMIC5", "MIC BIAS3",
+		"MIC BIAS3", "Digital Mic5",
+		"IN1_HPHL", "HPHL_OUT",
+		"IN2_HPHR", "HPHR_OUT",
+		"IN3_AUX", "AUX_OUT",
+		"TX SWR_ADC0", "ADC1_OUTPUT",
+		"TX SWR_ADC1", "ADC2_OUTPUT",
+		"TX SWR_ADC2", "ADC3_OUTPUT",
+		"TX SWR_ADC3", "ADC4_OUTPUT",
+		"TX SWR_DMIC0", "DMIC1_OUTPUT",
+		"TX SWR_DMIC1", "DMIC2_OUTPUT",
+		"TX SWR_DMIC2", "DMIC3_OUTPUT",
+		"TX SWR_DMIC3", "DMIC4_OUTPUT",
+		"TX SWR_DMIC4", "DMIC5_OUTPUT",
+		"TX SWR_DMIC5", "DMIC6_OUTPUT",
+		"TX SWR_DMIC6", "DMIC7_OUTPUT",
+		"TX SWR_DMIC7", "DMIC8_OUTPUT",
+		"WSA SRC0_INP", "SRC0",
+		"WSA_TX DEC0_INP", "TX DEC0 MUX",
+		"WSA_TX DEC1_INP", "TX DEC1 MUX",
+		"RX_TX DEC0_INP", "TX DEC0 MUX",
+		"RX_TX DEC1_INP", "TX DEC1 MUX",
+		"RX_TX DEC2_INP", "TX DEC2 MUX",
+		"RX_TX DEC3_INP", "TX DEC3 MUX",
+		"SpkrRight IN", "WSA_SPK2 OUT",
+		"VA_AIF1 CAP", "VA_SWR_CLK",
+		"VA_AIF2 CAP", "VA_SWR_CLK",
+		"VA_AIF3 CAP", "VA_SWR_CLK",
+		"VA MIC BIAS3", "Digital Mic0",
+		"VA MIC BIAS3", "Digital Mic1",
+		"VA MIC BIAS1", "Digital Mic2",
+		"VA MIC BIAS1", "Digital Mic3",
+		"VA MIC BIAS4", "Digital Mic5",
+		"VA DMIC0", "VA MIC BIAS3",
+		"VA DMIC1", "VA MIC BIAS3",
+		"VA DMIC2", "VA MIC BIAS1",
+		"VA DMIC3", "VA MIC BIAS1",
+		"VA DMIC5", "VA MIC BIAS4",
+		"VA SWR_ADC1", "VA_SWR_CLK",
+		"VA SWR_MIC0", "VA_SWR_CLK",
+		"VA SWR_MIC1", "VA_SWR_CLK",
+		"VA SWR_MIC2", "VA_SWR_CLK",
+		"VA SWR_MIC3", "VA_SWR_CLK",
+		"VA SWR_MIC4", "VA_SWR_CLK",
+		"VA SWR_MIC5", "VA_SWR_CLK",
+		"VA SWR_MIC6", "VA_SWR_CLK",
+		"VA SWR_MIC7", "VA_SWR_CLK",
+		"VA SWR_MIC0", "DMIC1_OUTPUT",
+		"VA SWR_MIC1", "DMIC2_OUTPUT",
+		"VA SWR_MIC2", "DMIC3_OUTPUT",
+		"VA SWR_MIC3", "DMIC4_OUTPUT",
+		"VA SWR_MIC4", "DMIC5_OUTPUT",
+		"VA SWR_MIC5", "DMIC6_OUTPUT",
+		"VA SWR_MIC6", "DMIC7_OUTPUT",
+		"VA SWR_MIC7", "DMIC8_OUTPUT",
+		"VA SWR_ADC1", "ADC2_OUTPUT";
+};
+
 &pm8150_l10 {
 	regulator-max-microvolt = <3304000>;
 	qcom,init-voltage = <3304000>;
diff --git a/qcom/kona.dtsi b/qcom/kona.dtsi
index 4188793f..70acf6d4 100644
--- a/qcom/kona.dtsi
+++ b/qcom/kona.dtsi
@@ -55,6 +55,9 @@
 		swr0 = &swr0;
 		swr1 = &swr1;
 		swr2 = &swr2;
+		swr_ar0 = &swr_ar0;
+		swr_ar1 = &swr_ar1;
+		swr_ar2 = &swr_ar2;
 		mhi-netdev0 = &mhi_netdev_0;
 	};
 
@@ -4729,6 +4732,7 @@
 		reg-names = "smmu_iova_ipa", "tcs_cmd";
 		wlan-en-gpio = <&tlmm 20 0>;
 		qcom,bt-en-gpio = <&tlmm 21 0>;
+		qcom,sw-ctrl-gpio = <&tlmm 124 0>;
 		pinctrl-names = "wlan_en_active", "wlan_en_sleep";
 		pinctrl-0 = <&cnss_wlan_en_active>;
 		pinctrl-1 = <&cnss_wlan_en_sleep>;
@@ -5058,6 +5062,7 @@
 #include "camera/kona-camera.dtsi"
 #include "kona-qupv3.dtsi"
 #include "kona-audio.dtsi"
+#include "kona-audio-ar.dtsi"
 #include "kona-thermal.dtsi"
 #include "kona-vidc.dtsi"
 #include "kona-cvp.dtsi"
diff --git a/qcom/litomagnus-cdp-overlay.dts b/qcom/litomagnus-cdp-overlay.dts
index 878110c0..9924e3b2 100644
--- a/qcom/litomagnus-cdp-overlay.dts
+++ b/qcom/litomagnus-cdp-overlay.dts
@@ -11,11 +11,3 @@
 	qcom,msm-id = <400 0x20000>, <440 0x20000>;
 	qcom,board-id = <1 1>;
 };
-
-/*
- * overriding adsp-fw-names with empty string
- * to allow default adsp img load
- */
-&adsp_loader {
-	adsp-fw-names="";
-};
diff --git a/qcom/litomagnus-mtp-overlay.dts b/qcom/litomagnus-mtp-overlay.dts
index 58a6b346..4bce6191 100644
--- a/qcom/litomagnus-mtp-overlay.dts
+++ b/qcom/litomagnus-mtp-overlay.dts
@@ -11,11 +11,3 @@
 	qcom,msm-id = <400 0x20000>, <440 0x20000>;
 	qcom,board-id = <8 1>;
 };
-
-/*
- * overriding adsp-fw-names with empty string
- * to allow default adsp img load
- */
-&adsp_loader {
-	adsp-fw-names="";
-};
diff --git a/qcom/msm-arm-smmu-lagoon.dtsi b/qcom/msm-arm-smmu-lagoon.dtsi
index 6d7eabcc..be474f75 100644
--- a/qcom/msm-arm-smmu-lagoon.dtsi
+++ b/qcom/msm-arm-smmu-lagoon.dtsi
@@ -7,6 +7,7 @@
 		reg = <0x3d40000 0x10000>;
 		#iommu-cells = <1>;
 		qcom,use-3-lvl-tables;
+		qcom,no-dynamic-asid;
 		#global-interrupts = <2>;
 		qcom,regulator-names = "vdd";
 		vdd-supply = <&gpu_cx_gdsc>;
diff --git a/qcom/msm-audio-lpass.dtsi b/qcom/msm-audio-lpass.dtsi
index 360e984a..a9496d85 100644
--- a/qcom/msm-audio-lpass.dtsi
+++ b/qcom/msm-audio-lpass.dtsi
@@ -253,6 +253,71 @@
 
 	qcom,msm-dai-q6 {
 		compatible = "qcom,msm-dai-q6";
+		sb_0_rx: qcom,msm-dai-q6-sb-0-rx {
+			compatible = "qcom,msm-dai-q6-dev";
+			qcom,msm-dai-q6-dev-id = <16384>;
+		};
+
+		sb_0_tx: qcom,msm-dai-q6-sb-0-tx {
+			compatible = "qcom,msm-dai-q6-dev";
+			qcom,msm-dai-q6-dev-id = <16385>;
+		};
+
+		sb_1_rx: qcom,msm-dai-q6-sb-1-rx {
+			compatible = "qcom,msm-dai-q6-dev";
+			qcom,msm-dai-q6-dev-id = <16386>;
+		};
+
+		sb_1_tx: qcom,msm-dai-q6-sb-1-tx {
+			compatible = "qcom,msm-dai-q6-dev";
+			qcom,msm-dai-q6-dev-id = <16387>;
+		};
+
+		sb_2_rx: qcom,msm-dai-q6-sb-2-rx {
+			compatible = "qcom,msm-dai-q6-dev";
+			qcom,msm-dai-q6-dev-id = <16388>;
+		};
+
+		sb_2_tx: qcom,msm-dai-q6-sb-2-tx {
+			compatible = "qcom,msm-dai-q6-dev";
+			qcom,msm-dai-q6-dev-id = <16389>;
+		};
+
+		sb_3_rx: qcom,msm-dai-q6-sb-3-rx {
+			compatible = "qcom,msm-dai-q6-dev";
+			qcom,msm-dai-q6-dev-id = <16390>;
+		};
+
+		sb_3_tx: qcom,msm-dai-q6-sb-3-tx {
+			compatible = "qcom,msm-dai-q6-dev";
+			qcom,msm-dai-q6-dev-id = <16391>;
+		};
+
+		sb_4_rx: qcom,msm-dai-q6-sb-4-rx {
+			compatible = "qcom,msm-dai-q6-dev";
+			qcom,msm-dai-q6-dev-id = <16392>;
+		};
+
+		sb_4_tx: qcom,msm-dai-q6-sb-4-tx {
+			compatible = "qcom,msm-dai-q6-dev";
+			qcom,msm-dai-q6-dev-id = <16393>;
+		};
+
+		sb_5_tx: qcom,msm-dai-q6-sb-5-tx {
+			compatible = "qcom,msm-dai-q6-dev";
+			qcom,msm-dai-q6-dev-id = <16395>;
+		};
+
+		sb_5_rx: qcom,msm-dai-q6-sb-5-rx {
+			compatible = "qcom,msm-dai-q6-dev";
+			qcom,msm-dai-q6-dev-id = <16394>;
+		};
+
+		sb_6_rx: qcom,msm-dai-q6-sb-6-rx {
+			compatible = "qcom,msm-dai-q6-dev";
+			qcom,msm-dai-q6-dev-id = <16396>;
+		};
+
 		sb_7_rx: qcom,msm-dai-q6-sb-7-rx {
 			compatible = "qcom,msm-dai-q6-dev";
 			qcom,msm-dai-q6-dev-id = <16398>;
@@ -265,6 +330,11 @@
 			qcom,msm-dai-q6-slim-dev-id = <0>;
 		};
 
+		sb_8_rx: qcom,msm-dai-q6-sb-8-rx {
+			compatible = "qcom,msm-dai-q6-dev";
+			qcom,msm-dai-q6-dev-id = <16400>;
+		};
+
 		sb_8_tx: qcom,msm-dai-q6-sb-8-tx {
 			compatible = "qcom,msm-dai-q6-dev";
 			qcom,msm-dai-q6-dev-id = <16401>;
diff --git a/qcom/msm8917-gpu.dtsi b/qcom/msm8917-gpu.dtsi
index a3ca272e..aa7d4104 100644
--- a/qcom/msm8917-gpu.dtsi
+++ b/qcom/msm8917-gpu.dtsi
@@ -8,21 +8,21 @@
 		compatible = "operating-points-v2";
 		opp-0    { opp-hz = /bits/ 64 < 0 >;     }; /* OFF */
 
-		opp-201  { opp-hz = /bits/ 64 < 769 >;   }; /* 1.  201 MHz */
+		opp-100 { opp-hz = /bits/ 64 < 769 >;   }; /* 1. 100 MHz */
 
-		opp-422  { opp-hz = /bits/ 64 < 1611 >;  }; /* 2.  422 MHz */
+		opp-211 { opp-hz = /bits/ 64 < 1611 >;  }; /* 2. 211 MHz */
 
-		opp-595  { opp-hz = /bits/ 64 < 2270 >;  }; /* 3.  595 MHz */
+		opp-297 { opp-hz = /bits/ 64 < 2270 >;  }; /* 3. 297 MHz */
 
-		opp-768  { opp-hz = /bits/ 64 < 2929 >;  }; /* 4.  768 MHz */
+		opp-384 { opp-hz = /bits/ 64 < 2929 >;  }; /* 4. 384 MHz */
 
-		opp-1113 { opp-hz = /bits/ 64 < 4248 >;  }; /* 5. 1113 MHz */
+		opp-557 { opp-hz = /bits/ 64 < 4248 >;  }; /* 5. 557 MHz */
 
-		opp-1190 { opp-hz = /bits/ 64 < 4541 >;  }; /* 6. 1190 MHz */
+		opp-595 { opp-hz = /bits/ 64 < 4541 >;  }; /* 6. 595 MHz */
 
-		opp-1344 { opp-hz = /bits/ 64 < 5126 >;  }; /* 7. 1344 MHz */
+		opp-672 { opp-hz = /bits/ 64 < 5126 >;  }; /* 7. 672 MHz */
 
-		opp-1478 { opp-hz = /bits/ 64 < 5639 >;  }; /* 8. 1478 MHz */
+		opp-739 { opp-hz = /bits/ 64 < 5639 >;  }; /* 8. 739 MHz */
 	};
 
 	/* Bus governor */
diff --git a/qcom/msm8917-pm.dtsi b/qcom/msm8917-pm.dtsi
index b9288ff7..30978710 100644
--- a/qcom/msm8917-pm.dtsi
+++ b/qcom/msm8917-pm.dtsi
@@ -33,7 +33,7 @@
 				reg = <0>;
 				label = "perf-l2-wfi";
 				qcom,psci-mode = <1>;
-				qcom,entry-latency-us = <38>; /* TBD */
+				qcom,entry-latency-us = <125>;
 				qcom,exit-latency-us = <180>;
 				qcom,min-residency-us = <305>;
 			};
@@ -42,9 +42,9 @@
 				reg = <1>;
 				label = "perf-l2-gdhs";
 				qcom,psci-mode = <4>;
-				qcom,entry-latency-us = <800>; /* TBD */
+				qcom,entry-latency-us = <240>;
 				qcom,exit-latency-us = <280>;
-				qcom,min-residency-us = <520>;
+				qcom,min-residency-us = <806>;
 				qcom,min-child-idx = <1>;
 				qcom,reset-level = <LPM_RESET_LVL_GDHS>;
 			};
@@ -53,9 +53,9 @@
 				reg = <2>;
 				label = "perf-l2-retention";
 				qcom,psci-mode = <2>;
-				qcom,entry-latency-us = <640>; /* TBD */
+				qcom,entry-latency-us = <700>;
 				qcom,exit-latency-us = <650>;
-				qcom,min-residency-us = <1350>;
+				qcom,min-residency-us = <1972>;
 				qcom,min-child-idx = <1>;
 				qcom,reset-level = <LPM_RESET_LVL_RET>;
 			};
@@ -64,9 +64,9 @@
 				reg = <3>;
 				label = "perf-l2-pc";
 				qcom,psci-mode = <5>;
-				qcom,entry-latency-us = <800>; /* TBD */
+				qcom,entry-latency-us = <800>;
 				qcom,exit-latency-us = <11200>;
-				qcom,min-residency-us = <1700>;
+				qcom,min-residency-us = <6501>;
 				qcom,min-child-idx = <1>;
 				qcom,is-reset;
 				qcom,notify-rpm;
@@ -84,7 +84,7 @@
 					reg = <0>;
 					label = "wfi";
 					qcom,psci-cpu-mode = <1>;
-					qcom,entry-latency-us = <49>; /* TBD */
+					qcom,entry-latency-us = <13>;
 					qcom,exit-latency-us = <12>;
 					qcom,min-residency-us = <25>;
 				};
@@ -93,9 +93,9 @@
 					reg = <1>;
 					label = "pc";
 					qcom,psci-cpu-mode = <3>;
-					qcom,entry-latency-us = <290>; /* TBD */
+					qcom,entry-latency-us = <125>;
 					qcom,exit-latency-us = <180>;
-					qcom,min-residency-us = <305>;
+					qcom,min-residency-us = <595>;
 					qcom,use-broadcast-timer;
 					qcom,is-reset;
 					qcom,reset-level = <LPM_RESET_LVL_PC>;
diff --git a/qcom/msm8917-vidc.dtsi b/qcom/msm8917-vidc.dtsi
index 7b1ac1a2..982a9f6f 100644
--- a/qcom/msm8917-vidc.dtsi
+++ b/qcom/msm8917-vidc.dtsi
@@ -114,7 +114,7 @@
 			label = "venus-ddr";
 			qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
 			qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
-			qcom,bus-mode = "venus-ddr";
+			qcom,mode = "venus-ddr";
 			qcom,bus-range-kbps = <1000 917000>;
 		};
 
@@ -123,7 +123,7 @@
 			label = "venus-arm9-ddr";
 			qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
 			qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
-			qcom,bus-mode = "performance";
+			qcom,mode = "performance";
 			qcom,bus-range-kbps = <1 1>;
 		};
 	};
diff --git a/qcom/msm8917.dtsi b/qcom/msm8917.dtsi
index 8628a7b3..037033b8 100644
--- a/qcom/msm8917.dtsi
+++ b/qcom/msm8917.dtsi
@@ -573,7 +573,7 @@
 	};
 
 	debugcc: qcom,cc-debug {
-		compatible = "qcom,msm8917-debugcc";
+		compatible = "qcom,qm215-debugcc";
 		reg = <0x1874000 0x4>,
 		      <0xb01101c 0x8>;
 		reg-names = "cc_base", "meas";
@@ -597,9 +597,10 @@
 		compatible = "qcom,cpu-clock-qm215";
 		reg =   <0xb011050 0x8>,
 			<0xb016000 0x34>,
-			<0x00a412c 0x8>;
+			<0x00a412c 0x8>,
+			<0xb011200 0x100>;
 		reg-names = "apcs-c1-rcg-base",
-			"apcs_pll", "efuse";
+			"apcs_pll1", "efuse", "spm_c1_base";
 		cpu-vdd-supply = <&apc_vreg_corner>;
 		vdd_dig_ao-supply = <&pm8916_s1_level_ao>;
 		vdd_hf_pll-supply = <&pm8916_l7_ao>;
diff --git a/qcom/msm8937-audio.dtsi b/qcom/msm8937-audio.dtsi
index 14701d6b..fbf539af 100644
--- a/qcom/msm8937-audio.dtsi
+++ b/qcom/msm8937-audio.dtsi
@@ -183,7 +183,7 @@
 		compatible = "qcom,audio-ref-clk";
 		qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
 		qcom,codec-lpass-ext-clk-freq = <9600000>;
-		qcom,codec-lpass-clk-id = <0x301>;
+		qcom,codec-lpass-clk-id = <0x300>;
 		#clock-cells = <1>;
 	};
 
@@ -257,23 +257,16 @@
 
 		asoc-cpu = <&dai_pri_auxpcm>,
 				<&dai_mi2s2>, <&dai_mi2s3>, <&dai_mi2s5>,
-			/* TBD
-			 * <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>,
-			 * <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>,
-			 * <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>,
-			 */
+				<&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>,
+				<&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>,
+				<&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>,
 				<&afe_pcm_rx>, <&afe_pcm_tx>,
 				<&afe_proxy_rx>, <&afe_proxy_tx>,
 				<&incall_record_rx>, <&incall_record_tx>,
 				<&incall_music_rx>, <&incall_music_2_rx>,
-				/* TBD
-				 * <&sb_5_rx>, <&bt_sco_rx>, <&bt_sco_tx>,
-				 */
-				<&int_fm_rx>, <&int_fm_tx>;
-				/* TBD
-				 * , <&sb_6_rx>,
-				 * <&proxy_rx>, <&proxy_tx>;
-				 */
+				<&sb_5_rx>, <&bt_sco_rx>, <&bt_sco_tx>,
+				<&int_fm_rx>, <&int_fm_tx>, <&sb_6_rx>,
+				<&proxy_rx>, <&proxy_tx>;
 
 		asoc-cpu-names = "msm-dai-q6-auxpcm.1",
 				"msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3",
@@ -289,10 +282,8 @@
 				"msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770",
 				"msm-dai-q6-dev.16394", "msm-dai-q6-dev.12288",
 				"msm-dai-q6-dev.12289", "msm-dai-q6-dev.12292",
-				"msm-dai-q6-dev.12293", "msm-dai-q6-dev.16396";
-				/* TBD
-				 * "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195";
-				 */
+				"msm-dai-q6-dev.12293", "msm-dai-q6-dev.16396",
+				"msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195";
 
 		asoc-codec = <&stub_codec>, <&hdmi_dba>;
 		asoc-codec-names = "msm-stub-codec.1", "msm-hdmi-dba-codec-rx";
@@ -322,6 +313,8 @@
 	clock_audio: audio_ext_clk {
 		status = "disabled";
 		compatible = "qcom,audio-ref-clk";
+		qcom,use-pinctrl = <1>;
+		qcom,codec-ext-clk-src = <14>;
 		clock-names = "osr_clk";
 		qcom,node_has_rpm_clock;
 		#clock-cells = <1>;
@@ -364,10 +357,8 @@
 		qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>;
 
 		clock-names = "wcd_clk", "wcd_native_clk";
-		/* TODO
-		 * clocks = < &clock_audio clk_audio_pmi_clk>,
-		 * <&clock_audio clk_audio_ap_clk2>;
-		 */
+		clocks = < &clock_audio 0>,
+			<&clock_audio_native 0>;
 
 		qcom,cdc-static-supplies =
 				"cdc-vdd-buck",
diff --git a/qcom/msm8937-camera.dtsi b/qcom/msm8937-camera.dtsi
index 16120ab7..98ed0d54 100644
--- a/qcom/msm8937-camera.dtsi
+++ b/qcom/msm8937-camera.dtsi
@@ -306,6 +306,7 @@
 			compatible = "qcom,msm-cam-smmu-cb";
 			iommus = <&apps_iommu 0x400 0x00>,
 				<&apps_iommu 0x2400 0x00>;
+			iommu-cells = <2>;
 			qcom,iommu-dma-addr-pool = <0x10000000 0x70000000>;
 			label = "vfe";
 			qcom,scratch-buf-support;
@@ -314,6 +315,7 @@
 		msm_cam_smmu_cb3: msm_cam_smmu_cb3 {
 			compatible = "qcom,msm-cam-smmu-cb";
 			iommus = <&apps_iommu 0x1c00 0x00>;
+			iommu-cells = <2>;
 			qcom,iommu-dma-addr-pool = <0x00020000 0x78000000>;
 			label = "cpp";
 		};
@@ -321,6 +323,7 @@
 		msm_cam_smmu_cb4: msm_cam_smmu_cb4 {
 			compatible = "qcom,msm-cam-smmu-cb";
 			iommus = <&apps_iommu 0x1800 0x00>;
+			iommu-cells = <2>;
 			qcom,iommu-dma-addr-pool = <0x00020000 0x78000000>;
 			label = "jpeg_enc0";
 		};
diff --git a/qcom/msm8937-coresight.dtsi b/qcom/msm8937-coresight.dtsi
index cbaa44a9..68477095 100644
--- a/qcom/msm8937-coresight.dtsi
+++ b/qcom/msm8937-coresight.dtsi
@@ -1,7 +1,7 @@
 &soc {
 	tmc_etr: tmc@6028000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b961>;
+		arm,primecell-periphid = <0x000bb961>;
 
 		reg = <0x6028000 0x1000>,
 				<0x6044000 0x15000>;
@@ -10,9 +10,9 @@
 		interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "byte-cntr-irq";
 
-		arm,buffer-size = <0x100000>;
-		arm,sg-enable;
+		arm,buffer-size = <0x400000>;
 		qcom,force-reg-dump;
+		arm,scatter-gather;
 
 		coresight-name = "coresight-tmc-etr";
 		coresight-csr = <&csr>;
@@ -32,7 +32,7 @@
 
 	tmc_etf: tmc@6027000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b961>;
+		arm,primecell-periphid = <0x000bb961>;
 
 		reg = <0x6027000 0x1000>;
 		reg-names = "tmc-base";
@@ -73,7 +73,7 @@
 
 	replicator: replicator@6026000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b909>;
+		arm,primecell-periphid = <0x000bb909>;
 
 		reg = <0x6026000 0x1000>;
 		reg-names = "replicator-base";
@@ -108,7 +108,7 @@
 
 	funnel_in0: funnel@6021000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b908>;
+		arm,primecell-periphid = <0x000bb908>;
 
 		reg = <0x6021000 0x1000>;
 		reg-names = "funnel-base";
@@ -178,7 +178,7 @@
 
 	funnel_center: funnel@6100000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b908>;
+		arm,primecell-periphid = <0x000bb908>;
 
 		reg = <0x6100000 0x1000>;
 		reg-names = "funnel-base";
@@ -222,7 +222,7 @@
 
 	funnel_right: funnel@6120000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b908>;
+		arm,primecell-periphid = <0x000bb908>;
 
 		reg = <0x6120000 0x1000>;
 		reg-names = "funnel-base";
@@ -266,7 +266,7 @@
 
 	funnel_mm: funnel@6130000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b908>;
+		arm,primecell-periphid = <0x000bb908>;
 
 		reg = <0x6130000 0x1000>;
 		reg-names = "funnel-base";
@@ -327,7 +327,7 @@
 
 	funnel_cam: funnel@6132000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b908>;
+		arm,primecell-periphid = <0x000bb908>;
 
 		reg = <0x6132000 0x1000>;
 		reg-names = "funnel-base";
@@ -347,7 +347,7 @@
 
 	funnel_apss: funnel@61a1000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b908>;
+		arm,primecell-periphid = <0x000bb908>;
 
 		reg = <0x61a1000 0x1000>;
 		reg-names = "funnel-base";
@@ -613,7 +613,7 @@
 
 	stm: stm@6002000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b962>;
+		arm,primecell-periphid = <0x000bb962>;
 
 		reg = <0x6002000 0x1000>,
 		      <0x9280000 0x180000>;
@@ -634,7 +634,7 @@
 
 	cti0: cti@6010000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x6010000 0x1000>;
 		reg-names = "cti-base";
@@ -647,7 +647,7 @@
 
 	cti1: cti@6011000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x6011000 0x1000>;
 		reg-names = "cti-base";
@@ -660,7 +660,7 @@
 
 	cti2: cti@6012000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x6012000 0x1000>;
 		reg-names = "cti-base";
@@ -673,7 +673,7 @@
 
 	cti3: cti@6013000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x6013000 0x1000>;
 		reg-names = "cti-base";
@@ -686,7 +686,7 @@
 
 	cti4: cti@6014000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x6014000 0x1000>;
 		reg-names = "cti-base";
@@ -699,7 +699,7 @@
 
 	cti5: cti@6015000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x6015000 0x1000>;
 		reg-names = "cti-base";
@@ -712,7 +712,7 @@
 
 	cti6: cti@6016000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x6016000 0x1000>;
 		reg-names = "cti-base";
@@ -725,7 +725,7 @@
 
 	cti7: cti@6017000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x6017000 0x1000>;
 		reg-names = "cti-base";
@@ -738,7 +738,7 @@
 
 	cti8: cti@6018000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x6018000 0x1000>;
 		reg-names = "cti-base";
@@ -751,7 +751,7 @@
 
 	cti9: cti@6019000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x6019000 0x1000>;
 		reg-names = "cti-base";
@@ -764,7 +764,7 @@
 
 	cti10: cti@601a000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x601a000 0x1000>;
 		reg-names = "cti-base";
@@ -777,7 +777,7 @@
 
 	cti11: cti@601b000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x601b000 0x1000>;
 		reg-names = "cti-base";
@@ -790,7 +790,7 @@
 
 	cti12: cti@601c000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x601c000 0x1000>;
 		reg-names = "cti-base";
@@ -803,7 +803,7 @@
 
 	cti13: cti@601d000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x601d000 0x1000>;
 		reg-names = "cti-base";
@@ -816,7 +816,7 @@
 
 	cti14: cti@601e000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x601e000 0x1000>;
 		reg-names = "cti-base";
@@ -829,7 +829,7 @@
 
 	cti15: cti@601f000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x601f000 0x1000>;
 		reg-names = "cti-base";
@@ -842,7 +842,7 @@
 
 	cti_cpu0: cti@61b8000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x61b8000 0x1000>;
 		reg-names = "cti-base";
@@ -857,7 +857,7 @@
 
 	cti_cpu1: cti@61b9000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x61b9000 0x1000>;
 		reg-names = "cti-base";
@@ -872,7 +872,7 @@
 
 	cti_cpu2: cti@61ba000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x61ba000 0x1000>;
 		reg-names = "cti-base";
@@ -887,7 +887,7 @@
 
 	cti_cpu3: cti@61bb000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x61bb000 0x1000>;
 		reg-names = "cti-base";
@@ -902,7 +902,7 @@
 
 	cti_cpu4: cti@6198000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x6198000 0x1000>;
 		reg-names = "cti-base";
@@ -917,7 +917,7 @@
 
 	cti_cpu5: cti@6199000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x6199000 0x1000>;
 		reg-names = "cti-base";
@@ -932,7 +932,7 @@
 
 	cti_cpu6: cti@619a000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x619a000 0x1000>;
 		reg-names = "cti-base";
@@ -947,7 +947,7 @@
 
 	cti_cpu7: cti@619b000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x619b000 0x1000>;
 		reg-names = "cti-base";
@@ -962,7 +962,7 @@
 
 	cti_modem_cpu0: cti@6124000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x6124000 0x1000>;
 		reg-names = "cti-base";
@@ -976,7 +976,7 @@
 	/* Venus CTI */
 	cti_video_cpu0: cti@6035000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x6035000 0x1000>;
 		reg-names = "cti-base";
@@ -991,7 +991,7 @@
 	/* Pronto CTI */
 	cti_wcn_cpu0: cti@6039000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x6039000 0x1000>;
 		reg-names = "cti-base";
@@ -1006,7 +1006,7 @@
 	/* LPASS CTI */
 	cti_audio_cpu0: cti@613c000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x613c000 0x1000>;
 		reg-names = "cti-base";
@@ -1019,7 +1019,7 @@
 
 	cti_rpm_cpu0: cti@610c000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x610c000 0x1000>;
 		reg-names = "cti-base";
@@ -1122,7 +1122,7 @@
 
 	tpda: tpda@6003000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b969>;
+		arm,primecell-periphid = <0x000bb969>;
 
 		reg = <0x6003000 0x1000>;
 		reg-names = "tpda-base";
@@ -1158,7 +1158,7 @@
 
 	tpdm_dcc: tpdm@6110000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b968>;
+		arm,primecell-periphid = <0x000bb968>;
 
 		reg = <0x6110000 0x1000>;
 		reg-names = "tpdm-base";
diff --git a/qcom/msm8937-interposer-sdm429.dtsi b/qcom/msm8937-interposer-sdm429.dtsi
index 85cd896b..c05f0135 100644
--- a/qcom/msm8937-interposer-sdm429.dtsi
+++ b/qcom/msm8937-interposer-sdm429.dtsi
@@ -1,6 +1,15 @@
 #include "msm8937-interposer-sdm439.dtsi"
 #include "sdm429-cpu.dtsi"
 
+&apsscc {
+	qcom,cpu-isolation {
+		/delete-node/ cpu4-isolate;
+		/delete-node/ cpu5-isolate;
+		/delete-node/ cpu6-isolate;
+		/delete-node/ cpu7-isolate;
+	};
+};
+
 &soc {
 	/delete-node/ etm@619c000;
 	/delete-node/ etm@619d000;
diff --git a/qcom/msm8937-interposer-sdm439.dtsi b/qcom/msm8937-interposer-sdm439.dtsi
index 543e3632..4c9e5127 100644
--- a/qcom/msm8937-interposer-sdm439.dtsi
+++ b/qcom/msm8937-interposer-sdm439.dtsi
@@ -159,9 +159,9 @@
 		qcom,cpr-enable;
 	};
 
-	qcom,cpu-clock-8939@b111050 {
+	qcom,clock-cpu@b111050 {
 		vdd-c0-supply = <&apc_vreg_corner>;
-		vdd-c1-supply = <&apc_vreg_corner>;
+		cpu-vdd-supply = <&apc_vreg_corner>;
 		vdd-cci-supply = <&apc_vreg_corner>;
 	};
 };
diff --git a/qcom/msm8937-pm.dtsi b/qcom/msm8937-pm.dtsi
index 69fe3b9d..0f2d91ff 100644
--- a/qcom/msm8937-pm.dtsi
+++ b/qcom/msm8937-pm.dtsi
@@ -37,8 +37,7 @@
 				reg = <0>;
 				label = "system-active";
 				qcom,psci-mode = <0>;
-				/* TBD */
-				qcom,entry-latency-us = <640>;
+				qcom,entry-latency-us = <565>;
 				qcom,exit-latency-us = <415>;
 				qcom,min-residency-us = <980>;
 			};
@@ -47,10 +46,9 @@
 				reg = <1>;
 				label = "system-wfi";
 				qcom,psci-mode = <1>;
-				/* TBD */
-				qcom,entry-latency-us = <38>;
+				qcom,entry-latency-us = <575>;
 				qcom,exit-latency-us = <475>;
-				qcom,min-residency-us = <1050>;
+				qcom,min-residency-us = <3288>;
 				qcom,min-child-idx = <1>;
 			};
 
@@ -58,10 +56,9 @@
 				reg = <2>;
 				label = "system-ret";
 				qcom,psci-mode = <2>;
-				/* TBD */
-				qcom,entry-latency-us = <640>;
+				qcom,entry-latency-us = <350>;
 				qcom,exit-latency-us = <900>;
-				qcom,min-residency-us = <1250>;
+				qcom,min-residency-us = <6272>;
 				qcom,min-child-idx = <1>;
 				qcom,reset-level = <LPM_RESET_LVL_RET>;
 			};
@@ -70,10 +67,9 @@
 				reg = <3>;
 				label = "system-pc";
 				qcom,psci-mode = <3>;
-				/* TBD */
-				qcom,entry-latency-us = <800>;
+				qcom,entry-latency-us = <644>;
 				qcom,exit-latency-us = <10782>;
-				qcom,min-residency-us = <1426>;
+				qcom,min-residency-us = <7500>;
 				qcom,min-child-idx = <2>;
 				qcom,notify-rpm;
 				qcom,is-reset;
@@ -92,8 +88,7 @@
 					reg = <0>;
 					label = "perf-l2-wfi";
 					qcom,psci-mode = <1>;
-					/* TBD */
-					qcom,entry-latency-us = <38>;
+					qcom,entry-latency-us = <116>;
 					qcom,exit-latency-us = <210>;
 					qcom,min-residency-us = <326>;
 				};
@@ -102,10 +97,9 @@
 					reg = <1>;
 					label = "perf-l2-gdhs";
 					qcom,psci-mode = <4>;
-					/* TBD */
-					qcom,entry-latency-us = <640>;
+					qcom,entry-latency-us = <360>;
 					qcom,exit-latency-us = <267>;
-					qcom,min-residency-us = <627>;
+					qcom,min-residency-us = <967>;
 					qcom,min-child-idx = <1>;
 					qcom,reset-level = <LPM_RESET_LVL_GDHS>;
 				};
@@ -114,10 +108,9 @@
 					reg = <2>;
 					label = "perf-l2-pc";
 					qcom,psci-mode = <5>;
-					/* TBD */
-					qcom,entry-latency-us = <800>;
+					qcom,entry-latency-us = <574>;
 					qcom,exit-latency-us = <305>;
-					qcom,min-residency-us = <879>;
+					qcom,min-residency-us = <3118>;
 					qcom,min-child-idx = <1>;
 					qcom,is-reset;
 					qcom,reset-level = <LPM_RESET_LVL_PC>;
@@ -134,8 +127,7 @@
 						reg = <0>;
 						qcom,psci-cpu-mode = <0>;
 						label = "wfi";
-						/* TBD */
-						qcom,entry-latency-us = <49>;
+						qcom,entry-latency-us = <66>;
 						qcom,exit-latency-us = <1>;
 						qcom,min-residency-us = <67>;
 					};
@@ -144,10 +136,9 @@
 						reg = <1>;
 						qcom,psci-cpu-mode = <3>;
 						label = "pc";
-						/* TBD */
-						qcom,entry-latency-us = <290>;
+						qcom,entry-latency-us = <136>;
 						qcom,exit-latency-us = <190>;
-						qcom,min-residency-us = <326>;
+						qcom,min-residency-us = <901>;
 						qcom,use-broadcast-timer;
 						qcom,is-reset;
 						qcom,reset-level =
@@ -168,8 +159,7 @@
 					reg = <0>;
 					label = "pwr-l2-wfi";
 					qcom,psci-mode = <1>;
-					/* TBD */
-					qcom,entry-latency-us = <38>;
+					qcom,entry-latency-us = <179>;
 					qcom,exit-latency-us = <221>;
 					qcom,min-residency-us = <400>;
 				};
@@ -178,10 +168,9 @@
 					reg = <1>;
 					label = "pwr-l2-gdhs";
 					qcom,psci-mode = <4>;
-					/* TBD */
-					qcom,entry-latency-us = <640>;
+					qcom,entry-latency-us = <380>;
 					qcom,exit-latency-us = <337>;
-					qcom,min-residency-us = <717>;
+					qcom,min-residency-us = <981>;
 					qcom,min-child-idx = <1>;
 					qcom,reset-level =
 						<LPM_RESET_LVL_GDHS>;
@@ -191,10 +180,9 @@
 					reg = <2>;
 					label = "pwr-l2-pc";
 					qcom,psci-mode = <5>;
-					/* TBD */
-					qcom,entry-latency-us = <800>;
+					qcom,entry-latency-us = <565>;
 					qcom,exit-latency-us = <415>;
-					qcom,min-residency-us = <980>;
+					qcom,min-residency-us = <3561>;
 					qcom,min-child-idx = <1>;
 					qcom,is-reset;
 					qcom,reset-level =
@@ -212,8 +200,7 @@
 						reg = <0>;
 						qcom,psci-cpu-mode = <0>;
 						label = "wfi";
-						/* TBD */
-						qcom,entry-latency-us = <49>;
+						qcom,entry-latency-us = <56>;
 						qcom,exit-latency-us = <1>;
 						qcom,min-residency-us = <57>;
 					};
@@ -222,10 +209,9 @@
 						reg = <1>;
 						qcom,psci-cpu-mode = <3>;
 						label = "pc";
-						/* TBD */
-						qcom,entry-latency-us = <290>;
+						qcom,entry-latency-us = <179>;
 						qcom,exit-latency-us = <221>;
-						qcom,min-residency-us = <400>;
+						qcom,min-residency-us = <401>;
 						qcom,use-broadcast-timer;
 						qcom,is-reset;
 						qcom,reset-level =
diff --git a/qcom/msm8937-thermal.dtsi b/qcom/msm8937-thermal.dtsi
index 28788978..d7a05a55 100644
--- a/qcom/msm8937-thermal.dtsi
+++ b/qcom/msm8937-thermal.dtsi
@@ -1,6 +1,6 @@
 #include <dt-bindings/thermal/thermal.h>
 
-&clock_cpu {
+&apsscc {
 	qcom,cpu-isolation {
 		compatible = "qcom,cpu-isolate";
 		cpu0_isolate: cpu0-isolate {
diff --git a/qcom/msm8937-vidc.dtsi b/qcom/msm8937-vidc.dtsi
index bea37e1e..fe387d30 100644
--- a/qcom/msm8937-vidc.dtsi
+++ b/qcom/msm8937-vidc.dtsi
@@ -115,7 +115,7 @@
 			label = "venus-ddr";
 			qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
 			qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
-			qcom,bus-mode = "venus-ddr";
+			qcom,mode = "venus-ddr";
 			qcom,bus-range-kbps = <1000 917000>;
 		};
 
@@ -124,7 +124,7 @@
 			label = "venus-arm9-ddr";
 			qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
 			qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
-			qcom,bus-mode = "performance";
+			qcom,mode = "performance";
 			qcom,bus-range-kbps = <1 1>;
 		};
 	};
diff --git a/qcom/msm8937.dtsi b/qcom/msm8937.dtsi
index 8e26d756..dfacaa50 100644
--- a/qcom/msm8937.dtsi
+++ b/qcom/msm8937.dtsi
@@ -3,6 +3,7 @@
 #include <dt-bindings/spmi/spmi.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-sdm429w.h>
+#include <dt-bindings/clock/qcom,cpu-sdm.h>
 #include <dt-bindings/clock/qcom,rpmcc.h>
 #include <dt-bindings/clock/mdss-28nm-pll-clk-legacy.h>
 
@@ -584,12 +585,15 @@
 		#reset-cells = <1>;
 	};
 
+	cpu_debug: syscon@0b11101c {
+		compatible = "syscon";
+		reg = <0xb11101c 0x4>;
+	};
+
 	debugcc: qcom,cc-debug {
-		compatible = "qcom,msm8937-debugcc";
-		reg = <0x1874000 0x4>,
-			<0xb11101c 0x8>;
-		reg-names = "cc_base", "meas";
+		compatible = "qcom,sdm439-debugcc";
 		qcom,gcc = <&gcc>;
+		qcom,cpu = <&cpu_debug>;
 		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
 		clock-names = "xo_clk_src";
 		#clock-cells = <1>;
@@ -607,17 +611,19 @@
 		#clock-cells = <1>;
 	};
 
-	clock_cpu: qcom,cpu-clock-8939@b111050 {
-		compatible = "qcom,cpu-clock-8939";
+	apsscc: qcom,clock-cpu@b111050 {
+		compatible = "qcom,cpu-clock-sdm439";
 		reg =   <0xb011050 0x8>,
-			<0xb111050 0x8>,
+			<0xb016000 0x34>,
+			<0xb011200 0x100>,
 			<0xb1d1050 0x8>,
+			<0xb111050 0x8>,
+			<0xb116000 0x34>,
+			<0xb111200 0x100>,
 			<0x00a412c 0x8>;
-		reg-names = "apcs-c1-rcg-base", "apcs-c0-rcg-base",
-				"apcs-cci-rcg-base", "efuse";
-		vdd-c0-supply = <&apc_vreg_corner>;
-		vdd-c1-supply = <&apc_vreg_corner>;
-		vdd-cci-supply = <&apc_vreg_corner>;
+		reg-names = "apcs-c1-rcg-base", "apcs_pll1", "spm_c1_base",
+			"apcs-cci-rcg-base", "apcs-c0-rcg-base",
+			"apcs_pll0", "spm_c0_base", "efuse";
 		clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
 			<&gcc GPLL0_AO_OUT_MAIN>;
 		clock-names = "xo_ao", "gpll0_ao" ;
@@ -878,20 +884,10 @@
 
 	msm_cpufreq: qcom,msm-cpufreq {
 		compatible = "qcom,msm-cpufreq";
-		clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk",
-				"cpu3_clk", "cpu4_clk", "cpu5_clk",
-				"cpu6_clk", "cpu7_clk";
-		/* TODO
-		 *clocks = <&clock_cpu clk_cci_clk>,
-		 * <&clock_cpu clk_a53_bc_clk>,
-		 * <&clock_cpu clk_a53_bc_clk>,
-		 * <&clock_cpu clk_a53_bc_clk>,
-		 * <&clock_cpu clk_a53_bc_clk>,
-		 * <&clock_cpu clk_a53_lc_clk>,
-		 * <&clock_cpu clk_a53_lc_clk>,
-		 * <&clock_cpu clk_a53_lc_clk>,
-		 * <&clock_cpu clk_a53_lc_clki>;
-		 */
+		clocks = <&apsscc APCS_MUX_CCI_CLK>,
+			<&apsscc APCS_MUX_C1_CLK>,
+			<&apsscc APCS_MUX_C0_CLK>;
+		clock-names = "l2_clk", "cpu0_clk", "cpu4_clk";
 
 		qcom,governor-per-policy;
 
@@ -915,9 +911,7 @@
 	cci_cache: qcom,cci {
 		compatible = "devfreq-simple-dev";
 		clock-names = "devfreq_clk";
-		/* TODO
-		 * clocks = <&clock_cpu clk_cci_clk/>;
-		 */
+		clocks = <&apsscc APCS_MUX_CCI_CLK>;
 		governor = "performance";
 		freq-tbl-khz =
 			<  400000 >,
@@ -956,7 +950,16 @@
 		qcom,target-dev = <&cpu_cpu_ddr_bw>;
 	};
 
-	cpu_cpu_ddr_latfloor: qcom,cpu-cpu-ddr-latfloor {
+	cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
+		compatible = "qcom,devbw";
+		governor = "performance";
+		qcom,src-dst-ports =
+			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+		qcom,active-only;
+		operating-points-v2 = <&ddr_bw_opp_table>;
+	};
+
+	cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {
 		compatible = "qcom,devbw";
 		governor = "performance";
 		qcom,src-dst-ports =
@@ -972,7 +975,7 @@
 		cpu0_computemon: qcom,cpu0-computemon {
 			compatible = "qcom,arm-compute-mon";
 			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
-			qcom,target-dev = <&cpu_cpu_ddr_latfloor>;
+			qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
 			qcom,core-dev-table =
 				< 1094400 MHZ_TO_MBPS(384, 8) >,
 				< 1497600 MHZ_TO_MBPS(557, 8) >;
@@ -986,7 +989,7 @@
 		cpu4_computemon: qcom,cpu4-computemon {
 			compatible = "qcom,arm-compute-mon";
 			qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
-			qcom,target-dev = <&cpu_cpu_ddr_latfloor>;
+			qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
 			qcom,core-dev-table =
 				<  998400 MHZ_TO_MBPS(384, 8) >,
 				< 1209600 MHZ_TO_MBPS(557, 8) >;
@@ -1042,6 +1045,7 @@
 	rpm_bus: qcom,rpm-smd {
 		compatible = "qcom,rpm-smd";
 		rpm-channel-name = "rpm_requests";
+		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 		rpm-channel-type = <15>; /* SMD_APPS_RPM */
 	};
 
@@ -1061,7 +1065,6 @@
 		HSUSB_1p8-supply = <&pm8937_l7>;
 		HSUSB_3p3-supply = <&pm8937_l13>;
 		qcom,vdd-voltage-level = <0 1200000 1200000>;
-		vbus_otg-supply = <&smbcharger_charger_otg>;
 
 		qcom,hsusb-otg-phy-type = <3>; /* SNPS Femto PHY */
 		qcom,hsusb-otg-mode = <3>; /* OTG mode */
@@ -2176,6 +2179,9 @@
 
 		qcom,snoc-wcnss-clock-freq = <200000000>;
 
+		qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>, <&apps_smsm 12>;
+		qcom,smem-state-names = "tx-enable", "tx-rings-empty", "wake-state";
+
 		qcom,has-autodetect-xo;
 		qcom,is-pronto-v3;
 		qcom,has-pronto-hw;
diff --git a/qcom/pm7250b.dtsi b/qcom/pm7250b.dtsi
index c92a2faa..5f6a40a2 100644
--- a/qcom/pm7250b.dtsi
+++ b/qcom/pm7250b.dtsi
@@ -34,6 +34,8 @@
 				3500000 3000000 2500000 2000000 1500000
 				1000000 500000>;
 			qcom,pmic-revid = <&pm7250b_revid>;
+			qcom,hvdcp2-max-icl-ua = <2000000>;
+			qcom,hvdcp2-12v-max-icl-ua = <1500000>;
 
 			qcom,chgr@1000 {
 				reg = <0x1000 0x100>;
diff --git a/qcom/pm8008.dtsi b/qcom/pm8008.dtsi
index 07c8824e..f4fc4e88 100644
--- a/qcom/pm8008.dtsi
+++ b/qcom/pm8008.dtsi
@@ -67,7 +67,7 @@ pm8008_9: qcom,pm8008@9 {
 			regulator-min-microvolt = <528000>;
 			regulator-max-microvolt = <1504000>;
 			qcom,min-dropout-voltage = <225000>;
-			qcom,hpm-min-load = <10000>;
+			qcom,hpm-min-load = <0>;
 		};
 
 		L2P: qcom,pm8008-l2@4100 {
@@ -76,7 +76,7 @@ pm8008_9: qcom,pm8008@9 {
 			regulator-min-microvolt = <528000>;
 			regulator-max-microvolt = <1504000>;
 			qcom,min-dropout-voltage = <225000>;
-			qcom,hpm-min-load = <10000>;
+			qcom,hpm-min-load = <0>;
 		};
 
 		L3P: qcom,pm8008-l3@4200 {
@@ -85,7 +85,7 @@ pm8008_9: qcom,pm8008@9 {
 			regulator-min-microvolt = <1500000>;
 			regulator-max-microvolt = <3400000>;
 			qcom,min-dropout-voltage = <200000>;
-			qcom,hpm-min-load = <10000>;
+			qcom,hpm-min-load = <0>;
 		};
 
 		L4P: qcom,pm8008-l4@4300 {
@@ -94,7 +94,7 @@ pm8008_9: qcom,pm8008@9 {
 			regulator-min-microvolt = <1500000>;
 			regulator-max-microvolt = <3400000>;
 			qcom,min-dropout-voltage = <200000>;
-			qcom,hpm-min-load = <10000>;
+			qcom,hpm-min-load = <0>;
 		};
 
 		L5P: qcom,pm8008-l5@4400 {
@@ -103,7 +103,7 @@ pm8008_9: qcom,pm8008@9 {
 			regulator-min-microvolt = <1500000>;
 			regulator-max-microvolt = <3400000>;
 			qcom,min-dropout-voltage = <300000>;
-			qcom,hpm-min-load = <10000>;
+			qcom,hpm-min-load = <0>;
 		};
 
 		L6P: qcom,pm8008-l6@4400 {
@@ -112,7 +112,7 @@ pm8008_9: qcom,pm8008@9 {
 			regulator-min-microvolt = <1500000>;
 			regulator-max-microvolt = <3400000>;
 			qcom,min-dropout-voltage = <300000>;
-			qcom,hpm-min-load = <10000>;
+			qcom,hpm-min-load = <0>;
 		};
 
 		L7P: qcom,pm8008-l7@4400 {
@@ -121,7 +121,7 @@ pm8008_9: qcom,pm8008@9 {
 			regulator-min-microvolt = <1500000>;
 			regulator-max-microvolt = <3400000>;
 			qcom,min-dropout-voltage = <300000>;
-			qcom,hpm-min-load = <10000>;
+			qcom,hpm-min-load = <0>;
 		};
 	};
 };
diff --git a/qcom/pm8916.dtsi b/qcom/pm8916.dtsi
index 2ceae733..f5059b43 100644
--- a/qcom/pm8916.dtsi
+++ b/qcom/pm8916.dtsi
@@ -1,3 +1,4 @@
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/spmi/spmi.h>
 
@@ -76,63 +77,67 @@
 		pm8916_vadc: vadc@3100 {
 			compatible = "qcom,spmi-vadc";
 			reg = <0x3100 0x100>;
+			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
-			interrupt-names = "eoc-int-en-set";
-			qcom,adc-bit-resolution = <15>;
-			qcom,adc-vdd-reference = <1800>;
-			qcom,vadc-poll-eoc;
-			qcom,pmic-revid = <&pm8916_revid>;
-			#thermal-sensor-cells = <1>;
+			#io-channel-cells = <1>;
 
-			chan@8 {
+			die_temp {
+				reg = <VADC_DIE_TEMP>;
 				label = "die_temp";
-				reg = <8>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "absolute";
-				qcom,scale-function = <3>;
-				qcom,hw-settle-time = <0>;
-				qcom,fast-avg-setup = <0>;
+				qcom,pre-scaling = <1 1>;
 			};
 
-			chan@9 {
+			ref_625mv {
+				reg = <VADC_REF_625MV>;
 				label = "ref_625mv";
-				reg = <9>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "absolute";
-				qcom,scale-function = <0>;
-				qcom,hw-settle-time = <0>;
-				qcom,fast-avg-setup = <0>;
+				qcom,pre-scaling = <1 1>;
 			};
 
-			chan@a {
+			ref_1250v {
+				reg = <VADC_REF_1250MV>;
 				label = "ref_1250v";
-				reg = <0xa>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "absolute";
-				qcom,scale-function = <0>;
-				qcom,hw-settle-time = <0>;
-				qcom,fast-avg-setup = <0>;
+				qcom,pre-scaling = <1 1>;
+			};
+
+			ref_buf_625mv {
+				reg = <VADC_SPARE1>;
+				label = "ref_buf_625mv";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			ref_vdd {
+				reg = <VADC_VDD_VADC>;
+				label = "ref_vdd";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			ref_gnd {
+				reg = <VADC_GND_REF>;
+				label = "ref_gnd";
+				qcom,pre-scaling = <1 1>;
 			};
 		};
 
-		pm8916_tz: qcom,temp-alarm@2400 {
+		pm8916_tz: temp-alarm@2400 {
 			compatible = "qcom,spmi-temp-alarm";
 			reg = <0x2400 0x100>;
-			interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
-			label = "pm8916_tz";
-			qcom,channel-num = <8>;
-			qcom,threshold-set = <0>;
-			qcom,temp_alarm-vadc = <&pm8916_vadc>;
+			interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
+			io-channels = <&pm8916_vadc VADC_DIE_TEMP>;
+			io-channel-names = "thermal";
 			#thermal-sensor-cells = <0>;
 		};
 
+		pm8916_adc_tm_iio: adc_tm_iio {
+			compatible = "qcom,adc-tm5-iio";
+			reg = <0x3500 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#thermal-sensor-cells = <1>;
+		};
+
 		pm8916_adc_tm: vadc@3400 {
-			compatible = "qcom,adc-tm-rev2";
+			compatible = "qcom,qpnp-adc-tm";
 			reg = <0x3400 0x100>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -142,10 +147,15 @@
 			interrupt-names = "eoc-int-en-set",
 					  "high-thr-en-set",
 					  "low-thr-en-set";
-			qcom,adc-bit-resolution = <15>;
 			qcom,adc-vdd-reference = <1800>;
-			qcom,adc_tm-vadc = <&pm8916_vadc>;
+			#thermal-sensor-cells = <1>;
 			qcom,pmic-revid = <&pm8916_revid>;
+			io-channels = <&pm8916_vadc VADC_REF_625MV>,
+					<&pm8916_vadc VADC_REF_1250MV>,
+					<&pm8916_vadc VADC_VDD_VADC>,
+					<&pm8916_vadc VADC_GND_REF>;
+			io-channel-names = "ref_625mv", "ref_1250v", "ref_vdd",
+						"ref_gnd";
 		};
 
 		pm8916_chg: qcom,charger {
@@ -154,6 +164,7 @@
 			#size-cells = <1>;
 			#cooling-cells = <2>;
 
+			qcom,v-cutoff-mv = <3400>;
 			qcom,vddmax-mv = <4200>;
 			qcom,vddsafe-mv = <4200>;
 			qcom,vinmin-mv = <4308>;
@@ -169,7 +180,9 @@
 			qcom,batt-cold-percentage = <80>;
 			qcom,tchg-mins = <232>;
 			qcom,resume-soc = <99>;
-			qcom,chg-vadc = <&pm8916_vadc>;
+			io-channels = <&pm8916_vadc VADC_VBAT_SNS>,
+				      <&pm8916_vadc VADC_LR_MUX1_BAT_THERM>;
+			io-channel-names = "vbat_sns", "batt_therm";
 			qcom,chg-adc_tm = <&pm8916_adc_tm>;
 
 			status = "disabled";
@@ -230,7 +243,15 @@
 			qcom,s3-ocv-tolerence-uv = <1200>;
 			qcom,s2-fifo-length = <5>;
 			qcom,low-soc-fifo-length = <2>;
-			qcom,bms-vadc = <&pm8916_vadc>;
+			io-channels = <&pm8916_vadc VADC_REF_625MV>,
+				      <&pm8916_vadc VADC_REF_1250MV>,
+				      <&pm8916_vadc VADC_VBAT_SNS>,
+				      <&pm8916_vadc VADC_LR_MUX1_BAT_THERM>,
+				      <&pm8916_vadc VADC_DIE_TEMP>,
+				      <&pm8916_vadc VADC_LR_MUX2_BAT_ID>;
+			io-channel-names = "ref_625mv", "ref_1250v",
+					   "vbat_sns", "batt_therm",
+					   "die_temp", "batt_id";
 			qcom,bms-adc_tm = <&pm8916_adc_tm>;
 			qcom,pmic-revid = <&pm8916_revid>;
 
diff --git a/qcom/pm8937.dtsi b/qcom/pm8937.dtsi
index 2a9ed193..701ad1c5 100644
--- a/qcom/pm8937.dtsi
+++ b/qcom/pm8937.dtsi
@@ -1,3 +1,7 @@
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
 &spmi_bus {
 
 	qcom,pm8937@0 {
@@ -37,14 +41,12 @@
 			};
 		};
 
-		pm8937_temp_alarm: qcom,temp-alarm@2400 {
+		pm8937_tz: qcom,temp-alarm@2400 {
 			compatible = "qcom,spmi-temp-alarm";
 			reg = <0x2400 0x100>;
 			interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
-			label = "pm8937_tz";
-			qcom,channel-num = <8>;
-			qcom,threshold-set = <0>;
-			qcom,temp_alarm-vadc = <&pm8937_vadc>;
+			io-channels = <&pm8937_vadc VADC_DIE_TEMP>;
+			io-channel-names = "thermal";
 			#thermal-sensor-cells = <0>;
 		};
 
@@ -104,185 +106,197 @@
 		pm8937_vadc: vadc@3100 {
 			compatible = "qcom,spmi-vadc";
 			reg = <0x3100 0x100>;
+			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
-			interrupt-names = "eoc-int-en-set";
-			qcom,adc-bit-resolution = <15>;
-			qcom,adc-vdd-reference = <1800>;
-			qcom,vadc-poll-eoc;
-			#thermal-sensor-cells = <1>;
+			#io-channel-cells = <1>;
+			io-channel-ranges;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pa_therm1_default &cas_therm_default>;
 
-			chan@5 {
+			/* Channel nodes */
+			vcoin {
+				reg = <VADC_VCOIN>;
 				label = "vcoin";
-				reg = <5>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <1>;
-				qcom,calibration-type = "absolute";
-				qcom,scale-function = <0>;
-				qcom,hw-settle-time = <0>;
-				qcom,fast-avg-setup = <0>;
+				qcom,pre-scaling = <1 3>;
 			};
 
-			chan@7 {
+			vph_pwr {
+				reg = <VADC_VSYS>;
 				label = "vph_pwr";
-				reg = <7>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <1>;
-				qcom,calibration-type = "absolute";
-				qcom,scale-function = <0>;
-				qcom,hw-settle-time = <0>;
-				qcom,fast-avg-setup = <0>;
+				qcom,pre-scaling = <1 3>;
 			};
 
-			chan@8 {
+			die_temp {
+				reg = <VADC_DIE_TEMP>;
 				label = "die_temp";
-				reg = <8>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "absolute";
-				qcom,scale-function = <3>;
-				qcom,hw-settle-time = <0>;
-				qcom,fast-avg-setup = <0>;
+				qcom,pre-scaling = <1 1>;
 			};
 
-			chan@9 {
+			ref_625mv {
+				reg = <VADC_REF_625MV>;
 				label = "ref_625mv";
-				reg = <9>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "absolute";
-				qcom,scale-function = <0>;
-				qcom,hw-settle-time = <0>;
-				qcom,fast-avg-setup = <0>;
+				qcom,pre-scaling = <1 1>;
 			};
 
-			chan@a {
+			ref_1250v {
+				reg = <VADC_REF_1250MV>;
 				label = "ref_1250v";
-				reg = <0xa>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "absolute";
-				qcom,scale-function = <0>;
-				qcom,hw-settle-time = <0>;
-				qcom,fast-avg-setup = <0>;
+				qcom,pre-scaling = <1 1>;
 			};
 
-			chan@c {
+			ref_buf_625mv {
+				reg = <VADC_SPARE1>;
 				label = "ref_buf_625mv";
-				reg = <0xc>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "absolute";
-				qcom,scale-function = <0>;
-				qcom,hw-settle-time = <0>;
-				qcom,fast-avg-setup = <0>;
+				qcom,pre-scaling = <1 1>;
+			};
+
+			ref_vdd {
+				reg = <VADC_VDD_VADC>;
+				label = "ref_vdd";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			ref_gnd {
+				reg = <VADC_GND_REF>;
+				label = "ref_gnd";
+				qcom,pre-scaling = <1 1>;
 			};
 
-			chan@36 {
+			pa_therm0 {
+				reg = <VADC_LR_MUX7_HW_ID>;
 				label = "pa_therm0";
-				reg = <0x36>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "ratiometric";
-				qcom,scale-function = <2>;
-				qcom,hw-settle-time = <2>;
-				qcom,fast-avg-setup = <0>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
 			};
 
-			chan@11 {
+			pa_therm1 {
+				reg = <VADC_P_MUX2_1_1>;
 				label = "pa_therm1";
-				reg = <0x11>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "ratiometric";
-				qcom,scale-function = <2>;
-				qcom,hw-settle-time = <2>;
-				qcom,fast-avg-setup = <0>;
-				qcom,vadc-thermal-node;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
 			};
 
-			chan@32 {
+			xo_therm {
+				reg = <VADC_LR_MUX3_XO_THERM>;
 				label = "xo_therm";
-				reg = <0x32>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "ratiometric";
-				qcom,scale-function = <4>;
-				qcom,hw-settle-time = <2>;
-				qcom,fast-avg-setup = <0>;
-				qcom,vadc-thermal-node;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
 			};
 
-			chan@3c {
+			xo_therm_buf {
+				reg = <VADC_LR_MUX3_BUF_XO_THERM>;
 				label = "xo_therm_buf";
-				reg = <0x3c>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "ratiometric";
-				qcom,scale-function = <4>;
-				qcom,hw-settle-time = <2>;
-				qcom,fast-avg-setup = <0>;
-				qcom,vadc-thermal-node;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
 			};
 
-			chan@13 {
+			case_therm {
+				reg = <VADC_P_MUX4_1_1>;
 				label = "case_therm";
-				reg = <0x13>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "ratiometric";
-				qcom,scale-function = <2>;
-				qcom,hw-settle-time = <2>;
-				qcom,fast-avg-setup = <0>;
-				qcom,vadc-thermal-node;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+			};
+		};
+
+		pm8937_adc_tm_iio: adc_tm_iio {
+			compatible = "qcom,adc-tm5-iio";
+			reg = <0x3500 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#thermal-sensor-cells = <1>;
+			io-channels = <&pm8937_vadc VADC_P_MUX2_1_1>,
+					<&pm8937_vadc VADC_LR_MUX3_XO_THERM>,
+					<&pm8937_vadc
+						VADC_LR_MUX3_BUF_XO_THERM>,
+					<&pm8937_vadc VADC_P_MUX4_1_1>;
+
+			pa_therm1 {
+				reg = <VADC_P_MUX2_1_1>;
+				label = "pa_therm1";
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+			};
+
+			xo_therm {
+				reg = <VADC_LR_MUX3_XO_THERM>;
+				label = "xo_therm";
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+			};
+
+			xo_therm_buf {
+				reg = <VADC_LR_MUX3_BUF_XO_THERM>;
+				label = "xo_therm_buf";
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+			};
+
+			case_therm {
+				reg = <VADC_P_MUX4_1_1>;
+				label = "case_therm";
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
 			};
 		};
 
 		pm8937_adc_tm: vadc@3400 {
-			compatible = "qcom,adc-tm-rev2";
+			compatible = "qcom,qpnp-adc-tm";
 			reg = <0x3400 0x100>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts =	<0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>,
+			interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>,
 					<0x0 0x34 0x3 IRQ_TYPE_EDGE_RISING>,
 					<0x0 0x34 0x4 IRQ_TYPE_EDGE_RISING>;
-			interrupt-names =	"eoc-int-en-set",
+			interrupt-names = "eoc-int-en-set",
 						"high-thr-en-set",
 						"low-thr-en-set";
-			qcom,adc-bit-resolution = <15>;
-			qcom,adc-vdd-reference = <1800>;
-			qcom,adc_tm-vadc = <&pm8937_vadc>;
 			#thermal-sensor-cells = <1>;
-
-			chan@36 {
+			qcom,adc-vdd-reference = <1800>;
+			io-channels = <&pm8937_vadc VADC_REF_625MV>,
+					<&pm8937_vadc VADC_REF_1250MV>,
+					<&pm8937_vadc VADC_VDD_VADC>,
+					<&pm8937_vadc VADC_GND_REF>;
+			io-channel-names = "ref_625mv", "ref_1250v", "ref_vdd",
+						"ref_gnd";
+
+			 pa_therm0 {
 				label = "pa_therm0";
-				reg = <0x36>;
+				reg = <VADC_LR_MUX7_HW_ID>;
+				io-channels = <&pm8937_vadc VADC_LR_MUX7_HW_ID>;
+				io-channel-names = "pa_therm0";
 				qcom,decimation = <0>;
 				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "ratiometric";
-				qcom,scale-function = <2>;
+				qcom,ratiometric;
+				qcom,scale-fn-type = <2>;
 				qcom,hw-settle-time = <2>;
 				qcom,fast-avg-setup = <0>;
 				qcom,btm-channel-number = <0x48>;
 				qcom,thermal-node;
 			};
 
-			chan@7 {
+			vph_pwr {
 				label = "vph_pwr";
-				reg = <0x7>;
+				reg = <VADC_VSYS>;
+				io-channels = <&pm8937_vadc VADC_VSYS>;
+				io-channel-names = "vph_pwr";
 				qcom,decimation = <0>;
 				qcom,pre-div-channel-scaling = <1>;
-				qcom,calibration-type = "absolute";
-				qcom,scale-function = <0>;
+				qcom,scale-fn-type = <0>;
 				qcom,hw-settle-time = <0>;
 				qcom,fast-avg-setup = <0>;
 				qcom,btm-channel-number = <0x68>;
 			};
 		};
-
 	};
 
 	pm8937_1: qcom,pm8937@1 {
@@ -307,7 +321,7 @@
 	pa-therm1-adc {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-sensors = <&pm8937_vadc 0x11>;
+		thermal-sensors = <&pm8937_adc_tm_iio VADC_P_MUX2_1_1>;
 		thermal-governor = "user_space";
 		wake-capable-sensor;
 
@@ -323,7 +337,7 @@
 	xo-therm-adc {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-sensors = <&pm8937_vadc 0x32>;
+		thermal-sensors = <&pm8937_adc_tm_iio VADC_LR_MUX3_XO_THERM>;
 		thermal-governor = "user_space";
 		wake-capable-sensor;
 
@@ -339,7 +353,8 @@
 	xo-therm-buf-adc {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-sensors = <&pm8937_vadc 0x3c>;
+		thermal-sensors = <&pm8937_adc_tm_iio
+					VADC_LR_MUX3_BUF_XO_THERM>;
 		thermal-governor = "user_space";
 		wake-capable-sensor;
 
@@ -355,7 +370,7 @@
 	case-therm-adc {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-sensors = <&pm8937_vadc 0x13>;
+		thermal-sensors = <&pm8937_adc_tm_iio VADC_P_MUX4_1_1>;
 		thermal-governor = "user_space";
 		wake-capable-sensor;
 
@@ -371,7 +386,7 @@
 	pa-therm0-adc {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-sensors = <&pm8937_adc_tm 0x36>;
+		thermal-sensors = <&pm8937_adc_tm VADC_LR_MUX7_HW_ID>;
 		thermal-governor = "user_space";
 		wake-capable-sensor;
 
@@ -385,10 +400,10 @@
 	};
 
 	pm8937_tz {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <100>;
 		polling-delay = <0>;
 		thermal-governor = "step_wise";
-		thermal-sensors = <&pm8937_temp_alarm>;
+		thermal-sensors = <&pm8937_tz>;
 		wake-capable-sensor;
 
 		trips {
diff --git a/qcom/pm8953.dtsi b/qcom/pm8953.dtsi
index 05a07ecf..ba8b0711 100644
--- a/qcom/pm8953.dtsi
+++ b/qcom/pm8953.dtsi
@@ -1,3 +1,7 @@
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
 &spmi_bus {
 
 	qcom,pm8953@0 {
@@ -41,10 +45,8 @@
 			compatible = "qcom,spmi-temp-alarm";
 			reg = <0x2400 0x100>;
 			interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
-			label = "pm8953_tz";
-			qcom,channel-num = <8>;
-			qcom,threshold-set = <0>;
-			qcom,temp_alarm-vadc = <&pm8953_vadc>;
+			io-channels = <&pm8953_vadc VADC_DIE_TEMP>;
+			io-channel-names = "thermal";
 			#thermal-sensor-cells = <0>;
 		};
 
@@ -103,178 +105,166 @@
 		pm8953_vadc: vadc@3100 {
 			compatible = "qcom,spmi-vadc";
 			reg = <0x3100 0x100>;
+			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
-			interrupt-names = "eoc-int-en-set";
-			qcom,adc-bit-resolution = <15>;
-			qcom,adc-vdd-reference = <1800>;
-			qcom,vadc-poll-eoc;
-			#thermal-sensor-cells = <1>;
+			#io-channel-cells = <1>;
+			io-channel-ranges;
 			pinctrl-names = "default";
 			pinctrl-0 = <&pa_therm1_default &cas_therm_default>;
 
-			chan@5 {
+			/* Channel nodes */
+			vcoin {
+				reg = <VADC_VCOIN>;
 				label = "vcoin";
-				reg = <5>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <1>;
-				qcom,calibration-type = "absolute";
-				qcom,scale-function = <0>;
-				qcom,hw-settle-time = <0>;
-				qcom,fast-avg-setup = <0>;
+				qcom,pre-scaling = <1 3>;
 			};
 
-			chan@7 {
+			vph_pwr {
+				reg = <VADC_VSYS>;
 				label = "vph_pwr";
-				reg = <7>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <1>;
-				qcom,calibration-type = "absolute";
-				qcom,scale-function = <0>;
-				qcom,hw-settle-time = <0>;
-				qcom,fast-avg-setup = <0>;
+				qcom,pre-scaling = <1 3>;
 			};
 
-			chan@8 {
+			die_temp {
+				reg = <VADC_DIE_TEMP>;
 				label = "die_temp";
-				reg = <8>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "absolute";
-				qcom,scale-function = <3>;
-				qcom,hw-settle-time = <0>;
-				qcom,fast-avg-setup = <0>;
+				qcom,pre-scaling = <1 1>;
 			};
 
-			chan@9 {
+			ref_625mv {
+				reg = <VADC_REF_625MV>;
 				label = "ref_625mv";
-				reg = <9>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "absolute";
-				qcom,scale-function = <0>;
-				qcom,hw-settle-time = <0>;
-				qcom,fast-avg-setup = <0>;
+				qcom,pre-scaling = <1 1>;
 			};
 
-			chan@a {
+			ref_1250v {
+				reg = <VADC_REF_1250MV>;
 				label = "ref_1250v";
-				reg = <0xa>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "absolute";
-				qcom,scale-function = <0>;
-				qcom,hw-settle-time = <0>;
-				qcom,fast-avg-setup = <0>;
+				qcom,pre-scaling = <1 1>;
 			};
 
-			chan@c {
+			ref_buf_625mv {
+				reg = <VADC_SPARE1>;
 				label = "ref_buf_625mv";
-				reg = <0xc>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "absolute";
-				qcom,scale-function = <0>;
-				qcom,hw-settle-time = <0>;
-				qcom,fast-avg-setup = <0>;
+				qcom,pre-scaling = <1 1>;
+			};
+
+			ref_vdd {
+				reg = <VADC_VDD_VADC>;
+				label = "ref_vdd";
+				qcom,pre-scaling = <1 1>;
 			};
 
-			chan@36 {
+			ref_gnd {
+				reg = <VADC_GND_REF>;
+				label = "ref_gnd";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pa_therm0 {
+				reg = <VADC_LR_MUX7_HW_ID>;
 				label = "pa_therm0";
-				reg = <0x36>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "ratiometric";
-				qcom,scale-function = <2>;
-				qcom,hw-settle-time = <2>;
-				qcom,fast-avg-setup = <0>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
 			};
 
-			chan@11 {
+			pa_therm1 {
+				reg = <VADC_P_MUX2_1_1>;
 				label = "pa_therm1";
-				reg = <0x11>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "ratiometric";
-				qcom,scale-function = <2>;
-				qcom,hw-settle-time = <2>;
-				qcom,fast-avg-setup = <0>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
 			};
 
-
-			chan@32 {
+			xo_therm {
+				reg = <VADC_LR_MUX3_XO_THERM>;
 				label = "xo_therm";
-				reg = <0x32>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "ratiometric";
-				qcom,scale-function = <4>;
-				qcom,hw-settle-time = <2>;
-				qcom,fast-avg-setup = <0>;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
 			};
 
-			chan@3c {
+			xo_therm_buf {
+				reg = <VADC_LR_MUX3_BUF_XO_THERM>;
 				label = "xo_therm_buf";
-				reg = <0x3c>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "ratiometric";
-				qcom,scale-function = <4>;
-				qcom,hw-settle-time = <2>;
-				qcom,fast-avg-setup = <0>;
-				qcom,vadc-thermal-node;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
 			};
 
-			chan@13 {
+			case_therm {
+				reg = <VADC_P_MUX4_1_1>;
 				label = "case_therm";
-				reg = <0x13>;
-				qcom,decimation = <0>;
-				qcom,pre-div-channel-scaling = <0>;
-				qcom,calibration-type = "ratiometric";
-				qcom,scale-function = <2>;
-				qcom,hw-settle-time = <2>;
-				qcom,fast-avg-setup = <0>;
-				qcom,vadc-thermal-node;
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+			};
+		};
+
+		pm8953_adc_tm_iio: adc_tm_iio {
+			compatible = "qcom,adc-tm5-iio";
+			reg = <0x3500 0x100>;
+			#thermal-sensor-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			io-channels = <&pm8953_vadc VADC_LR_MUX3_BUF_XO_THERM>;
+
+			xo_therm_buf {
+				reg = <VADC_LR_MUX3_BUF_XO_THERM>;
+				label = "xo_therm_buf";
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
 			};
 		};
 
 		pm8953_adc_tm: vadc@3400 {
-			compatible = "qcom,adc-tm-rev2";
+			compatible = "qcom,qpnp-adc-tm";
 			reg = <0x3400 0x100>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			interrupts =	<0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>,
+			interrupts =    <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>,
 					<0x0 0x34 0x3 IRQ_TYPE_EDGE_RISING>,
 					<0x0 0x34 0x4 IRQ_TYPE_EDGE_RISING>;
-			interrupt-names =	"eoc-int-en-set",
+			interrupt-names =       "eoc-int-en-set",
 						"high-thr-en-set",
 						"low-thr-en-set";
-			qcom,adc-bit-resolution = <15>;
-			qcom,adc-vdd-reference = <1800>;
-			qcom,adc_tm-vadc = <&pm8953_vadc>;
 			#thermal-sensor-cells = <1>;
-
-			chan@36 {
+			qcom,adc-vdd-reference = <1800>;
+			io-channels = <&pm8953_vadc VADC_REF_625MV>,
+					<&pm8953_vadc VADC_REF_1250MV>,
+					<&pm8953_vadc VADC_VDD_VADC>,
+					<&pm8953_vadc VADC_GND_REF>;
+			io-channel-names = "ref_625mv", "ref_1250v", "ref_vdd",
+						"ref_gnd";
+
+			pa_therm0 {
 				label = "pa_therm0";
-				reg = <0x36>;
+				reg = <VADC_LR_MUX7_HW_ID>;
+				io-channels = <&pm8953_vadc VADC_LR_MUX7_HW_ID>;
+				io-channel-names = "pa_therm0";
 				qcom,pre-div-channel-scaling = <0>;
 				qcom,decimation = <0>;
-				qcom,calibration-type = "ratiometric";
-				qcom,scale-function = <2>;
+				qcom,ratiometric;
+				qcom,scale-fn-type = <2>;
 				qcom,hw-settle-time = <2>;
 				qcom,btm-channel-number = <0x48>;
 				qcom,fast-avg-setup = <0>;
 				qcom,thermal-node;
 			};
 
-			chan@32 {
+			xo_therm {
 				label = "xo_therm";
-				reg = <0x32>;
+				reg = <VADC_LR_MUX3_XO_THERM>;
+				io-channels = <&pm8953_vadc
+							VADC_LR_MUX3_XO_THERM>;
+				io-channel-names = "xo_therm";
 				qcom,pre-div-channel-scaling = <0>;
 				qcom,decimation = <0>;
-				qcom,calibration-type = "ratiometric";
-				qcom,scale-function = <4>;
+				qcom,ratiometric;
+				qcom,scale-fn-type = <4>;
 				qcom,hw-settle-time = <2>;
 				qcom,btm-channel-number = <0x68>;
 				qcom,fast-avg-setup = <0>;
@@ -329,7 +319,7 @@
 	xo-therm-adc {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-sensors = <&pm8953_adc_tm 0x32>;
+		thermal-sensors = <&pm8953_adc_tm VADC_LR_MUX3_XO_THERM>;
 		thermal-governor = "user_space";
 		wake-capable-sensor;
 
@@ -345,7 +335,8 @@
 	xo-therm-buf-adc {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-sensors = <&pm8953_vadc 0x3c>;
+		thermal-sensors = <&pm8953_adc_tm_iio
+					VADC_LR_MUX3_BUF_XO_THERM>;
 		thermal-governor = "user_space";
 		wake-capable-sensor;
 
@@ -358,9 +349,10 @@
 		};
 	};
 
-	pm8953_tz {
-		polling-delay-passive = <0>;
+	pm8953_temp_alarm: pm8953_tz {
+		polling-delay-passive = <100>;
 		polling-delay = <0>;
+		thermal-governor = "step_wise";
 		thermal-sensors = <&pm8953_tz>;
 		wake-capable-sensor;
 
diff --git a/qcom/qm215-camera.dtsi b/qcom/qm215-camera.dtsi
index 9169b3b8..d41f7868 100644
--- a/qcom/qm215-camera.dtsi
+++ b/qcom/qm215-camera.dtsi
@@ -304,6 +304,7 @@
 			compatible = "qcom,msm-cam-smmu-cb";
 			iommus = <&apps_iommu 0x400 0x00>,
 				<&apps_iommu 0x2400 0x00>;
+			iommu-cells = <2>;
 			qcom,iommu-dma-addr-pool = <0x10000000 0x70000000>;
 			label = "vfe";
 			qcom,scratch-buf-support;
@@ -312,6 +313,7 @@
 		msm_cam_smmu_cb3: msm_cam_smmu_cb3 {
 			compatible = "qcom,msm-cam-smmu-cb";
 			iommus = <&apps_iommu 0x1c00 0x00>;
+			iommu-cells = <2>;
 			qcom,iommu-dma-addr-pool = <0x00020000 0x78000000>;
 			label = "cpp";
 		};
@@ -319,6 +321,7 @@
 		msm_cam_smmu_cb4: msm_cam_smmu_cb4 {
 			compatible = "qcom,msm-cam-smmu-cb";
 			iommus = <&apps_iommu 0x1800 0x00>;
+			iommu-cells = <2>;
 			qcom,iommu-dma-addr-pool = <0x00020000 0x78000000>;
 			label = "jpeg_enc0";
 		};
diff --git a/qcom/qm215-pm8916.dtsi b/qcom/qm215-pm8916.dtsi
index 2433e885..13797f13 100644
--- a/qcom/qm215-pm8916.dtsi
+++ b/qcom/qm215-pm8916.dtsi
@@ -198,165 +198,159 @@
 };
 
 &pm8916_vadc {
-	chan@0 {
+	#thermal-sensor-cells = <1>;
+	usb_in {
+		reg = <VADC_USBIN>;
 		label = "usb_in";
-		reg = <0>;
-		qcom,decimation = <0>;
-		qcom,pre-div-channel-scaling = <7>;
-		qcom,calibration-type = "absolute";
-		qcom,scale-function = <0>;
-		qcom,hw-settle-time = <0>;
-		qcom,fast-avg-setup = <0>;
+		qcom,pre-scaling = <1 10>;
 	};
 
-	chan@2 {
+	ireg_fb {
+		reg = <VADC_VCHG_SNS>;
 		label = "ireg_fb";
-		reg = <2>;
-		qcom,decimation = <0>;
-		qcom,pre-div-channel-scaling = <6>;
-		qcom,calibration-type = "absolute";
-		qcom,scale-function = <0>;
-		qcom,hw-settle-time = <0>;
-		qcom,fast-avg-setup = <0>;
+		qcom,pre-scaling = <10 81>;
 	};
 
-	chan@5 {
+	vcoin {
+		reg = <VADC_VCOIN>;
 		label = "vcoin";
-		reg = <5>;
-		qcom,decimation = <0>;
-		qcom,pre-div-channel-scaling = <1>;
-		qcom,calibration-type = "absolute";
-		qcom,scale-function = <0>;
-		qcom,hw-settle-time = <0>;
-		qcom,fast-avg-setup = <0>;
+		qcom,pre-scaling = <1 3>;
 	};
 
-	chan@6 {
+	vbat_sns {
+		reg = <VADC_VBAT_SNS>;
 		label = "vbat_sns";
-		reg = <6>;
-		qcom,decimation = <0>;
-		qcom,pre-div-channel-scaling = <1>;
-		qcom,calibration-type = "absolute";
-		qcom,scale-function = <0>;
-		qcom,hw-settle-time = <0>;
-		qcom,fast-avg-setup = <0>;
+		qcom,pre-scaling = <1 3>;
 	};
 
-	chan@7 {
+	vph_pwr {
+		reg = <VADC_VSYS>;
 		label = "vph_pwr";
-		reg = <7>;
-		qcom,decimation = <0>;
-		qcom,pre-div-channel-scaling = <1>;
-		qcom,calibration-type = "absolute";
-		qcom,scale-function = <0>;
-		qcom,hw-settle-time = <0>;
-		qcom,fast-avg-setup = <0>;
+		qcom,pre-scaling = <1 3>;
 	};
 
-	chan@b {
+	chg_temp {
+		reg = <VADC_CHG_TEMP>;
 		label = "chg_temp";
-		reg = <0xb>;
-		qcom,decimation = <0>;
-		qcom,pre-div-channel-scaling = <0>;
-		qcom,calibration-type = "absolute";
-		qcom,scale-function = <3>;
-		qcom,hw-settle-time = <0>;
-		qcom,fast-avg-setup = <0>;
+		qcom,pre-scaling = <1 1>;
 	};
 
-	chan@11 {
+	skin_therm {
+		reg = <VADC_P_MUX2_1_1>;
 		label = "skin_therm";
-		reg = <0x11>;
-		qcom,decimation = <0>;
-		qcom,pre-div-channel-scaling = <0>;
-		qcom,calibration-type = "ratiometric";
-		qcom,scale-function = <2>;
-		qcom,hw-settle-time = <2>;
-		qcom,fast-avg-setup = <0>;
-		qcom,vadc-thermal-node;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
 	};
 
-	chan@30 {
+	batt_therm {
+		reg = <VADC_LR_MUX1_BAT_THERM>;
 		label = "batt_therm";
-		reg = <0x30>;
-		qcom,decimation = <0>;
-		qcom,pre-div-channel-scaling = <0>;
 		qcom,calibration-type = "ratiometric";
-		qcom,scale-function = <26>;
-		qcom,hw-settle-time = <0xb>;
-		qcom,fast-avg-setup = <0>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <2000>;
+		qcom,pre-scaling = <1 1>;
 	};
 
-	chan@31 {
+	batt_id {
+		reg = <VADC_LR_MUX2_BAT_ID>;
 		label = "batt_id";
-		reg = <0x31>;
-		qcom,decimation = <0>;
-		qcom,pre-div-channel-scaling = <0>;
-		qcom,calibration-type = "ratiometric";
-		qcom,scale-function = <0>;
-		qcom,hw-settle-time = <0xb>;
-		qcom,fast-avg-setup = <0>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <2000>;
+		qcom,pre-scaling = <1 1>;
 	};
 
-	chan@36 {
+	pa_therm0 {
+		reg = <VADC_LR_MUX7_HW_ID>;
 		label = "pa_therm0";
-		reg = <0x36>;
-		qcom,decimation = <0>;
-		qcom,pre-div-channel-scaling = <0>;
-		qcom,calibration-type = "ratiometric";
-		qcom,scale-function = <2>;
-		qcom,hw-settle-time = <2>;
-		qcom,fast-avg-setup = <0>;
-		qcom,vadc-thermal-node;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
 	};
 
-	chan@32 {
+	xo_therm {
+		reg = <VADC_LR_MUX3_XO_THERM>;
 		label = "xo_therm";
-		reg = <0x32>;
-		qcom,decimation = <0>;
-		qcom,pre-div-channel-scaling = <0>;
-		qcom,calibration-type = "ratiometric";
-		qcom,scale-function = <4>;
-		qcom,hw-settle-time = <2>;
-		qcom,fast-avg-setup = <0>;
-		qcom,vadc-thermal-node;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
 	};
 
-	chan@3c {
+	xo_therm_buf {
+		reg = <VADC_LR_MUX3_BUF_XO_THERM>;
 		label = "xo_therm_buf";
-		reg = <0x3c>;
-		qcom,decimation = <0>;
-		qcom,pre-div-channel-scaling = <0>;
-		qcom,calibration-type = "ratiometric";
-		qcom,scale-function = <4>;
-		qcom,hw-settle-time = <2>;
-		qcom,fast-avg-setup = <0>;
-		qcom,vadc-thermal-node;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+};
+
+&pm8916_adc_tm_iio {
+	io-channels = <&pm8916_vadc VADC_LR_MUX3_BUF_XO_THERM>,
+			<&pm8916_vadc VADC_LR_MUX3_XO_THERM>,
+			<&pm8916_vadc VADC_LR_MUX7_HW_ID>,
+			<&pm8916_vadc VADC_P_MUX2_1_1>;
+	io-channel-names = "xo_therm_buf", "xo_therm", "pa_therm0",
+				"skin_therm";
+
+	pa_therm0 {
+		reg = <VADC_LR_MUX7_HW_ID>;
+		label = "pa_therm0";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	xo_therm {
+		reg = <VADC_LR_MUX3_XO_THERM>;
+		label = "xo_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	xo_therm_buf {
+		reg = <VADC_LR_MUX3_BUF_XO_THERM>;
+		label = "xo_therm_buf";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	skin_therm {
+		reg = <VADC_P_MUX2_1_1>;
+		label = "skin_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
 	};
 };
 
 &pm8916_adc_tm {
-	/* Channel Node */
-	chan@30 {
+	/* Channel Nodes */
+	batt_therm {
+		reg = <VADC_LR_MUX1_BAT_THERM>;
 		label = "batt_therm";
-		reg = <0x30>;
-		qcom,decimation = <0>;
+		io-channels = <&pm8916_vadc VADC_LR_MUX1_BAT_THERM>;
+		io-channel-names = "batt_therm";
 		qcom,pre-div-channel-scaling = <0>;
-		qcom,calibration-type = "ratiometric";
-		qcom,scale-function = <8>;
+		qcom,decimation = <0>;
+		qcom,ratiometric;
 		qcom,hw-settle-time = <0xb>;
+		qcom,scale-fn-type = <8>;
 		qcom,fast-avg-setup = <0x2>;
 		qcom,btm-channel-number = <0x48>;
 	};
 
-	chan@6 {
+	vbat_sns {
+		reg = <VADC_VBAT_SNS>;
 		label = "vbat_sns";
-		reg = <0x6>;
-		qcom,decimation = <0>;
+		io-channels = <&pm8916_vadc VADC_VBAT_SNS>;
+		io-channel-names = "vbat_sns";
 		qcom,pre-div-channel-scaling = <1>;
-		qcom,calibration-type = "absolute";
-		qcom,scale-function = <0>;
+		qcom,decimation = <0>;
 		qcom,hw-settle-time = <0xb>;
+		qcom,scale-fn-type = <0>;
 		qcom,fast-avg-setup = <0x2>;
 		qcom,btm-channel-number = <0x68>;
 	};
@@ -367,7 +361,8 @@
 		xo-therm-buf-adc {
 			polling-delay-passive = <0>;
 			polling-delay = <5000>;
-			thermal-sensors = <&pm8916_vadc 0x3c>;
+			thermal-sensors = <&pm8916_adc_tm_iio
+						VADC_LR_MUX3_BUF_XO_THERM>;
 			thermal-governor = "user_space";
 
 			trips {
@@ -382,7 +377,8 @@
 		xo-therm-adc {
 			polling-delay-passive = <0>;
 			polling-delay = <5000>;
-			thermal-sensors = <&pm8916_vadc 0x32>;
+			thermal-sensors = <&pm8916_adc_tm_iio
+						VADC_LR_MUX3_XO_THERM>;
 			thermal-governor = "user_space";
 
 			trips {
@@ -397,7 +393,8 @@
 		pa-therm0-adc {
 			polling-delay-passive = <0>;
 			polling-delay = <5000>;
-			thermal-sensors = <&pm8916_vadc 0x36>;
+			thermal-sensors = <&pm8916_adc_tm_iio
+						VADC_LR_MUX7_HW_ID>;
 			thermal-governor = "user_space";
 
 			trips {
@@ -412,7 +409,8 @@
 		skin-therm-adc {
 			polling-delay-passive = <0>;
 			polling-delay = <5000>;
-			thermal-sensors = <&pm8916_vadc 0x11>;
+			thermal-sensors = <&pm8916_adc_tm_iio
+						VADC_P_MUX2_1_1>;
 			thermal-governor = "user_space";
 
 			trips {
@@ -433,7 +431,7 @@
 		};
 
 		pm8916_tz {
-			polling-delay-passive = <0>;
+			polling-delay-passive = <100>;
 			polling-delay = <0>;
 			thermal-governor = "step_wise";
 			thermal-sensors = <&pm8916_tz>;
@@ -462,7 +460,8 @@
 		xo-therm-step {
 			polling-delay-passive = <1000>;
 			polling-delay = <5000>;
-			thermal-sensors = <&pm8916_vadc 0x32>;
+			thermal-sensors = <&pm8916_adc_tm_iio
+						VADC_LR_MUX3_XO_THERM>;
 			thermal-governor = "step_wise";
 
 			trips {
diff --git a/qcom/qm215-qrd-smb1360.dtsi b/qcom/qm215-qrd-smb1360.dtsi
index 84e9e78b..97568702 100644
--- a/qcom/qm215-qrd-smb1360.dtsi
+++ b/qcom/qm215-qrd-smb1360.dtsi
@@ -1,4 +1,5 @@
 #include "qm215-qrd.dtsi"
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
 
 &pm8916_chg {
 	qcom,use-external-charger;
@@ -71,6 +72,8 @@
 		qcom,cool-bat-mv = <4200>;
 		qcom,warm-bat-ma = <1000>;
 		qcom,cool-bat-ma = <1000>;
+		io-channels = <&pm8916_vadc VADC_LR_MUX2_BAT_ID>;
+		io-channel-names = "batt_id";
 		status= "okay";
 	};
 };
diff --git a/qcom/qm215.dtsi b/qcom/qm215.dtsi
index baddee56..3efe1657 100644
--- a/qcom/qm215.dtsi
+++ b/qcom/qm215.dtsi
@@ -27,10 +27,6 @@
 	compatible = "qcom,gcc-qm215", "syscon";
 };
 
-&debugcc {
-	compatible = "qcom,qm215-debugcc";
-};
-
 &msm_cpufreq {
 	/delete-property/qcom,cpufreq-table;
 	qcom,cpufreq-table =
diff --git a/qcom/qrb5165n-iot-rb5.dts b/qcom/qrb5165n-iot-rb5.dts
new file mode 100644
index 00000000..b046e532
--- /dev/null
+++ b/qcom/qrb5165n-iot-rb5.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "qrb5165n.dtsi"
+#include "qrb5165n-iot-rb5.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. QRB5165N IOT RB5";
+	compatible = "qcom,kona-iot", "qcom,kona", "qcom,iot";
+	qcom,board-id = <11 3>;
+};
diff --git a/qcom/qrb5165n-iot-rb5.dtsi b/qcom/qrb5165n-iot-rb5.dtsi
new file mode 100644
index 00000000..4a59978f
--- /dev/null
+++ b/qcom/qrb5165n-iot-rb5.dtsi
@@ -0,0 +1,48 @@
+#include "kona-v2.1-iot-rb5.dtsi"
+
+&pcie0 {
+	/delete-property/ qcom,config-recovery;
+	iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+		<0x100 &apps_smmu 0x1c01 0x1>,
+		<0x200 &apps_smmu 0x1c02 0x1>,
+		<0x210 &apps_smmu 0x1c03 0x1>,
+		<0x230 &apps_smmu 0x1c04 0x1>,
+		<0x270 &apps_smmu 0x1c05 0x1>,
+		<0x500 &apps_smmu 0x1c06 0x1>;
+};
+
+&pcie0_rp {
+	#address-cells = <5>;
+	#size-cells = <0>;
+
+	/delete-node/ cnss_pci;
+	asm2806_switch: asm2806_switch {
+		reg = <0x00010000 0x0 0x0 0x0 0x0>;
+		#address-cells = <5>;
+		#size-cells = <0>;
+
+		lane6: lane6 {
+			reg = <0x00023000 0x0 0x0 0x0 0x0>;
+			#address-cells = <5>;
+			#size-cells = <0>;
+
+			cnss_pci: cnss_pci {
+				reg = <0x00050000 0x0 0x0 0x0 0x0>;
+				qcom,iommu-group = <&cnss_pci_iommu_group>;
+				memory-region = <&cnss_wlan_mem>;
+
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				cnss_pci_iommu_group: cnss_pci_iommu_group {
+					qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
+					qcom,iommu-dma = "fastmap";
+					qcom,iommu-pagetable = "coherent";
+					qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE",
+							    "non-fatal";
+				};
+			};
+		};
+	};
+};
+
diff --git a/qcom/qrb5165n.dtsi b/qcom/qrb5165n.dtsi
new file mode 100644
index 00000000..ccd1c3ec
--- /dev/null
+++ b/qcom/qrb5165n.dtsi
@@ -0,0 +1,7 @@
+#include "kona-v2.1.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. QRB5165N";
+	compatible = "qcom,kona";
+	qcom,msm-id = <496 0x20001>;
+};
diff --git a/qcom/scuba-usb.dtsi b/qcom/scuba-usb.dtsi
index 819e7442..1ac6525d 100644
--- a/qcom/scuba-usb.dtsi
+++ b/qcom/scuba-usb.dtsi
@@ -88,6 +88,7 @@
 			snps,dis_enblslpm_quirk;
 			snps,has-lpm-erratum;
 			snps,hird-threshold = /bits/ 8 <0x10>;
+			snps,usb3-u1u2-disable;
 			snps,usb3_lpm_capable;
 			usb-core-id = <0>;
 			maximum-speed = "super-speed";
diff --git a/qcom/sdm429-cpu.dtsi b/qcom/sdm429-cpu.dtsi
index d1749dc7..944023aa 100644
--- a/qcom/sdm429-cpu.dtsi
+++ b/qcom/sdm429-cpu.dtsi
@@ -31,25 +31,21 @@
 			reg = <0x100>;
 			enable-method = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
-			efficiency = <1024>;
+			capacity-dmips-mhz = <1024>;
 			sched-energy-costs = <&CPU_COST_0>;
 			next-level-cache = <&L2_1>;
 			#cooling-cells = <2>;
 			L2_1: l2-cache {
 			      compatible = "arm,arch-cache";
 			      cache-level = <2>;
-			      /* A53 L2 dump not supported */
-			      qcom,dump-size = <0x0>;
 			};
 
 			L1_I_100: l1-icache {
 				compatible = "arm,arch-cache";
-				qcom,dump-size = <0x8800>;
 			};
 
 			L1_D_100: l1-dcache {
 				compatible = "arm,arch-cache";
-				qcom,dump-size = <0x9000>;
 			};
 		};
 
@@ -59,18 +55,16 @@
 			reg = <0x101>;
 			enable-method = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
-			efficiency = <1024>;
+			capacity-dmips-mhz = <1024>;
 			sched-energy-costs = <&CPU_COST_0>;
 			next-level-cache = <&L2_1>;
 			#cooling-cells = <2>;
 			L1_I_101: l1-icache {
 				compatible = "arm,arch-cache";
-				qcom,dump-size = <0x8800>;
 			};
 
 			L1_D_101: l1-dcache {
 				compatible = "arm,arch-cache";
-				qcom,dump-size = <0x9000>;
 			};
 		};
 
@@ -80,18 +74,16 @@
 			reg = <0x102>;
 			enable-method = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
-			efficiency = <1024>;
+			capacity-dmips-mhz = <1024>;
 			sched-energy-costs = <&CPU_COST_0>;
 			next-level-cache = <&L2_1>;
 			#cooling-cells = <2>;
 			L1_I_102: l1-icache {
 				compatible = "arm,arch-cache";
-				qcom,dump-size = <0x8800>;
 			};
 
 			L1_D_102: l1-dcache {
 				compatible = "arm,arch-cache";
-				qcom,dump-size = <0x9000>;
 			};
 		};
 
@@ -101,18 +93,16 @@
 			reg = <0x103>;
 			enable-method = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
-			efficiency = <1024>;
+			capacity-dmips-mhz = <1024>;
 			sched-energy-costs = <&CPU_COST_0>;
 			next-level-cache = <&L2_1>;
 			#cooling-cells = <2>;
 			L1_I_103: l1-icache {
 				compatible = "arm,arch-cache";
-				qcom,dump-size = <0x8800>;
 			};
 
 			L1_D_103: l1-dcache {
 				compatible = "arm,arch-cache";
-				qcom,dump-size = <0x9000>;
 			};
 		};
 
@@ -122,13 +112,13 @@
 
 		CPU_COST_0: core-cost0 {
 			busy-cost-data = <
-				 960000	159
-				1305600	207
-				1497600	256
-				1708800	327
-				1804800	343
-				1958400	445
-				2016000	470
+				 488 159
+				 663 207
+				 761 256
+				 868 327
+				 917 343
+				 995 445
+				1024 470
 			>;
 		};
 	};
diff --git a/qcom/sdm429.dtsi b/qcom/sdm429.dtsi
index a7b859f6..bbe4452a 100644
--- a/qcom/sdm429.dtsi
+++ b/qcom/sdm429.dtsi
@@ -31,16 +31,18 @@
 		};
 	};
 
+	/delete-node/ syscon@0b11101c;
+	cpu_debug: syscon@0b01101c {
+		compatible = "syscon";
+		reg = <0x0b01101c 0x4>;
+	};
+
 	/delete-node/ qcom,msm-cpufreq;
 	msm_cpufreq: qcom,msm-cpufreq {
 		compatible = "qcom,msm-cpufreq";
-		clock-names =
-			"l2_clk",
-			"cpu0_clk";
-		/* TODO
-		 * clocks = <&clock_cpu clk_cci_clk>,
-		 * <&clock_cpu clk_a53_bc_clk>;
-		 */
+		clocks = <&apsscc APCS_MUX_CCI_CLK>,
+			 <&apsscc APCS_MUX_C1_CLK>;
+		clock-names = "l2_clk", "cpu0_clk";
 
 		qcom,governor-per-policy;
 
@@ -54,6 +56,8 @@
 			 < 2016000 >;
 	};
 
+	/delete-node/ qcom,cpu4-cpu-ddr-latfloor;
+
 	/delete-node/ qcom,cpu0-cpugrp;
 	cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
 		compatible = "qcom,arm-memlat-cpugrp";
@@ -62,10 +66,10 @@
 		cpu0_computemon: qcom,cpu0-computemon {
 			compatible = "qcom,arm-compute-mon";
 			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
-			qcom,target-dev = <&cpu_cpu_ddr_latfloor>;
+			qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
 			qcom,core-dev-table =
 				< 1305600 MHZ_TO_MBPS(384, 8) >,
-				< 1804800 MHZ_TO_MBPS(557, 8) >;
+				< 1804800 MHZ_TO_MBPS(749, 8) >;
 		};
 	};
 
@@ -109,36 +113,28 @@
 };
 
 &debugcc {
-	compatible = "qcom,msm8937-debugcc";
-	reg = <0x1874000 0x4>,
-		<0xb01101c 0x8>;
-	reg-names = "cc_base", "meas";
-	#clock-cells = <1>;
+	compatible = "qcom,sdm429-debugcc";
+	qcom,cpu = <&cpu_debug>;
 };
 
 &soc {
-	/delete-node/ qcom,cpu-clock-8939@b111050;
-	clock_cpu: qcom,cpu-clock-8939@b111050 {
+	/delete-node/ qcom,clock-cpu@b111050;
+	apsscc: qcom,clock-cpu@b111050 {
 		compatible = "qcom,cpu-clock-sdm429";
-
 		reg =   <0xb011050 0x8>,
 			<0xb1d1050 0x8>,
-			<0x00a412c 0x8>;
+			<0xb016000 0x34>,
+			<0x00a412c 0x8>,
+			<0xb011200 0x100>;
 		reg-names = "apcs-c1-rcg-base",
-			"apcs-cci-rcg-base", "efuse";
-
-		qcom,num-cluster;
-		vdd-c1-supply = <&apc_vreg_corner>;
-		vdd-cci-supply = <&apc_vreg_corner>;
-
-		clocks = <&gcc GPLL0_AO_CLK_SRC>,
-			/* TODO
-			 * <&gcc A53SS_C1_PLL TODO>,
-			 */
-			<&gcc GPLL0_AO_CLK_SRC>,
-			<&gcc GPLL0_AO_CLK_SRC>;
-		clock-names = "clk-c1-4", "clk-c1-5",
-				"clk-cci-4", "clk-cci-2";
+			"apcs-cci-rcg-base", "apcs_pll1", "efuse",
+			"spm_c1_base";
+		clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
+			<&gcc GPLL0_AO_OUT_MAIN>;
+		clock-names = "xo_ao", "gpll0_ao" ;
+		cpu-vdd-supply = <&apc_vreg_corner>;
+		vdd_dig_ao-supply = <&pm8953_s2_level_ao>;
+		vdd_hf_pll-supply = <&pm8953_l7_ao>;
 
 		qcom,speed0-bin-v0-c1 =
 			<          0 0>,
@@ -193,6 +189,29 @@
 			<  533333333 3>;
 
 		#clock-cells = <1>;
+
+		qcom,cpu-isolation {
+			compatible = "qcom,cpu-isolate";
+			cpu0_isolate: cpu0-isolate {
+				qcom,cpu = <&CPU0>;
+				#cooling-cells = <2>;
+			};
+
+			cpu1_isolate: cpu1-isolate {
+				qcom,cpu = <&CPU1>;
+				#cooling-cells = <2>;
+			};
+
+			cpu2_isolate: cpu2-isolate {
+				qcom,cpu = <&CPU2>;
+				#cooling-cells = <2>;
+			};
+
+			cpu3_isolate: cpu3-isolate {
+				qcom,cpu = <&CPU3>;
+				#cooling-cells = <2>;
+			};
+		};
 	};
 
 	/* Disable secure_mem node */
diff --git a/qcom/sdm439-audio.dtsi b/qcom/sdm439-audio.dtsi
index 45af372f..3c4bc7ec 100644
--- a/qcom/sdm439-audio.dtsi
+++ b/qcom/sdm439-audio.dtsi
@@ -16,6 +16,8 @@
 	clock_audio_native: audio_ext_clk_native {
 		status = "disabled";
 		compatible = "qcom,audio-ref-clk";
+		qcom,use-pinctrl = <1>;
+		qcom,codec-ext-clk-src = <2>;
 		#clock-cells = <1>;
 		qcom,codec-mclk-clk-freq = <11289600>;
 		qcom,audio-ref-clk-gpio = <&tlmm 66 0>;
diff --git a/qcom/sdm439-camera-sensor-cdp.dtsi b/qcom/sdm439-camera-sensor-cdp.dtsi
index 6e93d685..2702749e 100644
--- a/qcom/sdm439-camera-sensor-cdp.dtsi
+++ b/qcom/sdm439-camera-sensor-cdp.dtsi
@@ -191,7 +191,7 @@
 		qcom,csiphy-sd-index = <0>;
 		qcom,csid-sd-index = <0>;
 		qcom,mount-angle = <270>;
-		qcom,led-flash-src = </*&led_flash0 TODO*/>;
+		qcom,led-flash-src = <&led_flash0>;
 		qcom,eeprom-src = <&eeprom0>;
 		qcom,actuator-src = <&actuator0>;
 		cam_vana-supply = <&pm8953_l22>;
diff --git a/qcom/sdm439-camera-sensor-mtp.dtsi b/qcom/sdm439-camera-sensor-mtp.dtsi
index cb1f4a2f..58352526 100644
--- a/qcom/sdm439-camera-sensor-mtp.dtsi
+++ b/qcom/sdm439-camera-sensor-mtp.dtsi
@@ -15,7 +15,7 @@
 		qcom,cam-vreg-min-voltage = <2850000>;
 		qcom,cam-vreg-max-voltage = <2850000>;
 		qcom,cam-vreg-op-mode = <80000>;
-		status = "disabled";
+		status = "ok";
 	};
 
 	actuator1: qcom,actuator@1 {
@@ -28,7 +28,7 @@
 		qcom,cam-vreg-min-voltage = <2850000>;
 		qcom,cam-vreg-max-voltage = <2850000>;
 		qcom,cam-vreg-op-mode = <80000>;
-		status = "disabled";
+		status = "ok";
 	};
 
 	eeprom0: qcom,eeprom@0 {
@@ -62,7 +62,7 @@
 		qcom,gpio-req-tbl-label = "CAMIF_MCLK0",
 			"CAM_RESET0",
 			"CAM_VANA";
-		status = "disabled";
+		status = "ok";
 		clocks = <&gcc MCLK0_CLK_SRC>,
 			<&gcc GCC_CAMSS_MCLK0_CLK>;
 		clock-names = "cam_src_clk", "cam_clk";
@@ -142,7 +142,7 @@
 			"sensor_cam_mclk";
 		qcom,cam-power-seq-cfg-val = <1 1 1 1 1 24000000>;
 		qcom,cam-power-seq-delay = <1 1 1 30 30 5>;
-		status = "disabled";
+		status = "ok";
 		clocks = <&gcc MCLK2_CLK_SRC>,
 			<&gcc GCC_CAMSS_MCLK2_CLK>;
 		clock-names = "cam_src_clk", "cam_clk";
@@ -179,7 +179,7 @@
 		qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
 					  "CAM_RESET2",
 					  "CAM_STANDBY2";
-		status = "disabled";
+		status = "ok";
 		clocks = <&gcc MCLK2_CLK_SRC>,
 				<&gcc GCC_CAMSS_MCLK2_CLK>;
 		clock-names = "cam_src_clk", "cam_clk";
@@ -193,7 +193,7 @@
 		qcom,csiphy-sd-index = <0>;
 		qcom,csid-sd-index = <0>;
 		qcom,mount-angle = <270>;
-		qcom,led-flash-src = </*&led_flash0 TODO*/>;
+		qcom,led-flash-src = <&led_flash0>;
 		qcom,eeprom-src = <&eeprom0>;
 		qcom,actuator-src = <&actuator0>;
 		cam_vana-supply = <&pm8953_l22>;
diff --git a/qcom/sdm439-camera-sensor-qrd.dtsi b/qcom/sdm439-camera-sensor-qrd.dtsi
index 1c60c8df..25882a4b 100644
--- a/qcom/sdm439-camera-sensor-qrd.dtsi
+++ b/qcom/sdm439-camera-sensor-qrd.dtsi
@@ -15,7 +15,7 @@
 		qcom,cam-vreg-min-voltage = <2850000>;
 		qcom,cam-vreg-max-voltage = <2850000>;
 		qcom,cam-vreg-op-mode = <80000>;
-		status = "disabled";
+		status = "ok";
 	};
 
 	actuator1: qcom,actuator@1 {
@@ -28,7 +28,7 @@
 		qcom,cam-vreg-min-voltage = <2850000>;
 		qcom,cam-vreg-max-voltage = <2850000>;
 		qcom,cam-vreg-op-mode = <80000>;
-		status = "disabled";
+		status = "ok";
 	};
 
 	eeprom0: qcom,eeprom@0 {
@@ -62,7 +62,7 @@
 		qcom,gpio-req-tbl-label = "CAMIF_MCLK0",
 			"CAM_RESET0",
 			"CAM_VANA";
-		status = "disabled";
+		status = "ok";
 		clocks = <&gcc MCLK0_CLK_SRC>,
 			<&gcc GCC_CAMSS_MCLK0_CLK>;
 		clock-names = "cam_src_clk", "cam_clk";
@@ -143,7 +143,7 @@
 			"sensor_cam_mclk";
 		qcom,cam-power-seq-cfg-val = <1 1 1 1 1 24000000>;
 		qcom,cam-power-seq-delay = <1 1 1 30 30 5>;
-		status = "disabled";
+		status = "ok";
 		clocks = <&gcc MCLK2_CLK_SRC>,
 			<&gcc GCC_CAMSS_MCLK2_CLK>;
 		clock-names = "cam_src_clk", "cam_clk";
@@ -157,7 +157,7 @@
 		qcom,csiphy-sd-index = <0>;
 		qcom,csid-sd-index = <0>;
 		qcom,mount-angle = <90>;
-		qcom,led-flash-src = </*&led_flash0 TODO*/>;
+		qcom,led-flash-src = <&led_flash0>;
 		qcom,eeprom-src = <&eeprom0>;
 		qcom,actuator-src = <&actuator0>;
 		cam_vana-supply = <&pm8953_l22>;
diff --git a/qcom/sdm439-ext-audio-mtp.dtsi b/qcom/sdm439-ext-audio-mtp.dtsi
index 2d53e873..ff2dc250 100644
--- a/qcom/sdm439-ext-audio-mtp.dtsi
+++ b/qcom/sdm439-ext-audio-mtp.dtsi
@@ -2,6 +2,10 @@
 	status = "disabled";
 };
 
+&pmic_analog_codec {
+	status = "disabled";
+};
+
 &wsa881x_i2c_f {
 	status = "disabled";
 };
@@ -10,6 +14,10 @@
 	status = "disabled";
 };
 
+&wsa881x_analog_clk {
+	status = "disabled";
+};
+
 &cdc_pri_mi2s_gpios {
 	status = "disabled";
 };
@@ -42,6 +50,10 @@
 	status = "okay";
 };
 
+&clock_audio_native {
+	status = "okay";
+};
+
 &wcd9335 {
 	status = "okay";
 };
diff --git a/qcom/sdm439-pm8953.dtsi b/qcom/sdm439-pm8953.dtsi
index 7dad3778..27b9179e 100644
--- a/qcom/sdm439-pm8953.dtsi
+++ b/qcom/sdm439-pm8953.dtsi
@@ -76,9 +76,9 @@
 		vdd_hf_pll-supply = <&pm8953_l7_ao>;
 	};
 
-	qcom,cpu-clock-8939@b111050 {
+	qcom,clock-cpu@b111050 {
 		/delete-property/ vdd-c0-supply;
-		/delete-property/ vdd-c1-supply;
+		/delete-property/ cpu-vdd-supply;
 		/delete-property/ vdd-cci-supply;
 	};
 
@@ -271,7 +271,7 @@
 	pa-therm0 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-sensors = <&pm8953_adc_tm 0x36>;
+		thermal-sensors = <&pm8953_adc_tm VADC_LR_MUX7_HW_ID>;
 		thermal-governor = "user_space";
 		wake-capable-sensor;
 
@@ -287,7 +287,7 @@
 
 &pm8953_vadc {
 	pinctrl-0 = <&pa_therm1_default>;
-	/delete-node/ chan@13;
+	/delete-node/ case_therm;
 };
 
 &pm8953_mpps {
diff --git a/qcom/sdm439-pmi632.dtsi b/qcom/sdm439-pmi632.dtsi
index 6ddeacff..e9a3d57f 100644
--- a/qcom/sdm439-pmi632.dtsi
+++ b/qcom/sdm439-pmi632.dtsi
@@ -16,7 +16,6 @@
 };
 
 &usb_otg {
-	vbus_otg-supply = <&smb5_vbus>;
 	extcon = <&pmi632_charger>;
 };
 
@@ -25,6 +24,17 @@
 	qcom,ps-hold-shutdown-disable;
 };
 
+&soc {
+	led_flash0: qcom,camera-flash {
+		cell-index = <0>;
+		compatible = "qcom,camera-flash";
+		qcom,flash-type = <1>;
+		qcom,flash-source = <&pmi632_flash0 &pmi632_flash1>;
+		qcom,torch-source = <&pmi632_torch0 &pmi632_torch1>;
+		qcom,switch-source = <&pmi632_switch0>;
+	};
+};
+
 / {
 	mtp_batterydata: qcom,battery-data {
 		qcom,batt-id-range-pct = <15>;
diff --git a/qcom/sdm439-qrd.dtsi b/qcom/sdm439-qrd.dtsi
index b2b1384e..ddcaeb33 100644
--- a/qcom/sdm439-qrd.dtsi
+++ b/qcom/sdm439-qrd.dtsi
@@ -346,12 +346,6 @@
 #include "smb1355.dtsi"
 };
 
-&pmi632_vadc {
-	chan@4a {
-		qcom,scale-function = <22>;
-	};
-};
-
 &pmi632_gpios {
 	smb_en {
 		smb_en_default: smb_en_default {
diff --git a/qcom/sdm439.dtsi b/qcom/sdm439.dtsi
index e740be3f..e0006c1f 100644
--- a/qcom/sdm439.dtsi
+++ b/qcom/sdm439.dtsi
@@ -36,15 +36,11 @@
 	/delete-node/ qcom,msm-cpufreq;
 	msm_cpufreq: qcom,msm-cpufreq {
 		compatible = "qcom,msm-cpufreq";
-		clock-names =
-			"l2_clk",
-			"cpu0_clk",
-			"cpu4_clk";
-		/* TODO
-		 * clocks = <&clock_cpu clk_cci_clk>,
-		 * <&clock_cpu clk_a53_bc_clk>,
-		 * <&clock_cpu clk_a53_lc_clk>;
-		 */
+
+		clocks = <&apsscc APCS_MUX_CCI_CLK>,
+			<&apsscc APCS_MUX_C1_CLK>,
+			<&apsscc APCS_MUX_C0_CLK>;
+		clock-names = "l2_clk", "cpu0_clk", "cpu4_clk";
 
 		qcom,governor-per-policy;
 
@@ -101,13 +97,21 @@
 		operating-points-v2 = <&ddr_bw_opp_table>;
 	};
 
+	/delete-node/ qcom,cpu4-cpu-ddr-latfloor;
+	cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {
+		compatible = "qcom,devbw";
+		governor = "performance";
+		qcom,src-dst-ports =
+			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+		qcom,active-only;
+		operating-points-v2 = <&ddr_bw_opp_table>;
+	};
+
 	/delete-node/ qcom,cci;
 	cci_cache: qcom,cci {
 		compatible = "devfreq-simple-dev";
 		clock-names = "devfreq_clk";
-		/* TODO
-		 * clocks = <&clock_cpu clk_cci_clk>;
-		 */
+		clocks = <&apsscc APCS_MUX_CCI_CLK>;
 		governor = "performance";
 		freq-tbl-khz =
 			<  400000 >,
@@ -125,7 +129,7 @@
 		cpu0_computemon: qcom,cpu0-computemon {
 			compatible = "qcom,arm-compute-mon";
 			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
-			qcom,target-dev = <&cpu_cpu_ddr_latfloor>;
+			qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
 			qcom,core-dev-table =
 				< 1305600 MHZ_TO_MBPS(384, 8) >,
 				< 1804800 MHZ_TO_MBPS(557, 8) >;
@@ -140,7 +144,7 @@
 		cpu4_computemon: qcom,cpu4-computemon {
 			compatible = "qcom,arm-compute-mon";
 			qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
-			qcom,target-dev = <&cpu_cpu_ddr_latfloor>;
+			qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
 			qcom,core-dev-table =
 				< 1171200 MHZ_TO_MBPS(384, 8) >,
 				< 1459200 MHZ_TO_MBPS(749, 8) >;
@@ -155,13 +159,13 @@
 
 		CPU_COST_0: core-cost0 {
 			busy-cost-data = <
-				 800000	137
-				1305600	207
-				1497600	256
-				1708800	327
-				1804800	343
-				1958400	445
-				2016000	470
+				 406 137
+				 663 207
+				 761 256
+				 868 327
+				 917 343
+				 995 445
+				1024 470
 			>;
 			idle-cost-data = <
 				100 80 60 40
@@ -170,11 +174,11 @@
 
 		CPU_COST_1: core-cost1 {
 			busy-cost-data = <
-				 768000	43
-				 998400	56
-				1171200	71
-				1305600	89
-				1459200	120
+				355 43
+				461 56
+				541 71
+				603 89
+				674 120
 			>;
 		};
 	};
@@ -233,11 +237,12 @@
 	};
 };
 
-&clock_cpu {
-	compatible = "qcom,cpu-clock-sdm439";
-	vdd-c0-supply = <&apc_vreg_corner>;
-	vdd-c1-supply = <&apc_vreg_corner>;
-	vdd-cci-supply = <&apc_vreg_corner>;
+&apsscc {
+	cpu-vdd-supply = <&apc_vreg_corner>;
+	vdd_hf_pll-supply = <&pm8953_l7_ao>;
+	vdd_dig_ao-supply = <&pm8953_s2_level_ao>;
+	vdd_sr2_pll-supply = <&pm8953_l7_ao>;
+	vdd_sr2_dig_ao-supply = <&pm8953_s2_level_ao>;
 	qcom,speed0-bin-v0-c0 =
 		<          0 0>,
 		<  768000000 1>,
diff --git a/qcom/sdm660-camera.dtsi b/qcom/sdm660-camera.dtsi
index bd3827a9..420102e1 100644
--- a/qcom/sdm660-camera.dtsi
+++ b/qcom/sdm660-camera.dtsi
@@ -298,6 +298,7 @@
 					<&mmss_bimc_smmu 0xc01>,
 					<&mmss_bimc_smmu 0xc02>,
 					<&mmss_bimc_smmu 0xc03>;
+			iommu-cells = <1>;
 			label = "vfe";
 			qcom,scratch-buf-support;
 		};
@@ -305,18 +306,21 @@
 		msm_cam_smmu_cb2 {
 			compatible = "qcom,msm-cam-smmu-cb";
 			iommus = <&mmss_bimc_smmu 0xa00>;
+			iommu-cells = <1>;
 			label = "cpp";
 		};
 
 		msm_cam_smmu_cb4 {
 			compatible = "qcom,msm-cam-smmu-cb";
 			iommus = <&mmss_bimc_smmu 0x800>;
+			iommu-cells = <1>;
 			label = "jpeg_enc0";
 		};
 
 		msm_cam_smmu_cb5 {
 			compatible = "qcom,msm-cam-smmu-cb";
 			iommus = <&mmss_bimc_smmu 0x801>;
+			iommu-cells = <1>;
 			label = "jpeg_dma";
 		};
 	};
diff --git a/qcom/sdm660-coresight.dtsi b/qcom/sdm660-coresight.dtsi
index 041e8a4d..0758d73a 100644
--- a/qcom/sdm660-coresight.dtsi
+++ b/qcom/sdm660-coresight.dtsi
@@ -17,14 +17,14 @@
 
 	tmc_etr: tmc@6048000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b961>;
+		arm,primecell-periphid = <0x000bb961>;
 
 		reg = <0x6048000 0x1000>,
 		      <0x6064000 0x15000>;
 		reg-names = "tmc-base", "bam-base";
 
 		arm,buffer-size = <0x400000>;
-		arm,sg-enable;
+		arm,scatter-gather;
 		arm,default-sink;
 		coresight-csr = <&csr>;
 
@@ -46,7 +46,7 @@
 
 	replicator_qdss: replicator@6046000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b909>;
+		arm,primecell-periphid = <0x000bb909>;
 
 		reg = <0x6046000 0x1000>;
 		reg-names = "replicator-base";
@@ -81,7 +81,7 @@
 
 	tmc_etf: tmc@6047000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b961>;
+		arm,primecell-periphid = <0x000bb961>;
 
 		reg = <0x6047000 0x1000>;
 		reg-names = "tmc-base";
@@ -120,7 +120,7 @@
 
 	funnel_merg: funnel@6045000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b908>;
+		arm,primecell-periphid = <0x000bb908>;
 
 		reg = <0x6045000 0x1000>;
 		reg-names = "funnel-base";
@@ -163,7 +163,7 @@
 
 	funnel_in0: funnel@6041000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b908>;
+		arm,primecell-periphid = <0x000bb908>;
 
 		reg = <0x6041000 0x1000>;
 		reg-names = "funnel-base";
@@ -213,7 +213,7 @@
 
 	funnel_in1: funnel@6042000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b908>;
+		arm,primecell-periphid = <0x000bb908>;
 
 		reg = <0x6042000 0x1000>;
 		reg-names = "funnel-base";
@@ -272,7 +272,7 @@
 
 	funnel_apss_merg: funnel@7b70000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b908>;
+		arm,primecell-periphid = <0x000bb908>;
 
 		reg = <0x7b70000 0x1000>;
 		reg-names = "funnel-base";
@@ -323,7 +323,7 @@
 
 	funnel_apss: funnel@7b60000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b908>;
+		arm,primecell-periphid = <0x000bb908>;
 
 		reg = <0x7b60000 0x1000>;
 		reg-names = "funnel-base";
@@ -414,7 +414,7 @@
 
 	stm: stm@6002000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b962>;
+		arm,primecell-periphid = <0x000bb962>;
 
 		reg = <0x6002000 0x1000>,
 		      <0x16280000 0x180000>;
@@ -596,7 +596,7 @@
 	cti0: cti@6010000 {
 		compatible = "arm,primecell";
 		reg = <0x6010000 0x1000>;
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg-names = "cti-base";
 
 		coresight-name = "coresight-cti0";
@@ -608,7 +608,7 @@
 
 	cti1: cti@6011000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x6011000 0x1000>;
 		reg-names = "cti-base";
 
@@ -621,7 +621,7 @@
 
 	cti2: cti@6012000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x6012000 0x1000>;
 		reg-names = "cti-base";
 
@@ -638,7 +638,7 @@
 
 	cti3: cti@6013000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x6013000 0x1000>;
 		reg-names = "cti-base";
 
@@ -651,7 +651,7 @@
 
 	cti4: cti@6014000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x6014000 0x1000>;
 		reg-names = "cti-base";
 
@@ -664,7 +664,7 @@
 
 	cti5: cti@6015000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x6015000 0x1000>;
 		reg-names = "cti-base";
 
@@ -677,7 +677,7 @@
 
 	cti6: cti@6016000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x6016000 0x1000>;
 		reg-names = "cti-base";
 
@@ -690,7 +690,7 @@
 
 	cti7: cti@6017000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x6017000 0x1000>;
 		reg-names = "cti-base";
 
@@ -703,7 +703,7 @@
 
 	cti8: cti@6018000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x6018000 0x1000>;
 		reg-names = "cti-base";
 
@@ -716,7 +716,7 @@
 
 	cti9: cti@6019000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x6019000 0x1000>;
 		reg-names = "cti-base";
 
@@ -729,7 +729,7 @@
 
 	cti10: cti@601a000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x601a000 0x1000>;
 		reg-names = "cti-base";
 
@@ -742,7 +742,7 @@
 
 	cti11: cti@601b000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x601b000 0x1000>;
 		reg-names = "cti-base";
 
@@ -755,7 +755,7 @@
 
 	cti12: cti@601c000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x601c000 0x1000>;
 		reg-names = "cti-base";
 
@@ -768,7 +768,7 @@
 
 	cti13: cti@601d000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x601d000 0x1000>;
 		reg-names = "cti-base";
 
@@ -781,7 +781,7 @@
 
 	cti14: cti@601e000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x601e000 0x1000>;
 		reg-names = "cti-base";
 
@@ -794,7 +794,7 @@
 
 	cti15: cti@601f000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x601f000 0x1000>;
 		reg-names = "cti-base";
 
@@ -807,7 +807,7 @@
 
 	cti_cpu0: cti@7820000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 
 		reg = <0x7820000 0x1000>;
 		reg-names = "cti-base";
@@ -822,7 +822,7 @@
 
 	cti_cpu1: cti@7920000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x7920000 0x1000>;
 		reg-names = "cti-base";
 
@@ -836,7 +836,7 @@
 
 	cti_cpu2: cti@7a20000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x7a20000 0x1000>;
 		reg-names = "cti-base";
 
@@ -850,7 +850,7 @@
 
 	cti_cpu3: cti@7b20000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x7b20000 0x1000>;
 		reg-names = "cti-base";
 
@@ -864,7 +864,7 @@
 
 	cti_cpu4: cti@7c20000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x7c20000 0x1000>;
 		reg-names = "cti-base";
 
@@ -878,7 +878,7 @@
 
 	cti_cpu5: cti@7d20000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x7d20000 0x1000>;
 		reg-names = "cti-base";
 
@@ -892,7 +892,7 @@
 
 	cti_cpu6: cti@7e20000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x7e20000 0x1000>;
 		reg-names = "cti-base";
 
@@ -906,7 +906,7 @@
 
 	cti_cpu7: cti@7f20000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x7f20000 0x1000>;
 		reg-names = "cti-base";
 
@@ -920,7 +920,7 @@
 
 	cti_apss: cti@7b80000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x7b80000 0x1000>;
 		reg-names = "cti-base";
 
@@ -933,7 +933,7 @@
 
 	cti_apss_dl: cti@7bc1000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x7bc1000 0x1000>;
 		reg-names = "cti-base";
 
@@ -946,7 +946,7 @@
 
 	cti_olc: cti@7b91000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x7b91000 0x1000>;
 		reg-names = "cti-base";
 
@@ -959,7 +959,7 @@
 
 	cti_turing: cti@7068000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x7068000 0x1000>;
 		reg-names = "cti-base";
 
@@ -972,7 +972,7 @@
 
 	cti_wcss0: cti@71a4000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x71a4000 0x1000>;
 		reg-names = "cti-base";
 
@@ -986,7 +986,7 @@
 
 	cti_wcss1: cti@71a5000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x71a5000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1000,7 +1000,7 @@
 
 	cti_wcss2: cti@71a6000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x71a6000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1014,7 +1014,7 @@
 
 	cti_mmss: cti@7188000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x7188000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1027,7 +1027,7 @@
 
 	cti_isdb: cti@7121000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x7121000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1041,7 +1041,7 @@
 
 	cti_rpm: cti@7048000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x7048000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1054,7 +1054,7 @@
 
 	cti_mss: cti@7041000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b966>;
+		arm,primecell-periphid = <0x000bb966>;
 		reg = <0x7041000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1067,7 +1067,7 @@
 
 	funnel_qatb: funnel@6005000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b908>;
+		arm,primecell-periphid = <0x000bb908>;
 
 		reg = <0x6005000 0x1000>;
 		reg-names = "funnel-base";
@@ -1525,7 +1525,7 @@
 
 	funnel_dlct: funnel@71c3000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x0003b908>;
+		arm,primecell-periphid = <0x000bb908>;
 
 		reg = <0x71c3000 0x1000>;
 		reg-names = "funnel-base";
diff --git a/qcom/sdm660-vidc.dtsi b/qcom/sdm660-vidc.dtsi
index 00d9058c..6bcf1feb 100644
--- a/qcom/sdm660-vidc.dtsi
+++ b/qcom/sdm660-vidc.dtsi
@@ -14,7 +14,6 @@
 		qcom,hfi = "venus";
 		qcom,hfi-version = "3xx";
 		qcom,firmware-name = "venus";
-		qcom,never-unload-fw;
 		qcom,sw-power-collapse;
 		qcom,max-secure-instances = <5>;
 		qcom,reg-presets =
diff --git a/qcom/sdm660.dtsi b/qcom/sdm660.dtsi
index ba1e2bde..7bfc1f8e 100644
--- a/qcom/sdm660.dtsi
+++ b/qcom/sdm660.dtsi
@@ -387,7 +387,7 @@
 			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
 			reusable;
 			alignment = <0x0 0x400000>;
-			size = <0x0 0x140000>;
+			size = <0x0 0x1a0000>;
 		};
 
 		venus_fw_mem: venus_fw_region {
@@ -543,6 +543,101 @@
 			compatible = "qcom,mem-dump";
 			memory-region = <&dump_mem>;
 
+			rpm_sw_dump {
+				qcom,dump-size = <0x28000>;
+				qcom,dump-id = <0xea>;
+			};
+
+			pmic_dump {
+				qcom,dump-size = <0x10000>;
+				qcom,dump-id = <0xe4>;
+			};
+
+			vsense_dump {
+				qcom,dump-size = <0x1000>;
+				qcom,dump-id = <0xe9>;
+			};
+
+			tmc_etf_dump {
+				qcom,dump-size = <0x10000>;
+				qcom,dump-id = <0xf0>;
+			};
+
+			tmc_etr_reg_dump {
+				qcom,dump-size = <0x1000>;
+				qcom,dump-id = <0x100>;
+			};
+
+			tmc_etf_reg_dump {
+				qcom,dump-size = <0x1000>;
+				qcom,dump-id = <0x101>;
+			};
+
+			misc_data_dump {
+				qcom,dump-size = <0x1000>;
+				qcom,dump-id = <0xe8>;
+			};
+
+			dcc_reg_dump {
+				qcom,dump-size = <0x1000>;
+				qcom,dump-id = <0xe6>;
+			};
+
+			dcc_sram_dump {
+				qcom,dump-size = <0x2000>;
+				qcom,dump-id = <0xe7>;
+			};
+
+			log_buf_dump {
+				qcom,dump-size = <0x10000>;
+				qcom,dump-id = <0x110>;
+			};
+
+			log_buf_first_idx_dump {
+				qcom,dump-size = <0x0>;
+				qcom,dump-id = <0x111>;
+			};
+
+			etm_reg0_dump {
+				qcom,dump-size = <0x1000>;
+				qcom,dump-id = <0xa0>;
+			};
+
+			etm_reg1_dump {
+				qcom,dump-size = <0x1000>;
+				qcom,dump-id = <0xa1>;
+			};
+
+			etm_reg2_dump {
+				qcom,dump-size = <0x1000>;
+				qcom,dump-id = <0xa2>;
+			};
+
+			etm_reg3_dump {
+				qcom,dump-size = <0x1000>;
+				qcom,dump-id = <0xa3>;
+			};
+
+			etm_reg4_dump {
+				qcom,dump-size = <0x1000>;
+				qcom,dump-id = <0xa4>;
+			};
+
+			etm_reg5_dump {
+				qcom,dump-size = <0x1000>;
+				qcom,dump-id = <0xa5>;
+			};
+
+			etm_reg6_dump {
+				qcom,dump-size = <0x1000>;
+				qcom,dump-id = <0xa6>;
+			};
+
+			etm_reg7_dump {
+				qcom,dump-size = <0x1000>;
+				qcom,dump-id = <0xa7>;
+			};
+
 			c_scandump {
 				qcom,dump-size = <0x40000>;
 				qcom,dump-id = <0xeb>;
diff --git a/qcom/smb1394.dtsi b/qcom/smb1394.dtsi
new file mode 100644
index 00000000..23d03b6b
--- /dev/null
+++ b/qcom/smb1394.dtsi
@@ -0,0 +1,40 @@
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+smb1394: qcom,smb1394@34 {
+	compatible = "qcom,i2c-pmic";
+	reg = <0x34>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <3>;
+	qcom,periph-map = <0x6 0x26 0x27>;
+	status = "disabled";
+
+	smb1394_revid: qcom,revid {
+		compatible = "qcom,qpnp-revid";
+		reg = <0x100>;
+	};
+
+	smb1394_div2_cp_primary: qcom,div2_cp_pry {
+		compatible = "qcom,smb1394-div2-cp-primary";
+		qcom,pmic-revid = <&smb1394_revid>;
+		#io-channel-cells = <1>;
+		interrupts = <0x26 0x1 IRQ_TYPE_EDGE_RISING>,
+			     <0x26 0x3 IRQ_TYPE_EDGE_RISING>,
+			     <0x26 0x5 IRQ_TYPE_EDGE_RISING>,
+			     <0x26 0x7 IRQ_TYPE_EDGE_RISING>,
+			     <0x27 0x5 IRQ_TYPE_EDGE_RISING>,
+			     <0x27 0x6 IRQ_TYPE_EDGE_RISING>,
+			     <0x27 0x7 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "temp-shdwn",
+				  "div2-irev",
+				  "usbin-uv",
+				  "usbin-ov",
+				  "div2-ilim",
+				  "div2-win-uv",
+				  "div2-win-ov";
+		qcom,div2-cp-min-ilim-ua = <1000000>;
+		status = "disabled";
+	};
+};
author	JohnnLee <johnnlee@google.com>	2022-01-05 18:37:44 +0800
committer	JohnnLee <johnnlee@google.com>	2022-01-05 18:38:18 +0800
commit	0a9d6a7a641c752059414bf71c8821313d91d390 (patch)
tree	d757baebb4d172bf452befb0c6b88cb813628bcf
parent	9aa479ab86afd2c5c0114143de441b7b404f3101 (diff)
parent	e15a3ffd15056de6bd8f149434d1e5034d957ea5 (diff)
download	devicetree-android-msm-redbull-4.19-t-beta-2.tar.gz