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authorMidas Chien <midaschieh@google.com>2024-03-15 01:20:51 +0000
committerAutomerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com>2024-03-15 01:20:51 +0000
commit29693bdeb73addbc7009e7afbf10d7378765d00a (patch)
tree63dc1238a450392f74f762c8a526ffc4922faed4
parent25090b874bdcd1f570136bc3d63851dcb1a22313 (diff)
parent2decb3faf39d4be5cfc34d09aeabc91d6230e7ac (diff)
downloadshusky-android-gs-shusky-5.15-android15-dp.tar.gz
Original change: https://partner-android-review.googlesource.com/c/kernel/private/devices/google/shusky/+/2757053 Change-Id: Iff0a6d961f6ced2b18c6e16c564baa7127447bbb Signed-off-by: Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com>
-rw-r--r--display/panel-google-hk3.c17
1 files changed, 14 insertions, 3 deletions
diff --git a/display/panel-google-hk3.c b/display/panel-google-hk3.c
index 8986378..7020f8e 100644
--- a/display/panel-google-hk3.c
+++ b/display/panel-google-hk3.c
@@ -323,7 +323,7 @@ static const struct drm_dsc_config fhd_pps_config = {
#define HK3_TE_USEC_AOD 693
#define HK3_TE_USEC_120HZ 273
#define HK3_TE_USEC_60HZ_HS 8500
-#define HK3_TE_USEC_60HZ_NS 546
+#define HK3_TE_USEC_60HZ_NS 1223
#define HK3_TE_PERIOD_DELTA_TOLERANCE_USEC 2000
#define MIPI_DSI_FREQ_DEFAULT 1368
@@ -584,13 +584,24 @@ static void hk3_set_panel_feat(struct exynos_panel *ctx,
EXYNOS_DCS_BUF_ADD(ctx, 0xB0, 0x00, 0x02, 0xB9);
val = test_bit(FEAT_OP_NS, feat) ? 0x01 : 0x00;
EXYNOS_DCS_BUF_ADD(ctx, 0xB9, val);
+ /* Fixed TE width setting */
+ EXYNOS_DCS_BUF_ADD(ctx, 0xB0, 0x00, 0x08, 0xB9);
+ if (test_bit(FEAT_OP_NS, feat)) {
+ EXYNOS_DCS_BUF_ADD(ctx, 0xB9, 0x0B, 0x43, 0x00, 0x2F,
+ 0x0B, 0x43, 0x00, 0x2F);
+ } else {
+ EXYNOS_DCS_BUF_ADD(ctx, 0xB9, 0x0B, 0xBB, 0x00, 0x2F,
+ 0x0B, 0xBB, 0x00, 0x2F);
+ }
} else {
/* Changeable TE */
EXYNOS_DCS_BUF_ADD(ctx, 0xB9, 0x04);
/* Changeable TE width setting and frequency */
EXYNOS_DCS_BUF_ADD(ctx, 0xB0, 0x00, 0x04, 0xB9);
- /* width 273us in normal mode */
- EXYNOS_DCS_BUF_ADD(ctx, 0xB9, 0x0B, 0xBB, 0x00, 0x2F);
+ if (test_bit(FEAT_OP_NS, feat))
+ EXYNOS_DCS_BUF_ADD(ctx, 0xB9, 0x0B, 0x43, 0x00, 0x2F);
+ else
+ EXYNOS_DCS_BUF_ADD(ctx, 0xB9, 0x0B, 0xBB, 0x00, 0x2F);
}
}