diff options
| author | Midas Chien <midaschieh@google.com> | 2024-03-04 14:54:04 +0000 |
|---|---|---|
| committer | Midas Chien <midaschieh@google.com> | 2024-03-15 00:58:51 +0000 |
| commit | 2decb3faf39d4be5cfc34d09aeabc91d6230e7ac (patch) | |
| tree | 14bfad477ff5f8924fb9a7379b69efaa2ffc2cc0 | |
| parent | c9dae677233c70bd804d39e29c24b49b9348a080 (diff) | |
| download | shusky-android-gs-shusky-5.15-android14-qpr3-beta.tar.gz | |
panel: hk3: adjust TE pulse width at NS modeandroid-u-qpr3-beta-2.1_r0.8android-gs-shusky-5.15-android14-qpr3-beta
Increase TE pulse width at NS mode to avoid underrun issue.
Bug: 324009663
Test: NS/HS switch, various video, camera, chrome, YT
Change-Id: Ie180cf30c601e8dbd11ac4d47640d2f740f30d1e
Signed-off-by: Midas Chien <midaschieh@google.com>
| -rw-r--r-- | display/panel-google-hk3.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/display/panel-google-hk3.c b/display/panel-google-hk3.c index 8986378..7020f8e 100644 --- a/display/panel-google-hk3.c +++ b/display/panel-google-hk3.c @@ -323,7 +323,7 @@ static const struct drm_dsc_config fhd_pps_config = { #define HK3_TE_USEC_AOD 693 #define HK3_TE_USEC_120HZ 273 #define HK3_TE_USEC_60HZ_HS 8500 -#define HK3_TE_USEC_60HZ_NS 546 +#define HK3_TE_USEC_60HZ_NS 1223 #define HK3_TE_PERIOD_DELTA_TOLERANCE_USEC 2000 #define MIPI_DSI_FREQ_DEFAULT 1368 @@ -584,13 +584,24 @@ static void hk3_set_panel_feat(struct exynos_panel *ctx, EXYNOS_DCS_BUF_ADD(ctx, 0xB0, 0x00, 0x02, 0xB9); val = test_bit(FEAT_OP_NS, feat) ? 0x01 : 0x00; EXYNOS_DCS_BUF_ADD(ctx, 0xB9, val); + /* Fixed TE width setting */ + EXYNOS_DCS_BUF_ADD(ctx, 0xB0, 0x00, 0x08, 0xB9); + if (test_bit(FEAT_OP_NS, feat)) { + EXYNOS_DCS_BUF_ADD(ctx, 0xB9, 0x0B, 0x43, 0x00, 0x2F, + 0x0B, 0x43, 0x00, 0x2F); + } else { + EXYNOS_DCS_BUF_ADD(ctx, 0xB9, 0x0B, 0xBB, 0x00, 0x2F, + 0x0B, 0xBB, 0x00, 0x2F); + } } else { /* Changeable TE */ EXYNOS_DCS_BUF_ADD(ctx, 0xB9, 0x04); /* Changeable TE width setting and frequency */ EXYNOS_DCS_BUF_ADD(ctx, 0xB0, 0x00, 0x04, 0xB9); - /* width 273us in normal mode */ - EXYNOS_DCS_BUF_ADD(ctx, 0xB9, 0x0B, 0xBB, 0x00, 0x2F); + if (test_bit(FEAT_OP_NS, feat)) + EXYNOS_DCS_BUF_ADD(ctx, 0xB9, 0x0B, 0x43, 0x00, 0x2F); + else + EXYNOS_DCS_BUF_ADD(ctx, 0xB9, 0x0B, 0xBB, 0x00, 0x2F); } } |