diff options
| author | Jacob Pan <jacob.jun.pan@intel.com> | 2009-08-20 12:37:15 -0700 |
|---|---|---|
| committer | Patrick Tjin <pattjin@google.com> | 2014-07-21 20:22:39 -0700 |
| commit | 438855bcdd65afc849689f334bc2c7e870301573 (patch) | |
| tree | 0a1d9f43c59548c09a7fb8d3d61be9a36c6204e7 | |
| parent | 5dec7c4fa651e7b20e3c79e1187da5e35aeba08f (diff) | |
| download | bootstub-438855bcdd65afc849689f334bc2c7e870301573.tar.gz | |
spi: ported spi clock auto detect from kernel mrst_spi.c
Signed-off-by: Jacob Pan <jacob.jun.pan@intel.com>
| -rw-r--r-- | spi-uart.c | 7 | ||||
| -rw-r--r-- | spi-uart.h | 13 |
2 files changed, 18 insertions, 2 deletions
@@ -27,6 +27,7 @@ static volatile struct mrst_spi_reg *pspi = 0; static void spi_init() { u32 ctrlr0; + u32 *clk_reg, clk_cdiv; switch (*(int *)SPI_TYPE) { case 0: @@ -52,8 +53,10 @@ static void spi_init() /* set a default baud rate, 115200 */ /* feng, need make sure SPIC and MAXIM3110 match */ //spi_enable_clk(32); - /* 100MHz SPI clock / 115200 BAUD rate */ - pspi->baudr = 0x364; + /* get SPI controller operating freq info */ + clk_reg = (u32 *)MRST_CLK_SPI0_REG; + clk_cdiv = ((*clk_reg) & CLK_SPI_CDIV_MASK) >> CLK_SPI_CDIV_OFFSET; + pspi->baudr = MRST_SPI_CLK_BASE / (clk_cdiv + 1) / 115200; /* need set the transmit threshhol? */ /* pspi->txftlr = 0x3; */ @@ -12,6 +12,19 @@ typedef volatile unsigned int vu32; #define MRST_REGBASE_SPI1 0xff128400 #define MRST_REGBASE_SPI2 0xff128800 +/* HW info for MRST CLk Control Unit, one 32b reg */ +#define MRST_SPI_CLK_BASE 100000000 /* 100m */ +#define MRST_CLK_SPI0_REG 0xff11d86c +#define CLK_SPI_BDIV_OFFSET 0 +#define CLK_SPI_BDIV_MASK 0x00000007 +#define CLK_SPI_CDIV_OFFSET 9 +#define CLK_SPI_CDIV_MASK 0x00000e00 +#define CLK_SPI_CDIV_100M 0x0 +#define CLK_SPI_CDIV_50M 0x1 +#define CLK_SPI_CDIV_33M 0x2 +#define CLK_SPI_CDIV_25M 0x3 +#define CLK_SPI_DISABLE_OFFSET 8 + struct mrst_spi_reg { vu32 ctrlr0; /* control reg 0 */ vu32 ctrlr1; /* control reg 1 */ |