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| author | Petri Gynther <pgynther@google.com> | 2023-03-14 14:04:02 -0700 |
|---|---|---|
| committer | Petri Gynther <pgynther@google.com> | 2023-04-17 16:20:14 -0700 |
| commit | 7ec069210c5f35bcfecf8f228307ee30a8a44cab (patch) | |
| tree | 19ee91f952928f8faeae1618f003ba05c8985775 | |
| parent | f780ac56981c61e7a1bb746c43fd6fc775540954 (diff) | |
| download | zuma-7ec069210c5f35bcfecf8f228307ee30a8a44cab.tar.gz | |
libhwc2.1: Assign 3 DPPs for external display
External display will use these DPPs:
DPP_GFS6, DPP_GFS7, DPP_VGRFS5
All of them in DPUF1, connected with AXI0 port.
Bug: 238373481
Bug: 272157718
Bug: 272184398
Test: manual DP unit test
Change-Id: I92739abca0ecc816e2f43cffdab352ae77254582
| -rw-r--r-- | libhwc2.1/ExynosHWCModule.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/libhwc2.1/ExynosHWCModule.h b/libhwc2.1/ExynosHWCModule.h index 16dd98d..d434a0e 100644 --- a/libhwc2.1/ExynosHWCModule.h +++ b/libhwc2.1/ExynosHWCModule.h @@ -118,13 +118,13 @@ static const exynos_mpp_t available_otf_mpp_units[] = { static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)}, // DPP11(IDMA_GFS6) in DPUF1 is connected with AXI0 port - {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS6", 6, 0, HWC_DISPLAY_SECONDARY_BIT, + {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS6", 6, 0, HWC_DISPLAY_EXTERNAL_BIT, static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI0)}, // DPP12(IDMA_VGRFS5) in DPUF1 is connected with AXI0 port {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS5", 5, 0, HWC_DISPLAY_EXTERNAL_BIT, static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI0)}, // DPP13(IDMA_GFS7) in DPUF1 is connected with AXI0 port - {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS7", 7, 0, HWC_DISPLAY_SECONDARY_BIT, + {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS7", 7, 0, HWC_DISPLAY_EXTERNAL_BIT, static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI0)}, }; |