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| author | joenchen <joenchen@google.com> | 2023-03-06 15:18:37 +0000 |
|---|---|---|
| committer | Joen Chen <joenchen@google.com> | 2023-03-08 02:31:15 +0000 |
| commit | 290d35b446a1801b14b1d835c811f4e6ded16c14 (patch) | |
| tree | 795bda8a26043555348e8fb62b106a431b940aa7 | |
| parent | 071cdcea072b8b82ee5393c6fd3f551e32dca07e (diff) | |
| download | zuma-290d35b446a1801b14b1d835c811f4e6ded16c14.tar.gz | |
libhwc2.1: correct HW resource table
HWC reserves the DPUF1 resources for virtual displays, so the
maximum assigned amount for the DPU1 TDM attributes cannot be zero.
Bug: 271659893
Test: show frames correctly on displays
Change-Id: I1875042e4f8b74ee24e757a73dda91168d095b71
| -rw-r--r-- | libhwc2.1/ExynosHWCModule.h | 82 |
1 files changed, 41 insertions, 41 deletions
diff --git a/libhwc2.1/ExynosHWCModule.h b/libhwc2.1/ExynosHWCModule.h index bbdb80e..0f0280a 100644 --- a/libhwc2.1/ExynosHWCModule.h +++ b/libhwc2.1/ExynosHWCModule.h @@ -157,47 +157,47 @@ typedef struct HWResourceAmounts { * Primary amount = total - others */ const std::map<HWResourceIndexes, HWResourceAmounts_t> HWResourceTables = { - {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF0, HWC_DISPLAY_PRIMARY), {0, 80}}, - {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF0, HWC_DISPLAY_EXTERNAL), {80, 80}}, - {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF0, HWC_DISPLAY_VIRTUAL), {80, 80}}, - {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF1, HWC_DISPLAY_PRIMARY), {80, 80}}, - {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF1, HWC_DISPLAY_EXTERNAL), {0, 80}}, - {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF1, HWC_DISPLAY_VIRTUAL), {0, 80}}, - - {HWResourceIndexes(TDM_ATTR_SCALE, DPUF0, HWC_DISPLAY_PRIMARY), {0, 2}}, - {HWResourceIndexes(TDM_ATTR_SCALE, DPUF0, HWC_DISPLAY_EXTERNAL), {2, 2}}, - {HWResourceIndexes(TDM_ATTR_SCALE, DPUF0, HWC_DISPLAY_VIRTUAL), {2, 2}}, - {HWResourceIndexes(TDM_ATTR_SCALE, DPUF1, HWC_DISPLAY_PRIMARY), {2, 2}}, - {HWResourceIndexes(TDM_ATTR_SCALE, DPUF1, HWC_DISPLAY_EXTERNAL), {0, 2}}, - {HWResourceIndexes(TDM_ATTR_SCALE, DPUF1, HWC_DISPLAY_VIRTUAL), {0, 2}}, - - {HWResourceIndexes(TDM_ATTR_SBWC, DPUF0, HWC_DISPLAY_PRIMARY), {0, 2}}, - {HWResourceIndexes(TDM_ATTR_SBWC, DPUF0, HWC_DISPLAY_EXTERNAL), {2, 2}}, - {HWResourceIndexes(TDM_ATTR_SBWC, DPUF0, HWC_DISPLAY_VIRTUAL), {2, 2}}, - {HWResourceIndexes(TDM_ATTR_SBWC, DPUF1, HWC_DISPLAY_PRIMARY), {2, 2}}, - {HWResourceIndexes(TDM_ATTR_SBWC, DPUF1, HWC_DISPLAY_EXTERNAL), {0, 2}}, - {HWResourceIndexes(TDM_ATTR_SBWC, DPUF1, HWC_DISPLAY_VIRTUAL), {0, 2}}, - - {HWResourceIndexes(TDM_ATTR_AFBC, DPUF0, HWC_DISPLAY_PRIMARY), {0, 4}}, - {HWResourceIndexes(TDM_ATTR_AFBC, DPUF0, HWC_DISPLAY_EXTERNAL), {4, 4}}, - {HWResourceIndexes(TDM_ATTR_AFBC, DPUF0, HWC_DISPLAY_VIRTUAL), {4, 4}}, - {HWResourceIndexes(TDM_ATTR_AFBC, DPUF1, HWC_DISPLAY_PRIMARY), {4, 4}}, - {HWResourceIndexes(TDM_ATTR_AFBC, DPUF1, HWC_DISPLAY_EXTERNAL), {0, 4}}, - {HWResourceIndexes(TDM_ATTR_AFBC, DPUF1, HWC_DISPLAY_VIRTUAL), {0, 4}}, - - {HWResourceIndexes(TDM_ATTR_ITP, DPUF0, HWC_DISPLAY_PRIMARY), {0, 4}}, - {HWResourceIndexes(TDM_ATTR_ITP, DPUF0, HWC_DISPLAY_EXTERNAL), {4, 4}}, - {HWResourceIndexes(TDM_ATTR_ITP, DPUF0, HWC_DISPLAY_VIRTUAL), {4, 4}}, - {HWResourceIndexes(TDM_ATTR_ITP, DPUF1, HWC_DISPLAY_PRIMARY), {4, 4}}, - {HWResourceIndexes(TDM_ATTR_ITP, DPUF1, HWC_DISPLAY_EXTERNAL), {0, 4}}, - {HWResourceIndexes(TDM_ATTR_ITP, DPUF1, HWC_DISPLAY_VIRTUAL), {0, 4}}, - - {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF0, HWC_DISPLAY_PRIMARY), {0, 2}}, - {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF0, HWC_DISPLAY_EXTERNAL), {2, 2}}, - {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF0, HWC_DISPLAY_VIRTUAL), {2, 2}}, - {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF1, HWC_DISPLAY_PRIMARY), {2, 2}}, - {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF1, HWC_DISPLAY_EXTERNAL), {0, 2}}, - {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF1, HWC_DISPLAY_VIRTUAL), {0, 2}}, + {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF0, HWC_DISPLAY_PRIMARY), {80, 80}}, + {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF0, HWC_DISPLAY_EXTERNAL), {0, 80}}, + {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF0, HWC_DISPLAY_VIRTUAL), {0, 80}}, + {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF1, HWC_DISPLAY_PRIMARY), {0, 80}}, + {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF1, HWC_DISPLAY_EXTERNAL), {80, 80}}, + {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF1, HWC_DISPLAY_VIRTUAL), {80, 80}}, + + {HWResourceIndexes(TDM_ATTR_SCALE, DPUF0, HWC_DISPLAY_PRIMARY), {2, 2}}, + {HWResourceIndexes(TDM_ATTR_SCALE, DPUF0, HWC_DISPLAY_EXTERNAL), {0, 2}}, + {HWResourceIndexes(TDM_ATTR_SCALE, DPUF0, HWC_DISPLAY_VIRTUAL), {0, 2}}, + {HWResourceIndexes(TDM_ATTR_SCALE, DPUF1, HWC_DISPLAY_PRIMARY), {0, 2}}, + {HWResourceIndexes(TDM_ATTR_SCALE, DPUF1, HWC_DISPLAY_EXTERNAL), {2, 2}}, + {HWResourceIndexes(TDM_ATTR_SCALE, DPUF1, HWC_DISPLAY_VIRTUAL), {2, 2}}, + + {HWResourceIndexes(TDM_ATTR_SBWC, DPUF0, HWC_DISPLAY_PRIMARY), {2, 2}}, + {HWResourceIndexes(TDM_ATTR_SBWC, DPUF0, HWC_DISPLAY_EXTERNAL), {0, 2}}, + {HWResourceIndexes(TDM_ATTR_SBWC, DPUF0, HWC_DISPLAY_VIRTUAL), {0, 2}}, + {HWResourceIndexes(TDM_ATTR_SBWC, DPUF1, HWC_DISPLAY_PRIMARY), {0, 2}}, + {HWResourceIndexes(TDM_ATTR_SBWC, DPUF1, HWC_DISPLAY_EXTERNAL), {2, 2}}, + {HWResourceIndexes(TDM_ATTR_SBWC, DPUF1, HWC_DISPLAY_VIRTUAL), {2, 2}}, + + {HWResourceIndexes(TDM_ATTR_AFBC, DPUF0, HWC_DISPLAY_PRIMARY), {4, 4}}, + {HWResourceIndexes(TDM_ATTR_AFBC, DPUF0, HWC_DISPLAY_EXTERNAL), {0, 4}}, + {HWResourceIndexes(TDM_ATTR_AFBC, DPUF0, HWC_DISPLAY_VIRTUAL), {0, 4}}, + {HWResourceIndexes(TDM_ATTR_AFBC, DPUF1, HWC_DISPLAY_PRIMARY), {0, 4}}, + {HWResourceIndexes(TDM_ATTR_AFBC, DPUF1, HWC_DISPLAY_EXTERNAL), {4, 4}}, + {HWResourceIndexes(TDM_ATTR_AFBC, DPUF1, HWC_DISPLAY_VIRTUAL), {4, 4}}, + + {HWResourceIndexes(TDM_ATTR_ITP, DPUF0, HWC_DISPLAY_PRIMARY), {4, 4}}, + {HWResourceIndexes(TDM_ATTR_ITP, DPUF0, HWC_DISPLAY_EXTERNAL), {0, 4}}, + {HWResourceIndexes(TDM_ATTR_ITP, DPUF0, HWC_DISPLAY_VIRTUAL), {0, 4}}, + {HWResourceIndexes(TDM_ATTR_ITP, DPUF1, HWC_DISPLAY_PRIMARY), {0, 4}}, + {HWResourceIndexes(TDM_ATTR_ITP, DPUF1, HWC_DISPLAY_EXTERNAL), {4, 4}}, + {HWResourceIndexes(TDM_ATTR_ITP, DPUF1, HWC_DISPLAY_VIRTUAL), {4, 4}}, + + {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF0, HWC_DISPLAY_PRIMARY), {2, 2}}, + {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF0, HWC_DISPLAY_EXTERNAL), {0, 2}}, + {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF0, HWC_DISPLAY_VIRTUAL), {0, 2}}, + {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF1, HWC_DISPLAY_PRIMARY), {0, 2}}, + {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF1, HWC_DISPLAY_EXTERNAL), {2, 2}}, + {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF1, HWC_DISPLAY_VIRTUAL), {2, 2}}, }; typedef enum lbWidthIndex { |