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| author | Chris Masone <cmasone@google.com> | 2024-02-29 22:53:29 +0000 |
|---|---|---|
| committer | Gerrit Code Review <noreply-gerritcodereview@google.com> | 2024-02-29 22:53:29 +0000 |
| commit | f1242f942e7b79ca0445bc1172f1788cd968dc64 (patch) | |
| tree | 239a8187b193ec0db28f47f5a3004484de9f5a08 | |
| parent | 54903471035b2442dc3a9bc147b95b7663cd554c (diff) | |
| parent | 5eb26295f38f74a4b8fb76e4c416249b2ec2b808 (diff) | |
| download | aemu-f1242f942e7b79ca0445bc1172f1788cd968dc64.tar.gz | |
Merge "Implement Sequence Lock for RISC-V" into main
| -rw-r--r-- | base/include/aemu/base/synchronization/Lock.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/base/include/aemu/base/synchronization/Lock.h b/base/include/aemu/base/synchronization/Lock.h index 2b88f05..281a970 100644 --- a/base/include/aemu/base/synchronization/Lock.h +++ b/base/include/aemu/base/synchronization/Lock.h @@ -237,6 +237,8 @@ static inline __attribute__((always_inline)) void SmpWmb() { asm volatile("dmb ishst" ::: "memory"); #elif defined(__x86_64__) std::atomic_thread_fence(std::memory_order_release); +#elif defined(__riscv) && (__riscv_xlen == 64) + std::atomic_thread_fence(std::memory_order_release); #else #error "Unimplemented SmpWmb for current CPU architecture" #endif @@ -247,6 +249,8 @@ static inline __attribute__((always_inline)) void SmpRmb() { asm volatile("dmb ishld" ::: "memory"); #elif defined(__x86_64__) std::atomic_thread_fence(std::memory_order_acquire); +#elif defined(__riscv) && (__riscv_xlen == 64) + std::atomic_thread_fence(std::memory_order_acquire); #else #error "Unimplemented SmpRmb for current CPU architecture" #endif |