arm: dts: add dmc support for rk322x

Change-Id: Ibf72cb8d2e26490386212d564309f5b85692105a
Signed-off-by: Liang Chen <cl@rock-chips.com>
(cherry picked from commit d826c69c4d33d8e3734c163e1f5a04f50b47fa84)

3 files changed, 172 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/rk322x-dram-default-timing.dtsi b/arch/arm/boot/dts/rk322x-dram-default-timing.dtsi
new file mode 100644
index 000000000000..cd5d080ed732
--- /dev/null
+++ b/arch/arm/boot/dts/rk322x-dram-default-timing.dtsi
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#include <dt-bindings/clock/rockchip-ddr.h>
+#include <dt-bindings/dram/rockchip,rk322x.h>
+
+/ {
+	dram_timing: dram_timing {
+		compatible = "rockchip,dram-timing";
+		dram_spd_bin = <DDR3_DEFAULT>;
+		sr_idle = <0x18>;
+		pd_idle = <0x20>;
+		dram_dll_disb_freq = <300>;
+		phy_dll_disb_freq = <400>;
+		dram_odt_disb_freq = <333>;
+		phy_odt_disb_freq = <333>;
+		ddr3_drv = <DDR3_DS_40ohm>;
+		ddr3_odt = <DDR3_ODT_120ohm>;
+		lpddr3_drv = <LP3_DS_34ohm>;
+		lpddr3_odt = <LP3_ODT_240ohm>;
+		lpddr2_drv = <LP2_DS_34ohm>;
+		/* lpddr2 not supported odt */
+		phy_ddr3_clk_drv = <PHY_DDR3_RON_RTT_45ohm>;
+		phy_ddr3_cmd_drv = <PHY_DDR3_RON_RTT_45ohm>;
+		phy_ddr3_dqs_drv = <PHY_DDR3_RON_RTT_34ohm>;
+		phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
+		phy_lp23_clk_drv = <PHY_LP23_RON_RTT_43ohm>;
+		phy_lp23_cmd_drv = <PHY_LP23_RON_RTT_34ohm>;
+		phy_lp23_dqs_drv = <PHY_LP23_RON_RTT_34ohm>;
+		phy_lp3_odt = <PHY_LP23_RON_RTT_240ohm>;
+	};
+};
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 79be4056cd8b..387c5ee75ad0 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -46,6 +46,8 @@
 #include <dt-bindings/suspend/rockchip-rk322x.h>
 #include <dt-bindings/soc/rockchip,boot-mode.h>
 #include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/soc/rockchip-system-status.h>
+#include <rk322x-dram-default-timing.dtsi>
 #include "skeleton.dtsi"
 
 / {
@@ -157,6 +159,51 @@
 		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 	};
 
+	dmc: dmc {
+		compatible = "rockchip,rk3228-dmc", "rockchip,rk322x-dram";
+		clocks = <&cru SCLK_DDRC>;
+		clock-names = "dmc_clk";
+		operating-points-v2 = <&dmc_opp_table>;
+		system-status-freq = <
+			/*system status         freq(KHz)*/
+			SYS_STATUS_NORMAL       400000
+			SYS_STATUS_VIDEO_4K	600000
+			SYS_STATUS_VIDEO_4K_10B 786000
+		>;
+		dram_freq = <786000000>;
+		rockchip,dram_timing = <&dram_timing>;
+		status = "disabled";
+	};
+
+	dmc_opp_table: dmc-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <1050000>;
+		};
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <1050000>;
+		};
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <1050000>;
+		};
+		opp-700000000 {
+			opp-hz = /bits/ 64 <700000000>;
+			opp-microvolt = <1100000>;
+		};
+		opp-786000000 {
+			opp-hz = /bits/ 64 <786000000>;
+			opp-microvolt = <1150000>;
+		};
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <1150000>;
+		};
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		arm,cpu-registers-not-fw-configured;
diff --git a/include/dt-bindings/dram/rockchip,rk322x.h b/include/dt-bindings/dram/rockchip,rk322x.h
new file mode 100644
index 000000000000..1ab3317d700e
--- /dev/null
+++ b/include/dt-bindings/dram/rockchip,rk322x.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H
+#define _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H
+
+#define DDR3_DS_34ohm		(1 << 1)
+#define DDR3_DS_40ohm		(0x0)
+
+#define LP2_DS_34ohm		(0x1)
+#define LP2_DS_40ohm		(0x2)
+#define LP2_DS_48ohm		(0x3)
+#define LP2_DS_60ohm		(0x4)
+#define LP2_DS_68_6ohm		(0x5)/* optional */
+#define LP2_DS_80ohm		(0x6)
+#define LP2_DS_120ohm		(0x7)/* optional */
+
+#define LP3_DS_34ohm		(0x1)
+#define LP3_DS_40ohm		(0x2)
+#define LP3_DS_48ohm		(0x3)
+#define LP3_DS_60ohm		(0x4)
+#define LP3_DS_80ohm		(0x6)
+#define LP3_DS_34D_40U		(0x9)
+#define LP3_DS_40D_48U		(0xa)
+#define LP3_DS_34D_48U		(0xb)
+
+#define DDR3_ODT_DIS		(0)
+#define DDR3_ODT_40ohm		((1 << 2) | (1 << 6))
+#define DDR3_ODT_60ohm		(1 << 2)
+#define DDR3_ODT_120ohm		(1 << 6)
+
+#define LP3_ODT_DIS		(0)
+#define LP3_ODT_60ohm		(1)
+#define LP3_ODT_120ohm		(2)
+#define LP3_ODT_240ohm		(3)
+
+#define PHY_DDR3_RON_RTT_DISABLE	(0)
+#define PHY_DDR3_RON_RTT_451ohm		(1)
+#define PHY_DDR3_RON_RTT_225ohm		(2)
+#define PHY_DDR3_RON_RTT_150ohm		(3)
+#define PHY_DDR3_RON_RTT_112ohm		(4)
+#define PHY_DDR3_RON_RTT_90ohm		(5)
+#define PHY_DDR3_RON_RTT_75ohm		(6)
+#define PHY_DDR3_RON_RTT_64ohm		(7)
+#define PHY_DDR3_RON_RTT_56ohm		(16)
+#define PHY_DDR3_RON_RTT_50ohm		(17)
+#define PHY_DDR3_RON_RTT_45ohm		(18)
+#define PHY_DDR3_RON_RTT_41ohm		(19)
+#define PHY_DDR3_RON_RTT_37ohm		(20)
+#define PHY_DDR3_RON_RTT_34ohm		(21)
+#define PHY_DDR3_RON_RTT_33ohm		(22)
+#define PHY_DDR3_RON_RTT_30ohm		(23)
+#define PHY_DDR3_RON_RTT_28ohm		(24)
+#define PHY_DDR3_RON_RTT_26ohm		(25)
+#define PHY_DDR3_RON_RTT_25ohm		(26)
+#define PHY_DDR3_RON_RTT_23ohm		(27)
+#define PHY_DDR3_RON_RTT_22ohm		(28)
+#define PHY_DDR3_RON_RTT_21ohm		(29)
+#define PHY_DDR3_RON_RTT_20ohm		(30)
+#define PHY_DDR3_RON_RTT_19ohm		(31)
+
+#define PHY_LP23_RON_RTT_DISABLE	(0)
+#define PHY_LP23_RON_RTT_480ohm		(1)
+#define PHY_LP23_RON_RTT_240ohm		(2)
+#define PHY_LP23_RON_RTT_160ohm		(3)
+#define PHY_LP23_RON_RTT_120ohm		(4)
+#define PHY_LP23_RON_RTT_96ohm		(5)
+#define PHY_LP23_RON_RTT_80ohm		(6)
+#define PHY_LP23_RON_RTT_68ohm		(7)
+#define PHY_LP23_RON_RTT_60ohm		(16)
+#define PHY_LP23_RON_RTT_53ohm		(17)
+#define PHY_LP23_RON_RTT_48ohm		(18)
+#define PHY_LP23_RON_RTT_43ohm		(19)
+#define PHY_LP23_RON_RTT_40ohm		(20)
+#define PHY_LP23_RON_RTT_37ohm		(21)
+#define PHY_LP23_RON_RTT_34ohm		(22)
+#define PHY_LP23_RON_RTT_32ohm		(23)
+#define PHY_LP23_RON_RTT_30ohm		(24)
+#define PHY_LP23_RON_RTT_28ohm		(25)
+#define PHY_LP23_RON_RTT_26ohm		(26)
+#define PHY_LP23_RON_RTT_25ohm		(27)
+#define PHY_LP23_RON_RTT_24ohm		(28)
+#define PHY_LP23_RON_RTT_22ohm		(29)
+#define PHY_LP23_RON_RTT_21ohm		(30)
+#define PHY_LP23_RON_RTT_20ohm		(31)
+
+#endif /* _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H */