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| author | Lin Huang <hl@rock-chips.com> | 2018-07-03 09:12:14 +0800 |
|---|---|---|
| committer | Amit Uttamchandani <amituttam@google.com> | 2018-07-02 21:17:32 -0700 |
| commit | 8b23ef63c65800205a60732e554d3ab25bb875ac (patch) | |
| tree | 862ecf22fe2d81da88f9c706f5c16c5a912281d1 | |
| parent | 9014fc64adf3649858f5ea01f7f9254fe3c46ea0 (diff) | |
| download | rk-u-boot-8b23ef63c65800205a60732e554d3ab25bb875ac.tar.gz | |
rockchip: clock: rk322x: apll support 1.4GHz
add apll 1.4G setting, so we can set apll to 1.4G if we need.
Change-Id: I7a75b26eb0bd713e8537f71b5bccabcf778274a1
Signed-off-by: Lin Huang <hl@rock-chips.com>
| -rw-r--r-- | drivers/clk/rockchip/clk_rk322x.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 6547c3fea3..a146056e65 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -325,6 +325,10 @@ static int rk322x_apll_set_clk(struct rk322x_cru *cru, unsigned int set_rate) apll_cfg = (struct pll_div) {.refdiv = 1, .fbdiv = 61, .postdiv1 = 1, .postdiv2 = 1}; break; + case 1392*MHz: + apll_cfg = (struct pll_div) + {.refdiv = 1, .fbdiv = 58, .postdiv1 = 1, .postdiv2 = 1}; + break; case 816*MHz: default: apll_cfg = (struct pll_div) |