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authorPrashanth Swaminathan <prashanthsw@google.com>2023-12-08 07:57:30 +0000
committerAutomerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com>2023-12-08 07:57:30 +0000
commit646217b7e8f609f06b8e0bb25e49f31d868b57af (patch)
tree1017018a5c4079fbb62b145363efc23ce2a8b706
parentdd312e418771a7ab181c1ddd01a70303a7a29e42 (diff)
parent36e031e13a91b59add1447d676568d13a5bce243 (diff)
downloadbinary_translation-646217b7e8f609f06b8e0bb25e49f31d868b57af.tar.gz
Rename opcodes to IVv,IVx,IVi to match category am: 5bf17fdd9d am: e9eb17fac8 am: 36e031e13a
Original change: https://android-review.googlesource.com/c/platform/frameworks/libs/binary_translation/+/2862691 Change-Id: I10fa5f8905270683a9ae1ba5a160dcb6deb14d33 Signed-off-by: Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com>
-rw-r--r--decoder/include/berberis/decoder/riscv64/decoder.h30
-rw-r--r--decoder/include/berberis/decoder/riscv64/semantics_player.h6
-rw-r--r--interpreter/riscv64/interpreter.cc168
3 files changed, 102 insertions, 102 deletions
diff --git a/decoder/include/berberis/decoder/riscv64/decoder.h b/decoder/include/berberis/decoder/riscv64/decoder.h
index 2f36fddc..ff3929e8 100644
--- a/decoder/include/berberis/decoder/riscv64/decoder.h
+++ b/decoder/include/berberis/decoder/riscv64/decoder.h
@@ -265,7 +265,7 @@ class Decoder {
kMaxValue = 0b111111111111'11111'111'11111,
};
- enum class VOpViOpcode {
+ enum class VOpIViOpcode {
kVaddvi = 0b000000,
kVrsubvi = 0b000011,
kVandvi = 0b001001,
@@ -298,7 +298,7 @@ class Decoder {
kMaxValue = 0b111111,
};
- enum class VOpVvOpcode {
+ enum class VOpIVvOpcode {
kVaddvv = 0b000000,
kVsubvv = 0b000010,
kVminuvv = 0b000100,
@@ -340,7 +340,7 @@ class Decoder {
kMaxValue = 0b111111
};
- enum class VOpVxOpcode {
+ enum class VOpIVxOpcode {
kVaddvx = 0b000000,
kVsubvx = 0b000010,
kVrsubvx = 0b000011,
@@ -620,24 +620,24 @@ class Decoder {
using OpImmArgs = OpImmArgsTemplate<OpImmOpcode>;
using OpImm32Args = OpImmArgsTemplate<OpImm32Opcode>;
- struct VOpViArgs {
- VOpViOpcode opcode;
+ struct VOpIViArgs {
+ VOpIViOpcode opcode;
bool vm;
uint8_t dst;
uint8_t src;
int8_t imm;
};
- struct VOpVvArgs {
- VOpVvOpcode opcode;
+ struct VOpIVvArgs {
+ VOpIVvOpcode opcode;
bool vm;
uint8_t dst;
uint8_t src1;
uint8_t src2;
};
- struct VOpVxArgs {
- VOpVxOpcode opcode;
+ struct VOpIVxArgs {
+ VOpIVxOpcode opcode;
bool vm;
uint8_t dst;
uint8_t src1;
@@ -1711,8 +1711,8 @@ class Decoder {
uint8_t src2 = GetBits<uint8_t, 15, 5>();
switch (low_opcode) {
case 0b000: {
- const VOpVvArgs args = {
- .opcode = VOpVvOpcode(opcode),
+ const VOpIVvArgs args = {
+ .opcode = VOpIVvOpcode(opcode),
.vm = vm,
.dst = dst,
.src1 = src1,
@@ -1721,8 +1721,8 @@ class Decoder {
return insn_consumer_->OpVector(args);
}
case 0b011: {
- const VOpViArgs args = {
- .opcode = VOpViOpcode(opcode),
+ const VOpIViArgs args = {
+ .opcode = VOpIViOpcode(opcode),
.vm = vm,
.dst = dst,
.src = src1,
@@ -1731,8 +1731,8 @@ class Decoder {
return insn_consumer_->OpVector(args);
}
case 0b100: {
- const VOpVxArgs args = {
- .opcode = VOpVxOpcode(opcode),
+ const VOpIVxArgs args = {
+ .opcode = VOpIVxOpcode(opcode),
.vm = vm,
.dst = dst,
.src1 = src1,
diff --git a/decoder/include/berberis/decoder/riscv64/semantics_player.h b/decoder/include/berberis/decoder/riscv64/semantics_player.h
index 4b922db9..cfa707c7 100644
--- a/decoder/include/berberis/decoder/riscv64/semantics_player.h
+++ b/decoder/include/berberis/decoder/riscv64/semantics_player.h
@@ -789,19 +789,19 @@ class SemanticsPlayer {
SetRegOrIgnore(args.dst, result);
}
- void OpVector(const typename Decoder::VOpViArgs& args) {
+ void OpVector(const typename Decoder::VOpIViArgs& args) {
// TODO(300690740): develop and implement strategy which would allow us to support vector
// intrinsics not just in the interpreter.
listener_->OpVector(args);
}
- void OpVector(const typename Decoder::VOpVvArgs& args) {
+ void OpVector(const typename Decoder::VOpIVvArgs& args) {
// TODO(300690740): develop and implement strategy which would allow us to support vector
// intrinsics not just in the interpreter.
listener_->OpVector(args);
}
- void OpVector(const typename Decoder::VOpVxArgs& args) {
+ void OpVector(const typename Decoder::VOpIVxArgs& args) {
// TODO(300690740): develop and implement strategy which would allow us to support vector
// intrinsics not just in the interpreter.
Register arg2 = GetRegOrZero(args.src2);
diff --git a/interpreter/riscv64/interpreter.cc b/interpreter/riscv64/interpreter.cc
index 61254b46..6785b4fa 100644
--- a/interpreter/riscv64/interpreter.cc
+++ b/interpreter/riscv64/interpreter.cc
@@ -548,50 +548,50 @@ class Interpreter {
}
template <typename ElementType, VectorRegisterGroupMultiplier vlmul, TailProcessing vta>
- void OpVector(const Decoder::VOpViArgs& args) {
+ void OpVector(const Decoder::VOpIViArgs& args) {
switch (args.opcode) {
- case Decoder::VOpViOpcode::kVaddvi:
+ case Decoder::VOpIViOpcode::kVaddvi:
return OpVectorvx<intrinsics::Vaddvx<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVrsubvi:
+ case Decoder::VOpIViOpcode::kVrsubvi:
return OpVectorvx<intrinsics::Vrsubvx<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVandvi:
+ case Decoder::VOpIViOpcode::kVandvi:
return OpVectorvx<intrinsics::Vandvx<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVorvi:
+ case Decoder::VOpIViOpcode::kVorvi:
return OpVectorvx<intrinsics::Vorvx<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVxorvi:
+ case Decoder::VOpIViOpcode::kVxorvi:
return OpVectorvx<intrinsics::Vxorvx<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVmseqvi:
+ case Decoder::VOpIViOpcode::kVmseqvi:
return OpVectorvx<intrinsics::Vmseqvx<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVmsnevi:
+ case Decoder::VOpIViOpcode::kVmsnevi:
return OpVectorvx<intrinsics::Vmsnevx<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVmsleuvi:
+ case Decoder::VOpIViOpcode::kVmsleuvi:
return OpVectorvx<intrinsics::Vmslevx<std::make_unsigned_t<ElementType>, vta>,
ElementType,
vlmul,
vta>(args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVmslevi:
+ case Decoder::VOpIViOpcode::kVmslevi:
return OpVectorvx<intrinsics::Vmslevx<std::make_signed_t<ElementType>, vta>,
ElementType,
vlmul,
vta>(args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVmsgtuvi:
+ case Decoder::VOpIViOpcode::kVmsgtuvi:
return OpVectorvx<intrinsics::Vmsgtvx<std::make_unsigned_t<ElementType>, vta>,
ElementType,
vlmul,
vta>(args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVmsgtvi:
+ case Decoder::VOpIViOpcode::kVmsgtvi:
return OpVectorvx<intrinsics::Vmsgtvx<std::make_signed_t<ElementType>, vta>,
ElementType,
vlmul,
vta>(args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVsllvi:
+ case Decoder::VOpIViOpcode::kVsllvi:
return OpVectorvx<intrinsics::Vsllvx<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src, args.imm);
default:
@@ -600,50 +600,50 @@ class Interpreter {
}
template <typename ElementType, VectorRegisterGroupMultiplier vlmul, TailProcessing vta>
- void OpVector(const Decoder::VOpVvArgs& args) {
+ void OpVector(const Decoder::VOpIVvArgs& args) {
switch (args.opcode) {
- case Decoder::VOpVvOpcode::kVaddvv:
+ case Decoder::VOpIVvOpcode::kVaddvv:
return OpVectorvv<intrinsics::Vaddvv<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVsubvv:
+ case Decoder::VOpIVvOpcode::kVsubvv:
return OpVectorvv<intrinsics::Vsubvv<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVandvv:
+ case Decoder::VOpIVvOpcode::kVandvv:
return OpVectorvv<intrinsics::Vandvv<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVorvv:
+ case Decoder::VOpIVvOpcode::kVorvv:
return OpVectorvv<intrinsics::Vorvv<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVxorvv:
+ case Decoder::VOpIVvOpcode::kVxorvv:
return OpVectorvv<intrinsics::Vxorvv<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVmseqvv:
+ case Decoder::VOpIVvOpcode::kVmseqvv:
return OpVectorvv<intrinsics::Vmseqvv<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVmsnevv:
+ case Decoder::VOpIVvOpcode::kVmsnevv:
return OpVectorvv<intrinsics::Vmsnevv<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVmsltuvv:
+ case Decoder::VOpIVvOpcode::kVmsltuvv:
return OpVectorvv<intrinsics::Vmsltvv<std::make_unsigned_t<ElementType>, vta>,
ElementType,
vlmul,
vta>(args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVmsltvv:
+ case Decoder::VOpIVvOpcode::kVmsltvv:
return OpVectorvv<intrinsics::Vmsltvv<std::make_signed_t<ElementType>, vta>,
ElementType,
vlmul,
vta>(args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVmsleuvv:
+ case Decoder::VOpIVvOpcode::kVmsleuvv:
return OpVectorvv<intrinsics::Vmslevv<std::make_unsigned_t<ElementType>, vta>,
ElementType,
vlmul,
vta>(args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVmslevv:
+ case Decoder::VOpIVvOpcode::kVmslevv:
return OpVectorvv<intrinsics::Vmslevv<std::make_signed_t<ElementType>, vta>,
ElementType,
vlmul,
vta>(args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVsllvv:
+ case Decoder::VOpIVvOpcode::kVsllvv:
return OpVectorvv<intrinsics::Vsllvv<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src1, args.src2);
default:
@@ -652,63 +652,63 @@ class Interpreter {
}
template <typename ElementType, VectorRegisterGroupMultiplier vlmul, TailProcessing vta>
- void OpVector(const Decoder::VOpVxArgs& args, Register arg2) {
+ void OpVector(const Decoder::VOpIVxArgs& args, Register arg2) {
switch (args.opcode) {
- case Decoder::VOpVxOpcode::kVaddvx:
+ case Decoder::VOpIVxOpcode::kVaddvx:
return OpVectorvx<intrinsics::Vaddvx<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVsubvx:
+ case Decoder::VOpIVxOpcode::kVsubvx:
return OpVectorvx<intrinsics::Vsubvx<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVrsubvx:
+ case Decoder::VOpIVxOpcode::kVrsubvx:
return OpVectorvx<intrinsics::Vrsubvx<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVandvx:
+ case Decoder::VOpIVxOpcode::kVandvx:
return OpVectorvx<intrinsics::Vandvx<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVorvx:
+ case Decoder::VOpIVxOpcode::kVorvx:
return OpVectorvx<intrinsics::Vorvx<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVxorvx:
+ case Decoder::VOpIVxOpcode::kVxorvx:
return OpVectorvx<intrinsics::Vxorvx<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVmseqvx:
+ case Decoder::VOpIVxOpcode::kVmseqvx:
return OpVectorvx<intrinsics::Vmseqvx<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVmsnevx:
+ case Decoder::VOpIVxOpcode::kVmsnevx:
return OpVectorvx<intrinsics::Vmsnevx<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVmsltuvx:
+ case Decoder::VOpIVxOpcode::kVmsltuvx:
return OpVectorvx<intrinsics::Vmsltvx<std::make_unsigned_t<ElementType>, vta>,
ElementType,
vlmul,
vta>(args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVmsltvx:
+ case Decoder::VOpIVxOpcode::kVmsltvx:
return OpVectorvx<intrinsics::Vmsltvx<std::make_signed_t<ElementType>, vta>,
ElementType,
vlmul,
vta>(args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVmsleuvx:
+ case Decoder::VOpIVxOpcode::kVmsleuvx:
return OpVectorvx<intrinsics::Vmslevx<std::make_unsigned_t<ElementType>, vta>,
ElementType,
vlmul,
vta>(args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVmslevx:
+ case Decoder::VOpIVxOpcode::kVmslevx:
return OpVectorvx<intrinsics::Vmslevx<std::make_signed_t<ElementType>, vta>,
ElementType,
vlmul,
vta>(args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVmsgtuvx:
+ case Decoder::VOpIVxOpcode::kVmsgtuvx:
return OpVectorvx<intrinsics::Vmsgtvx<std::make_unsigned_t<ElementType>, vta>,
ElementType,
vlmul,
vta>(args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVmsgtvx:
+ case Decoder::VOpIVxOpcode::kVmsgtvx:
return OpVectorvx<intrinsics::Vmsgtvx<std::make_signed_t<ElementType>, vta>,
ElementType,
vlmul,
vta>(args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVsllvx:
+ case Decoder::VOpIVxOpcode::kVsllvx:
return OpVectorvx<intrinsics::Vsllvx<ElementType, vta>, ElementType, vlmul, vta>(
args.dst, args.src1, arg2);
default:
@@ -772,60 +772,60 @@ class Interpreter {
VectorRegisterGroupMultiplier vlmul,
TailProcessing vta,
InactiveProcessing vma>
- void OpVector(const Decoder::VOpViArgs& args) {
+ void OpVector(const Decoder::VOpIViArgs& args) {
switch (args.opcode) {
- case Decoder::VOpViOpcode::kVaddvi:
+ case Decoder::VOpIViOpcode::kVaddvi:
return OpVectorvx<intrinsics::Vaddvxm<ElementType, vta, vma>, ElementType, vlmul, vta, vma>(
args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVrsubvi:
+ case Decoder::VOpIViOpcode::kVrsubvi:
return OpVectorvx<intrinsics::Vrsubvxm<ElementType, vta, vma>, ElementType, vlmul, vta, vma>(
args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVandvi:
+ case Decoder::VOpIViOpcode::kVandvi:
return OpVectorvx<intrinsics::Vandvxm<ElementType, vta, vma>, ElementType, vlmul, vta, vma>(
args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVorvi:
+ case Decoder::VOpIViOpcode::kVorvi:
return OpVectorvx<intrinsics::Vorvxm<ElementType, vta, vma>, ElementType, vlmul, vta, vma>(
args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVxorvi:
+ case Decoder::VOpIViOpcode::kVxorvi:
return OpVectorvx<intrinsics::Vxorvxm<ElementType, vta, vma>, ElementType, vlmul, vta, vma>(
args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVmseqvi:
+ case Decoder::VOpIViOpcode::kVmseqvi:
return OpVectorvx<intrinsics::Vmseqvxm<ElementType, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVmsnevi:
+ case Decoder::VOpIViOpcode::kVmsnevi:
return OpVectorvx<intrinsics::Vmsnevxm<ElementType, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVmsleuvi:
+ case Decoder::VOpIViOpcode::kVmsleuvi:
return OpVectorvx<intrinsics::Vmslevxm<std::make_unsigned_t<ElementType>, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVmslevi:
+ case Decoder::VOpIViOpcode::kVmslevi:
return OpVectorvx<intrinsics::Vmslevxm<std::make_signed_t<ElementType>, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVmsgtuvi:
+ case Decoder::VOpIViOpcode::kVmsgtuvi:
return OpVectorvx<intrinsics::Vmsgtvxm<std::make_unsigned_t<ElementType>, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVmsgtvi:
+ case Decoder::VOpIViOpcode::kVmsgtvi:
return OpVectorvx<intrinsics::Vmsgtvxm<std::make_signed_t<ElementType>, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src, args.imm);
- case Decoder::VOpViOpcode::kVsllvi:
+ case Decoder::VOpIViOpcode::kVsllvi:
return OpVectorvx<intrinsics::Vsllvxm<ElementType, vta, vma>, ElementType, vlmul, vta, vma>(
args.dst, args.src, args.imm);
default:
@@ -837,60 +837,60 @@ class Interpreter {
VectorRegisterGroupMultiplier vlmul,
TailProcessing vta,
InactiveProcessing vma>
- void OpVector(const Decoder::VOpVvArgs& args) {
+ void OpVector(const Decoder::VOpIVvArgs& args) {
switch (args.opcode) {
- case Decoder::VOpVvOpcode::kVaddvv:
+ case Decoder::VOpIVvOpcode::kVaddvv:
return OpVectorvv<intrinsics::Vaddvvm<ElementType, vta, vma>, ElementType, vlmul, vta, vma>(
args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVsubvv:
+ case Decoder::VOpIVvOpcode::kVsubvv:
return OpVectorvv<intrinsics::Vsubvvm<ElementType, vta, vma>, ElementType, vlmul, vta, vma>(
args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVandvv:
+ case Decoder::VOpIVvOpcode::kVandvv:
return OpVectorvv<intrinsics::Vandvvm<ElementType, vta, vma>, ElementType, vlmul, vta, vma>(
args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVorvv:
+ case Decoder::VOpIVvOpcode::kVorvv:
return OpVectorvv<intrinsics::Vorvvm<ElementType, vta, vma>, ElementType, vlmul, vta, vma>(
args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVxorvv:
+ case Decoder::VOpIVvOpcode::kVxorvv:
return OpVectorvv<intrinsics::Vxorvvm<ElementType, vta, vma>, ElementType, vlmul, vta, vma>(
args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVmseqvv:
+ case Decoder::VOpIVvOpcode::kVmseqvv:
return OpVectorvv<intrinsics::Vmseqvvm<ElementType, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVmsnevv:
+ case Decoder::VOpIVvOpcode::kVmsnevv:
return OpVectorvv<intrinsics::Vmsnevvm<ElementType, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVmsltuvv:
+ case Decoder::VOpIVvOpcode::kVmsltuvv:
return OpVectorvv<intrinsics::Vmsltvvm<std::make_unsigned_t<ElementType>, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVmsltvv:
+ case Decoder::VOpIVvOpcode::kVmsltvv:
return OpVectorvv<intrinsics::Vmsltvvm<std::make_signed_t<ElementType>, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVmsleuvv:
+ case Decoder::VOpIVvOpcode::kVmsleuvv:
return OpVectorvv<intrinsics::Vmslevvm<std::make_unsigned_t<ElementType>, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVmslevv:
+ case Decoder::VOpIVvOpcode::kVmslevv:
return OpVectorvv<intrinsics::Vmslevvm<std::make_signed_t<ElementType>, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src1, args.src2);
- case Decoder::VOpVvOpcode::kVsllvv:
+ case Decoder::VOpIVvOpcode::kVsllvv:
return OpVectorvv<intrinsics::Vsllvvm<ElementType, vta, vma>, ElementType, vlmul, vta, vma>(
args.dst, args.src1, args.src2);
default:
@@ -902,75 +902,75 @@ class Interpreter {
VectorRegisterGroupMultiplier vlmul,
TailProcessing vta,
InactiveProcessing vma>
- void OpVector(const Decoder::VOpVxArgs& args, Register arg2) {
+ void OpVector(const Decoder::VOpIVxArgs& args, Register arg2) {
switch (args.opcode) {
- case Decoder::VOpVxOpcode::kVaddvx:
+ case Decoder::VOpIVxOpcode::kVaddvx:
return OpVectorvx<intrinsics::Vaddvxm<ElementType, vta, vma>, ElementType, vlmul, vta, vma>(
args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVsubvx:
+ case Decoder::VOpIVxOpcode::kVsubvx:
return OpVectorvx<intrinsics::Vsubvxm<ElementType, vta, vma>, ElementType, vlmul, vta, vma>(
args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVrsubvx:
+ case Decoder::VOpIVxOpcode::kVrsubvx:
return OpVectorvx<intrinsics::Vrsubvxm<ElementType, vta, vma>, ElementType, vlmul, vta, vma>(
args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVandvx:
+ case Decoder::VOpIVxOpcode::kVandvx:
return OpVectorvx<intrinsics::Vandvxm<ElementType, vta, vma>, ElementType, vlmul, vta, vma>(
args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVorvx:
+ case Decoder::VOpIVxOpcode::kVorvx:
return OpVectorvx<intrinsics::Vorvxm<ElementType, vta, vma>, ElementType, vlmul, vta, vma>(
args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVxorvx:
+ case Decoder::VOpIVxOpcode::kVxorvx:
return OpVectorvx<intrinsics::Vxorvxm<ElementType, vta, vma>, ElementType, vlmul, vta, vma>(
args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVmseqvx:
+ case Decoder::VOpIVxOpcode::kVmseqvx:
return OpVectorvx<intrinsics::Vmseqvxm<ElementType, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVmsnevx:
+ case Decoder::VOpIVxOpcode::kVmsnevx:
return OpVectorvx<intrinsics::Vmsnevxm<ElementType, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVmsltuvx:
+ case Decoder::VOpIVxOpcode::kVmsltuvx:
return OpVectorvx<intrinsics::Vmsltvxm<std::make_unsigned_t<ElementType>, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVmsltvx:
+ case Decoder::VOpIVxOpcode::kVmsltvx:
return OpVectorvx<intrinsics::Vmsltvxm<std::make_signed_t<ElementType>, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVmsleuvx:
+ case Decoder::VOpIVxOpcode::kVmsleuvx:
return OpVectorvx<intrinsics::Vmslevxm<std::make_unsigned_t<ElementType>, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVmslevx:
+ case Decoder::VOpIVxOpcode::kVmslevx:
return OpVectorvx<intrinsics::Vmslevxm<std::make_signed_t<ElementType>, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVmsgtuvx:
+ case Decoder::VOpIVxOpcode::kVmsgtuvx:
return OpVectorvx<intrinsics::Vmsgtvxm<std::make_unsigned_t<ElementType>, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVmsgtvx:
+ case Decoder::VOpIVxOpcode::kVmsgtvx:
return OpVectorvx<intrinsics::Vmsgtvxm<std::make_signed_t<ElementType>, vta, vma>,
ElementType,
vlmul,
vta,
vma>(args.dst, args.src1, arg2);
- case Decoder::VOpVxOpcode::kVsllvx:
+ case Decoder::VOpIVxOpcode::kVsllvx:
return OpVectorvx<intrinsics::Vsllvxm<ElementType, vta, vma>, ElementType, vlmul, vta, vma>(
args.dst, args.src1, arg2);
default: