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| author | Usama Arif <usama.arif@linaro.org> | 2019-11-22 15:09:49 +0000 |
|---|---|---|
| committer | Usama Arif <usama.arif@linaro.org> | 2019-12-05 10:22:56 +0000 |
| commit | 0f320914bc83db0086767d70adf6b62efae77a85 (patch) | |
| tree | 75f101f639c15ac42fa37270d7630bd641eba717 | |
| parent | 39f60178ae485dc61b8bb79ac03cb870b8576ee3 (diff) | |
| download | vixl-0f320914bc83db0086767d70adf6b62efae77a85.tar.gz | |
Remove non-zero register asserts from Csinc/Csinv/Csneg
This CL removes the asserts which check whether the source registers are zero
from the Csinc, Csinv and Csneg macroassembly functions.
Change-Id: I82c0b7e71f790d4a4822870b58b78e108c6590dd
| -rw-r--r-- | src/aarch64/macro-assembler-aarch64.h | 6 | ||||
| -rw-r--r-- | test/aarch64/test-assembler-aarch64.cc | 60 |
2 files changed, 60 insertions, 6 deletions
diff --git a/src/aarch64/macro-assembler-aarch64.h b/src/aarch64/macro-assembler-aarch64.h index 9c09f1c2..31db8dab 100644 --- a/src/aarch64/macro-assembler-aarch64.h +++ b/src/aarch64/macro-assembler-aarch64.h @@ -1273,8 +1273,6 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { Condition cond) { VIXL_ASSERT(allow_macro_instructions_); VIXL_ASSERT(!rd.IsZero()); - VIXL_ASSERT(!rn.IsZero()); - VIXL_ASSERT(!rm.IsZero()); VIXL_ASSERT((cond != al) && (cond != nv)); SingleEmissionCheckScope guard(this); csinc(rd, rn, rm, cond); @@ -1285,8 +1283,6 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { Condition cond) { VIXL_ASSERT(allow_macro_instructions_); VIXL_ASSERT(!rd.IsZero()); - VIXL_ASSERT(!rn.IsZero()); - VIXL_ASSERT(!rm.IsZero()); VIXL_ASSERT((cond != al) && (cond != nv)); SingleEmissionCheckScope guard(this); csinv(rd, rn, rm, cond); @@ -1297,8 +1293,6 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface { Condition cond) { VIXL_ASSERT(allow_macro_instructions_); VIXL_ASSERT(!rd.IsZero()); - VIXL_ASSERT(!rn.IsZero()); - VIXL_ASSERT(!rm.IsZero()); VIXL_ASSERT((cond != al) && (cond != nv)); SingleEmissionCheckScope guard(this); csneg(rd, rn, rm, cond); diff --git a/test/aarch64/test-assembler-aarch64.cc b/test/aarch64/test-assembler-aarch64.cc index f968c28c..c4696e5a 100644 --- a/test/aarch64/test-assembler-aarch64.cc +++ b/test/aarch64/test-assembler-aarch64.cc @@ -5941,6 +5941,66 @@ TEST(csel_reg) { } } +TEST(csel_zero) { + SETUP(); + + START(); + + __ Mov(x15, 0x0); + __ Mov(x16, 0x0000001f0000002f); + + // Check results when zero registers are used as inputs + // for Csinc, Csinv and Csneg for both true and false conditions. + __ Cmp(x15, 0); + __ Csinc(x0, x16, xzr, eq); + __ Csinc(x1, xzr, x16, eq); + __ Cmp(x15, 1); + __ Csinc(w2, w16, wzr, eq); + __ Csinc(w3, wzr, w16, eq); + + __ Csinc(x4, xzr, xzr, eq); + + __ Cmp(x15, 0); + __ Csinv(x5, x16, xzr, eq); + __ Csinv(x6, xzr, x16, eq); + __ Cmp(x15, 1); + __ Csinv(w7, w16, wzr, eq); + __ Csinv(w8, wzr, w16, eq); + + __ Csinv(x9, xzr, xzr, eq); + + __ Cmp(x15, 0); + __ Csneg(x10, x16, xzr, eq); + __ Csneg(x11, xzr, x16, eq); + __ Cmp(x15, 1); + __ Csneg(w12, w16, wzr, eq); + __ Csneg(w13, wzr, w16, eq); + + __ Csneg(x14, xzr, xzr, eq); + + END(); + + if (CAN_RUN()) { + RUN(); + + ASSERT_EQUAL_64(0x0000001f0000002f, x0); + ASSERT_EQUAL_64(0x0, x1); + ASSERT_EQUAL_32(0x1, w2); + ASSERT_EQUAL_32(0x30, w3); + ASSERT_EQUAL_64(0x1, x4); + ASSERT_EQUAL_64(0x0000001f0000002f, x5); + ASSERT_EQUAL_64(0x0, x6); + ASSERT_EQUAL_32(0xffffffff, w7); + ASSERT_EQUAL_32(0xffffffd0, w8); + ASSERT_EQUAL_64(0xffffffffffffffff, x9); + ASSERT_EQUAL_64(0x0000001f0000002f, x10); + ASSERT_EQUAL_64(0x0, x11); + ASSERT_EQUAL_32(0x0, w12); + ASSERT_EQUAL_32(0xffffffd1, w13); + ASSERT_EQUAL_64(0x0, x14); + } +} + TEST(csel_imm) { SETUP(); |