Initial import of aarch64-paging crate. am: ff4b4e17cb am: 3ddf1a7670

Original change: https://android-review.googlesource.com/c/platform/external/rust/crates/aarch64-paging/+/2105468

Change-Id: I89b2634cd6bbf13621b837ad66c5fb7ade37091e
Signed-off-by: Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com>

20 files changed, 1271 insertions, 0 deletions

diff --git a/.cargo_vcs_info.json b/.cargo_vcs_info.json
new file mode 100644
index 0000000..ff83bf0
--- /dev/null
+++ b/.cargo_vcs_info.json
@@ -0,0 +1,6 @@
+{
+  "git": {
+    "sha1": "2df8dc019d44f12a832535b47fcf7269960dfe26"
+  },
+  "path_in_vcs": ""
+}
\ No newline at end of file
diff --git a/.github/workflows/rust.yml b/.github/workflows/rust.yml
new file mode 100644
index 0000000..769c845
--- /dev/null
+++ b/.github/workflows/rust.yml
@@ -0,0 +1,37 @@
+name: Rust
+
+on:
+  push:
+    branches: [main]
+  pull_request:
+
+env:
+  CARGO_TERM_COLOR: always
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+      - name: Install aarch64 toolchain
+        uses: actions-rs/toolchain@v1
+        with:
+          toolchain: stable
+          target: aarch64-unknown-none
+      - name: Build
+        run: cargo build
+      - name: Build for aarch64
+        run: cargo build --target=aarch64-unknown-none
+      - name: Run tests
+        run: cargo test
+      - name: Run clippy
+        uses: actions-rs/clippy-check@v1
+        with:
+          token: ${{ secrets.GITHUB_TOKEN }}
+
+  format:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+      - name: Format Rust code
+        run: cargo fmt --all -- --check
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..ff0d847
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,3 @@
+/target
+/.vscode
+Cargo.lock
diff --git a/AUTHORS b/AUTHORS
new file mode 100644
index 0000000..78c435a
--- /dev/null
+++ b/AUTHORS
@@ -0,0 +1,7 @@
+# This is the list of aarch64-paging's significant contributors.
+#
+# This does not necessarily list everyone who has contributed code,
+# especially since many employees of one corporation may be contributing.
+# To see the full list of contributors, see the revision history in
+# source control.
+Google LLC
diff --git a/Android.bp b/Android.bp
new file mode 100644
index 0000000..89ce44a
--- /dev/null
+++ b/Android.bp
@@ -0,0 +1,27 @@
+// This file is generated by cargo2android.py --config cargo2android.json.
+// Do not modify this file as changes will be overridden on upgrade.
+
+
+
+rust_library {
+    name: "libaarch64_paging",
+    host_supported: true,
+    crate_name: "aarch64_paging",
+    cargo_env_compat: true,
+    cargo_pkg_version: "0.1.0",
+    srcs: ["src/lib.rs"],
+    edition: "2021",
+    rustlibs: [
+        "libbitflags",
+    ],
+    apex_available: [
+        "//apex_available:platform",
+        "com.android.virt",
+    ],
+    enabled: false,
+    arch: {
+        arm64: {
+            enabled: true,
+        },
+    },
+}
diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
new file mode 100644
index 0000000..c88469f
--- /dev/null
+++ b/CONTRIBUTING.md
@@ -0,0 +1,26 @@
+# How to Contribute
+
+We'd love to accept your patches and contributions to this project. There are just a few small
+guidelines you need to follow.
+
+## Contributor License Agreement
+
+Contributions to this project must be accompanied by a Contributor License Agreement (CLA). You (or
+your employer) retain the copyright to your contribution; this simply gives us permission to use and
+redistribute your contributions as part of the project. Head over to
+<https://cla.developers.google.com/> to see your current agreements on file or to sign a new one.
+
+You generally only need to submit a CLA once, so if you've already submitted one (even if it was for
+a different project), you probably don't need to do it again.
+
+## Code Reviews
+
+All submissions, including submissions by project members, require review. We use GitHub pull
+requests for this purpose. Consult
+[GitHub Help](https://help.github.com/articles/about-pull-requests/) for more information on using
+pull requests.
+
+## Community Guidelines
+
+This project follows
+[Google's Open Source Community Guidelines](https://opensource.google/conduct/).
diff --git a/Cargo.toml b/Cargo.toml
new file mode 100644
index 0000000..1192dda
--- /dev/null
+++ b/Cargo.toml
@@ -0,0 +1,41 @@
+# THIS FILE IS AUTOMATICALLY GENERATED BY CARGO
+#
+# When uploading crates to the registry Cargo will automatically
+# "normalize" Cargo.toml files for maximal compatibility
+# with all versions of Cargo and also rewrite `path` dependencies
+# to registry (e.g., crates.io) dependencies.
+#
+# If you are reading this file be aware that the original Cargo.toml
+# will likely look very different (and much more reasonable).
+# See Cargo.toml.orig for the original contents.
+
+[package]
+edition = "2021"
+name = "aarch64-paging"
+version = "0.1.0"
+authors = [
+    "Ard Biesheuvel <ardb@google.com>",
+    "Andrew Walbran <qwandor@google.com>",
+]
+description = "A library to manipulate AArch64 VMSA EL1 page tables."
+keywords = [
+    "arm",
+    "aarch64",
+    "cortex-a",
+    "vmsa",
+    "pagetable",
+]
+categories = [
+    "embedded",
+    "no-std",
+    "hardware-support",
+]
+license = "MIT OR Apache-2.0"
+repository = "https://github.com/google/aarch64-paging"
+resolver = "2"
+
+[package.metadata.docs.rs]
+default-target = "aarch64-unknown-none"
+
+[dependencies.bitflags]
+version = "1.3"
diff --git a/Cargo.toml.orig b/Cargo.toml.orig
new file mode 100644
index 0000000..a15bafc
--- /dev/null
+++ b/Cargo.toml.orig
@@ -0,0 +1,16 @@
+[package]
+name = "aarch64-paging"
+version = "0.1.0"
+edition = "2021"
+license = "MIT OR Apache-2.0"
+description = "A library to manipulate AArch64 VMSA EL1 page tables."
+authors = ["Ard Biesheuvel <ardb@google.com>", "Andrew Walbran <qwandor@google.com>"]
+repository = "https://github.com/google/aarch64-paging"
+keywords = ["arm", "aarch64", "cortex-a", "vmsa", "pagetable"]
+categories = ["embedded", "no-std", "hardware-support"]
+
+[dependencies]
+bitflags = "1.3"
+
+[package.metadata.docs.rs]
+default-target = "aarch64-unknown-none"
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000..fad2434
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,229 @@
+This project is dual-licensed under Apache 2.0 and MIT terms.
+
+====
+
+MIT License
+
+Copyright (c) 2022 The aarch64-paging Authors.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+
+====
+
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
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+      the copyright owner that is granting the License.
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+      "Legal Entity" shall mean the union of the acting entity and all
+      other entities that control, are controlled by, or are under common
+      control with that entity. For the purposes of this definition,
+      "control" means (i) the power, direct or indirect, to cause the
+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
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+
+      "Object" form shall mean any form resulting from mechanical
+      transformation or translation of a Source form, including but
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+      "Work" shall mean the work of authorship, whether in Source or
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+      "Derivative Works" shall mean any work, whether in Source or Object
+      form, that is based on (or derived from) the Work and for which the
+      editorial revisions, annotations, elaborations, or other modifications
+      represent, as a whole, an original work of authorship. For the purposes
+      of this License, Derivative Works shall not include works that remain
+      separable from, or merely link (or bind by name) to the interfaces of,
+      the Work and Derivative Works thereof.
+
+      "Contribution" shall mean any work of authorship, including
+      the original version of the Work and any modifications or additions
+      to that Work or Derivative Works thereof, that is intentionally
+      submitted to Licensor for inclusion in the Work by the copyright owner
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+      subsequently incorporated within the Work.
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+   2. Grant of Copyright License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      copyright license to reproduce, prepare Derivative Works of,
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+      Work and such Derivative Works in Source or Object form.
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+   3. Grant of Patent License. Subject to the terms and conditions of
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+      You may add Your own copyright statement to Your modifications and
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+
+   5. Submission of Contributions. Unless You explicitly state otherwise,
+      any Contribution intentionally submitted for inclusion in the Work
+      by You to the Licensor shall be under the terms and conditions of
+      this License, without any additional terms or conditions.
+      Notwithstanding the above, nothing herein shall supersede or modify
+      the terms of any separate license agreement you may have executed
+      with Licensor regarding such Contributions.
+
+   6. Trademarks. This License does not grant permission to use the trade
+      names, trademarks, service marks, or product names of the Licensor,
+      except as required for reasonable and customary use in describing the
+      origin of the Work and reproducing the content of the NOTICE file.
+
+   7. Disclaimer of Warranty. Unless required by applicable law or
+      agreed to in writing, Licensor provides the Work (and each
+      Contributor provides its Contributions) on an "AS IS" BASIS,
+      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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+   8. Limitation of Liability. In no event and under no legal theory,
+      whether in tort (including negligence), contract, or otherwise,
+      unless required by applicable law (such as deliberate and grossly
+      negligent acts) or agreed to in writing, shall any Contributor be
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diff --git a/LICENSE-APACHE b/LICENSE-APACHE
new file mode 100644
index 0000000..d645695
--- /dev/null
+++ b/LICENSE-APACHE
@@ -0,0 +1,202 @@
+
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+
+      "Legal Entity" shall mean the union of the acting entity and all
+      other entities that control, are controlled by, or are under common
+      control with that entity. For the purposes of this definition,
+      "control" means (i) the power, direct or indirect, to cause the
+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
+
+      "Source" form shall mean the preferred form for making modifications,
+      including but not limited to software source code, documentation
+      source, and configuration files.
+
+      "Object" form shall mean any form resulting from mechanical
+      transformation or translation of a Source form, including but
+      not limited to compiled object code, generated documentation,
+      and conversions to other media types.
+
+      "Work" shall mean the work of authorship, whether in Source or
+      Object form, made available under the License, as indicated by a
+      copyright notice that is included in or attached to the work
+      (an example is provided in the Appendix below).
+
+      "Derivative Works" shall mean any work, whether in Source or Object
+      form, that is based on (or derived from) the Work and for which the
+      editorial revisions, annotations, elaborations, or other modifications
+      represent, as a whole, an original work of authorship. For the purposes
+      of this License, Derivative Works shall not include works that remain
+      separable from, or merely link (or bind by name) to the interfaces of,
+      the Work and Derivative Works thereof.
+
+      "Contribution" shall mean any work of authorship, including
+      the original version of the Work and any modifications or additions
+      to that Work or Derivative Works thereof, that is intentionally
+      submitted to Licensor for inclusion in the Work by the copyright owner
+      or by an individual or Legal Entity authorized to submit on behalf of
+      the copyright owner. For the purposes of this definition, "submitted"
+      means any form of electronic, verbal, or written communication sent
+      to the Licensor or its representatives, including but not limited to
+      communication on electronic mailing lists, source code control systems,
+      and issue tracking systems that are managed by, or on behalf of, the
+      Licensor for the purpose of discussing and improving the Work, but
+      excluding communication that is conspicuously marked or otherwise
+      designated in writing by the copyright owner as "Not a Contribution."
+
+      "Contributor" shall mean Licensor and any individual or Legal Entity
+      on behalf of whom a Contribution has been received by Licensor and
+      subsequently incorporated within the Work.
+
+   2. Grant of Copyright License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      copyright license to reproduce, prepare Derivative Works of,
+      publicly display, publicly perform, sublicense, and distribute the
+      Work and such Derivative Works in Source or Object form.
+
+   3. Grant of Patent License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      (except as stated in this section) patent license to make, have made,
+      use, offer to sell, sell, import, and otherwise transfer the Work,
+      where such license applies only to those patent claims licensable
+      by such Contributor that are necessarily infringed by their
+      Contribution(s) alone or by combination of their Contribution(s)
+      with the Work to which such Contribution(s) was submitted. If You
+      institute patent litigation against any entity (including a
+      cross-claim or counterclaim in a lawsuit) alleging that the Work
+      or a Contribution incorporated within the Work constitutes direct
+      or contributory patent infringement, then any patent licenses
+      granted to You under this License for that Work shall terminate
+      as of the date such litigation is filed.
+
+   4. Redistribution. You may reproduce and distribute copies of the
+      Work or Derivative Works thereof in any medium, with or without
+      modifications, and in Source or Object form, provided that You
+      meet the following conditions:
+
+      (a) You must give any other recipients of the Work or
+          Derivative Works a copy of this License; and
+
+      (b) You must cause any modified files to carry prominent notices
+          stating that You changed the files; and
+
+      (c) You must retain, in the Source form of any Derivative Works
+          that You distribute, all copyright, patent, trademark, and
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+          excluding those notices that do not pertain to any part of
+          the Derivative Works; and
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+      (d) If the Work includes a "NOTICE" text file as part of its
+          distribution, then any Derivative Works that You distribute must
+          include a readable copy of the attribution notices contained
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+          pertain to any part of the Derivative Works, in at least one
+          of the following places: within a NOTICE text file distributed
+          as part of the Derivative Works; within the Source form or
+          documentation, if provided along with the Derivative Works; or,
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+          wherever such third-party notices normally appear. The contents
+          of the NOTICE file are for informational purposes only and
+          do not modify the License. You may add Your own attribution
+          notices within Derivative Works that You distribute, alongside
+          or as an addendum to the NOTICE text from the Work, provided
+          that such additional attribution notices cannot be construed
+          as modifying the License.
+
+      You may add Your own copyright statement to Your modifications and
+      may provide additional or different license terms and conditions
+      for use, reproduction, or distribution of Your modifications, or
+      for any such Derivative Works as a whole, provided Your use,
+      reproduction, and distribution of the Work otherwise complies with
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+
+   5. Submission of Contributions. Unless You explicitly state otherwise,
+      any Contribution intentionally submitted for inclusion in the Work
+      by You to the Licensor shall be under the terms and conditions of
+      this License, without any additional terms or conditions.
+      Notwithstanding the above, nothing herein shall supersede or modify
+      the terms of any separate license agreement you may have executed
+      with Licensor regarding such Contributions.
+
+   6. Trademarks. This License does not grant permission to use the trade
+      names, trademarks, service marks, or product names of the Licensor,
+      except as required for reasonable and customary use in describing the
+      origin of the Work and reproducing the content of the NOTICE file.
+
+   7. Disclaimer of Warranty. Unless required by applicable law or
+      agreed to in writing, Licensor provides the Work (and each
+      Contributor provides its Contributions) on an "AS IS" BASIS,
+      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+      implied, including, without limitation, any warranties or conditions
+      of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+      PARTICULAR PURPOSE. You are solely responsible for determining the
+      appropriateness of using or redistributing the Work and assume any
+      risks associated with Your exercise of permissions under this License.
+
+   8. Limitation of Liability. In no event and under no legal theory,
+      whether in tort (including negligence), contract, or otherwise,
+      unless required by applicable law (such as deliberate and grossly
+      negligent acts) or agreed to in writing, shall any Contributor be
+      liable to You for damages, including any direct, indirect, special,
+      incidental, or consequential damages of any character arising as a
+      result of this License or out of the use or inability to use the
+      Work (including but not limited to damages for loss of goodwill,
+      work stoppage, computer failure or malfunction, or any and all
+      other commercial damages or losses), even if such Contributor
+      has been advised of the possibility of such damages.
+
+   9. Accepting Warranty or Additional Liability. While redistributing
+      the Work or Derivative Works thereof, You may choose to offer,
+      and charge a fee for, acceptance of support, warranty, indemnity,
+      or other liability obligations and/or rights consistent with this
+      License. However, in accepting such obligations, You may act only
+      on Your own behalf and on Your sole responsibility, not on behalf
+      of any other Contributor, and only if You agree to indemnify,
+      defend, and hold each Contributor harmless for any liability
+      incurred by, or claims asserted against, such Contributor by reason
+      of your accepting any such warranty or additional liability.
+
+   END OF TERMS AND CONDITIONS
+
+   APPENDIX: How to apply the Apache License to your work.
+
+      To apply the Apache License to your work, attach the following
+      boilerplate notice, with the fields enclosed by brackets "[]"
+      replaced with your own identifying information. (Don't include
+      the brackets!)  The text should be enclosed in the appropriate
+      comment syntax for the file format. We also recommend that a
+      file or class name and description of purpose be included on the
+      same "printed page" as the copyright notice for easier
+      identification within third-party archives.
+
+   Copyright [yyyy] [name of copyright owner]
+
+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   You may obtain a copy of the License at
+
+       http://www.apache.org/licenses/LICENSE-2.0
+
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.
diff --git a/LICENSE-MIT b/LICENSE-MIT
new file mode 100644
index 0000000..cc11d8a
--- /dev/null
+++ b/LICENSE-MIT
@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2022 The aarch64-paging Authors.
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
diff --git a/METADATA b/METADATA
new file mode 100644
index 0000000..ad403ca
--- /dev/null
+++ b/METADATA
@@ -0,0 +1,20 @@
+name: "aarch64-paging"
+description: "A library to manipulate AArch64 VMSA EL1 page tables."
+third_party {
+  url {
+    type: HOMEPAGE
+    value: "https://crates.io/crates/aarch64-paging"
+  }
+  url {
+    type: ARCHIVE
+    value: "https://static.crates.io/crates/aarch64-paging/aarch64-paging-0.1.0.crate"
+  }
+  version: "0.1.0"
+  # Dual-licensed, using the least restrictive per go/thirdpartylicenses#same.
+  license_type: NOTICE
+  last_upgrade_date {
+    year: 2022
+    month: 5
+    day: 6
+  }
+}
diff --git a/MODULE_LICENSE_APACHE2 b/MODULE_LICENSE_APACHE2
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/MODULE_LICENSE_APACHE2
diff --git a/OWNERS b/OWNERS
new file mode 100644
index 0000000..45dc4dd
--- /dev/null
+++ b/OWNERS
@@ -0,0 +1 @@
+include platform/prebuilts/rust:master:/OWNERS
diff --git a/README.md b/README.md
new file mode 100644
index 0000000..2151df2
--- /dev/null
+++ b/README.md
@@ -0,0 +1,25 @@
+# aarch64 page table manipulation
+
+[![crates.io page](https://img.shields.io/crates/v/aarch64-paging.svg)](https://crates.io/crates/aarch64-paging)
+[![docs.rs page](https://docs.rs/aarch64-paging/badge.svg)](https://docs.rs/aarch64-paging)
+
+This crate provides a library to manipulate EL1 page tables conforming to the AArch64 Virtual Memory
+System Architecture.
+
+This is not an officially supported Google product.
+
+## License
+
+Licensed under either of
+
+- Apache License, Version 2.0
+  ([LICENSE-APACHE](LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0)
+- MIT license
+  ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+
+at your option.
+
+## Contributing
+
+If you want to contribute to the project, see details of
+[how we accept contributions](CONTRIBUTING.md).
diff --git a/cargo2android.json b/cargo2android.json
new file mode 100644
index 0000000..7cf9e83
--- /dev/null
+++ b/cargo2android.json
@@ -0,0 +1,11 @@
+{
+  "add-module-block": "cargo2android_module.bp",
+  "apex-available": [
+    "//apex_available:platform",
+    "com.android.virt"
+  ],
+  "dependencies": true,
+  "device": true,
+  "run": true,
+  "tests": true
+}
\ No newline at end of file
diff --git a/cargo2android_module.bp b/cargo2android_module.bp
new file mode 100644
index 0000000..da8df21
--- /dev/null
+++ b/cargo2android_module.bp
@@ -0,0 +1,6 @@
+enabled: false,
+arch: {
+    arm64: {
+        enabled: true,
+    },
+}
\ No newline at end of file
diff --git a/src/idmap.rs b/src/idmap.rs
new file mode 100644
index 0000000..95a8818
--- /dev/null
+++ b/src/idmap.rs
@@ -0,0 +1,161 @@
+// Copyright 2022 The aarch64-paging Authors.
+// This project is dual-licensed under Apache 2.0 and MIT terms.
+// See LICENSE-APACHE and LICENSE-MIT for details.
+
+//! Functionality for managing page tables with identity mapping.
+
+use crate::paging::{
+    Attributes, MemoryRegion, PhysicalAddress, RootTable, Translation, VirtualAddress,
+};
+#[cfg(target_arch = "aarch64")]
+use core::arch::asm;
+
+/// Manages a level 1 page-table using identity mapping, where every virtual address is either
+/// unmapped or mapped to the identical IPA.
+///
+/// Mappings should be added with [`map_range`](Self::map_range) before calling
+/// [`activate`](Self::activate) to start using the new page table. To make changes which may
+/// require break-before-make semantics you must first call [`deactivate`](Self::deactivate) to
+/// switch back to a previous static page table, and then `activate` again after making the desired
+/// changes.
+///
+/// # Example
+///
+/// ```
+/// use aarch64_paging::{
+///     idmap::IdMap,
+///     paging::{Attributes, MemoryRegion},
+/// };
+///
+/// const ASID: usize = 1;
+/// const ROOT_LEVEL: usize = 1;
+///
+/// // Create a new page table with identity mapping.
+/// let mut idmap = IdMap::new(ASID, ROOT_LEVEL);
+/// // Map a 2 MiB region of memory as read-write.
+/// idmap.map_range(
+///     &MemoryRegion::new(0x80200000, 0x80400000),
+///     Attributes::NORMAL | Attributes::NON_GLOBAL | Attributes::EXECUTE_NEVER,
+/// );
+/// // Set `TTBR0_EL1` to activate the page table.
+/// # #[cfg(target_arch = "aarch64")]
+/// idmap.activate();
+///
+/// // Write something to the memory...
+///
+/// // Restore `TTBR0_EL1` to its earlier value while we modify the page table.
+/// # #[cfg(target_arch = "aarch64")]
+/// idmap.deactivate();
+/// // Now change the mapping to read-only and executable.
+/// idmap.map_range(
+///     &MemoryRegion::new(0x80200000, 0x80400000),
+///     Attributes::NORMAL | Attributes::NON_GLOBAL | Attributes::READ_ONLY,
+/// );
+/// # #[cfg(target_arch = "aarch64")]
+/// idmap.activate();
+/// ```
+#[derive(Debug)]
+pub struct IdMap {
+    root: RootTable<IdMap>,
+    #[allow(unused)]
+    asid: usize,
+    #[allow(unused)]
+    previous_ttbr: Option<usize>,
+}
+
+impl Translation for IdMap {
+    fn virtual_to_physical(va: VirtualAddress) -> PhysicalAddress {
+        PhysicalAddress(va.0)
+    }
+
+    fn physical_to_virtual(pa: PhysicalAddress) -> VirtualAddress {
+        VirtualAddress(pa.0)
+    }
+}
+
+impl IdMap {
+    /// Creates a new identity-mapping page table with the given ASID and root level.
+    pub fn new(asid: usize, rootlevel: usize) -> IdMap {
+        IdMap {
+            root: RootTable::new(rootlevel),
+            asid,
+            previous_ttbr: None,
+        }
+    }
+
+    /// Activates the page table by setting `TTBR0_EL1` to point to it, and saves the previous value
+    /// of `TTBR0_EL1` so that it may later be restored by [`deactivate`](Self::deactivate).
+    ///
+    /// Panics if a previous value of `TTBR0_EL1` is already saved and not yet used by a call to
+    /// `deactivate`.
+    #[cfg(target_arch = "aarch64")]
+    pub fn activate(&mut self) {
+        assert!(self.previous_ttbr.is_none());
+
+        let mut previous_ttbr;
+        unsafe {
+            // Safe because we trust that self.root.to_physical() returns a valid physical address
+            // of a page table, and the `Drop` implementation will reset `TTRB0_EL1` before it
+            // becomes invalid.
+            asm!(
+                "mrs   {previous_ttbr}, ttbr0_el1",
+                "msr   ttbr0_el1, {ttbrval}",
+                "isb",
+                ttbrval = in(reg) self.root.to_physical().0 | (self.asid << 48),
+                previous_ttbr = out(reg) previous_ttbr,
+                options(preserves_flags),
+            );
+        }
+        self.previous_ttbr = Some(previous_ttbr);
+    }
+
+    /// Deactivates the page table, by setting `TTBR0_EL1` back to the value it had before
+    /// [`activate`](Self::activate) was called, and invalidating the TLB for this page table's
+    /// configured ASID.
+    ///
+    /// Panics if there is no saved `TTRB0_EL1` value because `activate` has not previously been
+    /// called.
+    #[cfg(target_arch = "aarch64")]
+    pub fn deactivate(&mut self) {
+        unsafe {
+            // Safe because this just restores the previously saved value of `TTBR0_EL1`, which must
+            // have been valid.
+            asm!(
+                "msr   ttbr0_el1, {ttbrval}",
+                "isb",
+                "tlbi  aside1, {asid}",
+                "dsb   nsh",
+                "isb",
+                asid = in(reg) self.asid << 48,
+                ttbrval = in(reg) self.previous_ttbr.unwrap(),
+                options(preserves_flags),
+            );
+        }
+        self.previous_ttbr = None;
+    }
+
+    /// Maps the given range of virtual addresses to the identical physical addresses with the given
+    /// flags.
+    ///
+    /// This should generally only be called while the page table is not active. In particular, any
+    /// change that may require break-before-make per the architecture must be made while the page
+    /// table is inactive. Mapping a previously unmapped memory range may be done while the page
+    /// table is active.
+    pub fn map_range(&mut self, range: &MemoryRegion, flags: Attributes) {
+        self.root.map_range(range, flags);
+        #[cfg(target_arch = "aarch64")]
+        unsafe {
+            // Safe because this is just a memory barrier.
+            asm!("dsb ishst");
+        }
+    }
+}
+
+impl Drop for IdMap {
+    fn drop(&mut self) {
+        if self.previous_ttbr.is_some() {
+            #[cfg(target_arch = "aarch64")]
+            self.deactivate();
+        }
+    }
+}
diff --git a/src/lib.rs b/src/lib.rs
new file mode 100644
index 0000000..158fb41
--- /dev/null
+++ b/src/lib.rs
@@ -0,0 +1,44 @@
+// Copyright 2022 The aarch64-paging Authors.
+// This project is dual-licensed under Apache 2.0 and MIT terms.
+// See LICENSE-APACHE and LICENSE-MIT for details.
+
+//! A library to manipulate AArch64 VMSA page tables.
+//!
+//! Currently it only supports:
+//!   - stage 1 page tables
+//!   - EL1
+//!   - 4 KiB pages
+//!
+//! Full support is only provided for identity mapping; for other mapping schemes the user of the
+//! library must implement some functionality themself including an implementation of the
+//! [`Translation`](paging::Translation) trait.
+//!
+//! # Example
+//!
+//! ```
+//! use aarch64_paging::{
+//!     idmap::IdMap,
+//!     paging::{Attributes, MemoryRegion},
+//! };
+//!
+//! const ASID: usize = 1;
+//! const ROOT_LEVEL: usize = 1;
+//!
+//! // Create a new page table with identity mapping.
+//! let mut idmap = IdMap::new(ASID, ROOT_LEVEL);
+//! // Map a 2 MiB region of memory as read-only.
+//! idmap.map_range(
+//!     &MemoryRegion::new(0x80200000, 0x80400000),
+//!     Attributes::NORMAL | Attributes::NON_GLOBAL | Attributes::READ_ONLY,
+//! );
+//! // Set `TTBR0_EL1` to activate the page table.
+//! # #[cfg(target_arch = "aarch64")]
+//! idmap.activate();
+//! ```
+
+#![no_std]
+
+pub mod idmap;
+pub mod paging;
+
+extern crate alloc;
diff --git a/src/paging.rs b/src/paging.rs
new file mode 100644
index 0000000..09094d9
--- /dev/null
+++ b/src/paging.rs
@@ -0,0 +1,388 @@
+// Copyright 2022 The aarch64-paging Authors.
+// This project is dual-licensed under Apache 2.0 and MIT terms.
+// See LICENSE-APACHE and LICENSE-MIT for details.
+
+//! Generic aarch64 page table manipulation functionality which doesn't assume anything about how
+//! addresses are mapped.
+
+use alloc::{
+    alloc::{alloc_zeroed, handle_alloc_error},
+    boxed::Box,
+};
+use bitflags::bitflags;
+use core::alloc::Layout;
+use core::fmt::{self, Debug, Display, Formatter};
+use core::marker::PhantomData;
+use core::ops::Range;
+
+const PAGE_SHIFT: usize = 12;
+
+/// The page size in bytes assumed by this library, 4 KiB.
+pub const PAGE_SIZE: usize = 1 << PAGE_SHIFT;
+
+pub const BITS_PER_LEVEL: usize = PAGE_SHIFT - 3;
+
+/// An aarch64 virtual address, the input type of a stage 1 page table.
+#[derive(Copy, Clone, Eq, Ord, PartialEq, PartialOrd)]
+pub struct VirtualAddress(pub usize);
+
+impl<T> From<*const T> for VirtualAddress {
+    fn from(pointer: *const T) -> Self {
+        Self(pointer as usize)
+    }
+}
+
+impl<T> From<*mut T> for VirtualAddress {
+    fn from(pointer: *mut T) -> Self {
+        Self(pointer as usize)
+    }
+}
+
+impl Display for VirtualAddress {
+    fn fmt(&self, f: &mut Formatter) -> Result<(), fmt::Error> {
+        write!(f, "{:#016x}", self.0)
+    }
+}
+
+/// A range of virtual addresses which may be mapped in a page table.
+#[derive(Clone, Eq, PartialEq)]
+pub struct MemoryRegion(Range<VirtualAddress>);
+
+/// An aarch64 physical address or intermediate physical address, the output type of a stage 1 page
+/// table.
+#[derive(Copy, Clone, Eq, Ord, PartialEq, PartialOrd)]
+pub struct PhysicalAddress(pub usize);
+
+impl Display for PhysicalAddress {
+    fn fmt(&self, f: &mut Formatter) -> Result<(), fmt::Error> {
+        write!(f, "{:#016x}", self.0)
+    }
+}
+
+/// An implementation of this trait needs to be provided to the mapping routines, so that the
+/// physical addresses used in the page tables can be converted into virtual addresses that can be
+/// used to access their contents from the code.
+pub trait Translation {
+    fn virtual_to_physical(va: VirtualAddress) -> PhysicalAddress;
+    fn physical_to_virtual(pa: PhysicalAddress) -> VirtualAddress;
+}
+
+impl MemoryRegion {
+    /// Constructs a new `MemoryRegion` for the given range of virtual addresses.
+    ///
+    /// The start is inclusive and the end is exclusive. Both will be aligned to the [`PAGE_SIZE`],
+    /// with the start being rounded down and the end being rounded up.
+    pub const fn new(start: usize, end: usize) -> MemoryRegion {
+        MemoryRegion(
+            VirtualAddress(align_down(start, PAGE_SIZE))..VirtualAddress(align_up(end, PAGE_SIZE)),
+        )
+    }
+
+    /// Returns the first virtual address of the memory range.
+    pub const fn start(&self) -> VirtualAddress {
+        self.0.start
+    }
+
+    /// Returns the first virtual address after the memory range.
+    pub const fn end(&self) -> VirtualAddress {
+        self.0.end
+    }
+
+    /// Returns the length of the memory region in bytes.
+    pub const fn len(&self) -> usize {
+        self.0.end.0 - self.0.start.0
+    }
+
+    /// Returns whether the memory region contains exactly 0 bytes.
+    pub const fn is_empty(&self) -> bool {
+        self.0.start.0 == self.0.end.0
+    }
+}
+
+/// A complete hierarchy of page tables including all levels.
+#[derive(Debug)]
+pub struct RootTable<T: Translation> {
+    table: Box<PageTable<T>>,
+    level: usize,
+}
+
+impl<T: Translation> RootTable<T> {
+    /// Creates a new page table starting at the given root level.
+    pub fn new(level: usize) -> Self {
+        RootTable {
+            table: PageTable::new(),
+            level,
+        }
+    }
+
+    /// Recursively maps a range into the pagetable hierarchy starting at the root level.
+    pub fn map_range(&mut self, range: &MemoryRegion, flags: Attributes) {
+        self.table.map_range(range, flags, self.level);
+    }
+
+    /// Returns the physical address of the root table in memory.
+    pub fn to_physical(&self) -> PhysicalAddress {
+        self.table.to_physical()
+    }
+}
+
+struct ChunkedIterator<'a> {
+    range: &'a MemoryRegion,
+    granularity: usize,
+    start: usize,
+}
+
+impl Iterator for ChunkedIterator<'_> {
+    type Item = MemoryRegion;
+
+    fn next(&mut self) -> Option<MemoryRegion> {
+        if !self.range.0.contains(&VirtualAddress(self.start)) {
+            return None;
+        }
+        let end = self
+            .range
+            .0
+            .end
+            .0
+            .min((self.start | (self.granularity - 1)) + 1);
+        let c = MemoryRegion::new(self.start, end);
+        self.start = end;
+        Some(c)
+    }
+}
+
+impl MemoryRegion {
+    fn split(&self, level: usize) -> ChunkedIterator {
+        ChunkedIterator {
+            range: self,
+            granularity: PAGE_SIZE << ((3 - level) * BITS_PER_LEVEL),
+            start: self.0.start.0,
+        }
+    }
+
+    /// Returns whether this region can be mapped at 'level' using block mappings only.
+    fn is_block(&self, level: usize) -> bool {
+        let gran = PAGE_SIZE << ((3 - level) * BITS_PER_LEVEL);
+        (self.0.start.0 | self.0.end.0) & (gran - 1) == 0
+    }
+}
+
+bitflags! {
+    /// Attribute bits for a mapping in a page table.
+    pub struct Attributes: usize {
+        const VALID         = 1 << 0;
+        const TABLE_OR_PAGE = 1 << 1;
+
+        // The following memory types assume that the MAIR registers
+        // have been programmed accordingly.
+        const DEVICE_NGNRE  = 0 << 2;
+        const NORMAL        = 1 << 2 | 3 << 8; // inner shareable
+
+        const USER          = 1 << 6;
+        const READ_ONLY     = 1 << 7;
+        const ACCESSED      = 1 << 10;
+        const NON_GLOBAL    = 1 << 11;
+        const EXECUTE_NEVER = 3 << 53;
+    }
+}
+
+/// A single level of a page table.
+#[repr(C, align(4096))]
+struct PageTable<T: Translation> {
+    entries: [Descriptor; 1 << BITS_PER_LEVEL],
+    _phantom_data: PhantomData<T>,
+}
+
+/// An entry in a page table.
+///
+/// A descriptor may be:
+///   - Invalid, i.e. the virtual address range is unmapped
+///   - A page mapping, if it is in the lowest level page table.
+///   - A block mapping, if it is not in the lowest level page table.
+///   - A pointer to a lower level pagetable, if it is not in the lowest level page table.
+#[derive(Clone, Copy)]
+#[repr(C)]
+struct Descriptor(usize);
+
+impl Descriptor {
+    fn output_address(&self) -> Option<PhysicalAddress> {
+        if self.is_valid() {
+            Some(PhysicalAddress(
+                self.0 & (!(PAGE_SIZE - 1) & !(0xffff << 48)),
+            ))
+        } else {
+            None
+        }
+    }
+
+    fn flags(self) -> Option<Attributes> {
+        if self.is_valid() {
+            Attributes::from_bits(self.0 & ((PAGE_SIZE - 1) | (0xffff << 48)))
+        } else {
+            None
+        }
+    }
+
+    fn is_valid(self) -> bool {
+        (self.0 & Attributes::VALID.bits()) != 0
+    }
+
+    fn is_table(self) -> bool {
+        if let Some(flags) = self.flags() {
+            flags.contains(Attributes::TABLE_OR_PAGE)
+        } else {
+            false
+        }
+    }
+
+    fn set(&mut self, pa: PhysicalAddress, flags: Attributes) {
+        self.0 = pa.0 | (flags | Attributes::VALID).bits();
+    }
+
+    fn subtable<T: Translation>(&self) -> Option<&mut PageTable<T>> {
+        if self.is_table() {
+            if let Some(output_address) = self.output_address() {
+                let va = T::physical_to_virtual(output_address);
+                return Some(unsafe { &mut *(va.0 as *mut PageTable<T>) });
+            }
+        }
+        None
+    }
+}
+
+impl Debug for Descriptor {
+    fn fmt(&self, f: &mut Formatter) -> Result<(), fmt::Error> {
+        write!(f, "{:#016x}", self.0)?;
+        if let (Some(flags), Some(address)) = (self.flags(), self.output_address()) {
+            write!(f, " ({}, {:?})", address, flags)?;
+        }
+        Ok(())
+    }
+}
+
+impl<T: Translation> Debug for PageTable<T> {
+    fn fmt(&self, f: &mut Formatter) -> Result<(), fmt::Error> {
+        writeln!(f)?;
+        self.fmt_indented(f, 0)
+    }
+}
+
+/// Allocates appropriately aligned heap space for a `T` and zeroes it.
+fn allocate_zeroed<T>() -> *mut T {
+    let layout = Layout::new::<T>();
+    // Safe because we know the layout has non-zero size.
+    let pointer = unsafe { alloc_zeroed(layout) };
+    if pointer.is_null() {
+        handle_alloc_error(layout);
+    }
+    pointer as *mut T
+}
+
+impl<T: Translation> PageTable<T> {
+    /// Allocates a new, zeroed, appropriately-aligned page table on the heap.
+    pub fn new() -> Box<Self> {
+        // Safe because the pointer has been allocated with the appropriate layout by the global
+        // allocator, and the memory is zeroed which is valid initialisation for a PageTable.
+        unsafe {
+            // We need to use Box::from_raw here rather than Box::new to avoid allocating on the
+            // stack and copying to the heap.
+            // TODO: Use Box::new_zeroed().assume_init() once it is stable.
+            Box::from_raw(allocate_zeroed())
+        }
+    }
+
+    /// Returns the physical address of this page table in memory.
+    pub fn to_physical(&self) -> PhysicalAddress {
+        T::virtual_to_physical(VirtualAddress::from(self as *const Self))
+    }
+
+    fn get_entry_mut(&mut self, va: usize, level: usize) -> &mut Descriptor {
+        let shift = PAGE_SHIFT + (3 - level) * BITS_PER_LEVEL;
+        let index = (va >> shift) % (1 << BITS_PER_LEVEL);
+        &mut self.entries[index]
+    }
+
+    fn map_range(&mut self, range: &MemoryRegion, flags: Attributes, level: usize) {
+        assert!(level <= 3);
+        let mut pa = T::virtual_to_physical(range.start());
+
+        for chunk in range.split(level) {
+            let entry = self.get_entry_mut(chunk.0.start.0, level);
+
+            if level == 3 {
+                // Put down a page mapping.
+                entry.set(pa, flags | Attributes::ACCESSED | Attributes::TABLE_OR_PAGE);
+            } else if chunk.is_block(level) && !entry.is_table() {
+                // Rather than leak the entire subhierarchy, only put down
+                // a block mapping if the region is not already covered by
+                // a table mapping.
+                entry.set(pa, flags | Attributes::ACCESSED);
+            } else {
+                let subtable = if let Some(subtable) = entry.subtable::<T>() {
+                    subtable
+                } else {
+                    let old = *entry;
+                    let subtable = Box::leak(PageTable::<T>::new());
+                    if let Some(old_flags) = old.flags() {
+                        let granularity = PAGE_SIZE << ((3 - level) * BITS_PER_LEVEL);
+                        // Old was a valid block entry, so we need to split it.
+                        // Recreate the entire block in the newly added table.
+                        let a = align_down(chunk.0.start.0, granularity);
+                        let b = align_up(chunk.0.end.0, granularity);
+                        subtable.map_range(&MemoryRegion::new(a, b), old_flags, level + 1);
+                    }
+                    entry.set(subtable.to_physical(), Attributes::TABLE_OR_PAGE);
+                    subtable
+                };
+                subtable.map_range(&chunk, flags, level + 1);
+            }
+            pa.0 += chunk.len();
+        }
+    }
+
+    fn fmt_indented(&self, f: &mut Formatter, indentation: usize) -> Result<(), fmt::Error> {
+        let mut i = 0;
+        while i < self.entries.len() {
+            if self.entries[i].0 == 0 {
+                let first_zero = i;
+                while i < self.entries.len() && self.entries[i].0 == 0 {
+                    i += 1;
+                }
+                if i - 1 == first_zero {
+                    writeln!(f, "{:indentation$}{}: 0", "", first_zero)?;
+                } else {
+                    writeln!(f, "{:indentation$}{}-{}: 0", "", first_zero, i - 1)?;
+                }
+            } else {
+                writeln!(f, "{:indentation$}{}: {:?}", "", i, self.entries[i])?;
+                if let Some(subtable) = self.entries[i].subtable::<T>() {
+                    subtable.fmt_indented(f, indentation + 2)?;
+                }
+                i += 1;
+            }
+        }
+        Ok(())
+    }
+}
+
+impl<T: Translation> Drop for PageTable<T> {
+    fn drop(&mut self) {
+        for entry in self.entries {
+            if let Some(subtable) = entry.subtable::<T>() {
+                // Safe because the subtable was allocated by `PageTable::new` with the global
+                // allocator and appropriate layout.
+                unsafe {
+                    drop(Box::from_raw(subtable));
+                }
+            }
+        }
+    }
+}
+
+const fn align_down(value: usize, alignment: usize) -> usize {
+    value & !(alignment - 1)
+}
+
+const fn align_up(value: usize, alignment: usize) -> usize {
+    ((value - 1) | (alignment - 1)) + 1
+}