diff options
author | Treehugger Robot <android-test-infra-autosubmit@system.gserviceaccount.com> | 2023-06-23 20:52:54 +0000 |
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committer | Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com> | 2023-06-23 20:52:54 +0000 |
commit | 64433e2515a7c675f95220ebbc9932ad642515ec (patch) | |
tree | 9d56a8348ebdc9938367498c59ef9f9fcfce2090 | |
parent | ac21f6e34c3288334fabda5632f81028d154777b (diff) | |
parent | 1c3129e1cb777dba025ab2be9d4c8f59aa9cf0dc (diff) | |
download | libdrm-64433e2515a7c675f95220ebbc9932ad642515ec.tar.gz |
Merge "Merge tag 'libdrm-2.4.110'" am: 061d95fa32 am: 1c3129e1cb
Original change: https://android-review.googlesource.com/c/platform/external/libdrm/+/2626636
Change-Id: I66e663b8bd9fbdbdf57fa2512edbdacaf3a5d9e1
Signed-off-by: Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com>
31 files changed, 895 insertions, 128 deletions
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 876be951..c5aa7a2b 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -41,10 +41,10 @@ stages: BUILD_OS: debian FDO_DISTRIBUTION_VERSION: buster FDO_DISTRIBUTION_PACKAGES: 'build-essential docbook-xsl libatomic-ops-dev libcairo2-dev libcunit1-dev libpciaccess-dev meson ninja-build pkg-config python3 python3-pip python3-wheel python3-setuptools python3-docutils valgrind' - FDO_DISTRIBUTION_EXEC: 'pip3 install meson==0.52.1' + FDO_DISTRIBUTION_EXEC: 'pip3 install meson==0.53.0' # bump this tag every time you change something which requires rebuilding the # base image - FDO_DISTRIBUTION_TAG: "2021-08-03.0" + FDO_DISTRIBUTION_TAG: "2022-01-19.0" .debian-x86_64: extends: @@ -18,9 +18,9 @@ Follow these steps to release a new version of libdrm: builddir/meson-dist/ matches the number you bumped to. Move that tarball to the libdrm repo root for the release script to pick up. - 3) Push the updated master branch with the bumped version number: + 3) Push the updated main branch with the bumped version number: - git push origin master + git push origin main assuming the remote for the upstream libdrm repo is called origin. diff --git a/amdgpu/amdgpu-symbols.txt b/amdgpu/amdgpu-symbols.txt index af2b6439..d41d9c24 100644 --- a/amdgpu/amdgpu-symbols.txt +++ b/amdgpu/amdgpu-symbols.txt @@ -25,6 +25,7 @@ amdgpu_cs_ctx_create amdgpu_cs_ctx_create2 amdgpu_cs_ctx_free amdgpu_cs_ctx_override_priority +amdgpu_cs_ctx_stable_pstate amdgpu_cs_destroy_semaphore amdgpu_cs_destroy_syncobj amdgpu_cs_export_syncobj diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index cde8585c..5ef2524a 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -940,6 +940,21 @@ int amdgpu_cs_ctx_override_priority(amdgpu_device_handle dev, unsigned priority); /** + * Set or query the stable power state for GPU profiling. + * + * \param dev - \c [in] device handle + * \param op - \c [in] AMDGPU_CTX_OP_{GET,SET}_STABLE_PSTATE + * \param flags - \c [in] AMDGPU_CTX_STABLE_PSTATE_* + * \param out_flags - \c [out] output current stable pstate + * + * \return 0 on success otherwise POSIX Error code. + */ +int amdgpu_cs_ctx_stable_pstate(amdgpu_context_handle context, + uint32_t op, + uint32_t flags, + uint32_t *out_flags); + +/** * Query reset state for the specific GPU Context * * \param context - \c [in] GPU Context handle diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index fad484bf..638fd7d6 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -167,6 +167,28 @@ drm_public int amdgpu_cs_ctx_override_priority(amdgpu_device_handle dev, return 0; } +drm_public int amdgpu_cs_ctx_stable_pstate(amdgpu_context_handle context, + uint32_t op, + uint32_t flags, + uint32_t *out_flags) +{ + union drm_amdgpu_ctx args; + int r; + + if (!context) + return -EINVAL; + + memset(&args, 0, sizeof(args)); + args.in.op = op; + args.in.ctx_id = context->id; + args.in.flags = flags; + r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX, + &args, sizeof(args)); + if (!r && out_flags) + *out_flags = args.out.pstate.flags; + return r; +} + drm_public int amdgpu_cs_query_reset_state(amdgpu_context_handle context, uint32_t *state, uint32_t *hangs) { diff --git a/amdgpu/meson.build b/amdgpu/meson.build index 3301a10e..a1cca5a2 100644 --- a/amdgpu/meson.build +++ b/amdgpu/meson.build @@ -44,11 +44,9 @@ libdrm_amdgpu = library( install_headers('amdgpu.h', subdir : 'libdrm') pkg.generate( + libdrm_amdgpu, name : 'libdrm_amdgpu', - libraries : libdrm_amdgpu, subdirs : ['.', 'libdrm'], - version : meson.project_version(), - requires_private : 'libdrm', description : 'Userspace interface to kernel DRM services for amdgpu', ) @@ -57,6 +55,10 @@ ext_libdrm_amdgpu = declare_dependency( include_directories : [inc_drm, include_directories('.')], ) +if meson.version().version_compare('>= 0.54.0') + meson.override_dependency('libdrm_amdgpu', ext_libdrm_amdgpu) +endif + test( 'amdgpu-symbols-check', symbols_check, diff --git a/etnaviv/meson.build b/etnaviv/meson.build index 8b82ed07..591f20f0 100644 --- a/etnaviv/meson.build +++ b/etnaviv/meson.build @@ -31,6 +31,7 @@ libdrm_etnaviv = library( include_directories : [inc_root, inc_drm], link_with : libdrm, c_args : libdrm_c_args, + gnu_symbol_visibility : 'hidden', dependencies : [dep_pthread_stubs, dep_rt, dep_atomic_ops], version : '1.0.0', install : true, @@ -39,11 +40,9 @@ libdrm_etnaviv = library( install_headers('etnaviv_drmif.h', subdir : 'libdrm') pkg.generate( + libdrm_etnaviv, name : 'libdrm_etnaviv', - libraries : libdrm_etnaviv, subdirs : ['.', 'libdrm'], - version : meson.project_version(), - requires_private : 'libdrm', description : 'Userspace interface to Tegra kernel DRM services', ) @@ -52,6 +51,10 @@ ext_libdrm_etnaviv = declare_dependency( include_directories : [inc_drm, include_directories('.')], ) +if meson.version().version_compare('>= 0.54.0') + meson.override_dependency('libdrm_etnaviv', ext_libdrm_etnaviv) +endif + test( 'etnaviv-symbols-check', symbols_check, diff --git a/exynos/meson.build b/exynos/meson.build index 7d1edfea..2f02ae71 100644 --- a/exynos/meson.build +++ b/exynos/meson.build @@ -22,6 +22,7 @@ libdrm_exynos = library( 'drm_exynos', [files('exynos_drm.c', 'exynos_fimg2d.c'), config_file], c_args : libdrm_c_args, + gnu_symbol_visibility : 'hidden', include_directories : [inc_root, inc_drm], link_with : libdrm, dependencies : [dep_pthread_stubs], @@ -37,12 +38,15 @@ ext_libdrm_exynos = declare_dependency( include_directories : [inc_drm, include_directories('.')], ) +if meson.version().version_compare('>= 0.54.0') + meson.override_dependency('libdrm_exynos', ext_libdrm_exynos) +endif + pkg.generate( + libdrm_exynos, name : 'libdrm_exynos', - libraries : libdrm_exynos, subdirs : ['.', 'libdrm', 'exynos'], version : '0.7', - requires_private : 'libdrm', description : 'Userspace interface to exynos kernel DRM services', ) diff --git a/freedreno/meson.build b/freedreno/meson.build index 49e66593..de9ee148 100644 --- a/freedreno/meson.build +++ b/freedreno/meson.build @@ -55,17 +55,19 @@ ext_libdrm_freedreno = declare_dependency( include_directories : [inc_drm, include_directories('.')], ) +if meson.version().version_compare('>= 0.54.0') + meson.override_dependency('libdrm_freedreno', ext_libdrm_freedreno) +endif + install_headers( 'freedreno_drmif.h', 'freedreno_ringbuffer.h', subdir : 'freedreno' ) pkg.generate( + libdrm_freedreno, name : 'libdrm_freedreno', - libraries : libdrm_freedreno, subdirs : ['.', 'libdrm', 'freedreno'], - version : meson.project_version(), - requires_private : 'libdrm', description : 'Userspace interface to freedreno kernel DRM services', ) diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index 0cbd1540..7f01f983 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -80,7 +80,7 @@ extern "C" { * * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the * GPU's virtual address space via gart. Gart memory linearizes non-contiguous - * pages of system memory, allows GPU access system memory in a linezrized + * pages of system memory, allows GPU access system memory in a linearized * fashion. * * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory @@ -206,6 +206,8 @@ union drm_amdgpu_bo_list { #define AMDGPU_CTX_OP_FREE_CTX 2 #define AMDGPU_CTX_OP_QUERY_STATE 3 #define AMDGPU_CTX_OP_QUERY_STATE2 4 +#define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 +#define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 /* GPU reset status */ #define AMDGPU_CTX_NO_RESET 0 @@ -238,10 +240,18 @@ union drm_amdgpu_bo_list { #define AMDGPU_CTX_PRIORITY_HIGH 512 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 +/* select a stable profiling pstate for perfmon tools */ +#define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf +#define AMDGPU_CTX_STABLE_PSTATE_NONE 0 +#define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 +#define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 +#define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 +#define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 + struct drm_amdgpu_ctx_in { /** AMDGPU_CTX_OP_* */ __u32 op; - /** For future use, no flags defined so far */ + /** Flags */ __u32 flags; __u32 ctx_id; /** AMDGPU_CTX_PRIORITY_* */ @@ -262,6 +272,11 @@ union drm_amdgpu_ctx_out { /** Reset status since the last call of the ioctl. */ __u32 reset_status; } state; + + struct { + __u32 flags; + __u32 _pad; + } pstate; }; union drm_amdgpu_ctx { @@ -786,13 +801,6 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F /* query ras mask of enabled features*/ #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 -/* query video encode/decode caps */ -#define AMDGPU_INFO_VIDEO_CAPS 0x21 - /* Subquery id: Decode */ - #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 - /* Subquery id: Encode */ - #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 - /* RAS MASK: UMC (VRAM) */ #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) /* RAS MASK: SDMA */ @@ -821,6 +829,12 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) /* RAS MASK: FUSE */ #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) +/* query video encode/decode caps */ +#define AMDGPU_INFO_VIDEO_CAPS 0x21 + /* Subquery id: Decode */ + #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 + /* Subquery id: Encode */ + #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff diff --git a/intel/i915_pciids.h b/intel/i915_pciids.h index c00ac546..8076d40c 100644 --- a/intel/i915_pciids.h +++ b/intel/i915_pciids.h @@ -666,4 +666,19 @@ INTEL_VGA_DEVICE(0x46C2, info), \ INTEL_VGA_DEVICE(0x46C3, info) +/* ADL-N */ +#define INTEL_ADLN_IDS(info) \ + INTEL_VGA_DEVICE(0x46D0, info), \ + INTEL_VGA_DEVICE(0x46D1, info), \ + INTEL_VGA_DEVICE(0x46D2, info) + +/* RPL-S */ +#define INTEL_RPLS_IDS(info) \ + INTEL_VGA_DEVICE(0xA780, info), \ + INTEL_VGA_DEVICE(0xA781, info), \ + INTEL_VGA_DEVICE(0xA782, info), \ + INTEL_VGA_DEVICE(0xA783, info), \ + INTEL_VGA_DEVICE(0xA788, info), \ + INTEL_VGA_DEVICE(0xA789, info) + #endif /* _I915_PCIIDS_H */ diff --git a/intel/intel_chipset.c b/intel/intel_chipset.c index f0da6d81..99ad04ae 100644 --- a/intel/intel_chipset.c +++ b/intel/intel_chipset.c @@ -35,6 +35,8 @@ static const struct pci_device { uint16_t gen; } pciids[] = { /* Keep ids sorted by gen; latest gen first */ + INTEL_RPLS_IDS(12), + INTEL_ADLN_IDS(12), INTEL_ADLP_IDS(12), INTEL_ADLS_IDS(12), INTEL_RKL_IDS(12), diff --git a/intel/meson.build b/intel/meson.build index 5fa06c28..e6550daa 100644 --- a/intel/meson.build +++ b/intel/meson.build @@ -31,6 +31,7 @@ libdrm_intel = library( link_with : libdrm, dependencies : [dep_pciaccess, dep_pthread_stubs, dep_rt, dep_valgrind, dep_atomic_ops], c_args : libdrm_c_args, + gnu_symbol_visibility : 'hidden', version : '1.0.0', install : true, ) @@ -40,16 +41,19 @@ ext_libdrm_intel = declare_dependency( include_directories : [inc_drm, include_directories('.')], ) +if meson.version().version_compare('>= 0.54.0') + meson.override_dependency('libdrm_intel', ext_libdrm_intel) +endif + install_headers( 'intel_bufmgr.h', 'intel_aub.h', 'intel_debug.h', subdir : 'libdrm', ) pkg.generate( + libdrm_intel, name : 'libdrm_intel', - libraries : libdrm_intel, subdirs : ['.', 'libdrm'], - version : meson.project_version(), requires : 'libdrm', description : 'Userspace interface to intel kernel DRM services', ) @@ -60,6 +64,7 @@ test_decode = executable( include_directories : [inc_root, inc_drm], link_with : [libdrm, libdrm_intel], c_args : libdrm_c_args, + gnu_symbol_visibility : 'hidden', ) test( diff --git a/libdrm_lists.h b/libdrm_lists.h index 8926d8d1..7f55fc0d 100644 --- a/libdrm_lists.h +++ b/libdrm_lists.h @@ -96,19 +96,19 @@ typedef struct _drmMMListHead (__item) = (__temp), (__temp) = (__item)->prev) #define DRMLISTFOREACHENTRY(__item, __list, __head) \ - for ((__item) = DRMLISTENTRY(typeof(*__item), (__list)->next, __head); \ - &(__item)->__head != (__list); \ - (__item) = DRMLISTENTRY(typeof(*__item), \ - (__item)->__head.next, __head)) + for ((__item) = DRMLISTENTRY(__typeof__(*__item), (__list)->next, __head); \ + &(__item)->__head != (__list); \ + (__item) = DRMLISTENTRY(__typeof__(*__item), \ + (__item)->__head.next, __head)) #define DRMLISTFOREACHENTRYSAFE(__item, __temp, __list, __head) \ - for ((__item) = DRMLISTENTRY(typeof(*__item), (__list)->next, __head), \ - (__temp) = DRMLISTENTRY(typeof(*__item), \ - (__item)->__head.next, __head); \ - &(__item)->__head != (__list); \ - (__item) = (__temp), \ - (__temp) = DRMLISTENTRY(typeof(*__item), \ - (__temp)->__head.next, __head)) + for ((__item) = DRMLISTENTRY(__typeof__(*__item), (__list)->next, __head), \ + (__temp) = DRMLISTENTRY(__typeof__(*__item), \ + (__item)->__head.next, __head); \ + &(__item)->__head != (__list); \ + (__item) = (__temp), \ + (__temp) = DRMLISTENTRY(__typeof__(*__item), \ + (__temp)->__head.next, __head)) #define DRMLISTJOIN(__list, __join) if (!DRMLISTEMPTY(__list)) { \ (__list)->next->prev = (__join); \ diff --git a/libkms/meson.build b/libkms/meson.build index 8d17bb2e..e2adaea3 100644 --- a/libkms/meson.build +++ b/libkms/meson.build @@ -56,14 +56,17 @@ ext_libkms = declare_dependency( include_directories : [libkms_include], ) +if meson.version().version_compare('>= 0.54.0') + meson.override_dependency('kms', ext_libkms) +endif + install_headers('libkms.h', subdir : 'libkms') pkg.generate( + libkms, name : 'libkms', - libraries : libkms, subdirs : ['libkms'], version : '1.0.0', - requires_private : 'libdrm', description : 'Library that abstracts away the different mm interfaces for kernel drivers', ) diff --git a/meson.build b/meson.build index 5824da8a..210d29e0 100644 --- a/meson.build +++ b/meson.build @@ -21,10 +21,10 @@ project( 'libdrm', ['c'], - version : '2.4.109', + version : '2.4.110', license : 'MIT', - meson_version : '>= 0.46', - default_options : ['buildtype=debugoptimized', 'c_std=gnu99'], + meson_version : '>= 0.53', + default_options : ['buildtype=debugoptimized', 'c_std=c99'], ) pkg = import('pkgconfig') @@ -54,8 +54,10 @@ intel_atomics = false lib_atomics = false python3 = import('python').find_installation() -format_mod_static_table = custom_target('format_mod_static_table', - output : 'generated_static_table_fourcc.h', input: 'include/drm/drm_fourcc.h', +format_mod_static_table = custom_target( + 'format_mod_static_table', + output : 'generated_static_table_fourcc.h', + input : 'include/drm/drm_fourcc.h', command : [python3, files('gen_table_fourcc.py'), '@INPUT@', '@OUTPUT@']) dep_atomic_ops = dependency('atomic_ops', required : false) @@ -89,6 +91,7 @@ if _intel != 'false' with_intel = _intel == 'true' or host_machine.cpu_family().startswith('x86') endif endif +summary('Intel', with_intel) with_radeon = false _radeon = get_option('radeon') @@ -98,6 +101,7 @@ if _radeon != 'false' endif with_radeon = true endif +summary('Radeon', with_radeon) with_amdgpu = false _amdgpu = get_option('amdgpu') @@ -107,6 +111,7 @@ if _amdgpu != 'false' endif with_amdgpu = true endif +summary('AMDGPU', with_amdgpu) with_nouveau = false _nouveau = get_option('nouveau') @@ -116,12 +121,14 @@ if _nouveau != 'false' endif with_nouveau = true endif +summary('Nouveau', with_nouveau) with_vmwgfx = false _vmwgfx = get_option('vmwgfx') if _vmwgfx != 'false' with_vmwgfx = true endif +summary('vmwgfx', with_vmwgfx) with_omap = false _omap = get_option('omap') @@ -131,6 +138,7 @@ if _omap == 'true' endif with_omap = true endif +summary('OMAP', with_omap) with_freedreno = false _freedreno = get_option('freedreno') @@ -141,6 +149,8 @@ if _freedreno != 'false' with_freedreno = _freedreno == 'true' or ['arm', 'aarch64'].contains(host_machine.cpu_family()) endif endif +summary('Freedreno', with_freedreno) +summary('Freedreon-kgsl', with_freedreno_kgsl) with_tegra = false _tegra = get_option('tegra') @@ -150,6 +160,7 @@ if _tegra == 'true' endif with_tegra = true endif +summary('Tegra', with_tegra) with_etnaviv = false _etnaviv = get_option('etnaviv') @@ -159,14 +170,17 @@ if _etnaviv == 'true' endif with_etnaviv = true endif +summary('Etnaviv', with_etnaviv) with_exynos = get_option('exynos') == 'true' +summary('EXYNOS', with_exynos) with_vc4 = false _vc4 = get_option('vc4') if _vc4 != 'false' with_vc4 = _vc4 == 'true' or ['arm', 'aarch64'].contains(host_machine.cpu_family()) endif +summary('VC4', with_vc4) # XXX: Apparently only freebsd and dragonfly bsd actually need this (and # gnu/kfreebsd), not openbsd and netbsd @@ -175,6 +189,7 @@ _libkms = get_option('libkms') if _libkms != 'false' with_libkms = _libkms == 'true' or (['linux', 'freebsd', 'dragonfly'].contains(host_machine.system()) and not android) endif +summary('libkms', with_libkms) # Among others FreeBSD does not have a separate dl library. if not cc.has_function('dlsym') @@ -203,8 +218,7 @@ else endif foreach header : ['sys/select.h', 'alloca.h'] - config.set10('HAVE_' + header.underscorify().to_upper(), - cc.compiles('#include <@0@>'.format(header), name : '@0@ works'.format(header))) + config.set10('HAVE_' + header.underscorify().to_upper(), cc.check_header(header)) endforeach if (cc.has_header_symbol('sys/sysmacros.h', 'major') and @@ -219,30 +233,15 @@ if (cc.has_header_symbol('sys/mkdev.h', 'major') and endif config.set10('HAVE_OPEN_MEMSTREAM', cc.has_function('open_memstream')) -warn_c_args = [] -foreach a : ['-Wall', '-Wextra', '-Wsign-compare', '-Werror=undef', - '-Werror=implicit-function-declaration', '-Wpointer-arith', - '-Wwrite-strings', '-Wstrict-prototypes', '-Wmissing-prototypes', - '-Wmissing-declarations', '-Wnested-externs', '-Wpacked', - '-Wswitch-enum', '-Wmissing-format-attribute', - '-Wstrict-aliasing=2', '-Winit-self', '-Winline', '-Wshadow', - '-Wdeclaration-after-statement', '-Wold-style-definition'] - if cc.has_argument(a) - warn_c_args += a - endif -endforeach -# GCC will never error for -Wno-*, so check for -W* then add -Wno-* to the list -# of options -foreach a : ['unused-parameter', 'attributes', 'long-long', - 'missing-field-initializers'] - if cc.has_argument('-W@0@'.format(a)) - warn_c_args += '-Wno-@0@'.format(a) - endif -endforeach - -# all c args: -libdrm_c_args = warn_c_args + ['-fvisibility=hidden'] - +libdrm_c_args = cc.get_supported_arguments([ + '-Wsign-compare', '-Werror=undef', '-Werror=implicit-function-declaration', + '-Wpointer-arith', '-Wwrite-strings', '-Wstrict-prototypes', + '-Wmissing-prototypes', '-Wmissing-declarations', '-Wnested-externs', + '-Wpacked', '-Wswitch-enum', '-Wmissing-format-attribute', + '-Wstrict-aliasing=2', '-Winit-self', '-Winline', '-Wshadow', + '-Wdeclaration-after-statement', '-Wold-style-definition', + '-Wno-unused-parameter', '-Wno-attributes', '-Wno-long-long', + '-Wno-missing-field-initializers']) dep_pciaccess = dependency('pciaccess', version : '>= 0.10', required : with_intel) dep_cunit = dependency('cunit', version : '>= 2.1', required : false) @@ -271,9 +270,7 @@ with_man_pages = get_option('man-pages') prog_rst2man = find_program('rst2man', 'rst2man.py', required: with_man_pages == 'true') with_man_pages = with_man_pages != 'false' and prog_rst2man.found() -config.set10('HAVE_VISIBILITY', - cc.compiles('''int foo_hidden(void) __attribute__((visibility(("hidden"))));''', - name : 'compiler supports __attribute__(("hidden"))')) +config.set10('HAVE_VISIBILITY', cc.has_function_attribute('visibility:hidden')) foreach t : [ [with_exynos, 'EXYNOS'], @@ -308,22 +305,23 @@ libdrm_files = [files( config_file, format_mod_static_table ] +# Build an unversioned so on android if android - libdrm = library('drm', libdrm_files, - c_args : libdrm_c_args, - dependencies : [dep_valgrind, dep_rt, dep_m], - include_directories : inc_drm, - install : true, - ) + libdrm_kw = {} else - libdrm = library('drm', libdrm_files, - c_args : libdrm_c_args, - dependencies : [dep_valgrind, dep_rt, dep_m], - include_directories : inc_drm, - install : true, - version: '2.4.0' - ) -endif + libdrm_kw = {'version' : '2.4.0'} +endif + +libdrm = library( + 'drm', + libdrm_files, + c_args : libdrm_c_args, + dependencies : [dep_valgrind, dep_rt, dep_m], + include_directories : inc_drm, + install : true, + kwargs : libdrm_kw, + gnu_symbol_visibility : 'hidden', +) test( 'core-symbols-check', @@ -340,6 +338,10 @@ ext_libdrm = declare_dependency( include_directories : [inc_root, inc_drm], ) +if meson.version().version_compare('>= 0.54.0') + meson.override_dependency('libdrm', ext_libdrm) +endif + install_headers('libsync.h', 'xf86drm.h', 'xf86drmMode.h') install_headers( 'include/drm/drm.h', 'include/drm/drm_fourcc.h', 'include/drm/drm_mode.h', @@ -358,10 +360,9 @@ if with_vmwgfx endif pkg.generate( + libdrm, name : 'libdrm', - libraries : libdrm, subdirs : ['.', 'libdrm'], - version : meson.project_version(), description : 'Userspace interface to kernel DRM services', ) @@ -403,20 +404,3 @@ if with_man_pages endif subdir('data') subdir('tests') - -message('') -message('@0@ will be compiled with:'.format(meson.project_name())) -message('') -message(' libkms @0@'.format(with_libkms)) -message(' Intel API @0@'.format(with_intel)) -message(' vmwgfx API @0@'.format(with_vmwgfx)) -message(' Radeon API @0@'.format(with_radeon)) -message(' AMDGPU API @0@'.format(with_amdgpu)) -message(' Nouveau API @0@'.format(with_nouveau)) -message(' OMAP API @0@'.format(with_omap)) -message(' EXYNOS API @0@'.format(with_exynos)) -message(' Freedreno API @0@ (kgsl: @1@)'.format(with_freedreno, with_freedreno_kgsl)) -message(' Tegra API @0@'.format(with_tegra)) -message(' VC4 API @0@'.format(with_vc4)) -message(' Etnaviv API @0@'.format(with_etnaviv)) -message('') diff --git a/nouveau/meson.build b/nouveau/meson.build index af45336c..350f34c4 100644 --- a/nouveau/meson.build +++ b/nouveau/meson.build @@ -23,6 +23,7 @@ libdrm_nouveau = library( 'drm_nouveau', [files( 'nouveau.c', 'pushbuf.c', 'bufctx.c', 'abi16.c'), config_file], c_args : libdrm_c_args, + gnu_symbol_visibility : 'hidden', include_directories : [inc_root, inc_drm], link_with : libdrm, dependencies : [dep_threads, dep_atomic_ops], @@ -35,6 +36,10 @@ ext_libdrm_nouveau = declare_dependency( include_directories : [inc_drm, include_directories('.')], ) +if meson.version().version_compare('>= 0.54.0') + meson.override_dependency('libdrm_nouveau', ext_libdrm_nouveau) +endif + install_headers('nouveau.h', subdir : 'libdrm/nouveau') install_headers( 'nvif/class.h', 'nvif/cl0080.h', 'nvif/cl9097.h', 'nvif/if0002.h', @@ -43,11 +48,9 @@ install_headers( ) pkg.generate( + libdrm_nouveau, name : 'libdrm_nouveau', - libraries : libdrm_nouveau, subdirs : ['.', 'libdrm', 'libdrm/nouveau'], - version : meson.project_version(), - requires_private : 'libdrm', description : 'Userspace interface to nouveau kernel DRM services', ) diff --git a/omap/meson.build b/omap/meson.build index bfd59f05..22159184 100644 --- a/omap/meson.build +++ b/omap/meson.build @@ -23,6 +23,7 @@ libdrm_omap = library( [files('omap_drm.c'), config_file], include_directories : [inc_root, inc_drm], c_args : libdrm_c_args, + gnu_symbol_visibility : 'hidden', link_with : libdrm, dependencies : [dep_pthread_stubs, dep_atomic_ops], version : '1.0.0', @@ -34,15 +35,18 @@ ext_libdrm_omap = declare_dependency( include_directories : [inc_drm, include_directories('.')], ) +if meson.version().version_compare('>= 0.54.0') + meson.override_dependency('libdrm_omap', ext_libdrm_omap) +endif + install_headers('omap_drmif.h', subdir : 'libdrm') install_headers('omap_drm.h', subdir : 'omap') pkg.generate( + libdrm_omap, name : 'libdrm_omap', - libraries : libdrm_omap, subdirs : ['.', 'libdrm', 'omap'], version : '0.6', - requires_private : 'libdrm', description : 'Userspace interface to omap kernel DRM services', ) diff --git a/radeon/meson.build b/radeon/meson.build index 31fe9cd0..4c1c71e0 100644 --- a/radeon/meson.build +++ b/radeon/meson.build @@ -29,6 +29,7 @@ libdrm_radeon = library( config_file, ], c_args : libdrm_c_args, + gnu_symbol_visibility : 'hidden', include_directories : [inc_root, inc_drm], link_with : libdrm, dependencies : [dep_pthread_stubs, dep_atomic_ops], @@ -41,6 +42,10 @@ ext_libdrm_radeon = declare_dependency( include_directories : [inc_drm, include_directories('.')], ) +if meson.version().version_compare('>= 0.54.0') + meson.override_dependency('libdrm_radeon', ext_libdrm_radeon) +endif + install_headers( 'radeon_bo.h', 'radeon_cs.h', 'radeon_surface.h', 'radeon_bo_gem.h', 'radeon_cs_gem.h', 'radeon_bo_int.h', 'radeon_cs_int.h', 'r600_pci_ids.h', @@ -48,11 +53,9 @@ install_headers( ) pkg.generate( + libdrm_radeon, name : 'libdrm_radeon', - libraries : libdrm_radeon, subdirs : ['.', 'libdrm'], - version : meson.project_version(), - requires_private : 'libdrm', description : 'Userspace interface to kernel DRM services for radeon', ) diff --git a/tegra/meson.build b/tegra/meson.build index edddf72b..7585c8b5 100644 --- a/tegra/meson.build +++ b/tegra/meson.build @@ -25,6 +25,7 @@ libdrm_tegra = library( link_with : libdrm, dependencies : [dep_pthread_stubs, dep_atomic_ops], c_args : libdrm_c_args, + gnu_symbol_visibility : 'hidden', version : '0.0.0', install : true, ) @@ -34,14 +35,16 @@ ext_libdrm_tegra = declare_dependency( include_directories : [inc_drm, include_directories('.')], ) +if meson.version().version_compare('>= 0.54.0') + meson.override_dependency('libdrm_tegra', ext_libdrm_tegra) +endif + install_headers('tegra.h', subdir : 'libdrm') pkg.generate( + libdrm_tegra, name : 'libdrm_tegra', - libraries : libdrm_tegra, subdirs : ['.', 'libdrm'], - version : meson.project_version(), - requires_private : 'libdrm', description : 'Userspace interface to Tegra kernel DRM services', ) diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index c4224c91..6a2ff8ba 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -65,6 +65,7 @@ #define CS_TESTS_STR "CS Tests" #define VCE_TESTS_STR "VCE Tests" #define VCN_TESTS_STR "VCN Tests" +#define JPEG_TESTS_STR "JPEG Tests" #define UVD_ENC_TESTS_STR "UVD ENC Tests" #define DEADLOCK_TESTS_STR "Deadlock Tests" #define VM_TESTS_STR "VM Tests" @@ -115,6 +116,12 @@ static CU_SuiteInfo suites[] = { .pTests = vcn_tests, }, { + .pName = JPEG_TESTS_STR, + .pInitFunc = suite_jpeg_tests_init, + .pCleanupFunc = suite_jpeg_tests_clean, + .pTests = jpeg_tests, + }, + { .pName = UVD_ENC_TESTS_STR, .pInitFunc = suite_uvd_enc_tests_init, .pCleanupFunc = suite_uvd_enc_tests_clean, @@ -194,6 +201,10 @@ static Suites_Active_Status suites_active_stat[] = { .pActive = suite_vcn_tests_enable, }, { + .pName = JPEG_TESTS_STR, + .pActive = suite_jpeg_tests_enable, + }, + { .pName = UVD_ENC_TESTS_STR, .pActive = suite_uvd_enc_tests_enable, }, diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h index cc12756d..2c43a2fa 100644 --- a/tests/amdgpu/amdgpu_test.h +++ b/tests/amdgpu/amdgpu_test.h @@ -140,6 +140,26 @@ CU_BOOL suite_vcn_tests_enable(void); extern CU_TestInfo vcn_tests[]; /** ++ * Initialize jpeg test suite ++ */ +int suite_jpeg_tests_init(); + +/** ++ * Deinitialize jpeg test suite ++ */ +int suite_jpeg_tests_clean(); + +/** + * Decide if the suite is enabled by default or not. + */ +CU_BOOL suite_jpeg_tests_enable(void); + +/** ++ * Tests in vcn test suite ++ */ +extern CU_TestInfo jpeg_tests[]; + +/** * Initialize uvd enc test suite */ int suite_uvd_enc_tests_init(); diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 0180f9ce..8afd05c1 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -62,6 +62,7 @@ static void amdgpu_compute_dispatch_test(void); static void amdgpu_gfx_dispatch_test(void); static void amdgpu_draw_test(void); static void amdgpu_gpu_reset_test(void); +static void amdgpu_stable_pstate_test(void); static void amdgpu_command_submission_write_linear_helper(unsigned ip_type); static void amdgpu_command_submission_const_fill_helper(unsigned ip_type); @@ -87,6 +88,7 @@ CU_TestInfo basic_tests[] = { { "Dispatch Test (GFX)", amdgpu_gfx_dispatch_test }, { "Draw Test", amdgpu_draw_test }, { "GPU reset Test", amdgpu_gpu_reset_test }, + { "Stable pstate Test", amdgpu_stable_pstate_test }, CU_TEST_INFO_NULL, }; #define BUFFER_SIZE (MAX2(8 * 1024, getpagesize())) @@ -3881,3 +3883,33 @@ static void amdgpu_gpu_reset_test(void) amdgpu_compute_dispatch_test(); amdgpu_gfx_dispatch_test(); } + +static void amdgpu_stable_pstate_test(void) +{ + int r; + amdgpu_context_handle context_handle; + uint32_t current_pstate = 0, new_pstate = 0; + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_stable_pstate(context_handle, + AMDGPU_CTX_OP_GET_STABLE_PSTATE, + 0, ¤t_pstate); + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL(new_pstate, AMDGPU_CTX_STABLE_PSTATE_NONE); + + r = amdgpu_cs_ctx_stable_pstate(context_handle, + AMDGPU_CTX_OP_SET_STABLE_PSTATE, + AMDGPU_CTX_STABLE_PSTATE_PEAK, NULL); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_stable_pstate(context_handle, + AMDGPU_CTX_OP_GET_STABLE_PSTATE, + 0, &new_pstate); + CU_ASSERT_EQUAL(r, 0); + CU_ASSERT_EQUAL(new_pstate, AMDGPU_CTX_STABLE_PSTATE_PEAK); + + r = amdgpu_cs_ctx_free(context_handle); + CU_ASSERT_EQUAL(r, 0); +} diff --git a/tests/amdgpu/decode_messages.h b/tests/amdgpu/decode_messages.h index ee1deb4f..218cd779 100644 --- a/tests/amdgpu/decode_messages.h +++ b/tests/amdgpu/decode_messages.h @@ -851,4 +851,31 @@ static const uint8_t feedback_msg[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, }; +static const uint8_t jpeg_bitstream[] = { + 0xFF, 0xD8, 0xFF, 0xDB, 0x01, 0x06, 0x00, 0x08, 0x04, 0x04, 0x04, 0x04, 0x04, 0x05, 0x05, 0x05, + 0x05, 0x05, 0x05, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, + 0x07, 0x07, 0x07, 0x08, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, 0x08, 0x08, 0x08, + 0x08, 0x09, 0x09, 0x09, 0x08, 0x08, 0x08, 0x08, 0x09, 0x09, 0x0A, 0x0A, 0x0A, 0x0C, 0x0C, 0x0B, + 0x0B, 0x0E, 0x0E, 0x0E, 0x11, 0x11, 0x14, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xC4, 0x00, 0x4B, 0x00, 0x01, + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xC0, 0x00, 0x11, 0x08, 0x00, 0x08, 0x00, 0x08, + 0x03, 0x00, 0x22, 0x00, 0x01, 0x11, 0x00, 0x02, 0x11, 0x00, 0xFF, 0xDA, 0x00, 0x0C, 0x03, 0x00, + 0x00, 0x01, 0x11, 0x02, 0x11, 0x00, 0x3F, 0x00, 0x9F, 0xC0, 0x07, 0xFF, 0xD9, 0xFF, 0xD9, +}; + #endif /* _DECODE_MESSAGES_H_ */ diff --git a/tests/amdgpu/jpeg_tests.c b/tests/amdgpu/jpeg_tests.c new file mode 100644 index 00000000..5e50bef6 --- /dev/null +++ b/tests/amdgpu/jpeg_tests.c @@ -0,0 +1,582 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include <inttypes.h> +#include <stdio.h> + +#include "CUnit/Basic.h" + +#include "util_math.h" + +#include "amdgpu_drm.h" +#include "amdgpu_internal.h" +#include "amdgpu_test.h" +#include "decode_messages.h" + +/* jpeg registers */ +#define mmUVD_JPEG_CNTL 0x0200 +#define mmUVD_JPEG_RB_BASE 0x0201 +#define mmUVD_JPEG_RB_WPTR 0x0202 +#define mmUVD_JPEG_RB_RPTR 0x0203 +#define mmUVD_JPEG_RB_SIZE 0x0204 +#define mmUVD_JPEG_TIER_CNTL2 0x021a +#define mmUVD_JPEG_UV_TILING_CTRL 0x021c +#define mmUVD_JPEG_TILING_CTRL 0x021e +#define mmUVD_JPEG_OUTBUF_RPTR 0x0220 +#define mmUVD_JPEG_OUTBUF_WPTR 0x0221 +#define mmUVD_JPEG_PITCH 0x0222 +#define mmUVD_JPEG_INT_EN 0x0229 +#define mmUVD_JPEG_UV_PITCH 0x022b +#define mmUVD_JPEG_INDEX 0x023e +#define mmUVD_JPEG_DATA 0x023f +#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0438 +#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0439 +#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x045a +#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x045b +#define mmUVD_CTX_INDEX 0x0528 +#define mmUVD_CTX_DATA 0x0529 +#define mmUVD_SOFT_RESET 0x05a0 + +#define vcnipUVD_JPEG_DEC_SOFT_RST 0x402f +#define vcnipUVD_JRBC_IB_COND_RD_TIMER 0x408e +#define vcnipUVD_JRBC_IB_REF_DATA 0x408f +#define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x40e1 +#define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x40e0 +#define vcnipUVD_JPEG_RB_BASE 0x4001 +#define vcnipUVD_JPEG_RB_SIZE 0x4004 +#define vcnipUVD_JPEG_RB_WPTR 0x4002 +#define vcnipUVD_JPEG_PITCH 0x401f +#define vcnipUVD_JPEG_UV_PITCH 0x4020 +#define vcnipJPEG_DEC_ADDR_MODE 0x4027 +#define vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE 0x4024 +#define vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE 0x4025 +#define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x40e3 +#define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x40e2 +#define vcnipUVD_JPEG_INDEX 0x402c +#define vcnipUVD_JPEG_DATA 0x402d +#define vcnipUVD_JPEG_TIER_CNTL2 0x400f +#define vcnipUVD_JPEG_OUTBUF_RPTR 0x401e +#define vcnipUVD_JPEG_OUTBUF_CNTL 0x401c +#define vcnipUVD_JPEG_INT_EN 0x400a +#define vcnipUVD_JPEG_CNTL 0x4000 +#define vcnipUVD_JPEG_RB_RPTR 0x4003 +#define vcnipUVD_JPEG_OUTBUF_WPTR 0x401d + + +#define RDECODE_PKT_REG_J(x) ((unsigned)(x)&0x3FFFF) +#define RDECODE_PKT_RES_J(x) (((unsigned)(x)&0x3F) << 18) +#define RDECODE_PKT_COND_J(x) (((unsigned)(x)&0xF) << 24) +#define RDECODE_PKT_TYPE_J(x) (((unsigned)(x)&0xF) << 28) +#define RDECODE_PKTJ(reg, cond, type) (RDECODE_PKT_REG_J(reg) | \ + RDECODE_PKT_RES_J(0) | \ + RDECODE_PKT_COND_J(cond) | \ + RDECODE_PKT_TYPE_J(type)) + +#define UVD_BASE_INST0_SEG1 0x00007E00 +#define SOC15_REG_ADDR(reg) (UVD_BASE_INST0_SEG1 + reg) + +#define COND0 0 +#define COND1 1 +#define COND3 3 +#define TYPE0 0 +#define TYPE1 1 +#define TYPE3 3 +#define JPEG_DEC_DT_PITCH 0x100 +#define JPEG_DEC_BSD_SIZE 0x180 +#define JPEG_DEC_LUMA_OFFSET 0 +#define JPEG_DEC_CHROMA_OFFSET 0x1000 +#define JPEG_DEC_SUM 4096 +#define IB_SIZE 4096 +#define MAX_RESOURCES 16 + +struct amdgpu_jpeg_bo { + amdgpu_bo_handle handle; + amdgpu_va_handle va_handle; + uint64_t addr; + uint64_t size; + uint8_t *ptr; +}; + +static amdgpu_device_handle device_handle; +static uint32_t major_version; +static uint32_t minor_version; +static uint32_t family_id; +static uint32_t chip_rev; +static uint32_t chip_id; +static uint32_t asic_id; +static uint32_t chip_rev; +static uint32_t chip_id; + +static amdgpu_context_handle context_handle; +static amdgpu_bo_handle ib_handle; +static amdgpu_va_handle ib_va_handle; +static uint64_t ib_mc_address; +static uint32_t *ib_cpu; +static uint32_t len; + +static amdgpu_bo_handle resources[MAX_RESOURCES]; +static unsigned num_resources; +bool jpeg_direct_reg; + +static void set_reg_jpeg(unsigned reg, unsigned cond, unsigned type, + uint32_t val); +static void send_cmd_bitstream(uint64_t addr); +static void send_cmd_target(uint64_t addr); +static void send_cmd_bitstream_direct(uint64_t addr); +static void send_cmd_target_direct(uint64_t addr); + +static void amdgpu_cs_jpeg_decode(void); + +CU_TestInfo jpeg_tests[] = { + {"JPEG decode", amdgpu_cs_jpeg_decode}, + CU_TEST_INFO_NULL, +}; + +CU_BOOL suite_jpeg_tests_enable(void) +{ + struct drm_amdgpu_info_hw_ip info; + int r; + + if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version, + &device_handle)) + return CU_FALSE; + + family_id = device_handle->info.family_id; + asic_id = device_handle->info.asic_id; + chip_rev = device_handle->info.chip_rev; + chip_id = device_handle->info.chip_external_rev; + + r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_JPEG, 0, &info); + + if (amdgpu_device_deinitialize(device_handle)) + return CU_FALSE; + + if (r != 0 || !info.available_rings || + (family_id < AMDGPU_FAMILY_RV && + (family_id == AMDGPU_FAMILY_AI && + (chip_id - chip_rev) < 0x32))) { /* Arcturus */ + printf("\n\nThe ASIC NOT support JPEG, suite disabled\n"); + return CU_FALSE; + } + + if (family_id == AMDGPU_FAMILY_RV) { + if (chip_id >= (chip_rev + 0x91)) + jpeg_direct_reg = true; + else + jpeg_direct_reg = false; + } else if (family_id == AMDGPU_FAMILY_NV) + jpeg_direct_reg = true; + else + return CU_FALSE; + + return CU_TRUE; +} + +int suite_jpeg_tests_init(void) +{ + int r; + + r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version, + &device_handle); + if (r) + return CUE_SINIT_FAILED; + + family_id = device_handle->info.family_id; + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + if (r) + return CUE_SINIT_FAILED; + + r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096, + AMDGPU_GEM_DOMAIN_GTT, 0, &ib_handle, + (void **)&ib_cpu, &ib_mc_address, &ib_va_handle); + if (r) + return CUE_SINIT_FAILED; + + return CUE_SUCCESS; +} + +int suite_jpeg_tests_clean(void) +{ + int r; + + r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, ib_mc_address, IB_SIZE); + if (r) + return CUE_SCLEAN_FAILED; + + r = amdgpu_cs_ctx_free(context_handle); + if (r) + return CUE_SCLEAN_FAILED; + + r = amdgpu_device_deinitialize(device_handle); + if (r) + return CUE_SCLEAN_FAILED; + + return CUE_SUCCESS; +} + +static int submit(unsigned ndw, unsigned ip) +{ + struct amdgpu_cs_request ibs_request = {0}; + struct amdgpu_cs_ib_info ib_info = {0}; + struct amdgpu_cs_fence fence_status = {0}; + uint32_t expired; + int r; + + ib_info.ib_mc_address = ib_mc_address; + ib_info.size = ndw; + + ibs_request.ip_type = ip; + + r = amdgpu_bo_list_create(device_handle, num_resources, resources, NULL, + &ibs_request.resources); + if (r) + return r; + + ibs_request.number_of_ibs = 1; + ibs_request.ibs = &ib_info; + ibs_request.fence_info.handle = NULL; + + r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); + if (r) + return r; + + r = amdgpu_bo_list_destroy(ibs_request.resources); + if (r) + return r; + + fence_status.context = context_handle; + fence_status.ip_type = ip; + fence_status.fence = ibs_request.seq_no; + + r = amdgpu_cs_query_fence_status(&fence_status, AMDGPU_TIMEOUT_INFINITE, 0, + &expired); + if (r) + return r; + + return 0; +} + +static void alloc_resource(struct amdgpu_jpeg_bo *jpeg_bo, unsigned size, + unsigned domain) +{ + struct amdgpu_bo_alloc_request req = {0}; + amdgpu_bo_handle buf_handle; + amdgpu_va_handle va_handle; + uint64_t va = 0; + int r; + + req.alloc_size = ALIGN(size, 4096); + req.preferred_heap = domain; + r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_va_range_alloc(device_handle, amdgpu_gpu_va_range_general, + req.alloc_size, 1, 0, &va, &va_handle, 0); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_MAP); + CU_ASSERT_EQUAL(r, 0); + jpeg_bo->addr = va; + jpeg_bo->handle = buf_handle; + jpeg_bo->size = req.alloc_size; + jpeg_bo->va_handle = va_handle; + r = amdgpu_bo_cpu_map(jpeg_bo->handle, (void **)&jpeg_bo->ptr); + CU_ASSERT_EQUAL(r, 0); + memset(jpeg_bo->ptr, 0, size); + r = amdgpu_bo_cpu_unmap(jpeg_bo->handle); + CU_ASSERT_EQUAL(r, 0); +} + +static void free_resource(struct amdgpu_jpeg_bo *jpeg_bo) +{ + int r; + + r = amdgpu_bo_va_op(jpeg_bo->handle, 0, jpeg_bo->size, jpeg_bo->addr, 0, + AMDGPU_VA_OP_UNMAP); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_va_range_free(jpeg_bo->va_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_free(jpeg_bo->handle); + CU_ASSERT_EQUAL(r, 0); + memset(jpeg_bo, 0, sizeof(*jpeg_bo)); +} + +static void set_reg_jpeg(unsigned reg, unsigned cond, unsigned type, + uint32_t val) +{ + ib_cpu[len++] = RDECODE_PKTJ(reg, cond, type); + ib_cpu[len++] = val; +} + +/* send a bitstream buffer command */ +static void send_cmd_bitstream(uint64_t addr) +{ + + /* jpeg soft reset */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 1); + + /* ensuring the Reset is asserted in SCLK domain */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C2); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0x01400200); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 9)); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9)); + + /* wait mem */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0); + + /* ensuring the Reset is de-asserted in SCLK domain */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9)); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9)); + + /* set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH), COND0, TYPE0, + (addr >> 32)); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW), COND0, TYPE0, + (unsigned int)addr); + + /* set jpeg_rb_base */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_BASE), COND0, TYPE0, 0); + + /* set jpeg_rb_base */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_SIZE), COND0, TYPE0, 0xFFFFFFF0); + + /* set jpeg_rb_wptr */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_WPTR), COND0, TYPE0, + (JPEG_DEC_BSD_SIZE >> 2)); +} + +/* send a target buffer command */ +static void send_cmd_target(uint64_t addr) +{ + + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_PITCH), COND0, TYPE0, + (JPEG_DEC_DT_PITCH >> 4)); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_UV_PITCH), COND0, TYPE0, + (JPEG_DEC_DT_PITCH >> 4)); + + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_TILING_CTRL), COND0, TYPE0, 0); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_UV_TILING_CTRL), COND0, TYPE0, 0); + + /* set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH), COND0, + TYPE0, (addr >> 32)); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW), COND0, TYPE0, + (unsigned int)addr); + + /* set output buffer data address */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_INDEX), COND0, TYPE0, 0); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_DATA), COND0, TYPE0, + JPEG_DEC_LUMA_OFFSET); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_INDEX), COND0, TYPE0, 1); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_DATA), COND0, TYPE0, + JPEG_DEC_CHROMA_OFFSET); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_TIER_CNTL2), COND0, TYPE3, 0); + + /* set output buffer read pointer */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_OUTBUF_RPTR), COND0, TYPE0, 0); + + /* enable error interrupts */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_INT_EN), COND0, TYPE0, 0xFFFFFFFE); + + /* start engine command */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0x6); + + /* wait for job completion, wait for job JBSI fetch done */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, + (JPEG_DEC_BSD_SIZE >> 2)); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C2); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0x01400200); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_RPTR), COND0, TYPE3, 0xFFFFFFFF); + + /* wait for job jpeg outbuf idle */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0xFFFFFFFF); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_OUTBUF_WPTR), COND0, TYPE3, + 0x00000001); + + /* stop engine */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0x4); + + /* asserting jpeg lmi drop */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x0005); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, + (1 << 23 | 1 << 0)); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE1, 0); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0); + + /* asserting jpeg reset */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 1); + + /* ensure reset is asserted in sclk domain */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 9)); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9)); + + /* de-assert jpeg reset */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0); + + /* ensure reset is de-asserted in sclk domain */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9)); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9)); + + /* de-asserting jpeg lmi drop */ + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x0005); + set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0); +} + +/* send a bitstream buffer command */ +static void send_cmd_bitstream_direct(uint64_t addr) +{ + + /* jpeg soft reset */ + set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 1); + + /* ensuring the Reset is asserted in SCLK domain */ + set_reg_jpeg(vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0, 0x01400200); + set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, (0x1 << 0x10)); + set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3, (0x1 << 0x10)); + + /* wait mem */ + set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 0); + + /* ensuring the Reset is de-asserted in SCLK domain */ + set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, (0 << 0x10)); + set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3, (0x1 << 0x10)); + + /* set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address */ + set_reg_jpeg(vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH, COND0, TYPE0, + (addr >> 32)); + set_reg_jpeg(vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW, COND0, TYPE0, addr); + + /* set jpeg_rb_base */ + set_reg_jpeg(vcnipUVD_JPEG_RB_BASE, COND0, TYPE0, 0); + + /* set jpeg_rb_base */ + set_reg_jpeg(vcnipUVD_JPEG_RB_SIZE, COND0, TYPE0, 0xFFFFFFF0); + + /* set jpeg_rb_wptr */ + set_reg_jpeg(vcnipUVD_JPEG_RB_WPTR, COND0, TYPE0, (JPEG_DEC_BSD_SIZE >> 2)); +} + +/* send a target buffer command */ +static void send_cmd_target_direct(uint64_t addr) +{ + + set_reg_jpeg(vcnipUVD_JPEG_PITCH, COND0, TYPE0, (JPEG_DEC_DT_PITCH >> 4)); + set_reg_jpeg(vcnipUVD_JPEG_UV_PITCH, COND0, TYPE0, (JPEG_DEC_DT_PITCH >> 4)); + + set_reg_jpeg(vcnipJPEG_DEC_ADDR_MODE, COND0, TYPE0, 0); + set_reg_jpeg(vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE, COND0, TYPE0, 0); + set_reg_jpeg(vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE, COND0, TYPE0, 0); + + /* set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address */ + set_reg_jpeg(vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH, COND0, TYPE0, + (addr >> 32)); + set_reg_jpeg(vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW, COND0, TYPE0, addr); + + /* set output buffer data address */ + set_reg_jpeg(vcnipUVD_JPEG_INDEX, COND0, TYPE0, 0); + set_reg_jpeg(vcnipUVD_JPEG_DATA, COND0, TYPE0, JPEG_DEC_LUMA_OFFSET); + set_reg_jpeg(vcnipUVD_JPEG_INDEX, COND0, TYPE0, 1); + set_reg_jpeg(vcnipUVD_JPEG_DATA, COND0, TYPE0, JPEG_DEC_CHROMA_OFFSET); + set_reg_jpeg(vcnipUVD_JPEG_TIER_CNTL2, COND0, 0, 0); + + /* set output buffer read pointer */ + set_reg_jpeg(vcnipUVD_JPEG_OUTBUF_RPTR, COND0, TYPE0, 0); + set_reg_jpeg(vcnipUVD_JPEG_OUTBUF_CNTL, COND0, TYPE0, + ((0x00001587 & (~0x00000180L)) | (0x1 << 0x7) | (0x1 << 0x6))); + + /* enable error interrupts */ + set_reg_jpeg(vcnipUVD_JPEG_INT_EN, COND0, TYPE0, 0xFFFFFFFE); + + /* start engine command */ + set_reg_jpeg(vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0xE); + + /* wait for job completion, wait for job JBSI fetch done */ + set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, + (JPEG_DEC_BSD_SIZE >> 2)); + set_reg_jpeg(vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0, 0x01400200); + set_reg_jpeg(vcnipUVD_JPEG_RB_RPTR, COND3, TYPE3, 0xFFFFFFFF); + + /* wait for job jpeg outbuf idle */ + set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, 0xFFFFFFFF); + set_reg_jpeg(vcnipUVD_JPEG_OUTBUF_WPTR, COND3, TYPE3, 0x00000001); + + /* stop engine */ + set_reg_jpeg(vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0x4); +} + +static void amdgpu_cs_jpeg_decode(void) +{ + + struct amdgpu_jpeg_bo dec_buf; + int size, r; + uint8_t *dec; + int sum = 0, i, j; + + size = 16 * 1024; /* 8K bitstream + 8K output */ + num_resources = 0; + alloc_resource(&dec_buf, size, AMDGPU_GEM_DOMAIN_VRAM); + resources[num_resources++] = dec_buf.handle; + resources[num_resources++] = ib_handle; + r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr); + CU_ASSERT_EQUAL(r, 0); + memcpy(dec_buf.ptr, jpeg_bitstream, sizeof(jpeg_bitstream)); + + len = 0; + + if (jpeg_direct_reg == true) { + send_cmd_bitstream_direct(dec_buf.addr); + send_cmd_target_direct(dec_buf.addr + (size / 2)); + } else { + send_cmd_bitstream(dec_buf.addr); + send_cmd_target(dec_buf.addr + (size / 2)); + } + + amdgpu_bo_cpu_unmap(dec_buf.handle); + r = submit(len, AMDGPU_HW_IP_VCN_JPEG); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr); + CU_ASSERT_EQUAL(r, 0); + + dec = dec_buf.ptr + (size / 2); + + /* calculate result checksum */ + for (i = 0; i < 8; i++) + for (j = 0; j < 8; j++) + sum += *((dec + JPEG_DEC_LUMA_OFFSET + i * JPEG_DEC_DT_PITCH) + j); + for (i = 0; i < 4; i++) + for (j = 0; j < 8; j++) + sum += *((dec + JPEG_DEC_CHROMA_OFFSET + i * JPEG_DEC_DT_PITCH) + j); + + amdgpu_bo_cpu_unmap(dec_buf.handle); + CU_ASSERT_EQUAL(sum, JPEG_DEC_SUM); + + free_resource(&dec_buf); +} diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build index 3a3b7601..e027bccc 100644 --- a/tests/amdgpu/meson.build +++ b/tests/amdgpu/meson.build @@ -25,7 +25,7 @@ if dep_cunit.found() 'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c', 'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c', 'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c', 'security_tests.c', - 'hotunplug_tests.c' + 'hotunplug_tests.c', 'jpeg_tests.c' ), dependencies : [dep_cunit, dep_threads, dep_atomic_ops], include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')], diff --git a/tests/amdgpu/security_tests.c b/tests/amdgpu/security_tests.c index 280e862d..e6c9f9a8 100644 --- a/tests/amdgpu/security_tests.c +++ b/tests/amdgpu/security_tests.c @@ -305,7 +305,7 @@ static void amdgpu_secure_bounce(void) /* Fill Alice with a pattern. */ for (pp = alice.bo->cpu_ptr; - pp < (typeof(pp)) alice.bo->cpu_ptr + SECURE_BUFFER_SIZE; + pp < (__typeof__(pp)) alice.bo->cpu_ptr + SECURE_BUFFER_SIZE; pp += sizeof(secure_pattern)) memcpy(pp, secure_pattern, sizeof(secure_pattern)); @@ -343,7 +343,7 @@ static void amdgpu_secure_bounce(void) /* Verify the contents of Alice. */ for (pp = alice.bo->cpu_ptr; - pp < (typeof(pp)) alice.bo->cpu_ptr + SECURE_BUFFER_SIZE; + pp < (__typeof__(pp)) alice.bo->cpu_ptr + SECURE_BUFFER_SIZE; pp += sizeof(secure_pattern)) { res = memcmp(pp, secure_pattern, sizeof(secure_pattern)); if (res) { diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c index 628b4910..15d573d3 100644 --- a/tests/amdgpu/vcn_tests.c +++ b/tests/amdgpu/vcn_tests.c @@ -142,7 +142,8 @@ CU_BOOL suite_vcn_tests_enable(void) } else if (family_id == AMDGPU_FAMILY_NV) { if (chip_id == (chip_rev + 0x28) || chip_id == (chip_rev + 0x32) || - chip_id == (chip_rev + 0x3c)) { + chip_id == (chip_rev + 0x3c) || + chip_id == (chip_rev + 0x46)) { reg.data0 = 0x10; reg.data1 = 0x11; reg.cmd = 0xf; diff --git a/tests/nouveau/threaded.c b/tests/nouveau/threaded.c index ddbac74e..eaa469e0 100644 --- a/tests/nouveau/threaded.c +++ b/tests/nouveau/threaded.c @@ -31,7 +31,7 @@ #include "xf86drm.h" #include "nouveau.h" -static typeof(ioctl) *old_ioctl; +static __typeof__(ioctl) *old_ioctl; static int failed; static int import_fd; diff --git a/util_double_list.h b/util_double_list.h index 7e48b26c..9bdca137 100644 --- a/util_double_list.h +++ b/util_double_list.h @@ -110,7 +110,7 @@ static inline void list_delinit(struct list_head *item) #ifndef container_of #define container_of(ptr, sample, member) \ (void *)((char *)(ptr) \ - - ((char *)&((typeof(sample))0)->member)) + - ((char *)&((__typeof__(sample))0)->member)) #endif #define LIST_FOR_EACH_ENTRY(pos, head, member) \ diff --git a/xf86drmMode.c b/xf86drmMode.c index 84d3c771..87e96603 100644 --- a/xf86drmMode.c +++ b/xf86drmMode.c @@ -1324,6 +1324,7 @@ struct _drmModeAtomicReqItem { uint32_t object_id; uint32_t property_id; uint64_t value; + uint32_t cursor; }; struct _drmModeAtomicReq { @@ -1379,6 +1380,8 @@ drm_public drmModeAtomicReqPtr drmModeAtomicDuplicate(drmModeAtomicReqPtr old) drm_public int drmModeAtomicMerge(drmModeAtomicReqPtr base, drmModeAtomicReqPtr augment) { + uint32_t i; + if (!base) return -EINVAL; @@ -1401,6 +1404,8 @@ drm_public int drmModeAtomicMerge(drmModeAtomicReqPtr base, memcpy(&base->items[base->cursor], augment->items, augment->cursor * sizeof(*augment->items)); + for (i = base->cursor; i < base->cursor + augment->cursor; i++) + base->items[i].cursor = i; base->cursor += augment->cursor; return 0; @@ -1446,6 +1451,7 @@ drm_public int drmModeAtomicAddProperty(drmModeAtomicReqPtr req, req->items[req->cursor].object_id = object_id; req->items[req->cursor].property_id = property_id; req->items[req->cursor].value = value; + req->items[req->cursor].cursor = req->cursor; req->cursor++; return req->cursor; @@ -1466,12 +1472,12 @@ static int sort_req_list(const void *misc, const void *other) const drmModeAtomicReqItem *first = misc; const drmModeAtomicReqItem *second = other; - if (first->object_id < second->object_id) - return -1; - else if (first->object_id > second->object_id) - return 1; + if (first->object_id != second->object_id) + return first->object_id - second->object_id; + else if (first->property_id != second->property_id) + return first->property_id - second->property_id; else - return second->property_id - first->property_id; + return first->cursor - second->cursor; } drm_public int drmModeAtomicCommit(int fd, drmModeAtomicReqPtr req, @@ -1523,6 +1529,9 @@ drm_public int drmModeAtomicCommit(int fd, drmModeAtomicReqPtr req, sorted->cursor--; } + for (i = 0; i < sorted->cursor; i++) + sorted->items[i].cursor = i; + objs_ptr = drmMalloc(atomic.count_objs * sizeof objs_ptr[0]); if (!objs_ptr) { errno = ENOMEM; |