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| author | Ashwin Natesan <ashwin.natesan@ittiam.com> | 2023-10-10 19:18:38 +0530 |
|---|---|---|
| committer | Harish Mahendrakar <harish.mahendrakar@ittiam.com> | 2023-10-10 07:07:21 -0700 |
| commit | ea694873e05631415ba7047159775a81ad4c1306 (patch) | |
| tree | f7c9616cd2487b5e8ac7c2dfa23fcb4417b0d798 | |
| parent | b5a861581ec1e47f11abb39ce3f9b49bb4c29082 (diff) | |
| download | libavc-ea694873e05631415ba7047159775a81ad4c1306.tar.gz | |
svcenc: Enabled and verified 420sp inputs
Test: svc_enc_fuzzer
| -rw-r--r-- | common/x86/svc/isvc_mem_fns_ssse3.c | 7 | ||||
| -rw-r--r-- | encoder/svc/isvce_api.c | 7 |
2 files changed, 7 insertions, 7 deletions
diff --git a/common/x86/svc/isvc_mem_fns_ssse3.c b/common/x86/svc/isvc_mem_fns_ssse3.c index 6467b8d..f6fb257 100644 --- a/common/x86/svc/isvc_mem_fns_ssse3.c +++ b/common/x86/svc/isvc_mem_fns_ssse3.c @@ -76,6 +76,13 @@ void isvc_copy_2d_ssse3(UWORD8 *pu1_dst, WORD32 i4_dst_stride, UWORD8 *pu1_src, /* all 128 bit registers are named with a suffix mxnb, where m is the */ /* number of n bits packed in the register */ + if(((i4_blk_wd % 4) != 0) || ((i4_blk_ht % 4) != 0)) + { + isvc_copy_2d(pu1_dst, i4_dst_stride, pu1_src, i4_src_stride, i4_blk_wd, i4_blk_ht); + + return; + } + if(0 == (i4_blk_wd & 31)) /* wd multiple of 32 case */ { __m128i src0_16x8b, src1_16x8b, src2_16x8b, src3_16x8b; diff --git a/encoder/svc/isvce_api.c b/encoder/svc/isvce_api.c index cc20161..2004dba 100644 --- a/encoder/svc/isvce_api.c +++ b/encoder/svc/isvce_api.c @@ -434,13 +434,6 @@ static IV_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle, void *pv_api_ip, return (IV_FAIL); } - if(ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420P) - { - ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; - ps_op->s_ive_op.u4_error_code |= IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED; - return (IV_FAIL); - } - if(ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420P) { ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |