1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
|
/*
* This file was generated automatically by gen-template.py for 'armv5te'.
*
* --> DO NOT EDIT <--
*/
/* File: armv5te/header.S */
/*
* Copyright (C) 2008 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined(WITH_JIT)
/*
* ARMv5 definitions and declarations.
*/
/*
ARM EABI general notes:
r0-r3 hold first 4 args to a method; they are not preserved across method calls
r4-r8 are available for general use
r9 is given special treatment in some situations, but not for us
r10 (sl) seems to be generally available
r11 (fp) is used by gcc (unless -fomit-frame-pointer is set)
r12 (ip) is scratch -- not preserved across method calls
r13 (sp) should be managed carefully in case a signal arrives
r14 (lr) must be preserved
r15 (pc) can be tinkered with directly
r0 holds returns of <= 4 bytes
r0-r1 hold returns of 8 bytes, low word in r0
Callee must save/restore r4+ (except r12) if it modifies them.
Stack is "full descending". Only the arguments that don't fit in the first 4
registers are placed on the stack. "sp" points at the first stacked argument
(i.e. the 5th arg).
VFP: single-precision results in s0, double-precision results in d0.
In the EABI, "sp" must be 64-bit aligned on entry to a function, and any
64-bit quantities (long long, double) must be 64-bit aligned.
*/
/*
JIT and ARM notes:
The following registers have fixed assignments:
reg nick purpose
r5 rFP interpreted frame pointer, used for accessing locals and args
r6 rSELF thread pointer
The following registers have fixed assignments in mterp but are scratch
registers in compiled code
reg nick purpose
r4 rPC interpreted program counter, used for fetching instructions
r7 rINST first 16-bit code unit of current instruction
r8 rIBASE interpreted instruction base pointer, used for computed goto
Macros are provided for common operations. Each macro MUST emit only
one instruction to make instruction-counting easier. They MUST NOT alter
unspecified registers or condition codes.
*/
/* single-purpose registers, given names for clarity */
#define rPC r4
#define rFP r5
#define rSELF r6
#define rINST r7
#define rIBASE r8
/*
* Given a frame pointer, find the stack save area.
*
* In C this is "((StackSaveArea*)(_fp) -1)".
*/
#define SAVEAREA_FROM_FP(_reg, _fpreg) \
sub _reg, _fpreg, #sizeofStackSaveArea
#define EXPORT_PC() \
str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)]
/*
* This is a #include, not a %include, because we want the C pre-processor
* to expand the macros into assembler assignment statements.
*/
#include "../../../mterp/common/asm-constants.h"
/* File: armv5te/platform.S */
/*
* ===========================================================================
* CPU-version-specific defines and utility
* ===========================================================================
*/
.global dvmCompilerTemplateStart
.type dvmCompilerTemplateStart, %function
.text
dvmCompilerTemplateStart:
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_CMP_LONG
dvmCompiler_TEMPLATE_CMP_LONG:
/* File: armv5te/TEMPLATE_CMP_LONG.S */
/*
* Compare two 64-bit values. Puts 0, 1, or -1 into the destination
* register based on the results of the comparison.
*
* We load the full values with LDM, but in practice many values could
* be resolved by only looking at the high word. This could be made
* faster or slower by splitting the LDM into a pair of LDRs.
*
* If we just wanted to set condition flags, we could do this:
* subs ip, r0, r2
* sbcs ip, r1, r3
* subeqs ip, r0, r2
* Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific
* integer value, which we can do with 2 conditional mov/mvn instructions
* (set 1, set -1; if they're equal we already have 0 in ip), giving
* us a constant 5-cycle path plus a branch at the end to the
* instruction epilogue code. The multi-compare approach below needs
* 2 or 3 cycles + branch if the high word doesn't match, 6 + branch
* in the worst case (the 64-bit values are equal).
*/
/* cmp-long vAA, vBB, vCC */
cmp r1, r3 @ compare (vBB+1, vCC+1)
blt .LTEMPLATE_CMP_LONG_less @ signed compare on high part
bgt .LTEMPLATE_CMP_LONG_greater
subs r0, r0, r2 @ r0<- r0 - r2
bxeq lr
bhi .LTEMPLATE_CMP_LONG_greater @ unsigned compare on low part
.LTEMPLATE_CMP_LONG_less:
mvn r0, #0 @ r0<- -1
bx lr
.LTEMPLATE_CMP_LONG_greater:
mov r0, #1 @ r0<- 1
bx lr
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_RETURN
dvmCompiler_TEMPLATE_RETURN:
/* File: armv5te/TEMPLATE_RETURN.S */
/*
* Unwind a frame from the Dalvik stack for compiled OP_RETURN_XXX.
* If the stored value in returnAddr
* is non-zero, the caller is compiled by the JIT thus return to the
* address in the code cache following the invoke instruction. Otherwise
* return to the special dvmJitToInterpNoChain entry point.
*/
#if defined(TEMPLATE_INLINE_PROFILING)
stmfd sp!, {r0-r2,lr} @ preserve live registers
mov r0, r6
@ r0=rSELF
mov lr, pc
ldr pc, .LdvmFastMethodTraceExit
ldmfd sp!, {r0-r2,lr} @ restore live registers
#endif
SAVEAREA_FROM_FP(r0, rFP) @ r0<- saveArea (old)
ldr r10, [r0, #offStackSaveArea_prevFrame] @ r10<- saveArea->prevFrame
ldrb r8, [rSELF, #offThread_breakFlags] @ r8<- breakFlags
ldr rPC, [r0, #offStackSaveArea_savedPc] @ rPC<- saveArea->savedPc
#if !defined(WITH_SELF_VERIFICATION)
ldr r9, [r0, #offStackSaveArea_returnAddr] @ r9<- chaining cell ret
#else
mov r9, #0 @ disable chaining
#endif
ldr r2, [r10, #(offStackSaveArea_method - sizeofStackSaveArea)]
@ r2<- method we're returning to
cmp r2, #0 @ break frame?
#if !defined(WITH_SELF_VERIFICATION)
beq 1f @ bail to interpreter
#else
blxeq lr @ punt to interpreter and compare state
#endif
ldr r1, .LdvmJitToInterpNoChainNoProfile @ defined in footer.S
mov rFP, r10 @ publish new FP
ldr r10, [r2, #offMethod_clazz] @ r10<- method->clazz
str r2, [rSELF, #offThread_method]@ self->method = newSave->method
ldr r0, [r10, #offClassObject_pDvmDex] @ r0<- method->clazz->pDvmDex
str rFP, [rSELF, #offThread_curFrame] @ curFrame = fp
add rPC, rPC, #6 @ publish new rPC (advance 6 bytes)
str r0, [rSELF, #offThread_methodClassDex]
cmp r8, #0 @ check the break flags
movne r9, #0 @ clear the chaining cell address
str r9, [rSELF, #offThread_inJitCodeCache] @ in code cache or not
cmp r9, #0 @ chaining cell exists?
blxne r9 @ jump to the chaining cell
#if defined(WITH_JIT_TUNING)
mov r0, #kCallsiteInterpreted
#endif
mov pc, r1 @ callsite is interpreted
1:
mov r0, #0
str r0, [rSELF, #offThread_inJitCodeCache] @ reset inJitCodeCache
stmia rSELF, {rPC, rFP} @ SAVE_PC_FP_TO_SELF()
ldr r2, .LdvmMterpStdBail @ defined in footer.S
mov r0, rSELF @ Expecting rSELF in r0
blx r2 @ exit the interpreter
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_INVOKE_METHOD_NO_OPT
dvmCompiler_TEMPLATE_INVOKE_METHOD_NO_OPT:
/* File: armv5te/TEMPLATE_INVOKE_METHOD_NO_OPT.S */
/*
* For polymorphic callsites - setup the Dalvik frame and load Dalvik PC
* into rPC then jump to dvmJitToInterpNoChain to dispatch the
* runtime-resolved callee.
*/
@ r0 = methodToCall, r1 = returnCell, rPC = dalvikCallsite
ldrh r7, [r0, #offMethod_registersSize] @ r7<- methodToCall->regsSize
ldrh r2, [r0, #offMethod_outsSize] @ r2<- methodToCall->outsSize
ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd
ldrb r8, [rSELF, #offThread_breakFlags] @ r8<- breakFlags
add r3, r1, #1 @ Thumb addr is odd
SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area
sub r1, r1, r7, lsl #2 @ r1<- newFp (old savearea - regsSize)
SAVEAREA_FROM_FP(r10, r1) @ r10<- stack save area
sub r10, r10, r2, lsl #2 @ r10<- bottom (newsave - outsSize)
cmp r10, r9 @ bottom < interpStackEnd?
bxlo lr @ return to raise stack overflow excep.
@ r1 = newFP, r0 = methodToCall, r3 = returnCell, rPC = dalvikCallsite
ldr r9, [r0, #offMethod_clazz] @ r9<- method->clazz
ldr r10, [r0, #offMethod_accessFlags] @ r10<- methodToCall->accessFlags
str rPC, [rFP, #(offStackSaveArea_currentPc - sizeofStackSaveArea)]
str rPC, [r1, #(offStackSaveArea_savedPc - sizeofStackSaveArea)]
ldr rPC, [r0, #offMethod_insns] @ rPC<- methodToCall->insns
@ set up newSaveArea
str rFP, [r1, #(offStackSaveArea_prevFrame - sizeofStackSaveArea)]
str r3, [r1, #(offStackSaveArea_returnAddr - sizeofStackSaveArea)]
str r0, [r1, #(offStackSaveArea_method - sizeofStackSaveArea)]
cmp r8, #0 @ breakFlags != 0
bxne lr @ bail to the interpreter
tst r10, #ACC_NATIVE
#if !defined(WITH_SELF_VERIFICATION)
bne .LinvokeNative
#else
bxne lr @ bail to the interpreter
#endif
ldr r10, .LdvmJitToInterpTraceSelectNoChain
ldr r3, [r9, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex
@ Update "thread" values for the new method
str r0, [rSELF, #offThread_method] @ self->method = methodToCall
str r3, [rSELF, #offThread_methodClassDex] @ self->methodClassDex = ...
mov rFP, r1 @ fp = newFp
str rFP, [rSELF, #offThread_curFrame] @ curFrame = newFp
#if defined(TEMPLATE_INLINE_PROFILING)
stmfd sp!, {r0-r3} @ preserve r0-r3
mov r1, r6
@ r0=methodToCall, r1=rSELF
mov lr, pc
ldr pc, .LdvmFastMethodTraceEnter
ldmfd sp!, {r0-r3} @ restore r0-r3
#endif
@ Start executing the callee
#if defined(WITH_JIT_TUNING)
mov r0, #kInlineCacheMiss
#endif
mov pc, r10 @ dvmJitToInterpTraceSelectNoChain
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_INVOKE_METHOD_CHAIN
dvmCompiler_TEMPLATE_INVOKE_METHOD_CHAIN:
/* File: armv5te/TEMPLATE_INVOKE_METHOD_CHAIN.S */
/*
* For monomorphic callsite, setup the Dalvik frame and return to the
* Thumb code through the link register to transfer control to the callee
* method through a dedicated chaining cell.
*/
@ r0 = methodToCall, r1 = returnCell, r2 = methodToCall->outsSize
@ rPC = dalvikCallsite, r7 = methodToCall->registersSize
@ methodToCall is guaranteed to be non-native
.LinvokeChain:
ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd
ldrb r8, [rSELF, #offThread_breakFlags] @ r8<- breakFlags
add r3, r1, #1 @ Thumb addr is odd
SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area
sub r1, r1, r7, lsl #2 @ r1<- newFp (old savearea - regsSize)
SAVEAREA_FROM_FP(r10, r1) @ r10<- stack save area
add r12, lr, #2 @ setup the punt-to-interp address
sub r10, r10, r2, lsl #2 @ r10<- bottom (newsave - outsSize)
cmp r10, r9 @ bottom < interpStackEnd?
bxlo r12 @ return to raise stack overflow excep.
@ r1 = newFP, r0 = methodToCall, r3 = returnCell, rPC = dalvikCallsite
ldr r9, [r0, #offMethod_clazz] @ r9<- method->clazz
str rPC, [rFP, #(offStackSaveArea_currentPc - sizeofStackSaveArea)]
str rPC, [r1, #(offStackSaveArea_savedPc - sizeofStackSaveArea)]
@ set up newSaveArea
str rFP, [r1, #(offStackSaveArea_prevFrame - sizeofStackSaveArea)]
str r3, [r1, #(offStackSaveArea_returnAddr - sizeofStackSaveArea)]
str r0, [r1, #(offStackSaveArea_method - sizeofStackSaveArea)]
cmp r8, #0 @ breakFlags != 0
bxne r12 @ bail to the interpreter
ldr r3, [r9, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex
@ Update "thread" values for the new method
str r0, [rSELF, #offThread_method] @ self->method = methodToCall
str r3, [rSELF, #offThread_methodClassDex] @ self->methodClassDex = ...
mov rFP, r1 @ fp = newFp
str rFP, [rSELF, #offThread_curFrame] @ curFrame = newFp
#if defined(TEMPLATE_INLINE_PROFILING)
stmfd sp!, {r0-r2,lr} @ preserve clobbered live registers
mov r1, r6
@ r0=methodToCall, r1=rSELF
mov lr, pc
ldr pc, .LdvmFastMethodTraceEnter
ldmfd sp!, {r0-r2,lr} @ restore registers
#endif
bx lr @ return to the callee-chaining cell
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN
dvmCompiler_TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN:
/* File: armv5te/TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN.S */
/*
* For polymorphic callsite, check whether the cached class pointer matches
* the current one. If so setup the Dalvik frame and return to the
* Thumb code through the link register to transfer control to the callee
* method through a dedicated chaining cell.
*
* The predicted chaining cell is declared in ArmLIR.h with the
* following layout:
*
* typedef struct PredictedChainingCell {
* u4 branch;
* const ClassObject *clazz;
* const Method *method;
* u4 counter;
* } PredictedChainingCell;
*
* Upon returning to the callsite:
* - lr : to branch to the chaining cell
* - lr+2: to punt to the interpreter
* - lr+4: to fully resolve the callee and may rechain.
* r3 <- class
* r9 <- counter
*/
@ r0 = this, r1 = returnCell, r2 = predictedChainCell, rPC = dalvikCallsite
ldr r3, [r0, #offObject_clazz] @ r3 <- this->class
ldr r8, [r2, #4] @ r8 <- predictedChainCell->clazz
ldr r0, [r2, #8] @ r0 <- predictedChainCell->method
ldr r9, [rSELF, #offThread_icRechainCount] @ r1 <- shared rechainCount
cmp r3, r8 @ predicted class == actual class?
#if defined(WITH_JIT_TUNING)
ldr r7, .LdvmICHitCount
#if defined(WORKAROUND_CORTEX_A9_745320)
/* Don't use conditional loads if the HW defect exists */
bne 101f
ldr r10, [r7, #0]
101:
#else
ldreq r10, [r7, #0]
#endif
add r10, r10, #1
streq r10, [r7, #0]
#endif
ldreqh r7, [r0, #offMethod_registersSize] @ r7<- methodToCall->regsSize
ldreqh r2, [r0, #offMethod_outsSize] @ r2<- methodToCall->outsSize
beq .LinvokeChain @ predicted chain is valid
ldr r7, [r3, #offClassObject_vtable] @ r7 <- this->class->vtable
cmp r8, #0 @ initialized class or not
moveq r1, #0
subne r1, r9, #1 @ count--
strne r1, [rSELF, #offThread_icRechainCount] @ write back to thread
add lr, lr, #4 @ return to fully-resolve landing pad
/*
* r1 <- count
* r2 <- &predictedChainCell
* r3 <- this->class
* r4 <- dPC
* r7 <- this->class->vtable
*/
bx lr
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_INVOKE_METHOD_NATIVE
dvmCompiler_TEMPLATE_INVOKE_METHOD_NATIVE:
/* File: armv5te/TEMPLATE_INVOKE_METHOD_NATIVE.S */
@ r0 = methodToCall, r1 = returnCell, rPC = dalvikCallsite
@ r7 = methodToCall->registersSize
ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd
ldrb r8, [rSELF, #offThread_breakFlags] @ r8<- breakFlags
add r3, r1, #1 @ Thumb addr is odd
SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area
sub r1, r1, r7, lsl #2 @ r1<- newFp (old savearea - regsSize)
SAVEAREA_FROM_FP(r10, r1) @ r10<- stack save area
cmp r10, r9 @ bottom < interpStackEnd?
bxlo lr @ return to raise stack overflow excep.
@ r1 = newFP, r0 = methodToCall, r3 = returnCell, rPC = dalvikCallsite
str rPC, [rFP, #(offStackSaveArea_currentPc - sizeofStackSaveArea)]
str rPC, [r1, #(offStackSaveArea_savedPc - sizeofStackSaveArea)]
@ set up newSaveArea
str rFP, [r1, #(offStackSaveArea_prevFrame - sizeofStackSaveArea)]
str r3, [r1, #(offStackSaveArea_returnAddr - sizeofStackSaveArea)]
str r0, [r1, #(offStackSaveArea_method - sizeofStackSaveArea)]
cmp r8, #0 @ breakFlags != 0
ldr r8, [r0, #offMethod_nativeFunc] @ r8<- method->nativeFunc
#if !defined(WITH_SELF_VERIFICATION)
bxne lr @ bail to the interpreter
#else
bx lr @ bail to interpreter unconditionally
#endif
@ go ahead and transfer control to the native code
ldr r9, [rSELF, #offThread_jniLocal_topCookie]@r9<-thread->localRef->...
mov r2, #0
str r1, [rSELF, #offThread_curFrame] @ curFrame = newFp
str r2, [rSELF, #offThread_inJitCodeCache] @ not in the jit code cache
str r9, [r1, #(offStackSaveArea_localRefCookie - sizeofStackSaveArea)]
@ newFp->localRefCookie=top
SAVEAREA_FROM_FP(r10, r1) @ r10<- new stack save area
mov r2, r0 @ arg2<- methodToCall
mov r0, r1 @ arg0<- newFP
add r1, rSELF, #offThread_retval @ arg1<- &retval
mov r3, rSELF @ arg3<- self
#if defined(TEMPLATE_INLINE_PROFILING)
@ r2=methodToCall, r6=rSELF
stmfd sp!, {r2,r6} @ to be consumed after JNI return
stmfd sp!, {r0-r3} @ preserve r0-r3
mov r0, r2
mov r1, r6
@ r0=JNIMethod, r1=rSELF
mov lr, pc
ldr pc, .LdvmFastMethodTraceEnter
ldmfd sp!, {r0-r3} @ restore r0-r3
#endif
blx r8 @ off to the native code
#if defined(TEMPLATE_INLINE_PROFILING)
ldmfd sp!, {r0-r1} @ restore r2 and r6
@ r0=JNIMethod, r1=rSELF
mov lr, pc
ldr pc, .LdvmFastNativeMethodTraceExit
#endif
@ native return; r10=newSaveArea
@ equivalent to dvmPopJniLocals
ldr r2, [r10, #offStackSaveArea_returnAddr] @ r2 = chaining cell ret
ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved->top
ldr r1, [rSELF, #offThread_exception] @ check for exception
str rFP, [rSELF, #offThread_curFrame] @ curFrame = fp
cmp r1, #0 @ null?
str r0, [rSELF, #offThread_jniLocal_topCookie] @ new top <- old top
ldr r0, [rFP, #(offStackSaveArea_currentPc - sizeofStackSaveArea)]
@ r0 = dalvikCallsitePC
bne .LhandleException @ no, handle exception
str r2, [rSELF, #offThread_inJitCodeCache] @ set the mode properly
cmp r2, #0 @ return chaining cell still exists?
bxne r2 @ yes - go ahead
@ continue executing the next instruction through the interpreter
ldr r1, .LdvmJitToInterpTraceSelectNoChain @ defined in footer.S
add rPC, r0, #6 @ reconstruct new rPC (advance 6 bytes)
#if defined(WITH_JIT_TUNING)
mov r0, #kCallsiteInterpreted
#endif
mov pc, r1
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_CMPG_DOUBLE
dvmCompiler_TEMPLATE_CMPG_DOUBLE:
/* File: armv5te/TEMPLATE_CMPG_DOUBLE.S */
/* File: armv5te/TEMPLATE_CMPL_DOUBLE.S */
/*
* For the JIT: incoming arguments in r0-r1, r2-r3
* result in r0
*
* Compare two floating-point values. Puts 0, 1, or -1 into the
* destination register based on the results of the comparison.
*
* Provide a "naninst" instruction that puts 1 or -1 into r1 depending
* on what value we'd like to return when one of the operands is NaN.
*
* See OP_CMPL_FLOAT for an explanation.
*
* For: cmpl-double, cmpg-double
*/
/* op vAA, vBB, vCC */
push {r0-r3} @ save operands
mov r11, lr @ save return address
mov lr, pc
ldr pc, .L__aeabi_cdcmple @ PIC way of "bl __aeabi_cdcmple"
bhi .LTEMPLATE_CMPG_DOUBLE_gt_or_nan @ C set and Z clear, disambiguate
mvncc r0, #0 @ (less than) r1<- -1
moveq r0, #0 @ (equal) r1<- 0, trumps less than
add sp, #16 @ drop unused operands
bx r11
@ Test for NaN with a second comparison. EABI forbids testing bit
@ patterns, and we can't represent 0x7fc00000 in immediate form, so
@ make the library call.
.LTEMPLATE_CMPG_DOUBLE_gt_or_nan:
pop {r2-r3} @ restore operands in reverse order
pop {r0-r1} @ restore operands in reverse order
mov lr, pc
ldr pc, .L__aeabi_cdcmple @ r0<- Z set if eq, C clear if <
movcc r0, #1 @ (greater than) r1<- 1
bxcc r11
mov r0, #1 @ r1<- 1 or -1 for NaN
bx r11
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_CMPL_DOUBLE
dvmCompiler_TEMPLATE_CMPL_DOUBLE:
/* File: armv5te/TEMPLATE_CMPL_DOUBLE.S */
/*
* For the JIT: incoming arguments in r0-r1, r2-r3
* result in r0
*
* Compare two floating-point values. Puts 0, 1, or -1 into the
* destination register based on the results of the comparison.
*
* Provide a "naninst" instruction that puts 1 or -1 into r1 depending
* on what value we'd like to return when one of the operands is NaN.
*
* See OP_CMPL_FLOAT for an explanation.
*
* For: cmpl-double, cmpg-double
*/
/* op vAA, vBB, vCC */
push {r0-r3} @ save operands
mov r11, lr @ save return address
mov lr, pc
ldr pc, .L__aeabi_cdcmple @ PIC way of "bl __aeabi_cdcmple"
bhi .LTEMPLATE_CMPL_DOUBLE_gt_or_nan @ C set and Z clear, disambiguate
mvncc r0, #0 @ (less than) r1<- -1
moveq r0, #0 @ (equal) r1<- 0, trumps less than
add sp, #16 @ drop unused operands
bx r11
@ Test for NaN with a second comparison. EABI forbids testing bit
@ patterns, and we can't represent 0x7fc00000 in immediate form, so
@ make the library call.
.LTEMPLATE_CMPL_DOUBLE_gt_or_nan:
pop {r2-r3} @ restore operands in reverse order
pop {r0-r1} @ restore operands in reverse order
mov lr, pc
ldr pc, .L__aeabi_cdcmple @ r0<- Z set if eq, C clear if <
movcc r0, #1 @ (greater than) r1<- 1
bxcc r11
mvn r0, #0 @ r1<- 1 or -1 for NaN
bx r11
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_CMPG_FLOAT
dvmCompiler_TEMPLATE_CMPG_FLOAT:
/* File: armv5te/TEMPLATE_CMPG_FLOAT.S */
/* File: armv5te/TEMPLATE_CMPL_FLOAT.S */
/*
* For the JIT: incoming arguments in r0-r1, r2-r3
* result in r0
*
* Compare two floating-point values. Puts 0, 1, or -1 into the
* destination register based on the results of the comparison.
*
* Provide a "naninst" instruction that puts 1 or -1 into r1 depending
* on what value we'd like to return when one of the operands is NaN.
*
* The operation we're implementing is:
* if (x == y)
* return 0;
* else if (x < y)
* return -1;
* else if (x > y)
* return 1;
* else
* return {-1,1}; // one or both operands was NaN
*
* The straightforward implementation requires 3 calls to functions
* that return a result in r0. We can do it with two calls if our
* EABI library supports __aeabi_cfcmple (only one if we want to check
* for NaN directly):
* check x <= y
* if <, return -1
* if ==, return 0
* check y <= x
* if <, return 1
* return {-1,1}
*
* for: cmpl-float, cmpg-float
*/
/* op vAA, vBB, vCC */
mov r9, r0 @ Save copies - we may need to redo
mov r10, r1
mov r11, lr @ save return address
mov lr, pc
ldr pc, .L__aeabi_cfcmple @ cmp <=: C clear if <, Z set if eq
bhi .LTEMPLATE_CMPG_FLOAT_gt_or_nan @ C set and Z clear, disambiguate
mvncc r0, #0 @ (less than) r0<- -1
moveq r0, #0 @ (equal) r0<- 0, trumps less than
bx r11
@ Test for NaN with a second comparison. EABI forbids testing bit
@ patterns, and we can't represent 0x7fc00000 in immediate form, so
@ make the library call.
.LTEMPLATE_CMPG_FLOAT_gt_or_nan:
mov r0, r10 @ restore in reverse order
mov r1, r9
mov lr, pc
ldr pc, .L__aeabi_cfcmple @ r0<- Z set if eq, C clear if <
movcc r0, #1 @ (greater than) r1<- 1
bxcc r11
mov r0, #1 @ r1<- 1 or -1 for NaN
bx r11
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_CMPL_FLOAT
dvmCompiler_TEMPLATE_CMPL_FLOAT:
/* File: armv5te/TEMPLATE_CMPL_FLOAT.S */
/*
* For the JIT: incoming arguments in r0-r1, r2-r3
* result in r0
*
* Compare two floating-point values. Puts 0, 1, or -1 into the
* destination register based on the results of the comparison.
*
* Provide a "naninst" instruction that puts 1 or -1 into r1 depending
* on what value we'd like to return when one of the operands is NaN.
*
* The operation we're implementing is:
* if (x == y)
* return 0;
* else if (x < y)
* return -1;
* else if (x > y)
* return 1;
* else
* return {-1,1}; // one or both operands was NaN
*
* The straightforward implementation requires 3 calls to functions
* that return a result in r0. We can do it with two calls if our
* EABI library supports __aeabi_cfcmple (only one if we want to check
* for NaN directly):
* check x <= y
* if <, return -1
* if ==, return 0
* check y <= x
* if <, return 1
* return {-1,1}
*
* for: cmpl-float, cmpg-float
*/
/* op vAA, vBB, vCC */
mov r9, r0 @ Save copies - we may need to redo
mov r10, r1
mov r11, lr @ save return address
mov lr, pc
ldr pc, .L__aeabi_cfcmple @ cmp <=: C clear if <, Z set if eq
bhi .LTEMPLATE_CMPL_FLOAT_gt_or_nan @ C set and Z clear, disambiguate
mvncc r0, #0 @ (less than) r0<- -1
moveq r0, #0 @ (equal) r0<- 0, trumps less than
bx r11
@ Test for NaN with a second comparison. EABI forbids testing bit
@ patterns, and we can't represent 0x7fc00000 in immediate form, so
@ make the library call.
.LTEMPLATE_CMPL_FLOAT_gt_or_nan:
mov r0, r10 @ restore in reverse order
mov r1, r9
mov lr, pc
ldr pc, .L__aeabi_cfcmple @ r0<- Z set if eq, C clear if <
movcc r0, #1 @ (greater than) r1<- 1
bxcc r11
mvn r0, #0 @ r1<- 1 or -1 for NaN
bx r11
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_MUL_LONG
dvmCompiler_TEMPLATE_MUL_LONG:
/* File: armv5te/TEMPLATE_MUL_LONG.S */
/*
* Signed 64-bit integer multiply.
*
* For JIT: op1 in r0/r1, op2 in r2/r3, return in r0/r1
*
* Consider WXxYZ (r1r0 x r3r2) with a long multiply:
* WX
* x YZ
* --------
* ZW ZX
* YW YX
*
* The low word of the result holds ZX, the high word holds
* (ZW+YX) + (the high overflow from ZX). YW doesn't matter because
* it doesn't fit in the low 64 bits.
*
* Unlike most ARM math operations, multiply instructions have
* restrictions on using the same register more than once (Rd and Rm
* cannot be the same).
*/
/* mul-long vAA, vBB, vCC */
mul ip, r2, r1 @ ip<- ZxW
umull r9, r10, r2, r0 @ r9/r10 <- ZxX
mla r2, r0, r3, ip @ r2<- YxX + (ZxW)
add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX))
mov r0,r9
mov r1,r10
bx lr
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_SHL_LONG
dvmCompiler_TEMPLATE_SHL_LONG:
/* File: armv5te/TEMPLATE_SHL_LONG.S */
/*
* Long integer shift. This is different from the generic 32/64-bit
* binary operations because vAA/vBB are 64-bit but vCC (the shift
* distance) is 32-bit. Also, Dalvik requires us to ignore all but the low
* 6 bits.
*/
/* shl-long vAA, vBB, vCC */
and r2, r2, #63 @ r2<- r2 & 0x3f
mov r1, r1, asl r2 @ r1<- r1 << r2
rsb r3, r2, #32 @ r3<- 32 - r2
orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
subs ip, r2, #32 @ ip<- r2 - 32
movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32)
mov r0, r0, asl r2 @ r0<- r0 << r2
bx lr
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_SHR_LONG
dvmCompiler_TEMPLATE_SHR_LONG:
/* File: armv5te/TEMPLATE_SHR_LONG.S */
/*
* Long integer shift. This is different from the generic 32/64-bit
* binary operations because vAA/vBB are 64-bit but vCC (the shift
* distance) is 32-bit. Also, Dalvik requires us to ignore all but the low
* 6 bits.
*/
/* shr-long vAA, vBB, vCC */
and r2, r2, #63 @ r0<- r0 & 0x3f
mov r0, r0, lsr r2 @ r0<- r2 >> r2
rsb r3, r2, #32 @ r3<- 32 - r2
orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
subs ip, r2, #32 @ ip<- r2 - 32
movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
mov r1, r1, asr r2 @ r1<- r1 >> r2
bx lr
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_USHR_LONG
dvmCompiler_TEMPLATE_USHR_LONG:
/* File: armv5te/TEMPLATE_USHR_LONG.S */
/*
* Long integer shift. This is different from the generic 32/64-bit
* binary operations because vAA/vBB are 64-bit but vCC (the shift
* distance) is 32-bit. Also, Dalvik requires us to ignore all but the low
* 6 bits.
*/
/* ushr-long vAA, vBB, vCC */
and r2, r2, #63 @ r0<- r0 & 0x3f
mov r0, r0, lsr r2 @ r0<- r2 >> r2
rsb r3, r2, #32 @ r3<- 32 - r2
orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
subs ip, r2, #32 @ ip<- r2 - 32
movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
mov r1, r1, lsr r2 @ r1<- r1 >>> r2
bx lr
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_THROW_EXCEPTION_COMMON
dvmCompiler_TEMPLATE_THROW_EXCEPTION_COMMON:
/* File: armv5te/TEMPLATE_THROW_EXCEPTION_COMMON.S */
/*
* Throw an exception from JIT'ed code.
* On entry:
* r0 Dalvik PC that raises the exception
*/
b .LhandleException
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_MEM_OP_DECODE
dvmCompiler_TEMPLATE_MEM_OP_DECODE:
/* File: armv5te/TEMPLATE_MEM_OP_DECODE.S */
#if defined(WITH_SELF_VERIFICATION)
/*
* This handler encapsulates heap memory ops for selfVerification mode.
*
* The call to the handler is inserted prior to a heap memory operation.
* This handler then calls a function to decode the memory op, and process
* it accordingly. Afterwards, the handler changes the return address to
* skip the memory op so it never gets executed.
*/
push {r0-r12,lr} @ save out all registers
ldr r2, .LdvmSelfVerificationMemOpDecode @ defined in footer.S
mov r0, lr @ arg0 <- link register
mov r1, sp @ arg1 <- stack pointer
blx r2 @ decode and handle the mem op
pop {r0-r12,lr} @ restore all registers
bx lr @ return to compiled code
#endif
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_STRING_COMPARETO
dvmCompiler_TEMPLATE_STRING_COMPARETO:
/* File: armv5te/TEMPLATE_STRING_COMPARETO.S */
/*
* String's compareTo.
*
* Requires r0/r1 to have been previously checked for null. Will
* return negative if this's string is < comp, 0 if they are the
* same and positive if >.
*
* IMPORTANT NOTE:
*
* This code relies on hard-coded offsets for string objects, and must be
* kept in sync with definitions in UtfString.h. See asm-constants.h
*
* On entry:
* r0: this object pointer
* r1: comp object pointer
*
*/
mov r2, r0 @ this to r2, opening up r0 for return value
subs r0, r2, r1 @ Same?
bxeq lr
ldr r4, [r2, #STRING_FIELDOFF_OFFSET]
ldr r9, [r1, #STRING_FIELDOFF_OFFSET]
ldr r7, [r2, #STRING_FIELDOFF_COUNT]
ldr r10, [r1, #STRING_FIELDOFF_COUNT]
ldr r2, [r2, #STRING_FIELDOFF_VALUE]
ldr r1, [r1, #STRING_FIELDOFF_VALUE]
/*
* At this point, we have:
* value: r2/r1
* offset: r4/r9
* count: r7/r10
* We're going to compute
* r11 <- countDiff
* r10 <- minCount
*/
subs r11, r7, r10
movls r10, r7
/* Now, build pointers to the string data */
add r2, r2, r4, lsl #1
add r1, r1, r9, lsl #1
/*
* Note: data pointers point to previous element so we can use pre-index
* mode with base writeback.
*/
add r2, #16-2 @ offset to contents[-1]
add r1, #16-2 @ offset to contents[-1]
/*
* At this point we have:
* r2: *this string data
* r1: *comp string data
* r10: iteration count for comparison
* r11: value to return if the first part of the string is equal
* r0: reserved for result
* r3, r4, r7, r8, r9, r12 available for loading string data
*/
subs r10, #2
blt do_remainder2
/*
* Unroll the first two checks so we can quickly catch early mismatch
* on long strings (but preserve incoming alignment)
*/
ldrh r3, [r2, #2]!
ldrh r4, [r1, #2]!
ldrh r7, [r2, #2]!
ldrh r8, [r1, #2]!
subs r0, r3, r4
subeqs r0, r7, r8
bxne lr
cmp r10, #28
bgt do_memcmp16
subs r10, #3
blt do_remainder
loopback_triple:
ldrh r3, [r2, #2]!
ldrh r4, [r1, #2]!
ldrh r7, [r2, #2]!
ldrh r8, [r1, #2]!
ldrh r9, [r2, #2]!
ldrh r12,[r1, #2]!
subs r0, r3, r4
subeqs r0, r7, r8
subeqs r0, r9, r12
bxne lr
subs r10, #3
bge loopback_triple
do_remainder:
adds r10, #3
beq returnDiff
loopback_single:
ldrh r3, [r2, #2]!
ldrh r4, [r1, #2]!
subs r0, r3, r4
bxne lr
subs r10, #1
bne loopback_single
returnDiff:
mov r0, r11
bx lr
do_remainder2:
adds r10, #2
bne loopback_single
mov r0, r11
bx lr
/* Long string case */
do_memcmp16:
mov r4, lr
ldr lr, .Lmemcmp16
mov r7, r11
add r0, r2, #2
add r1, r1, #2
mov r2, r10
blx lr
cmp r0, #0
bxne r4
mov r0, r7
bx r4
.Lmemcmp16:
.word __memcmp16
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_STRING_INDEXOF
dvmCompiler_TEMPLATE_STRING_INDEXOF:
/* File: armv5te/TEMPLATE_STRING_INDEXOF.S */
/*
* String's indexOf.
*
* Requires r0 to have been previously checked for null. Will
* return index of match of r1 in r0.
*
* IMPORTANT NOTE:
*
* This code relies on hard-coded offsets for string objects, and must be
* kept in sync wth definitions in UtfString.h See asm-constants.h
*
* On entry:
* r0: string object pointer
* r1: char to match
* r2: Starting offset in string data
*/
ldr r7, [r0, #STRING_FIELDOFF_OFFSET]
ldr r8, [r0, #STRING_FIELDOFF_COUNT]
ldr r0, [r0, #STRING_FIELDOFF_VALUE]
/*
* At this point, we have:
* r0: object pointer
* r1: char to match
* r2: starting offset
* r7: offset
* r8: string length
*/
/* Build pointer to start of string data */
add r0, #16
add r0, r0, r7, lsl #1
/* Save a copy of starting data in r7 */
mov r7, r0
/* Clamp start to [0..count] */
cmp r2, #0
movlt r2, #0
cmp r2, r8
movgt r2, r8
/* Build pointer to start of data to compare and pre-bias */
add r0, r0, r2, lsl #1
sub r0, #2
/* Compute iteration count */
sub r8, r2
/*
* At this point we have:
* r0: start of data to test
* r1: chat to compare
* r8: iteration count
* r7: original start of string
* r3, r4, r9, r10, r11, r12 available for loading string data
*/
subs r8, #4
blt indexof_remainder
indexof_loop4:
ldrh r3, [r0, #2]!
ldrh r4, [r0, #2]!
ldrh r10, [r0, #2]!
ldrh r11, [r0, #2]!
cmp r3, r1
beq match_0
cmp r4, r1
beq match_1
cmp r10, r1
beq match_2
cmp r11, r1
beq match_3
subs r8, #4
bge indexof_loop4
indexof_remainder:
adds r8, #4
beq indexof_nomatch
indexof_loop1:
ldrh r3, [r0, #2]!
cmp r3, r1
beq match_3
subs r8, #1
bne indexof_loop1
indexof_nomatch:
mov r0, #-1
bx lr
match_0:
sub r0, #6
sub r0, r7
asr r0, r0, #1
bx lr
match_1:
sub r0, #4
sub r0, r7
asr r0, r0, #1
bx lr
match_2:
sub r0, #2
sub r0, r7
asr r0, r0, #1
bx lr
match_3:
sub r0, r7
asr r0, r0, #1
bx lr
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_INTERPRET
dvmCompiler_TEMPLATE_INTERPRET:
/* File: armv5te/TEMPLATE_INTERPRET.S */
/*
* This handler transfers control to the interpeter without performing
* any lookups. It may be called either as part of a normal chaining
* operation, or from the transition code in header.S. We distinquish
* the two cases by looking at the link register. If called from a
* translation chain, it will point to the chaining Dalvik PC -3.
* On entry:
* lr - if NULL:
* r1 - the Dalvik PC to begin interpretation.
* else
* [lr, #3] contains Dalvik PC to begin interpretation
* rSELF - pointer to thread
* rFP - Dalvik frame pointer
*/
cmp lr, #0
#if defined(WORKAROUND_CORTEX_A9_745320)
/* Don't use conditional loads if the HW defect exists */
beq 101f
ldr r1,[lr, #3]
101:
#else
ldrne r1,[lr, #3]
#endif
ldr r2, .LinterpPunt
mov r0, r1 @ set Dalvik PC
bx r2
@ doesn't return
.LinterpPunt:
.word dvmJitToInterpPunt
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_MONITOR_ENTER
dvmCompiler_TEMPLATE_MONITOR_ENTER:
/* File: armv5te/TEMPLATE_MONITOR_ENTER.S */
/*
* Call out to the runtime to lock an object. Because this thread
* may have been suspended in THREAD_MONITOR state and the Jit's
* translation cache subsequently cleared, we cannot return directly.
* Instead, unconditionally transition to the interpreter to resume.
*
* On entry:
* r0 - self pointer
* r1 - the object (which has already been null-checked by the caller
* r4 - the Dalvik PC of the following instruction.
*/
ldr r2, .LdvmLockObject
mov r3, #0 @ Record that we're not returning
str r3, [r0, #offThread_inJitCodeCache]
blx r2 @ dvmLockObject(self, obj)
ldr r2, .LdvmJitToInterpNoChain
@ Bail to interpreter - no chain [note - r4 still contains rPC]
#if defined(WITH_JIT_TUNING)
mov r0, #kHeavyweightMonitor
#endif
bx r2
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_MONITOR_ENTER_DEBUG
dvmCompiler_TEMPLATE_MONITOR_ENTER_DEBUG:
/* File: armv5te/TEMPLATE_MONITOR_ENTER_DEBUG.S */
/*
* To support deadlock prediction, this version of MONITOR_ENTER
* will always call the heavyweight dvmLockObject, check for an
* exception and then bail out to the interpreter.
*
* On entry:
* r0 - self pointer
* r1 - the object (which has already been null-checked by the caller
* r4 - the Dalvik PC of the following instruction.
*
*/
ldr r2, .LdvmLockObject
mov r3, #0 @ Record that we're not returning
str r3, [r0, #offThread_inJitCodeCache]
blx r2 @ dvmLockObject(self, obj)
@ test for exception
ldr r1, [rSELF, #offThread_exception]
cmp r1, #0
beq 1f
ldr r2, .LhandleException
sub r0, r4, #2 @ roll dPC back to this monitor instruction
bx r2
1:
@ Bail to interpreter - no chain [note - r4 still contains rPC]
#if defined(WITH_JIT_TUNING)
mov r0, #kHeavyweightMonitor
#endif
ldr pc, .LdvmJitToInterpNoChain
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_PERIODIC_PROFILING
dvmCompiler_TEMPLATE_PERIODIC_PROFILING:
/* File: armv5te/TEMPLATE_PERIODIC_PROFILING.S */
/*
* Increment profile counter for this trace, and decrement
* sample counter. If sample counter goes below zero, turn
* off profiling.
*
* On entry
* (lr-11) is address of pointer to counter. Note: the counter
* actually exists 10 bytes before the return target, but because
* we are arriving from thumb mode, lr will have its low bit set.
*/
ldr r0, [lr,#-11]
ldr r1, [rSELF, #offThread_pProfileCountdown]
ldr r2, [r0] @ get counter
ldr r3, [r1] @ get countdown timer
add r2, #1
subs r2, #1
blt .LTEMPLATE_PERIODIC_PROFILING_disable_profiling
str r2, [r0]
str r3, [r1]
bx lr
.LTEMPLATE_PERIODIC_PROFILING_disable_profiling:
mov r4, lr @ preserve lr
ldr r0, .LdvmJitTraceProfilingOff
blx r0
bx r4
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_RETURN_PROF
dvmCompiler_TEMPLATE_RETURN_PROF:
/* File: armv5te/TEMPLATE_RETURN_PROF.S */
#define TEMPLATE_INLINE_PROFILING
/* File: armv5te/TEMPLATE_RETURN.S */
/*
* Unwind a frame from the Dalvik stack for compiled OP_RETURN_XXX.
* If the stored value in returnAddr
* is non-zero, the caller is compiled by the JIT thus return to the
* address in the code cache following the invoke instruction. Otherwise
* return to the special dvmJitToInterpNoChain entry point.
*/
#if defined(TEMPLATE_INLINE_PROFILING)
stmfd sp!, {r0-r2,lr} @ preserve live registers
mov r0, r6
@ r0=rSELF
mov lr, pc
ldr pc, .LdvmFastMethodTraceExit
ldmfd sp!, {r0-r2,lr} @ restore live registers
#endif
SAVEAREA_FROM_FP(r0, rFP) @ r0<- saveArea (old)
ldr r10, [r0, #offStackSaveArea_prevFrame] @ r10<- saveArea->prevFrame
ldrb r8, [rSELF, #offThread_breakFlags] @ r8<- breakFlags
ldr rPC, [r0, #offStackSaveArea_savedPc] @ rPC<- saveArea->savedPc
#if !defined(WITH_SELF_VERIFICATION)
ldr r9, [r0, #offStackSaveArea_returnAddr] @ r9<- chaining cell ret
#else
mov r9, #0 @ disable chaining
#endif
ldr r2, [r10, #(offStackSaveArea_method - sizeofStackSaveArea)]
@ r2<- method we're returning to
cmp r2, #0 @ break frame?
#if !defined(WITH_SELF_VERIFICATION)
beq 1f @ bail to interpreter
#else
blxeq lr @ punt to interpreter and compare state
#endif
ldr r1, .LdvmJitToInterpNoChainNoProfile @ defined in footer.S
mov rFP, r10 @ publish new FP
ldr r10, [r2, #offMethod_clazz] @ r10<- method->clazz
str r2, [rSELF, #offThread_method]@ self->method = newSave->method
ldr r0, [r10, #offClassObject_pDvmDex] @ r0<- method->clazz->pDvmDex
str rFP, [rSELF, #offThread_curFrame] @ curFrame = fp
add rPC, rPC, #6 @ publish new rPC (advance 6 bytes)
str r0, [rSELF, #offThread_methodClassDex]
cmp r8, #0 @ check the break flags
movne r9, #0 @ clear the chaining cell address
str r9, [rSELF, #offThread_inJitCodeCache] @ in code cache or not
cmp r9, #0 @ chaining cell exists?
blxne r9 @ jump to the chaining cell
#if defined(WITH_JIT_TUNING)
mov r0, #kCallsiteInterpreted
#endif
mov pc, r1 @ callsite is interpreted
1:
mov r0, #0
str r0, [rSELF, #offThread_inJitCodeCache] @ reset inJitCodeCache
stmia rSELF, {rPC, rFP} @ SAVE_PC_FP_TO_SELF()
ldr r2, .LdvmMterpStdBail @ defined in footer.S
mov r0, rSELF @ Expecting rSELF in r0
blx r2 @ exit the interpreter
#undef TEMPLATE_INLINE_PROFILING
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_INVOKE_METHOD_NO_OPT_PROF
dvmCompiler_TEMPLATE_INVOKE_METHOD_NO_OPT_PROF:
/* File: armv5te/TEMPLATE_INVOKE_METHOD_NO_OPT_PROF.S */
#define TEMPLATE_INLINE_PROFILING
/* File: armv5te/TEMPLATE_INVOKE_METHOD_NO_OPT.S */
/*
* For polymorphic callsites - setup the Dalvik frame and load Dalvik PC
* into rPC then jump to dvmJitToInterpNoChain to dispatch the
* runtime-resolved callee.
*/
@ r0 = methodToCall, r1 = returnCell, rPC = dalvikCallsite
ldrh r7, [r0, #offMethod_registersSize] @ r7<- methodToCall->regsSize
ldrh r2, [r0, #offMethod_outsSize] @ r2<- methodToCall->outsSize
ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd
ldrb r8, [rSELF, #offThread_breakFlags] @ r8<- breakFlags
add r3, r1, #1 @ Thumb addr is odd
SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area
sub r1, r1, r7, lsl #2 @ r1<- newFp (old savearea - regsSize)
SAVEAREA_FROM_FP(r10, r1) @ r10<- stack save area
sub r10, r10, r2, lsl #2 @ r10<- bottom (newsave - outsSize)
cmp r10, r9 @ bottom < interpStackEnd?
bxlo lr @ return to raise stack overflow excep.
@ r1 = newFP, r0 = methodToCall, r3 = returnCell, rPC = dalvikCallsite
ldr r9, [r0, #offMethod_clazz] @ r9<- method->clazz
ldr r10, [r0, #offMethod_accessFlags] @ r10<- methodToCall->accessFlags
str rPC, [rFP, #(offStackSaveArea_currentPc - sizeofStackSaveArea)]
str rPC, [r1, #(offStackSaveArea_savedPc - sizeofStackSaveArea)]
ldr rPC, [r0, #offMethod_insns] @ rPC<- methodToCall->insns
@ set up newSaveArea
str rFP, [r1, #(offStackSaveArea_prevFrame - sizeofStackSaveArea)]
str r3, [r1, #(offStackSaveArea_returnAddr - sizeofStackSaveArea)]
str r0, [r1, #(offStackSaveArea_method - sizeofStackSaveArea)]
cmp r8, #0 @ breakFlags != 0
bxne lr @ bail to the interpreter
tst r10, #ACC_NATIVE
#if !defined(WITH_SELF_VERIFICATION)
bne .LinvokeNative
#else
bxne lr @ bail to the interpreter
#endif
ldr r10, .LdvmJitToInterpTraceSelectNoChain
ldr r3, [r9, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex
@ Update "thread" values for the new method
str r0, [rSELF, #offThread_method] @ self->method = methodToCall
str r3, [rSELF, #offThread_methodClassDex] @ self->methodClassDex = ...
mov rFP, r1 @ fp = newFp
str rFP, [rSELF, #offThread_curFrame] @ curFrame = newFp
#if defined(TEMPLATE_INLINE_PROFILING)
stmfd sp!, {r0-r3} @ preserve r0-r3
mov r1, r6
@ r0=methodToCall, r1=rSELF
mov lr, pc
ldr pc, .LdvmFastMethodTraceEnter
ldmfd sp!, {r0-r3} @ restore r0-r3
#endif
@ Start executing the callee
#if defined(WITH_JIT_TUNING)
mov r0, #kInlineCacheMiss
#endif
mov pc, r10 @ dvmJitToInterpTraceSelectNoChain
#undef TEMPLATE_INLINE_PROFILING
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_INVOKE_METHOD_CHAIN_PROF
dvmCompiler_TEMPLATE_INVOKE_METHOD_CHAIN_PROF:
/* File: armv5te/TEMPLATE_INVOKE_METHOD_CHAIN_PROF.S */
#define TEMPLATE_INLINE_PROFILING
/* File: armv5te/TEMPLATE_INVOKE_METHOD_CHAIN.S */
/*
* For monomorphic callsite, setup the Dalvik frame and return to the
* Thumb code through the link register to transfer control to the callee
* method through a dedicated chaining cell.
*/
@ r0 = methodToCall, r1 = returnCell, r2 = methodToCall->outsSize
@ rPC = dalvikCallsite, r7 = methodToCall->registersSize
@ methodToCall is guaranteed to be non-native
.LinvokeChainProf:
ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd
ldrb r8, [rSELF, #offThread_breakFlags] @ r8<- breakFlags
add r3, r1, #1 @ Thumb addr is odd
SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area
sub r1, r1, r7, lsl #2 @ r1<- newFp (old savearea - regsSize)
SAVEAREA_FROM_FP(r10, r1) @ r10<- stack save area
add r12, lr, #2 @ setup the punt-to-interp address
sub r10, r10, r2, lsl #2 @ r10<- bottom (newsave - outsSize)
cmp r10, r9 @ bottom < interpStackEnd?
bxlo r12 @ return to raise stack overflow excep.
@ r1 = newFP, r0 = methodToCall, r3 = returnCell, rPC = dalvikCallsite
ldr r9, [r0, #offMethod_clazz] @ r9<- method->clazz
str rPC, [rFP, #(offStackSaveArea_currentPc - sizeofStackSaveArea)]
str rPC, [r1, #(offStackSaveArea_savedPc - sizeofStackSaveArea)]
@ set up newSaveArea
str rFP, [r1, #(offStackSaveArea_prevFrame - sizeofStackSaveArea)]
str r3, [r1, #(offStackSaveArea_returnAddr - sizeofStackSaveArea)]
str r0, [r1, #(offStackSaveArea_method - sizeofStackSaveArea)]
cmp r8, #0 @ breakFlags != 0
bxne r12 @ bail to the interpreter
ldr r3, [r9, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex
@ Update "thread" values for the new method
str r0, [rSELF, #offThread_method] @ self->method = methodToCall
str r3, [rSELF, #offThread_methodClassDex] @ self->methodClassDex = ...
mov rFP, r1 @ fp = newFp
str rFP, [rSELF, #offThread_curFrame] @ curFrame = newFp
#if defined(TEMPLATE_INLINE_PROFILING)
stmfd sp!, {r0-r2,lr} @ preserve clobbered live registers
mov r1, r6
@ r0=methodToCall, r1=rSELF
mov lr, pc
ldr pc, .LdvmFastMethodTraceEnter
ldmfd sp!, {r0-r2,lr} @ restore registers
#endif
bx lr @ return to the callee-chaining cell
#undef TEMPLATE_INLINE_PROFILING
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN_PROF
dvmCompiler_TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN_PROF:
/* File: armv5te/TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN_PROF.S */
#define TEMPLATE_INLINE_PROFILING
/* File: armv5te/TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN.S */
/*
* For polymorphic callsite, check whether the cached class pointer matches
* the current one. If so setup the Dalvik frame and return to the
* Thumb code through the link register to transfer control to the callee
* method through a dedicated chaining cell.
*
* The predicted chaining cell is declared in ArmLIR.h with the
* following layout:
*
* typedef struct PredictedChainingCell {
* u4 branch;
* const ClassObject *clazz;
* const Method *method;
* u4 counter;
* } PredictedChainingCell;
*
* Upon returning to the callsite:
* - lr : to branch to the chaining cell
* - lr+2: to punt to the interpreter
* - lr+4: to fully resolve the callee and may rechain.
* r3 <- class
* r9 <- counter
*/
@ r0 = this, r1 = returnCell, r2 = predictedChainCell, rPC = dalvikCallsite
ldr r3, [r0, #offObject_clazz] @ r3 <- this->class
ldr r8, [r2, #4] @ r8 <- predictedChainCell->clazz
ldr r0, [r2, #8] @ r0 <- predictedChainCell->method
ldr r9, [rSELF, #offThread_icRechainCount] @ r1 <- shared rechainCount
cmp r3, r8 @ predicted class == actual class?
#if defined(WITH_JIT_TUNING)
ldr r7, .LdvmICHitCount
#if defined(WORKAROUND_CORTEX_A9_745320)
/* Don't use conditional loads if the HW defect exists */
bne 101f
ldr r10, [r7, #0]
101:
#else
ldreq r10, [r7, #0]
#endif
add r10, r10, #1
streq r10, [r7, #0]
#endif
ldreqh r7, [r0, #offMethod_registersSize] @ r7<- methodToCall->regsSize
ldreqh r2, [r0, #offMethod_outsSize] @ r2<- methodToCall->outsSize
beq .LinvokeChainProf @ predicted chain is valid
ldr r7, [r3, #offClassObject_vtable] @ r7 <- this->class->vtable
cmp r8, #0 @ initialized class or not
moveq r1, #0
subne r1, r9, #1 @ count--
strne r1, [rSELF, #offThread_icRechainCount] @ write back to thread
add lr, lr, #4 @ return to fully-resolve landing pad
/*
* r1 <- count
* r2 <- &predictedChainCell
* r3 <- this->class
* r4 <- dPC
* r7 <- this->class->vtable
*/
bx lr
#undef TEMPLATE_INLINE_PROFILING
/* ------------------------------ */
.balign 4
.global dvmCompiler_TEMPLATE_INVOKE_METHOD_NATIVE_PROF
dvmCompiler_TEMPLATE_INVOKE_METHOD_NATIVE_PROF:
/* File: armv5te/TEMPLATE_INVOKE_METHOD_NATIVE_PROF.S */
#define TEMPLATE_INLINE_PROFILING
/* File: armv5te/TEMPLATE_INVOKE_METHOD_NATIVE.S */
@ r0 = methodToCall, r1 = returnCell, rPC = dalvikCallsite
@ r7 = methodToCall->registersSize
ldr r9, [rSELF, #offThread_interpStackEnd] @ r9<- interpStackEnd
ldrb r8, [rSELF, #offThread_breakFlags] @ r8<- breakFlags
add r3, r1, #1 @ Thumb addr is odd
SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area
sub r1, r1, r7, lsl #2 @ r1<- newFp (old savearea - regsSize)
SAVEAREA_FROM_FP(r10, r1) @ r10<- stack save area
cmp r10, r9 @ bottom < interpStackEnd?
bxlo lr @ return to raise stack overflow excep.
@ r1 = newFP, r0 = methodToCall, r3 = returnCell, rPC = dalvikCallsite
str rPC, [rFP, #(offStackSaveArea_currentPc - sizeofStackSaveArea)]
str rPC, [r1, #(offStackSaveArea_savedPc - sizeofStackSaveArea)]
@ set up newSaveArea
str rFP, [r1, #(offStackSaveArea_prevFrame - sizeofStackSaveArea)]
str r3, [r1, #(offStackSaveArea_returnAddr - sizeofStackSaveArea)]
str r0, [r1, #(offStackSaveArea_method - sizeofStackSaveArea)]
cmp r8, #0 @ breakFlags != 0
ldr r8, [r0, #offMethod_nativeFunc] @ r8<- method->nativeFunc
#if !defined(WITH_SELF_VERIFICATION)
bxne lr @ bail to the interpreter
#else
bx lr @ bail to interpreter unconditionally
#endif
@ go ahead and transfer control to the native code
ldr r9, [rSELF, #offThread_jniLocal_topCookie]@r9<-thread->localRef->...
mov r2, #0
str r1, [rSELF, #offThread_curFrame] @ curFrame = newFp
str r2, [rSELF, #offThread_inJitCodeCache] @ not in the jit code cache
str r9, [r1, #(offStackSaveArea_localRefCookie - sizeofStackSaveArea)]
@ newFp->localRefCookie=top
SAVEAREA_FROM_FP(r10, r1) @ r10<- new stack save area
mov r2, r0 @ arg2<- methodToCall
mov r0, r1 @ arg0<- newFP
add r1, rSELF, #offThread_retval @ arg1<- &retval
mov r3, rSELF @ arg3<- self
#if defined(TEMPLATE_INLINE_PROFILING)
@ r2=methodToCall, r6=rSELF
stmfd sp!, {r2,r6} @ to be consumed after JNI return
stmfd sp!, {r0-r3} @ preserve r0-r3
mov r0, r2
mov r1, r6
@ r0=JNIMethod, r1=rSELF
mov lr, pc
ldr pc, .LdvmFastMethodTraceEnter
ldmfd sp!, {r0-r3} @ restore r0-r3
#endif
blx r8 @ off to the native code
#if defined(TEMPLATE_INLINE_PROFILING)
ldmfd sp!, {r0-r1} @ restore r2 and r6
@ r0=JNIMethod, r1=rSELF
mov lr, pc
ldr pc, .LdvmFastNativeMethodTraceExit
#endif
@ native return; r10=newSaveArea
@ equivalent to dvmPopJniLocals
ldr r2, [r10, #offStackSaveArea_returnAddr] @ r2 = chaining cell ret
ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved->top
ldr r1, [rSELF, #offThread_exception] @ check for exception
str rFP, [rSELF, #offThread_curFrame] @ curFrame = fp
cmp r1, #0 @ null?
str r0, [rSELF, #offThread_jniLocal_topCookie] @ new top <- old top
ldr r0, [rFP, #(offStackSaveArea_currentPc - sizeofStackSaveArea)]
@ r0 = dalvikCallsitePC
bne .LhandleException @ no, handle exception
str r2, [rSELF, #offThread_inJitCodeCache] @ set the mode properly
cmp r2, #0 @ return chaining cell still exists?
bxne r2 @ yes - go ahead
@ continue executing the next instruction through the interpreter
ldr r1, .LdvmJitToInterpTraceSelectNoChain @ defined in footer.S
add rPC, r0, #6 @ reconstruct new rPC (advance 6 bytes)
#if defined(WITH_JIT_TUNING)
mov r0, #kCallsiteInterpreted
#endif
mov pc, r1
#undef TEMPLATE_INLINE_PROFILING
.size dvmCompilerTemplateStart, .-dvmCompilerTemplateStart
/* File: armv5te/footer.S */
/*
* ===========================================================================
* Common subroutines and data
* ===========================================================================
*/
.text
.align 2
.LinvokeNative:
@ Prep for the native call
@ r1 = newFP, r0 = methodToCall
mov r2, #0
ldr r9, [rSELF, #offThread_jniLocal_topCookie]@r9<-thread->localRef->...
str r2, [rSELF, #offThread_inJitCodeCache] @ not in jit code cache
str r1, [rSELF, #offThread_curFrame] @ curFrame = newFp
str r9, [r1, #(offStackSaveArea_localRefCookie - sizeofStackSaveArea)]
@ newFp->localRefCookie=top
ldrh lr, [rSELF, #offThread_subMode]
SAVEAREA_FROM_FP(r10, r1) @ r10<- new stack save area
mov r2, r0 @ r2<- methodToCall
mov r0, r1 @ r0<- newFP
add r1, rSELF, #offThread_retval @ r1<- &retval
mov r3, rSELF @ arg3<- self
ands lr, #kSubModeMethodTrace
beq 121f @ hop if not profiling
@ r2: methodToCall, r6: rSELF
stmfd sp!, {r2,r6}
stmfd sp!, {r0-r3}
mov r0, r2
mov r1, r6
mov lr, pc
ldr pc, .LdvmFastMethodTraceEnter
ldmfd sp!, {r0-r3}
mov lr, pc
ldr pc, [r2, #offMethod_nativeFunc]
ldmfd sp!, {r0-r1}
mov lr, pc
ldr pc, .LdvmFastNativeMethodTraceExit
b 212f
121:
mov lr, pc
ldr pc, [r2, #offMethod_nativeFunc]
212:
@ native return; r10=newSaveArea
@ equivalent to dvmPopJniLocals
ldr r2, [r10, #offStackSaveArea_returnAddr] @ r2 = chaining cell ret
ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved->top
ldr r1, [rSELF, #offThread_exception] @ check for exception
str rFP, [rSELF, #offThread_curFrame] @ curFrame = fp
cmp r1, #0 @ null?
str r0, [rSELF, #offThread_jniLocal_topCookie] @ new top <- old top
ldr r0, [r10, #offStackSaveArea_savedPc] @ reload rPC
@ r0 = dalvikCallsitePC
bne .LhandleException @ no, handle exception
str r2, [rSELF, #offThread_inJitCodeCache] @ set the new mode
cmp r2, #0 @ return chaining cell still exists?
bxne r2 @ yes - go ahead
@ continue executing the next instruction through the interpreter
ldr r1, .LdvmJitToInterpTraceSelectNoChain @ defined in footer.S
add rPC, r0, #6 @ reconstruct new rPC (advance 6 bytes)
#if defined(WITH_JIT_TUNING)
mov r0, #kCallsiteInterpreted
#endif
mov pc, r1
/*
* On entry:
* r0 Faulting Dalvik PC
*/
.LhandleException:
#if defined(WITH_SELF_VERIFICATION)
ldr pc, .LdeadFood @ should not see this under self-verification mode
.LdeadFood:
.word 0xdeadf00d
#endif
mov r2, #0
str r2, [rSELF, #offThread_inJitCodeCache] @ in interpreter land
ldr r1, .LdvmMterpCommonExceptionThrown @ PIC way of getting &func
ldr rIBASE, .LdvmAsmInstructionStart @ same as above
mov rPC, r0 @ reload the faulting Dalvik address
mov pc, r1 @ branch to dvmMterpCommonExceptionThrown
.align 2
.LdvmAsmInstructionStart:
.word dvmAsmInstructionStart
.LdvmJitToInterpNoChainNoProfile:
.word dvmJitToInterpNoChainNoProfile
.LdvmJitToInterpTraceSelectNoChain:
.word dvmJitToInterpTraceSelectNoChain
.LdvmJitToInterpNoChain:
.word dvmJitToInterpNoChain
.LdvmMterpStdBail:
.word dvmMterpStdBail
.LdvmMterpCommonExceptionThrown:
.word dvmMterpCommonExceptionThrown
.LdvmLockObject:
.word dvmLockObject
.LdvmJitTraceProfilingOff:
.word dvmJitTraceProfilingOff
#if defined(WITH_JIT_TUNING)
.LdvmICHitCount:
.word gDvmICHitCount
#endif
#if defined(WITH_SELF_VERIFICATION)
.LdvmSelfVerificationMemOpDecode:
.word dvmSelfVerificationMemOpDecode
#endif
.LdvmFastMethodTraceEnter:
.word dvmFastMethodTraceEnter
.LdvmFastNativeMethodTraceExit:
.word dvmFastNativeMethodTraceExit
.LdvmFastMethodTraceExit:
.word dvmFastMethodTraceExit
.L__aeabi_cdcmple:
.word __aeabi_cdcmple
.L__aeabi_cfcmple:
.word __aeabi_cfcmple
.global dmvCompilerTemplateEnd
dmvCompilerTemplateEnd:
#endif /* WITH_JIT */
|