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git://git.linaro.org/landing-teams/working/arm/kernel into armlt-linaro-android-3.5
Conflicts:
drivers/cpuidle/coupled.c
drivers/misc/Kconfig
drivers/misc/Makefile
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Signed-off-by: Jon Medhurst <tixy@linaro.org>
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We can't rely on Kconfig options to set the fast and slow CPU lists for
HMP scheduling if we want a single kernel binary to support multiple
devices with different CPU topology. E.g. ARM's TC2, Fast Models, or
even non big.LITTLE devices.
This patch adds the function arch_get_fast_and_slow_cpus() to generate
the lists at run-time by parsing the CPU nodes in device-tree; it
assumes slow cores are A7s and everything else is fast. The function
still supports the old Kconfig options as this is useful for testing the
HMP scheduler on devices without big.LITTLE.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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into armlt-linaro-android-3.5
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git://git.linaro.org/people/jstultz/android into integration-android-vexpress
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Conflicts:
arch/arm/mach-vexpress/v2m.c
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into integration-linux-vexpress
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AIB Daemon expects this config, see bug #1026119
(https://bugs.launchpad.net/linaro-landing-team-arm/+bug/1026119)
Also enable CONFIG_INPUT_MISC as CONFIG_INPUT_UINPUT depends on it.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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AIB Daemon expects this config, see bug #1026119
(https://bugs.launchpad.net/linaro-landing-team-arm/+bug/1026119)
Also enable CONFIG_INPUT_MISC as CONFIG_INPUT_UINPUT depends on it.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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If CONFIG_SMP, cpufreq skips loops_per_jiffy update, because different
arch has different per-cpu loops_per_jiffy definition.
Signed-off-by: Richard Zhao <richard.zhao@linaro.org>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Notes by Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>:
Even though this patch is accepted by Russell, its not in the mainline
kernel yet. However this can be removed if Will Deacon's "Use architected
timers for delay loop" is accepted.
http://www.spinics.net/lists/arm-kernel/msg180836.html
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This patch adds CPU frequencies per cluster for TC2. The CPUFreq driver
reads the frequencies from the FDT.
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
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This patch adds support for CPU frequency scaling on ARM vexpress based
big.LITTLE platforms. The driver reads the frequencies from the device tree.
This driver depends on Serial Power Controller(SPC) for setting operating
performance points(OPPs). Ensure that SPC driver is built to avoid run-time
errors.
To support big.LITTLE topology, the frequencies are read from FDT and
registered seperately per-cluster. To achieve this the CPU topology is
used to set the affected/related CPUs in terms of their OPP dependencies.
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
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This patch enables ARCH_HAS_CPUFREQ for Versatile Express platforms in order
to support CPU frequency scaling.
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
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This patch provides a device tree update for TC2 in order to instantiate
the CCI and SPC drivers required for PM. It adds the required device nodes
accordingly.
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When a CPU has to be prepared for shutdown its own GIC CPU IF must
decouple the CPU IRQ line so that it cannot exit wfi when the CPU enters
standby wfi state. In order to carry out this operation, when the GIC
CPU IF is saved, the GIC CPU IF is disabled and IRQ bypass is disabled so
that the CPU IRQ line is forced into a deasserted mode.
This patch is a temporary solution since it might cause issues on system
that requires the GIC CPU IF to stay on when a CPU is shutdown.
Tested on T2 to allow CPU idle deep shutdown sleep states.
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TC2 test-chip integrates power management circuitry and firmware that
allows to remove voltage from both (A7 and A15) clusters when they are
idle or more generically when the system is forced into shutdown mode.
All CPUs in a cluster share the same voltage source so they cannot be
shutdown independently. In order to take advantage of TC2 power
management capabilities this patch implements a multi-cluster aware
CPU idle implementation. It is based on coupled C-state concept provided
by this code:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-April/097084.html
CPUs that are part of the same cluster are coupled using the mask
provided by the MPIDR at boot. Once all CPUs hit the coupled barrier the
primary CPU in the cluster (the one with MPIDR[7:0] == 0) waits for
secondaries to clean their L1 and enter wfi. Then it cleans all cache
levels, exits cluster coherency and starts the procedure to shutdown the
respective cluster. All wake-up IRQ sources are enabled by default.
Deep shutdown states for both clusters are not enabled by default.
To enable them:
A15 cluster
echo 0 > /sys/devices/system/debug/idle_debug/enable_idle
A7 cluster
echo 1 > /sys/devices/system/debug/idle_debug/enable_idle
Tested thoroughly using lookbusy to modulate system load and trigger idle
states entry/exit.
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On ARM multi-cluster systems coherency between cores running on
different clusters is managed by the cache-coherent interconnect (CCI).
It allows broadcasting of TLB invalidates and memory barriers and it
guarantees cache coherency at system level.
This patch enables the basic infrastructure required in Linux to
handle and programme the CCI component. The first implementation is
based on a platform device, its relative DT compatible property and
a simple programming interface.
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The TC2 core tile integrates a logic block that provides the interface
between the dual cluster test-chip and the M3 microcontroller that carries
out power management. The logic block, called SPC, contains several
memory mapped registers to control among other things low-power states,
operating points and reset control.
This patch provides a driver that enables run-time control of features
implemented by the SPC control logic.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
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This patch provides the new kernel infrastructure needed by versatile
express boards. Drivers are moved to drivers/misc/vexpress directory,
where Kconfig and Makefile are created. A coalesced include file is
created to cater for all versatile express required function declarations.
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The current version of cpu_{suspend}/{resume} relies on the 8 LSBs of
the MPIDR register to index the context pointer saved and restored on
CPU shutdown. This approach breaks as soon as platforms with populated
MPIDR affinity levels 1 and 2 are deployed, since the MPIDR cannot be
considered a linear index anymore.
There are multiple solutions to this problem, each with pros and cons.
This patch changes cpu_{suspend}/{resume} so that the CPU logical id
is used to retrieve an index into the context pointers array.
Performance is impacted on both save and restore paths. On save path
the CPU logical id has to be retrieved from thread_info; since caches
are on, the performance hit should be neglectable. In the resume code
path the MMU is off and so are the caches. The patch adds a trivial for
loop that polls the cpu_logical_map array scanning the present MPIDRs and
retrieves the actual CPU logical index. Since everything runs out of
strongly ordered memory the perfomance hit in the resume code path must
be measured and thought over; it worsens as the number of CPUs increases
since it is a linear search (but can be improved).
On the up side, the logical index approach is by far the easiest solution in
terms of coding and make dynamic changes to the cpu mapping trivial at
run-time.
Any change to the cpu_logical_map (ie in-kernel switcher) at run time must be
cleaned from the caches since this data has to be retrieved with the MMU
off, when caches are not searched.
Tested on A15/A7 fast models.
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When a CPU is hotplugged out caches that reside in its power domain
lose their contents and so must be cleaned to the next memory level.
Currently, __cpu_disable calls flush_cache_all() that for new generation
processor like A15/A7 ends up cleaning and invalidating all cache levels
up to Level of Coherency, which includes the unified L2.
This ends up being a waste of cycles since the L2 cache contents are not
lost on power down.
This patch updates __cpu_disable to use the newly introduced dcache
level cache operation, with the HW cache level passed as a parameter and
retrieved using the hook
flush_cache_level_cpu(void)
that returns the preferred cache level for the respective arch/platform
combination.
Tested lightly on A15 fast models and simple standby wfi.
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In processors like A15/A7 L2 cache is unified and integrated within the
processor cache hierarchy, so that it is not considered an outer cache
anymore. For processors like A15/A7 flush_cache_all() ends up cleaning
all cache levels up to Level of Coherency (LoC) that includes the L2
unified cache.
When a single CPU is suspended (CPU idle) a complete L2 clean is not
required, so generic cpu_suspend code must clean the data cache using the
newly introduced dcache level function. The HW cache level is retrieved
through the hook
flush_cache_level_cpu(void)
that returns the preferred data cache level to be flushed for the respective
architecture/platform.
The context and stack pointer (context pointer) are cleaned to main memory
using cache area functions that operate on MVA and guarantee that the data
is written back to main memory (perform cache cleaning up to the Point of
Coherency - PoC) so that the processor can fetch the context when the MMU
is off in the cpu_resume code path.
outer_cache management remains unchanged.
Tested on an A15 dual-core cluster through CPU soft-reset.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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ARM v7 architecture introduces the concept of cache levels and registers
to probe and manage cache levels accordingly.
This patch adds v7 support for dcache level operations and defines a
preferred cache level hook that by default is set to Level of
Unification Inner Shareable (LoUIS).
Allowed cache levels are:
-1: flush the entire cache system
0: no-op
[1-7] flush the corresponding data cache level
[LoUIS] has been chosen as preferred level since it represents the cache
levels which are not shared by CPUs in most of the current systems (i.e.
cache levels that are per-CPU as e.g. an integrated L1).
Power-down operations like hotplug and CPU idle require to clean/invalidate
only cache levels that are within the CPU power domain, and LoUIS reflects
this requirement properly in most of the systems.
To improve configurability and possibly optimize cache operations a DT binding
is in the making to allow platforms to define the preferred cache level in a
more flexible way.
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ARM v7 architecture introduced the concept of cache levels and related
coherency requirements. In order to select which cache levels must be
cleaned and invalidated, a new kernel cache maintenance API must be
added to the cpu_cache_fns structure of pointers.
This patch adds flush_dcache_level(level) to the ARM kernel cache
maintenance API.
This function cleans and invalidates all data cache levels up to the one
passed as an input parameter.
The cpu_cache_fns struct reflects this change by adding a new function
pointer that is initialized by arch specific assembly files.
The preferred cached level to be cleaned/invalidated can be retrieved
using the function call:
flush_cache_level_cpu(void)
By default, this function returns -1 which causes all cache levels to
be cleaned and invalidated to main memory.
Architectures can override the cache level returned by default by
patching/defining the preferred cache level hook for the arch in
question.
By default, all existing archs do not instantiate any cache level function
pointer, and flush_dcache_level just falls back to flush_kern_all.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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Adds cpuidle_coupled_parallel_barrier, which can be used by coupled
cpuidle state enter functions to handle resynchronization after
determining if any cpu needs to abort. The normal use case will
be:
static bool abort_flag;
static atomic_t abort_barrier;
int arch_cpuidle_enter(struct cpuidle_device *dev, ...)
{
if (arch_turn_off_irq_controller()) {
/* returns an error if an irq is pending and would be lost
if idle continued and turned off power */
abort_flag = true;
}
cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
if (abort_flag) {
/* One of the cpus didn't turn off it's irq controller */
arch_turn_on_irq_controller();
return -EINTR;
}
/* continue with idle */
...
}
This will cause all cpus to abort idle together if one of them needs
to abort.
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Colin Cross <ccross@android.com>
Signed-off-by: Len Brown <len.brown@intel.com>
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On some ARM SMP SoCs (OMAP4460, Tegra 2, and probably more), the
cpus cannot be independently powered down, either due to
sequencing restrictions (on Tegra 2, cpu 0 must be the last to
power down), or due to HW bugs (on OMAP4460, a cpu powering up
will corrupt the gic state unless the other cpu runs a work
around). Each cpu has a power state that it can enter without
coordinating with the other cpu (usually Wait For Interrupt, or
WFI), and one or more "coupled" power states that affect blocks
shared between the cpus (L2 cache, interrupt controller, and
sometimes the whole SoC). Entering a coupled power state must
be tightly controlled on both cpus.
The easiest solution to implementing coupled cpu power states is
to hotplug all but one cpu whenever possible, usually using a
cpufreq governor that looks at cpu load to determine when to
enable the secondary cpus. This causes problems, as hotplug is an
expensive operation, so the number of hotplug transitions must be
minimized, leading to very slow response to loads, often on the
order of seconds.
This file implements an alternative solution, where each cpu will
wait in the WFI state until all cpus are ready to enter a coupled
state, at which point the coupled state function will be called
on all cpus at approximately the same time.
Once all cpus are ready to enter idle, they are woken by an smp
cross call. At this point, there is a chance that one of the
cpus will find work to do, and choose not to enter idle. A
final pass is needed to guarantee that all cpus will call the
power state enter function at the same time. During this pass,
each cpu will increment the ready counter, and continue once the
ready counter matches the number of online coupled cpus. If any
cpu exits idle, the other cpus will decrement their counter and
retry.
To use coupled cpuidle states, a cpuidle driver must:
Set struct cpuidle_device.coupled_cpus to the mask of all
coupled cpus, usually the same as cpu_possible_mask if all cpus
are part of the same cluster. The coupled_cpus mask must be
set in the struct cpuidle_device for each cpu.
Set struct cpuidle_device.safe_state to a state that is not a
coupled state. This is usually WFI.
Set CPUIDLE_FLAG_COUPLED in struct cpuidle_state.flags for each
state that affects multiple cpus.
Provide a struct cpuidle_state.enter function for each state
that affects multiple cpus. This function is guaranteed to be
called on all cpus at approximately the same time. The driver
should ensure that the cpus all abort together if any cpu tries
to abort once the function is called.
update1:
cpuidle: coupled: fix count of online cpus
online_count was never incremented on boot, and was also counting
cpus that were not part of the coupled set. Fix both issues by
introducting a new function that counts online coupled cpus, and
call it from register as well as the hotplug notifier.
update2:
cpuidle: coupled: fix decrementing ready count
cpuidle_coupled_set_not_ready sometimes refuses to decrement the
ready count in order to prevent a race condition. This makes it
unsuitable for use when finished with idle. Add a new function
cpuidle_coupled_set_done that decrements both the ready count and
waiting count, and call it after idle is complete.
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: Arjan van de Ven <arjan@linux.intel.com>
Cc: Trinabh Gupta <g.trinabh@gmail.com>
Cc: Deepthi Dharwar <deepthi@linux.vnet.ibm.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Colin Cross <ccross@android.com>
Acked-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Len Brown <len.brown@intel.com>
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Fix the error handling in __cpuidle_register_device to include
the missing list_del. Move it to a label, which will simplify
the error handling when coupled states are added.
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Colin Cross <ccross@android.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Len Brown <len.brown@intel.com>
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Split the code to enter a state and update the stats into a helper
function, cpuidle_enter_state, and export it. This function will
be called by the coupled state code to handle entering the safe
state and the final coupled state.
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Colin Cross <ccross@android.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Len Brown <len.brown@intel.com>
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When a CPU is shutdown its architected timer comparators registers are
lost. Within CPU idle, before processors enter shutdown they enter
clock events broadcast mode through the
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, cpuid);
function where the local timers are emulated by a global always-on timer.
On CPU resume, the per-CPU tick device normal mode is restored by exiting
broadcast mode through
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, cpuid);
In order for this mechanism to function, architected timers should add to
their feature C3STOP, which means that they are not able to function when the
CPU is in off-mode.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Use SP804 timer as sched_clock instead of arch timers as work-around
until the arch timers have been fixed.
Inspired by patch from Morten Rasmussen <Morten.Rasmussen@arm.com>
with the same description but made configurable by a device tree hack,
to enable a single kernel binary to be used with multiple CoreTiles.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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A kernel may be compiled for multiple devices, some of which use
device-tree, and some which don't. To make cpuif_logical_map() work in
the absense of device-trees entries we initialise its table with the
same values as cpu_logical_map().
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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Signed-off-by: Jon Medhurst <tixy@linaro.org>
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All TC2 boards 'in the wild' will have 2GB of memory, so lets make it
all available.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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CoreTile.
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
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In ARM multi-cluster systems the MPIDR affinity level 0 cannot be used as a
single cpu identifier, affinity levels 1 and 2 must be taken into account as
well.
This patch extends the MPIDR usage to affinity levels 1 and 2 in versatile
secondary cores start up code in order to compare the passed pen_release
value with the full-blown affinity mask.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Commited-by: Liviu Dudau <Liviu.Dudau@arm.com>
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In order to set up a proper logical to per-cpu interrupt controller IF
mapping, the GIC interrupt controller device tree bindings must be enhanced
to define the CPU IF id for all present CPUs.
GIC CPU IF ids are needed to send interprocessor IPIs and to set affinity
levels. Since the way CPU IF ids are wired depends on the specific
system design, they cannot be extrapolated or probed in HW by the boot
CPU, so a binding to define them is needed to set-up the system properly.
This patch adds a logical map of per-cpu interrupt controller identifiers.
The newly introduced per-cpu IF map has to be initialized by the GIC
driver so that interprocessor interrupts and affinity levels can be set
accordingly in an SMP system, with a proper 1:1 relation between per-cpu
IF ids and logical cpu indexes.
This patch adds a function that parses the device tree properties and
initializes the cpu interfaces ids properly according to the latest GIC
device tree bindings.
If CONFIG_OF is not enabled, per-cpu CPU IF mappings are defined as
cpu_logical_map(), leaving the current functionality unchanged.
The GIC device tree bindings documentation is updated by the patch
accordingly.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Conflicts:
arch/arm/common/gic.c
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In ARM SMP systems the MPIDR register ([23:0] bits) is used to uniquely
identify CPUs.
In order to retrieve the logical CPU index corresponding to a given
MPIDR value and guarantee a consistent translation throughout the kernel, this
patch adds a look-up based on the MPIDR so that irq controller drivers and
other kernel subsystems can use it whenever the logical cpu index corresponding
to a given MPIDR value is needed.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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As soon as the device tree is unflattened the cpu logical to physical
mapping is carried out in setup_arch to build a proper array of MPIDR and
corresponding logical indexes.
The mapping could have been carried out using the flattened DT blob and
related primitives, but since the mapping is not needed by early boot
code it can safely be executed when the device tree has been uncompressed to
its tree data structure.
This patch adds the arm_dt_init_cpu maps() function call in setup_arch().
If the kernel is not compiled with DT support the function is empty and
no logical mapping takes place through it; the mapping carried out in
smp_setup_processor_id() is left unchanged.
If DT is supported the mapping created in smp_setup_processor_id() is overriden.
The DT mapping also sets the possible cpus mask, hence platform
code need not set it again in the respective smp_init_cpus() functions.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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When booting through a device tree, the kernel cpu logical id map can be
initialized using device tree data passed by FW or through an embedded blob.
This patch adds a function that parses device tree "cpu" nodes and
retrieves the corresponding CPUs hardware identifiers (MPIDR).
It sets the possible cpus and the cpu logical map values according to
the number of CPUs defined in the device tree and respective properties.
The primary CPU is assigned cpu logical number 0 to keep the current
convention valid.
Current bindings documentation is included in the patch:
Documentation/devicetree/bindings/arm/cpus.txt
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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'per-cpu-thread-hotplug-v3', 'task-placement-v1' and 'config-fragments' into big-LITTLE-MP-v3
Based on v3.5-rc7
$ git checkout -b big-LITTLE-MP-v3 v3.5-rc7
$ git merge arm-asymmetric-support-v3 cpuidle-next-v4 per-cpu-thread-hotplug-v3 per-task-load-average-v2 task-placement-v1 config-fragments
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Adds ftrace event for tracing forced task migrations using HMP
optimized scheduling.
Signed-off-by: Morten Rasmussen <Morten.Rasmussen@arm.com>
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This patch introduces a periodic check to look for high load tasks on
runqueues of low-performance cpus on heterogeneous platforms. These will
be migrated immediately rather than wait until next time they go to sleep
and goes through the wakeup migration.
The patch is proof-of-concept code and therefore attempts to have minimal
impact on existing scheduler code paths. The most of the functions can
potentially be merged with existing functions and reduce the size of this
patch considerably.
Signed-off-by: Morten Rasmussen <Morten.Rasmussen@arm.com>
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