arm: dts: dra7: restructure late attach dts

- Extract the common portions of late attach device tree attributes
into dra7x-late.dtsi.

- Enable late attach for a remotecore by defining a corresponding
  macro.

- Use a macro for setting the 3 late attach attributes on each node
  that needs to be modified.

Change-Id: I0a77742a4b7220d1d9542c6af80569e537802ddb
Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com>

4 files changed, 105 insertions, 451 deletions

diff --git a/arch/arm/boot/dts/dra7-evm-lcd-lg-late-attach-no-map.dts b/arch/arm/boot/dts/dra7-evm-lcd-lg-late-attach-no-map.dts
index e15f7bdc0eed..4a535273aedd 100644
--- a/arch/arm/boot/dts/dra7-evm-lcd-lg-late-attach-no-map.dts
+++ b/arch/arm/boot/dts/dra7-evm-lcd-lg-late-attach-no-map.dts
@@ -8,172 +8,7 @@
 
 #include "dra7-evm-lcd-lg.dts"
 
-/*
- * Memory reserved for IOMMU table carveout 0xbfc00000 for length 0x100000
- * Page Table Address for IPU1   0xbfc00000
- * Page Table Address for IPU2   0xbfc08000
- * Page Table Address for DSP1   0xbfc10000
- * Page Table Address for DSP2   0xbfc18000
- */
-
-&reserved_mem {
-	latea_pagetbl: late_pgtbl@bfc00000 {
-		reg = <0x0 0xbfc00000 0x0 0x100000>;
-		no-map;
-		status = "okay";
-	};
-};
-
-&ipu2_cma_pool {
-	/delete-property/ reusable;
-	no-map;
-};
-
-&ipu2 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer3 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer4 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer9 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&mmu_ipu2{
-	ti,late-attach;
-	ti,late-attach-dma-pool;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-/* Uncomment below block to enable late attach for IPU1 */
-
-/*
-&ipu1_cma_pool {
-	/delete-property/ reusable;
-	no-map;
-};
-
-&ipu1 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer11 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer7 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer8 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&mmu_ipu1{
-	ti,late-attach;
-	ti,late-attach-dma-pool;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-*/
-
-/* Uncomment below block to enable late attach for DSP1 */
-
-/*
-&dsp1_cma_pool {
-	/delete-property/ reusable;
-	no-map;
-};
-
-&dsp1 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer5 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer10 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&mmu0_dsp1 {
-	ti,late-attach;
-	ti,late-attach-dma-pool;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&mmu1_dsp1 {
-	ti,late-attach;
-	ti,late-attach-dma-pool;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-*/
-
-/* Uncomment below block to enable late attach for DSP2 */
-
-/*
-
-&dsp2_cma_pool {
-	/delete-property/ reusable;
-	no-map;
-};
-
-&dsp2 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer6 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&mmu0_dsp2 {
-	ti,late-attach;
-	ti,late-attach-dma-pool;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&mmu1_dsp2 {
-	ti,late-attach;
-	ti,late-attach-dma-pool;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
+#define IPU2_LATE_ATTACH
+#define LATE_ATTACH_DMA_POOL
 
-*/
+#include "dra7x-late.dtsi"
diff --git a/arch/arm/boot/dts/dra7-evm-lcd-lg-late-attach.dts b/arch/arm/boot/dts/dra7-evm-lcd-lg-late-attach.dts
index 939896b6e00b..58474f21a8d7 100644
--- a/arch/arm/boot/dts/dra7-evm-lcd-lg-late-attach.dts
+++ b/arch/arm/boot/dts/dra7-evm-lcd-lg-late-attach.dts
@@ -8,146 +8,6 @@
 
 #include "dra7-evm-lcd-lg.dts"
 
-/*
- * Memory reserved for IOMMU table carveout 0xbfc00000 for length 0x100000
- * Page Table Address for IPU1   0xbfc00000
- * Page Table Address for IPU2   0xbfc08000
- * Page Table Address for DSP1   0xbfc10000
- * Page Table Address for DSP2   0xbfc18000
- */
-
-&reserved_mem {
-	latea_pagetbl: late_pgtbl@bfc00000 {
-		reg = <0x0 0xbfc00000 0x0 0x100000>;
-		no-map;
-		status = "okay";
-	};
-};
-
-&ipu2 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer3 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer4 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer9 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&mmu_ipu2{
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-/* Uncomment below block to enable late attach for IPU1 */
-
-/*
-&ipu1 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer11 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer7 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer8 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&mmu_ipu1{
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-*/
-
-/* Uncomment below block to enable late attach for DSP1 */
-
-/*
-&dsp1 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer5 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer10 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&mmu0_dsp1 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&mmu1_dsp1 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-*/
-
-/* Uncomment below block to enable late attach for DSP2 */
-
-/*
-
-&dsp2 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer6 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&mmu0_dsp2 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&mmu1_dsp2 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
+#define IPU2_LATE_ATTACH
 
-*/
+#include "dra7x-late.dtsi"
diff --git a/arch/arm/boot/dts/dra7-evm-lcd-osd-late-attach.dts b/arch/arm/boot/dts/dra7-evm-lcd-osd-late-attach.dts
index 5416d2645517..92ff541f88c9 100644
--- a/arch/arm/boot/dts/dra7-evm-lcd-osd-late-attach.dts
+++ b/arch/arm/boot/dts/dra7-evm-lcd-osd-late-attach.dts
@@ -8,145 +8,6 @@
 
 #include "dra7-evm-lcd-osd.dts"
 
-/*
- * Memory reserved for IOMMU table carveout 0xbfc00000 for length 0x100000
- * Page Table Address for IPU1   0xbfc00000
- * Page Table Address for IPU2   0xbfc08000
- * Page Table Address for DSP1   0xbfc10000
- * Page Table Address for DSP2   0xbfc18000
- */
-
-&reserved_mem {
-	latea_pagetbl: late_pgtbl@bfc00000 {
-		reg = <0x0 0xbfc00000 0x0 0x100000>;
-		no-map;
-		status = "okay";
-	};
-};
-
-&ipu2 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer3 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer4 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer9 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&mmu_ipu2{
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-/*Uncomment below block to enable late attach for IPU1*/
-
-/*
-&ipu1 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer11 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer7 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer8 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&mmu_ipu1{
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-*/
-
-/*Uncomment below block to enable late attach for DSP1*/
-
-/*
-&dsp1 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer5 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer10 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&mmu0_dsp1 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&mmu1_dsp1 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-*/
-
-/*Uncomment below block to enable late attach for DSP2*/
-
-/*
-&dsp2 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&timer6 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&mmu0_dsp2 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-
-&mmu1_dsp2 {
-	ti,late-attach;
-	ti,no-idle-on-init;
-	ti,no-reset-on-init;
-};
-*/
+#define IPU2_LATE_ATTACH
 
+#include "dra7x-late.dtsi"
diff --git a/arch/arm/boot/dts/dra7x-late.dtsi b/arch/arm/boot/dts/dra7x-late.dtsi
new file mode 100644
index 000000000000..29d80d515445
--- /dev/null
+++ b/arch/arm/boot/dts/dra7x-late.dtsi
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This file conditionally enables late attach on the different remotecores on
+ * the DRA7x SOC.
+ *
+ */
+
+#define LATE_ATTACH(label) &label { \
+	ti,late-attach;\
+	ti,no-idle-on-init;\
+	ti,no-reset-on-init; }
+
+#define NO_MAP(label) &label { \
+	/delete-property/ reusable; \
+	no-map; }
+
+#ifdef IPU1_LATE_ATTACH
+
+LATE_ATTACH(ipu1);
+LATE_ATTACH(timer11);
+LATE_ATTACH(timer7);
+LATE_ATTACH(timer8);
+LATE_ATTACH(mmu_ipu1);
+
+#ifdef LATE_ATTACH_DMA_POOL
+NO_MAP(ipu1_cma_pool);
+#endif
+
+#endif
+
+#ifdef IPU2_LATE_ATTACH
+
+LATE_ATTACH(ipu2);
+LATE_ATTACH(timer3);
+LATE_ATTACH(timer4);
+LATE_ATTACH(timer9);
+LATE_ATTACH(mmu_ipu2);
+
+#ifdef LATE_ATTACH_DMA_POOL
+NO_MAP(ipu2_cma_pool);
+#endif
+
+#endif
+
+
+#ifdef DSP1_LATE_ATTACH
+
+LATE_ATTACH(dsp1);
+LATE_ATTACH(timer5);
+LATE_ATTACH(timer10);
+LATE_ATTACH(mmu0_dsp1);
+LATE_ATTACH(mmu1_dsp1);
+
+#ifdef LATE_ATTACH_DMA_POOL
+NO_MAP(dsp1_cma_pool);
+#endif
+
+#endif
+
+#ifdef DSP2_LATE_ATTACH
+
+LATE_ATTACH(dsp2);
+LATE_ATTACH(timer6);
+LATE_ATTACH(timer13);
+LATE_ATTACH(mmu0_dsp2);
+LATE_ATTACH(mmu1_dsp2);
+
+#ifdef LATE_ATTACH_DMA_POOL
+NO_MAP(dsp2_cma_pool);
+#endif
+
+#endif
+
+/*
+ * Memory reserved for IOMMU table carveout 0xbfc00000 for length 0x100000
+ * Page Table Address for IPU1   0xbfc00000
+ * Page Table Address for IPU2   0xbfc08000
+ * Page Table Address for DSP1   0xbfc10000
+ * Page Table Address for DSP2   0xbfc18000
+ */
+
+#if defined(IPU1_LATE_ATTACH) || defined(IPU2_LATE_ATTACH) || \
+	defined(DSP1_LATE_ATTACH) || defined(DSP2_LATE_ATTACH)
+
+&reserved_mem {
+	latea_pagetbl: late_pgtbl@bfc00000 {
+		reg = <0x0 0xbfc00000 0x0 0x100000>;
+		no-map;
+		status = "okay";
+	};
+};
+
+#endif