msm: kgsl: Update ACV perfmode vote for gen7_9_0

Targets from gen7_9_0 have CPU vs GPU policy differentiation for perfmode
and hence the provision to do independent GPU perfmode for improved
performance.

Add support to configure the ACV vote from GMU that sets the perfmode.
Since for gen7_9_0 the perfmode is set through GMU, disable the icc path as
well.

Change-Id: I05574bcfca6080cba147c92a2e3939dbbe7cfadf
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>

5 files changed, 30 insertions, 10 deletions

diff --git a/adreno-gpulist.h b/adreno-gpulist.h
index be4d9e7..8897f11 100644
--- a/adreno-gpulist.h
+++ b/adreno-gpulist.h
@@ -2320,6 +2320,7 @@ static const struct adreno_gen7_core adreno_gpu_core_gen7_9_0 = {
 	.gmu_hub_clk_freq = 200000000,
 	.gen7_snapshot_block_list = &gen7_9_0_snapshot_block_list,
 	.bcl_data = 1,
+	.acv_perfmode_vote = BIT(2),
 };
 
 static const struct kgsl_regmap_list a663_hwcg_regs[] = {
diff --git a/adreno_gen7.h b/adreno_gen7.h
index bc8f5c8..be69d83 100644
--- a/adreno_gen7.h
+++ b/adreno_gen7.h
@@ -118,6 +118,8 @@ struct adreno_gen7_core {
 	u32 preempt_level;
 	/** @qos_value: GPU qos value to set for each RB. */
 	const u32 *qos_value;
+	/** @acv_perfmode_vote: ACV vote for GPU perfmode */
+	u32 acv_perfmode_vote;
 };
 
 /**
diff --git a/adreno_gen7_gmu.c b/adreno_gen7_gmu.c
index 1b93f7d..6c19dc5 100644
--- a/adreno_gen7_gmu.c
+++ b/adreno_gen7_gmu.c
@@ -2153,7 +2153,9 @@ static int gen7_gmu_bus_set(struct adreno_device *adreno_dev, int buslevel,
 	struct kgsl_pwrctrl *pwr = &device->pwrctrl;
 	int ret = 0;
 
-	kgsl_icc_set_tag(pwr, buslevel);
+	/* Target gen7_9_0 votes for perfmode through ACV. Skip icc path for same */
+	if (!adreno_is_gen7_9_0(adreno_dev))
+		kgsl_icc_set_tag(pwr, buslevel);
 
 	if (buslevel == pwr->cur_buslevel)
 		buslevel = INVALID_DCVS_IDX;
diff --git a/adreno_gen7_hwsched.c b/adreno_gen7_hwsched.c
index 666b395..1dc9e05 100644
--- a/adreno_gen7_hwsched.c
+++ b/adreno_gen7_hwsched.c
@@ -1199,7 +1199,9 @@ static int gen7_hwsched_bus_set(struct adreno_device *adreno_dev, int buslevel,
 	struct kgsl_pwrctrl *pwr = &device->pwrctrl;
 	int ret = 0;
 
-	kgsl_icc_set_tag(pwr, buslevel);
+	/* Target gen7_9_0 votes for perfmode through ACV. Skip icc path for same */
+	if (!adreno_is_gen7_9_0(adreno_dev))
+		kgsl_icc_set_tag(pwr, buslevel);
 
 	if (buslevel == pwr->cur_buslevel)
 		buslevel = INVALID_DCVS_IDX;
diff --git a/adreno_gen7_rpmh.c b/adreno_gen7_rpmh.c
index 0c196ec..fd7c2fc 100644
--- a/adreno_gen7_rpmh.c
+++ b/adreno_gen7_rpmh.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -118,8 +118,8 @@ static int setup_volt_dependency_tbl(u32 *votes,
 }
 
 /* Generate a set of bandwidth votes for the list of BCMs */
-static void tcs_cmd_data(struct bcm *bcms, int count, u32 ab, u32 ib,
-		u32 *data)
+static void tcs_cmd_data(struct bcm *bcms, int count,
+		u32 ab, u32 ib, u32 *data, u32 perfmode_vote, bool set_perfmode)
 {
 	int i;
 
@@ -135,7 +135,8 @@ static void tcs_cmd_data(struct bcm *bcms, int count, u32 ab, u32 ib,
 			if (!ab && !ib)
 				data[i] = BCM_TCS_CMD(commit, false, 0x0, 0x0);
 			else
-				data[i] = BCM_TCS_CMD(commit, true, 0x0, 0x8);
+				data[i] = BCM_TCS_CMD(commit, true, 0x0,
+							set_perfmode ? perfmode_vote : 0x0);
 			continue;
 		}
 
@@ -193,9 +194,10 @@ static void free_rpmh_bw_votes(struct rpmh_bw_votes *votes)
 
 /* Build the votes table from the specified bandwidth levels */
 static struct rpmh_bw_votes *build_rpmh_bw_votes(struct bcm *bcms,
-		int bcm_count, u32 *levels, int levels_count)
+		int bcm_count, u32 *levels, int levels_count, u32 perfmode_vote, u32 perfmode_lvl)
 {
 	struct rpmh_bw_votes *votes;
+	bool set_perfmode;
 	int i;
 
 	votes = kzalloc(sizeof(*votes), GFP_KERNEL);
@@ -243,7 +245,9 @@ static struct rpmh_bw_votes *build_rpmh_bw_votes(struct bcm *bcms,
 			return ERR_PTR(-ENOMEM);
 		}
 
-		tcs_cmd_data(bcms, bcm_count, levels[i], levels[i], votes->cmds[i]);
+		set_perfmode = (i >= perfmode_lvl) ? true : false;
+		tcs_cmd_data(bcms, bcm_count, levels[i], levels[i], votes->cmds[i],
+								perfmode_vote, set_perfmode);
 	}
 
 	return votes;
@@ -455,18 +459,27 @@ static void build_bw_table_cmd(struct hfi_bwtable_cmd *cmd,
 			cmd->cnoc_cmd_data[i][j] = (u32) cnoc->cmds[i][j];
 }
 
+#define GEN7_9_0_DDR_NOM_IDX 6
+
 static int build_bw_table(struct adreno_device *adreno_dev)
 {
 	struct gen7_gmu_device *gmu = to_gen7_gmu(adreno_dev);
+	const struct adreno_gen7_core *gen7_core = to_gen7_core(adreno_dev);
 	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
 	struct kgsl_pwrctrl *pwr = &device->pwrctrl;
 	struct rpmh_bw_votes *ddr, *cnoc = NULL;
+	u32 perfmode_vote = gen7_core->acv_perfmode_vote;
+	u32 perfmode_lvl = adreno_is_gen7_9_0(adreno_dev) ? GEN7_9_0_DDR_NOM_IDX : 1;
 	u32 *cnoc_table;
 	u32 count;
 	int ret;
 
+	/* If perfmode vote is not defined, use default value as 0x8 */
+	if (!perfmode_vote)
+		perfmode_vote = BIT(3);
+
 	ddr = build_rpmh_bw_votes(gen7_ddr_bcms, ARRAY_SIZE(gen7_ddr_bcms),
-		pwr->ddr_table, pwr->ddr_table_count);
+		pwr->ddr_table, pwr->ddr_table_count, perfmode_vote, perfmode_lvl);
 	if (IS_ERR(ddr))
 		return PTR_ERR(ddr);
 
@@ -475,7 +488,7 @@ static int build_bw_table(struct adreno_device *adreno_dev)
 
 	if (count > 0)
 		cnoc = build_rpmh_bw_votes(gen7_cnoc_bcms,
-			ARRAY_SIZE(gen7_cnoc_bcms), cnoc_table, count);
+			ARRAY_SIZE(gen7_cnoc_bcms), cnoc_table, count, 0, 0);
 
 	kfree(cnoc_table);