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| author | qctecmdr <qctecmdr@localhost> | 2022-07-29 06:44:16 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2022-07-29 06:44:16 -0700 |
| commit | 7599a12e560247344b7a888b8fba0b0a2e96d59b (patch) | |
| tree | 8046e9740cabc690af1f766e8dc1c58fb988d031 | |
| parent | 986acec459f3ad55f4608b9703237b36bd75f57d (diff) | |
| parent | de87eaa35b4ac80d618ac50b1fd55dd7e6fffdb0 (diff) | |
| download | devicetree-7599a12e560247344b7a888b8fba0b0a2e96d59b.tar.gz | |
Merge "ARM: dts: msm: Add configuration for ice driver in kona.dtsi"
| -rw-r--r-- | qcom/kona.dtsi | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/qcom/kona.dtsi b/qcom/kona.dtsi index 39d805cf..87088d7a 100644 --- a/qcom/kona.dtsi +++ b/qcom/kona.dtsi @@ -3013,6 +3013,29 @@ }; }; + ufs_ice: ufsice@1d90000 { + compatible = "qcom,ice"; + reg = <0x1d90000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", "bus_clk", + "iface_clk", "ice_core_clk"; + clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_UFS_1X_CLKREF_EN>, + <&clock_gcc GCC_UFS_PHY_AHB_CLK>, + <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>; + qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; + vdd-hba-supply = <&ufs_phy_gdsc>; + qcom,msm-bus,name = "ufs_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 650 0 0>, /* No vote */ + <1 650 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs"; + }; + ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>, <0x1d90000 0x8000>; /* PHY regs */ reg-names = "phy_mem", "ufs_ice"; |