Commit label r00013.2 - ES1 0.0.013.2

TRACKING-ID:7fbefb95-e97b-453f-81b3-0fff0e2e0eb9

55 files changed, 3833 insertions, 296 deletions

diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt
index 0e89973e..b27e9a83 100755
--- a/bindings/clock/qcom,debugcc.txt
+++ b/bindings/clock/qcom,debugcc.txt
@@ -22,6 +22,7 @@ Required properties :
 			"qcom,lemans-debugcc"
 			"qcom,sdx55-debugcc"
 			"qcom,kona-debugcc"
+			"qcom,sdxpoorwills-debugcc"
 
 - qcom,gcc: phandle to the GCC device node.
 - qcom,videocc: phandle to the Video CC device node.
diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt
index 1e25cfb5..f43b489b 100755
--- a/bindings/clock/qcom,gcc.txt
+++ b/bindings/clock/qcom,gcc.txt
@@ -46,6 +46,7 @@ Required properties :
 			"qcom,bengal-gcc"
 			"qcom,lemans-gcc"
 			"qcom,gcc-sdx55"
+			"qcom,sdxpoorwills-gcc"
 
 - reg : shall contain base register location and length
 - vdd_cx-supply: The vdd_cx logic rail supply.
diff --git a/bindings/clock/qcom,rpmh-clk.txt b/bindings/clock/qcom,rpmh-clk.txt
index 2661800e..fd5bd322 100755
--- a/bindings/clock/qcom,rpmh-clk.txt
+++ b/bindings/clock/qcom,rpmh-clk.txt
@@ -18,6 +18,7 @@ Required properties :
 		"qcom,direwolf-rpmh-clk"
 		"qcom,lemans-rpmh-clk"
 		"qcom,sdx55-rpmh-clk"
+		"qcom,sdxpoorwills-rpmh-clk"
 
 - #clock-cells : must contain 1
 
diff --git a/bindings/clock/qcom,sdxlemur-apsscc.txt b/bindings/clock/qcom,sdxlemur-apsscc.txt
index 042705ee..f720b93e 100755
--- a/bindings/clock/qcom,sdxlemur-apsscc.txt
+++ b/bindings/clock/qcom,sdxlemur-apsscc.txt
@@ -10,6 +10,8 @@ Required properties:
 		"qcom,sdxnightjar-apsscc"
 		"qcom,qcs404-apsscc"
 		"qcom,sdx55-apsscc"
+		"qcom,sdxpoorwills-apsscc"
+
 - clocks:	Phandle to the clock device.
 - clock-names:	Names of the used clocks. Shall contain following:
 		"xo_ao", "gpll0_ao"
diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt
index 55f22e80..3f5e54f2 100755
--- a/bindings/cnss/cnss-wlan.txt
+++ b/bindings/cnss/cnss-wlan.txt
@@ -18,6 +18,7 @@ Required properties:
                 "qcom,cnss-qca6490" for QCA6490 device
                 "qcom,cnss-kiwi" for KIWI device
                 "qcom,cnss-qca-converged" for converged QCA devices
+                "qcom,cnss-qcn9000" for QCN9000 device
   - wlan-en-gpio: WLAN_EN GPIO signal specified by the chip specifications
   - vdd-wlan-supply: phandle to the regulator device tree node
   - pinctrl-names: Names corresponding to the numbered pinctrl states
diff --git a/bindings/interconnect/qcom,sdxpoorwills.txt b/bindings/interconnect/qcom,sdxpoorwills.txt
new file mode 100755
index 00000000..2beb3220
--- /dev/null
+++ b/bindings/interconnect/qcom,sdxpoorwills.txt
@@ -0,0 +1,24 @@
+Qualcomm Technologies, Inc. SDXPOORWILLS Network-On-Chip interconnect driver binding
+--------------------------------------------------------------------------------
+
+SDXPOORWILLS interconnect providers support system bandwidth requirements through
+RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
+able to communicate with the BCM through the Resource State Coordinator (RSC)
+associated with each execution environment. Provider nodes must point to at
+least one RPMh device child node pertaining to their RSC and each provider
+can map to multiple RPMh resources.
+
+Required properties :
+- compatible : shall contain only one of the following:
+			"qcom,sdxpoorwills-ipa_virt",
+			"qcom,sdxpoorwills-system_noc",
+			"qcom,sdxpoorwills-mem_noc",
+			"qcom,sdxpoorwills-mc_virt",
+- #interconnect-cells : should contain 1
+
+Examples:
+
+system_noc: interconnect@1620000 {
+	compatible = "qcom,sdxpoorwills-system_noc";
+	interconnect-cells = <1>;
+};
diff --git a/bindings/qcom,sa410m-pinctrl.yaml b/bindings/pinctrl/qcom,sa410m-pinctrl.yaml
index 2de2c065..2de2c065 100755
--- a/bindings/qcom,sa410m-pinctrl.yaml
+++ b/bindings/pinctrl/qcom,sa410m-pinctrl.yaml
diff --git a/bindings/pinctrl/qcom,sa410m-vm-pinctrl.yaml b/bindings/pinctrl/qcom,sa410m-vm-pinctrl.yaml
new file mode 100755
index 00000000..06bf8a16
--- /dev/null
+++ b/bindings/pinctrl/qcom,sa410m-vm-pinctrl.yaml
@@ -0,0 +1,194 @@
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,sa410m-vm-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. SA410M VM TLMM block
+
+description: |
+  This binding describes the Top Level Mode Multiplexer block found in the
+  SA410M VM platform.
+
+properties:
+  compatible:
+      Usage: required
+      Value type: <string>
+      Definition: must be "qcom,sa410m-vm-pinctrl"
+
+  reg:
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: the base address and size of the TLMM register space.
+
+  interrupts-extended:
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: should specify the TLMM summary IRQ.
+
+  interrupt-controller:
+      Usage: required
+      Value type: <none>
+      Definition: identifies this node as an interrupt controller
+
+  #interrupt-cells:
+      Usage: required
+      Value type: <u32>
+      Definition: must be 2. Specifying the pin number and flags, as defined
+                  in <dt-bindings/interrupt-controller/irq.h>
+
+  gpio-controller:
+      Usage: required
+      Value type: <none>
+      Definition: identifies this node as a gpio controller
+
+  #gpio-cells:
+      Usage: required
+      Value type: <u32>
+      Definition: must be 2. Specifying the pin number and flags, as defined
+                  in <dt-bindings/gpio/gpio.h>
+
+  gpios:
+      Definition: array of gpio pin number required by VM TLMM clients
+
+  Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+  a general description of GPIO and interrupt bindings.
+
+  Please refer to pinctrl-bindings.txt in this directory for details of the
+  common pinctrl bindings used by client devices, including the meaning of the
+  phrase "pin configuration node".
+
+  The pin configuration nodes act as a container for an arbitrary number of
+  subnodes. Each of these subnodes represents some desired configuration for a
+  pin, a group, or a list of pins or groups. This configuration can include the
+  mux function to select on those pin(s)/group(s), and various pin configuration
+  parameters, such as pull-up, drive strength, etc.
+
+
+  PIN CONFIGURATION NODES:
+
+  The name of each subnode is not important; all subnodes should be enumerated
+  and processed purely based on their content.
+
+  Each subnode only affects those parameters that are explicitly listed. In
+  other words, a subnode that lists a mux function but no pin configuration
+  parameters implies no information about any pin configuration parameters.
+  Similarly, a pin subnode that describes a pullup parameter implies no
+  information about e.g. the mux function.
+
+
+  The following generic properties as defined in pinctrl-bindings.txt are valid
+  to specify in a pin configuration subnode:
+
+  pins:
+        Usage: required
+        Value type: <string-array>
+        Definition: List of gpio pins affected by the properties specified in
+                    this subnode.
+
+        Valid pins:
+                  gpio0-gpio155
+                  Supports mux, bias and drive-strength
+
+                  sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
+                  sdc2_data sdc1_rclk
+                  Supports bias and drive-strength
+
+  function:
+        Usage: required
+        Value type: <string>
+        Definition: Specify the alternative function to be configured for the
+                    specified pins. Functions are only valid for gpio pins.
+        Valid values:
+          blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
+          bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
+          qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
+          dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
+          blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
+          mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
+          atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
+          cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
+          pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
+          qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
+          qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
+          atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
+          atest_usb20, atest_char0, dac_calib10, qdss_stm10,
+          qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
+          blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
+          qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
+          qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
+          dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
+          qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
+          dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
+          dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
+          dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
+          dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
+          sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
+          qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
+          uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
+          blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
+          qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
+          blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
+          cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
+          blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
+          qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
+          isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
+          qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
+          sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
+          gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
+          qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
+          tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
+          qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
+          sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
+          sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
+          ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
+          blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
+          pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
+          qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
+          qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
+          gpio
+
+  bias-disable:
+    Usage: optional
+    Value type: <none>
+    Definition: The specified pins should be configured as no pull.
+
+  bias-pull-down:
+    Usage: optional
+    Value type: <none>
+    Definition: The specified pins should be configured as pull down.
+
+  bias-pull-up:
+    Usage: optional
+    Value type: <none>
+    Definition: The specified pins should be configured as pull up.
+
+  output-high:
+    Usage: optional
+    Value type: <none>
+    Definition: The specified pins are configured in output mode, driven high.
+                  Not valid for sdc pins.
+
+  output-low:
+    Usage: optional
+    Value type: <none>
+    Definition: The specified pins are configured in output mode, driven low.
+                  Not valid for sdc pins.
+
+  drive-strength:
+    Usage: optional
+    Value type: <u32>
+    Definition: Selects the drive strength for the specified pins, in mA.
+    Valid values: 2, 4, 6, 8, 10, 12, 14 and 16
+
+examples:
+  - |
+    tlmm: pinctrl@400000 {
+      compatible = "qcom,sa410m-vm-pinctrl";
+      reg = <0x400000 0x800000>;
+      interrupts-extended = <0 227 0>;
+      gpio-controller;
+      #gpio-cells = <2>;
+      interrupt-controller;
+      #interrupt-cells = <2>;
+      gpios = /bits/ 16 <0 1>;
+    };
diff --git a/bindings/qseecom/qseecom.txt b/bindings/qseecom/qseecom.txt
index 8200afda..89264722 100755
--- a/bindings/qseecom/qseecom.txt
+++ b/bindings/qseecom/qseecom.txt
@@ -26,6 +26,7 @@ Optional properties:
   - vdd-hba-supply   : handle for fixed power regulator
   - qcom,qsee-reentrancy-support: indicates the qsee reentrancy phase supported by the target
   - qcom,commonlib64-loaded-by-uefi: indicates commonlib64 is loaded by uefi already
+  - qcom,commonlib-loaded-by-hostvm: indicates commonlibs (commonlib and commonlib64) are loaded by host VM already
   - qcom,fde-key-size: indicates which FDE key size is used in device.
 
 Example:
diff --git a/bindings/sound/qcom-audio-dev.txt b/bindings/sound/qcom-audio-dev.txt
index f780188d..d9d238cd 100755
--- a/bindings/sound/qcom-audio-dev.txt
+++ b/bindings/sound/qcom-audio-dev.txt
@@ -3021,7 +3021,7 @@ Example:
 		qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>;
 	};
 
-* SPF ASoC Machine driver
+* SPF SA8295 GVM ASoC Machine driver
 
 Required properties:
 - compatible : "qcom,gvm-auto-spf-asoc-snd-adp-star" for auto adp codec.
@@ -3041,3 +3041,47 @@ Example:
             asoc-codec-names = "msm-stub-codec.1";
     };
 
+* SPF SA8155 GVM ASoC Machine driver
+
+Required properties:
+- compatible : "qcom,8155-spf-asoc-snd-adp-star" for auto adp codec.
+- qcom,model : The user-visible name of this sound card.
+- asoc-codec: This is phandle list containing the references to codec dai device
+	      nodes that are used as part of the sound card dai-links.
+- asoc-codec-names: This property contains list of codec dai names. The order of the
+		    codec dai names should match to that of the phandle order given
+		    in "asoc-codec".
+
+Example:
+
+    spf_snd_8155: spf-sound-adp-star {
+            compatible = "qcom,8155-spf-asoc-snd-adp-star";
+            qcom,model = "gvmauto-8155-snd-card";
+            asoc-codec = <&stub_codec>;
+            asoc-codec-names = "msm-stub-codec.1";
+    };
+
+* SPF SA8255 ASoC Machine driver
+
+Required properties:
+- compatible : "qcom,sa8255-asoc-snd-adp-star" for auto adp codec.
+- qcom,model : The user-visible name of this sound card.
+- asoc-codec: This is phandle list containing the references to codec dai device
+        nodes that are used as part of the sound card dai-links.
+- asoc-codec-names: This property contains list of codec dai names. The order of the
+        codec dai names should match to that of the phandle order given
+        in "asoc-codec".
+
+Optional properties:
+- qcom,mi2s-audio-intf : Property to specify if MI2S interface is used for the target
+- qcom,auxpcm-audio-intf : Property to specify if AUX PCM interface is used for the target
+- qcom,msm-mi2s-master : List of master/slave configuration for MI2S interfaces
+
+Example:
+
+    spf_snd_8255: spf-sound-adp-star {
+            compatible = "qcom,sa8255-asoc-snd-adp-star";
+            qcom,model = "sa8255-adp-star-snd-card";
+            asoc-codec = <&stub_codec>;
+            asoc-codec-names = "msm-stub-codec.1";
+    };
diff --git a/qcom/Makefile b/qcom/Makefile
index 5b328cad..f53d720b 100755
--- a/qcom/Makefile
+++ b/qcom/Makefile
@@ -460,10 +460,14 @@ dtb-$(CONFIG_ARCH_KONA) += kona-v2-qrd.dtb \
 	kona-v2.1-mtp.dtb \
 	kona-v2.1-qrd.dtb \
 	kona-v2.1-iot-rb5.dtb \
+	kona-7230-iot-rb5.dtb \
+	kona-7230m-iot-rb5.dtb \
 	qrb5165-iot-rb5.dtb \
         qrb5165m-iot-rb5.dtb \
         qrb5165n-v2-iot-rb5.dtb \
-	qrb5165n-iot-rb5.dtb
+	qrb5165n-iot-rb5.dtb \
+	qrb5165m-iot-rb5-pine.dtb \
+	qrb5165-iot-rb5-pine.dtb
 
 ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
 	dtbo-$(CONFIG_ARCH_SM6150) += \
@@ -521,9 +525,11 @@ dtb-$(CONFIG_ARCH_SDXLEMUR) += sdxlemur-rumi.dtb \
 
 dtb-$(CONFIG_ARCH_SA515M) += sa515m-ccard.dtb \
 	sa515m-ccard-eth-ep.dtb \
+	sa515m-ccard-eth-phy-ep.dtb \
 	sa515m-ccard-pcie-ep.dtb \
 	sa515m-ccard-usb-ep.dtb \
 	sa515m-v2-ccard-eth-ep.dtb \
+	sa515m-v2-ccard-eth-phy-ep.dtb \
 	sa515m-v2-ccard-pcie-ep.dtb \
 	sa515m-v2-ccard-usb-ep.dtb \
 	sa515m-v2-ccard.dtb \
diff --git a/qcom/bengal-qrd.dtsi b/qcom/bengal-qrd.dtsi
index 3b1c067c..d1572794 100755
--- a/qcom/bengal-qrd.dtsi
+++ b/qcom/bengal-qrd.dtsi
@@ -348,23 +348,23 @@
 	leds {
 		compatible = "gpio-leds";
 
-		gpio52 {
-			label = "user4-led_green";
-			gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
-			default-state = "off";
-		};
-
-		gpio47 {
+		wifi_led {
 			label = "wifi-led_yellow";
 			gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
 
-		gpio45 {
+		bt_led {
 			label = "bt-led_blue";
 			gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
 			default-state = "off";
 		};
+
+		user_led0 {
+			label = "user-led0_green";
+			gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
 	};
 
 	fan0: pwm-fan {
@@ -381,6 +381,20 @@
 	};
 };
 
+&pmi632_rgb {
+	blue {
+		label = "user-led1_green";
+	};
+
+	green {
+		label = "user-led2_green";
+	};
+
+	red {
+		label = "user-led3_green";
+	};
+};
+
 &qupv3_se5_spi {
 	status = "okay";
 	mcp2518fd: can@0 {
diff --git a/qcom/direwolf-pinctrl.dtsi b/qcom/direwolf-pinctrl.dtsi
index f9d31416..6b31fa51 100755
--- a/qcom/direwolf-pinctrl.dtsi
+++ b/qcom/direwolf-pinctrl.dtsi
@@ -2683,6 +2683,62 @@
 	cci3_active: cci3_active {
 		mux {
 			/* CLK, DATA */
+			pins = "gpio123","gpio124";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio123","gpio124";
+			bias-pull-up; /* PULL UP*/
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci3_suspend: cci3_suspend {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio123","gpio124";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio123","gpio124";
+			bias-pull-down; /* PULL DOWN */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci4_active: cci4_active {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio117","gpio118";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio117","gpio118";
+			bias-pull-up; /* PULL UP*/
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci4_suspend: cci4_suspend {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio117","gpio118";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio117","gpio118";
+			bias-pull-down; /* PULL DOWN */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci5_active: cci5_active {
+		mux {
+			/* CLK, DATA */
 			pins = "gpio12","gpio13";
 			function = "cci_i2c";
 		};
@@ -2694,7 +2750,7 @@
 		};
 	};
 
-	cci3_suspend: cci3_suspend {
+	cci5_suspend: cci5_suspend {
 		mux {
 			/* CLK, DATA */
 			pins = "gpio12","gpio13";
@@ -2708,6 +2764,62 @@
 		};
 	};
 
+	cci6_active: cci6_active {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio145","gpio146";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio145","gpio146";
+			bias-pull-up; /* PULL UP*/
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci6_suspend: cci6_suspend {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio145","gpio146";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio145","gpio146";
+			bias-pull-down; /* PULL DOWN */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci7_active: cci7_active {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio164","gpio165";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio164","gpio165";
+			bias-pull-up; /* PULL UP*/
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci7_suspend: cci7_suspend {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio164","gpio165";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio164","gpio165";
+			bias-pull-down; /* PULL DOWN */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
 	cam_sensor0_active: cam_sensor0_active {
 		/* intr gpio for bridge chip 0 */
 		mux {
diff --git a/qcom/direwolf-vm-la-mt.dtsi b/qcom/direwolf-vm-la-mt.dtsi
index ae1b3958..bc530e82 100755
--- a/qcom/direwolf-vm-la-mt.dtsi
+++ b/qcom/direwolf-vm-la-mt.dtsi
@@ -3,6 +3,14 @@
 		reg = <0x1 0x6a500000 0x0 0x51400000>;
 		label = "pmem_shared_mem";
 	};
+
+	secure_display_memory: secure_display_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x05000000>;
+	};
 };
 
 #include "display/quin-vm-display-la.dtsi"
@@ -41,10 +49,22 @@
 	status = "okay";
 };
 
+&usb_qmp_dp_phy0 {
+	status = "okay";
+};
+
 &usb2 {
 	status = "okay";
 };
 
+&usb_qmp_phy0 {
+	status = "okay";
+};
+
+&usb_qmp_phy1 {
+	status = "okay";
+};
+
 &usb2_phy2 {
 	status = "okay";
 };
diff --git a/qcom/direwolf-vm-la1-mt.dtsi b/qcom/direwolf-vm-la1-mt.dtsi
index 0300d945..e63882c9 100755
--- a/qcom/direwolf-vm-la1-mt.dtsi
+++ b/qcom/direwolf-vm-la1-mt.dtsi
@@ -7,6 +7,14 @@
 		reg = <0x1 0x66500000 0x0 0x51400000>;
 		label = "pmem_shared_mem";
 	};
+
+	secure_display_memory: secure_display_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x05000000>;
+	};
 };
 
 / {
diff --git a/qcom/direwolf-vm-lv-mt.dtsi b/qcom/direwolf-vm-lv-mt.dtsi
index add1fe4e..f66052d0 100755
--- a/qcom/direwolf-vm-lv-mt.dtsi
+++ b/qcom/direwolf-vm-lv-mt.dtsi
@@ -19,6 +19,10 @@
 	status = "okay";
 };
 
+&usb_qmp_dp_phy1 {
+	status = "okay";
+};
+
 &pcie0 {
 	status = "okay";
 };
@@ -38,3 +42,7 @@
 &qupv3_2 {
 	status = "disabled";
 };
+
+&qcom_rng_ee3 {
+	status = "okay";
+};
diff --git a/qcom/direwolf-vm-lv.dtsi b/qcom/direwolf-vm-lv.dtsi
index 36e791a3..57054446 100755
--- a/qcom/direwolf-vm-lv.dtsi
+++ b/qcom/direwolf-vm-lv.dtsi
@@ -116,3 +116,7 @@
 &cnss_pcie2 {
 	status = "ok";
 };
+
+&qcom_rng_ee3 {
+	status = "okay";
+};
diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi
index cee848ed..ceebe6fd 100755
--- a/qcom/direwolf-vm.dtsi
+++ b/qcom/direwolf-vm.dtsi
@@ -352,6 +352,7 @@
 		qcom,qsee-ce-hw-instance = <0>;
 		qcom,disk-encrypt-pipe-pair = <2>;
 		qcom,no-clock-support;
+		qcom,commonlib-loaded-by-hostvm;
 		qcom,qsee-reentrancy-support = <2>;
 	};
 
diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi
index 8fe8f655..b9ceb2dd 100755
--- a/qcom/direwolf.dtsi
+++ b/qcom/direwolf.dtsi
@@ -3138,6 +3138,11 @@
 		compatible = "qcom,secure-buffer";
 		qcom,vmid-cp-camera-preview-ro;
 	};
+
+	qcom,sps {
+		compatible = "qcom,msm-sps-4k";
+		qcom,pipe-attr-ee;
+	};
 };
 
 #include "direwolf-gpu.dtsi"
diff --git a/qcom/kona-7230-iot-rb5.dts b/qcom/kona-7230-iot-rb5.dts
new file mode 100755
index 00000000..ecee912a
--- /dev/null
+++ b/qcom/kona-7230-iot-rb5.dts
@@ -0,0 +1,7 @@
+/dts-v1/;
+
+/ {
+	model = "Qualcomm Technologies, Inc. kona-7230 IOT RB5";
+	compatible = "qcom,kona-iot", "qcom,kona", "qcom,iot";
+	qcom,board-id = <11 3>;
+};
diff --git a/qcom/kona-7230m-iot-rb5.dts b/qcom/kona-7230m-iot-rb5.dts
new file mode 100755
index 00000000..30d8c930
--- /dev/null
+++ b/qcom/kona-7230m-iot-rb5.dts
@@ -0,0 +1,7 @@
+/dts-v1/;
+
+/ {
+	model = "Qualcomm Technologies, Inc. KONA-7230M IOT RB5";
+	compatible = "qcom,kona-iot", "qcom,kona", "qcom,iot";
+	qcom,board-id = <0x04000B 0x03>;
+};
diff --git a/qcom/kona-npu.dtsi b/qcom/kona-npu.dtsi
index 8baf90f6..31dd863a 100755
--- a/qcom/kona-npu.dtsi
+++ b/qcom/kona-npu.dtsi
@@ -93,9 +93,8 @@
 				IPCC_MPROC_SIGNAL_PING>;
 		mbox-names = "ipcc-glink", "ipcc-smp2p", "ipcc-ping";
 		#mbox-cells = <2>;
-		qcom,npubw-devs = <&npu_npu_llcc_bw>, <&npu_llcc_ddr_bw>,
-			<&npudsp_npu_ddr_bw>;
-		qcom,npubw-dev-names = "llcc_bw", "llcc_ddr_bw", "dsp_ddr_bw";
+		qcom,npubw-devs = <&npu_npu_llcc_bw>, <&npu_llcc_ddr_bw>;
+		qcom,npubw-dev-names = "llcc_bw", "llcc_ddr_bw";
 		qcom,npu-pwrlevels {
 			#address-cells = <1>;
 			#size-cells = <0>;
diff --git a/qcom/kona-pm.dtsi b/qcom/kona-pm.dtsi
index a5eba344..d49c4a2f 100755
--- a/qcom/kona-pm.dtsi
+++ b/qcom/kona-pm.dtsi
@@ -7,27 +7,31 @@
 			reg = <0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			label = "L3";
+			idle-state-name = "L3";
 			qcom,clstr-tmr-add = <1000>;
 			qcom,psci-mode-shift = <4>;
 			qcom,psci-mode-mask = <0xfff>;
 
-			qcom,pm-cluster-level@0 { /* D1 */
+			CLUSTER_WFI: qcom,pm-cluster-level@0 { /* D1 */
 				reg = <0>;
-				label = "l3-wfi";
+				compatible = "arm,idle-state";
+				idle-state-name = "l3-wfi";
 				qcom,psci-mode = <0x1>;
-				qcom,entry-latency-us = <48>;
-				qcom,exit-latency-us = <51>;
-				qcom,min-residency-us = <99>;
+				entry-latency-us = <48>;
+				exit-latency-us = <51>;
+				arm,psci-suspend-param = <0x10>;
+				min-residency-us = <99>;
 			};
 
-			qcom,pm-cluster-level@1 { /* LLCC off, AOSS sleep */
+			LLCC_OFF: qcom,pm-cluster-level@1 { /* LLCC off, AOSS sleep */
 				reg = <1>;
-				label = "llcc-off";
+				compatible = "arm,idle-state";
+				idle-state-name = "llcc-off";
 				qcom,psci-mode = <0xC24>;
-				qcom,entry-latency-us = <3263>;
-				qcom,exit-latency-us = <6562>;
-				qcom,min-residency-us = <9987>;
+				arm,psci-suspend-param = <0xc240>;
+				entry-latency-us = <3263>;
+				exit-latency-us = <6562>;
+				min-residency-us = <9987>;
 				qcom,min-child-idx = <1>;
 				qcom,is-reset;
 				qcom,notify-rpm;
@@ -45,22 +49,26 @@
 				qcom,disable-ipi-prediction;
 				qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>;
 
-				qcom,pm-cpu-level@0 { /* C1 */
+				SLVR_WFI: qcom,pm-cpu-level@0 { /* C1 */
 					reg = <0>;
-					label = "wfi";
+					compatible = "arm,idle-state";
+					idle-state-name = "wfi";
 					qcom,psci-cpu-mode = <0x1>;
-					qcom,entry-latency-us = <57>;
-					qcom,exit-latency-us = <43>;
-					qcom,min-residency-us = <100>;
+					arm,psci-suspend-param = <0x1>;
+					entry-latency-us = <57>;
+					exit-latency-us = <43>;
+					min-residency-us = <100>;
 				};
 
-				qcom,pm-cpu-level@1 {  /* C4 */
+				SLVR_RAIL_OFF: qcom,pm-cpu-level@1 {  /* C4 */
 					reg = <1>;
-					label = "rail-pc";
+					compatible = "arm,idle-state";
+					idle-state-name = "rail-pc";
 					qcom,psci-cpu-mode = <0x4>;
-					qcom,entry-latency-us = <360>;
-					qcom,exit-latency-us = <531>;
-					qcom,min-residency-us = <3934>;
+					arm,psci-suspend-param = <0x40000004>;
+					entry-latency-us = <360>;
+					exit-latency-us = <531>;
+					min-residency-us = <3934>;
 					qcom,is-reset;
 					qcom,use-broadcast-timer;
 				};
@@ -75,22 +83,26 @@
 				qcom,disable-ipi-prediction;
 				qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>;
 
-				qcom,pm-cpu-level@2 { /* C1 */
+				GOLD_WFI: qcom,pm-cpu-level@2 { /* C1 */
 					reg = <2>;
-					label = "wfi";
+					compatible = "arm,idle-state";
+					idle-state-name = "wfi";
 					qcom,psci-cpu-mode = <0x1>;
-					qcom,entry-latency-us = <57>;
-					qcom,exit-latency-us = <43>;
-					qcom,min-residency-us = <83>;
+					arm,psci-suspend-param = <0x1>;
+					entry-latency-us = <57>;
+					exit-latency-us = <43>;
+					min-residency-us = <83>;
 				};
 
-				qcom,pm-cpu-level@3 {  /* C4 */
+				GOLD_RAIL_OFF: qcom,pm-cpu-level@3 {  /* C4 */
 					reg = <3>;
-					label = "rail-pc";
+					compatible = "arm,idle-state";
+					idle-state-name = "rail-pc";
 					qcom,psci-cpu-mode = <0x4>;
-					qcom,entry-latency-us = <702>;
-					qcom,exit-latency-us = <1061>;
-					qcom,min-residency-us = <4488>;
+					arm,psci-suspend-param = <0x40000004>;
+					entry-latency-us = <702>;
+					exit-latency-us = <1061>;
+					min-residency-us = <4488>;
 					qcom,is-reset;
 					qcom,use-broadcast-timer;
 				};
@@ -98,20 +110,19 @@
 		};
 	};
 
-	qcom,rpm-stats@c3f0004 {
-		compatible = "qcom,rpm-stats";
-		reg = <0xc300000 0x1000>, <0xc3f0004 0x4>;
-		reg-names = "phys_addr_base", "offset_addr";
-		qcom,num-records = <3>;
+	soc-sleep-stats@c3f0000 {
+		compatible = "qcom,rpmh-sleep-stats";
+		reg = <0xc3f0000 0x400>;
 	};
 
-	qcom,ddr-stats@c3f0000 {
+	ddr-stats@c300000 {
 		compatible = "qcom,ddr-stats";
 		reg = <0xc300000 0x1000>, <0xc3f001c 0x4>;
 		reg-names = "phys_addr_base", "offset_addr";
+		mboxes = <&qmp_aop 0>;
 	};
 
-	qcom,rpmh-master-stats@b221200 {
+	rpmh-master-stats@b221200 {
 		compatible = "qcom,rpmh-master-stats-v1";
 		reg = <0xb221200 0x60>;
 	};
diff --git a/qcom/kona.dtsi b/qcom/kona.dtsi
index dfdabadd..1d4040b9 100755
--- a/qcom/kona.dtsi
+++ b/qcom/kona.dtsi
@@ -53,7 +53,6 @@
 		pci-domain1 = &pcie1; /* PCIe1 domain */
 		pci-domain2 = &pcie2; /* PCIe2 domain */
 		serial0 = &qupv3_se2_2uart; /* RUMI */
-		mhi-netdev0 = &mhi_netdev_0;
 		hsuart0 = &qupv3_se6_4uart;
 	};
 
@@ -577,7 +576,7 @@
 
 		mailbox_mem: mailbox_region {
 			compatible = "shared-dma-pool";
-			no-map;
+			reusable;
 			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
 			alignment = <0x0 0x400000>;
 			size = <0x0 0x20000>;
@@ -4622,6 +4621,10 @@
 		qcom,firmware-name = "slpi";
 	};
 
+	qtee_shmbridge {
+		compatible = "qcom,tee-shared-memory-bridge";
+	};
+
 	qcom_smcinvoke: smcinvoke@87900000 {
 		compatible = "qcom,smcinvoke";
 		reg = <0x87900000 0x2200000>;
diff --git a/qcom/lemans-audio.dtsi b/qcom/lemans-audio.dtsi
new file mode 100755
index 00000000..5215e7ed
--- /dev/null
+++ b/qcom/lemans-audio.dtsi
@@ -0,0 +1,119 @@
+#include "msm-audio-lpass.dtsi"
+#include "msm-arm-smmu-lemans.dtsi"
+
+/ {
+	aliases {
+		i2c4 = &qupv3_se11_i2c;
+		spi16 = &qupv3_se16_spi;
+	};
+};
+
+&soc {
+	spf_core_platform: spf_core_platform {
+		compatible = "qcom,spf-core-platform";
+	};
+
+	audio_pkt_core_platform: audio-pkt-platform {
+		compatible = "qcom,audio-pkt-core-platform";
+	};
+};
+
+&spf_core_platform {
+	spf_msm_audio_ion: qcom,spf-msm-audio-ion {
+		compatible = "qcom,msm-audio-ion";
+		qcom,smmu-version = <2>;
+		qcom,smmu-enabled;
+		iommus = <&apps_smmu 0x3001 0x0>;
+		qcom,smmu-sid-mask = /bits/ 64 <0xf>;
+	};
+
+	spf_tdm_sec: qcom,spf-msm-dai-tdm-sec {
+		compatible = "qcom,msm-pcm-pinctrl";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&sec_tdm_sck_active &sec_tdm_ws_active
+					&sec_tdm_din_active &sec_tdm_dout_active>;
+		pinctrl-1 = <&sec_tdm_sck_sleep &sec_tdm_ws_sleep
+					&sec_tdm_din_sleep &sec_tdm_dout_sleep>;
+		#gpio-cells = <0>;
+	};
+
+	spf_tdm_tert: qcom,spf-msm-dai-tdm-tert {
+		compatible = "qcom,msm-pcm-pinctrl";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&tert_tdm_sck_active &tert_tdm_ws_active
+					&tert_tdm_din_active &tert_tdm_dout_active>;
+		pinctrl-1 = <&tert_tdm_sck_sleep &tert_tdm_ws_sleep
+					&tert_tdm_din_sleep &tert_tdm_dout_sleep>;
+		#gpio-cells = <0>;
+	};
+
+	spf_tdm_hsif0: qcom,spf-msm-dai-tdm-hsif0 {
+		compatible = "qcom,msm-pcm-pinctrl";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&hs0_i2s_sck_active &hs0_i2s_ws_active
+					&hs0_i2s_data0_active &hs0_i2s_data1_active>;
+		pinctrl-1 = <&hs0_i2s_sck_sleep &hs0_i2s_ws_sleep
+					&hs0_i2s_data0_sleep &hs0_i2s_data1_sleep>;
+		#gpio-cells = <0>;
+	};
+
+	spf_tdm_hsif1: qcom,spf-msm-dai-tdm-hsif1 {
+		compatible = "qcom,msm-pcm-pinctrl";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&hs1_i2s_sck_active &hs1_i2s_ws_active
+					&hs1_i2s_data0_active &hs1_i2s_data1_active>;
+		pinctrl-1 = <&hs1_i2s_sck_sleep &hs1_i2s_ws_sleep
+					&hs1_i2s_data0_sleep &hs1_i2s_data1_sleep>;
+		#gpio-cells = <0>;
+	};
+
+	spf_tdm_hsif2: qcom,spf-msm-dai-tdm-hsif2 {
+		compatible = "qcom,msm-pcm-pinctrl";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&hs2_i2s_sck_active &hs2_i2s_ws_active
+					&hs2_i2s_data0_active &hs2_i2s_data1_active>;
+		pinctrl-1 = <&hs2_i2s_sck_sleep &hs2_i2s_ws_sleep
+					&hs2_i2s_data0_sleep &hs2_i2s_data1_sleep>;
+		#gpio-cells = <0>;
+	};
+
+	spf_internal_mclk1: qcom,spf-msm-internal-mclk1 {
+		compatible = "qcom,msm-pcm-pinctrl";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&audio_internal_mclk1_active>;
+		pinctrl-1 = <&audio_internal_mclk1_sleep>;
+		#gpio-cells = <0>;
+	};
+
+	spf_snd_8255: spf-sound-adp-star {
+		compatible = "qcom,sa8255-asoc-snd-adp-star";
+		qcom,model = "sa8255-adp-star-snd-card";
+		qcom,mi2s-audio-intf;
+		qcom,auxpcm-audio-intf;
+		qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>;
+
+		qcom,sec-tdm-gpios = <&spf_tdm_sec>;
+		qcom,tert-tdm-gpios = <&spf_tdm_tert>;
+		qcom,hsif0-tdm-gpios = <&spf_tdm_hsif0>;
+		qcom,hsif1-tdm-gpios = <&spf_tdm_hsif1>;
+		qcom,hsif2-tdm-gpios = <&spf_tdm_hsif2>;
+		qcom,internal-mclk1-gpios = <&spf_internal_mclk1>;
+
+		asoc-codec = <&stub_codec>;
+		asoc-codec-names = "msm-stub-codec.1";
+	};
+};
+
+&qupv3_se11_i2c {
+	status = "ok";
+};
+
+&qupv3_se16_spi {
+	status = "ok";
+	spi_codec@0 {
+		compatible = "qcom,spi-msm-codec-slave";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+		spi-cpha;
+	};
+};
diff --git a/qcom/lemans-pcie.dtsi b/qcom/lemans-pcie.dtsi
index d7592de9..9dfe50f9 100755
--- a/qcom/lemans-pcie.dtsi
+++ b/qcom/lemans-pcie.dtsi
@@ -85,25 +85,20 @@
 			<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
 			<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
 			<&gcc GCC_PCIE_CLKREF_EN>,
-			<&gcc GCC_PCIE_0_AUX_CLK_SRC>,
 			<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
 			<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
-			<&gcc GCC_PCIE_0_PHY_RCHNG_CLK_SRC>,
-			<&gcc GCC_PCIE_0_PIPE_DIV_CLK_SRC>,
 			<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
 			<&gcc GCC_PCIE_0_PHY_AUX_CLK>,
 			<&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
-			<&gcc GCC_PCIE_0_PHY_AUX_CLK_SRC>,
 			<&pcie_0_pipe_clk>;
 
 		clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
 				"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
 				"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
-				"pcie_0_ldo", "pcie_0_aux_clk_src",
+				"pcie_0_ldo",
 				"pcie_0_slv_q2a_axi_clk", "pcie_phy_refgen_clk",
-				"pcie_phy_refgen_clk_src", "pcie_0_pipe_div_clk_src",
 				"pcie_pipe_clk_mux", "pcie_phy_aux_clk",
-				"pcie_0_pipediv2_clk", "pcie_phy_aux_clk_src",
+				"pcie_0_pipediv2_clk",
 				"pcie_pipe_clk_ext_src";
 
 		max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
@@ -148,158 +143,213 @@
 		qcom,phy-status-bit = <7>;
 		qcom,phy-power-down-offset = <0x1240>;
 		qcom,phy-sequence = <0x1240 0x03 0x0
-					0x101c 0x31 0x0
-					0x1020 0x01 0x0
-					0x1024 0xde 0x0
-					0x1028 0x07 0x0
-					0x1030 0x97 0x0
-					0x1034 0x0c 0x0
-					0x1044 0x14 0x0
-					0x1048 0x90 0x0
-					0x1058 0x0f 0x0
-					0x1074 0x06 0x0
-					0x1078 0x06 0x0
-					0x107c 0x16 0x0
-					0x1080 0x16 0x0
-					0x1084 0x36 0x0
-					0x1088 0x36 0x0
-					0x1094 0x08 0x0
-					0x10a4 0x46 0x0
-					0x10a8 0x04 0x0
-					0x10ac 0x0a 0x0
-					0x10b0 0x1a 0x0
-					0x10b4 0x14 0x0
-					0x10b8 0x34 0x0
-					0x10bc 0x82 0x0
-					0x10c4 0xd0 0x0
-					0x10cc 0x55 0x0
-					0x10d0 0x55 0x0
-					0x10d4 0x03 0x0
-					0x10d8 0x55 0x0
-					0x10dc 0x55 0x0
-					0x10e0 0x05 0x0
-					0x110c 0x02 0x0
-					0x1154 0x34 0x0
-					0x1158 0x12 0x0
-					0x115c 0x00 0x0
-					0x1168 0x0a 0x0
-					0x116c 0x04 0x0
-					0x119c 0x88 0x0
-					0x1174 0x60 0x0
-					0x117c 0x06 0x0
-					0x11a0 0x14 0x0
-					0x11a8 0x0f 0x0
-					0x0220 0x16 0x0
-					0x03c0 0x38 0x0
-					0x0a20 0x16 0x0
-					0x0bc0 0x38 0x0
-					0x0360 0x9a 0x0
-					0x0364 0xb0 0x0
-					0x0368 0x12 0x0
-					0x036c 0xf0 0x0
-					0x0370 0x42 0x0
-					0x0374 0x99 0x0
-					0x0378 0x29 0x0
-					0x037c 0x9a 0x0
-					0x0380 0xb0 0x0
-					0x0384 0x12 0x0
-					0x0388 0xf0 0x0
-					0x038c 0x43 0x0
-					0x0390 0xdd 0x0
-					0x0394 0x0d 0x0
-					0x0398 0xdb 0x0
-					0x039c 0xb0 0x0
-					0x03a0 0x64 0x0
-					0x03a4 0xf0 0x0
-					0x03a8 0xc3 0x0
-					0x03ac 0xfd 0x0
-					0x03b0 0x7f 0x0
-					0x0b60 0x9a 0x0
-					0x0b64 0xb0 0x0
-					0x0b68 0x12 0x0
-					0x0b6c 0xf0 0x0
-					0x0b70 0x42 0x0
-					0x0b74 0x99 0x0
-					0x0b78 0x29 0x0
-					0x0b7c 0x9a 0x0
-					0x0b80 0xb0 0x0
-					0x0b84 0x12 0x0
-					0x0b88 0xf0 0x0
-					0x0b8c 0x43 0x0
-					0x0b90 0xdd 0x0
-					0x0b94 0x0d 0x0
-					0x0b98 0xdb 0x0
-					0x0b9c 0xb0 0x0
-					0x0ba0 0x64 0x0
-					0x0ba4 0xf0 0x0
-					0x0ba8 0xc3 0x0
-					0x0bac 0xfd 0x0
-					0x0bb0 0x7f 0x0
-					0x03b4 0x20 0x0
-					0x022c 0x3f 0x0
-					0x0230 0x37 0x0
-					0x0bb4 0x20 0x0
-					0x0a2c 0x3f 0x0
-					0x0a30 0x37 0x0
-					0x0078 0x05 0x0
-					0x007c 0x10 0x0
-					0x0878 0x05 0x0
-					0x087c 0x10 0x0
-					0x0290 0x05 0x0
-					0x0a90 0x05 0x0
-					0x03f8 0x1f 0x0
-					0x0400 0x1f 0x0
-					0x0408 0x1f 0x0
-					0x0410 0x1f 0x0
-					0x0418 0x1f 0x0
-					0x0420 0x1f 0x0
-					0x03f4 0x1f 0x0
-					0x03fc 0x1f 0x0
-					0x0404 0x1f 0x0
-					0x0bf8 0x1f 0x0
-					0x0c00 0x1f 0x0
-					0x0c08 0x1f 0x0
-					0x0c10 0x1f 0x0
-					0x0c18 0x1f 0x0
-					0x0c20 0x1f 0x0
-					0x0bf4 0x1f 0x0
-					0x0bfc 0x1f 0x0
-					0x0c04 0x1f 0x0
-					0x0208 0x0c 0x0
-					0x0a08 0x0c 0x0
-					0x020c 0x0a 0x0
-					0x0a0c 0x0a 0x0
-					0x02dc 0x0a 0x0
-					0x0adc 0x0a 0x0
-					0x0308 0x0b 0x0
-					0x0b08 0x0b 0x0
-					0x027c 0x10 0x0
-					0x0a7c 0x10 0x0
-					0x02b4 0x00 0x0
-					0x0ab4 0x00 0x0
-					0x02ec 0x0f 0x0
-					0x0aec 0x0f 0x0
-					0x02c4 0x00 0x0
-					0x02c8 0x1f 0x0
-					0x0ac4 0x00 0x0
-					0x0ac8 0x1f 0x0
-					0x0030 0x1a 0x0
-					0x0034 0x0c 0x0
-					0x0830 0x1a 0x0
-					0x0834 0x0c 0x0
-					0x141c 0xc1 0x0
-					0x1404 0x00 0x0
-					0x13e0 0x16 0x0
-					0x13e4 0x22 0x0
-					0x1508 0x02 0x0
-					0x14a0 0x16 0x0
-					0x1584 0x28 0x0
-					0x1370 0x2e 0x0
-					0x155c 0x2e 0x0
-					0x140c 0x1d 0x0
-					0x1388 0xaa 0x0
-					0x1200 0x00 0x0
-					0x1244 0x03 0x0>;
+				0x1010 0x00 0x0
+				0x101c 0x31 0x0
+				0x1020 0x01 0x0
+				0x1024 0xde 0x0
+				0x1028 0x07 0x0
+				0x1030 0x97 0x0
+				0x1034 0x0c 0x0
+				0x1044 0x14 0x0
+				0x1048 0x90 0x0
+				0x1058 0x0f 0x0
+				0x1074 0x06 0x0
+				0x1078 0x06 0x0
+				0x107c 0x16 0x0
+				0x1080 0x16 0x0
+				0x1084 0x36 0x0
+				0x1088 0x36 0x0
+				0x1094 0x08 0x0
+				0x10a4 0x46 0x0
+				0x10a8 0x04 0x0
+				0x10ac 0x0a 0x0
+				0x10b0 0x1a 0x0
+				0x10b4 0x14 0x0
+				0x10b8 0x34 0x0
+				0x10bc 0x82 0x0
+				0x10c4 0xd0 0x0
+				0x10cc 0x55 0x0
+				0x10d0 0x55 0x0
+				0x10d4 0x03 0x0
+				0x10d8 0x55 0x0
+				0x10dc 0x55 0x0
+				0x10e0 0x05 0x0
+				0x110c 0x02 0x0
+				0x1154 0x34 0x0
+				0x1158 0x12 0x0
+				0x115c 0x00 0x0
+				0x1168 0x0a 0x0
+				0x116c 0x04 0x0
+				0x119c 0x88 0x0
+				0x1174 0x60 0x0
+				0x117c 0x06 0x0
+				0x11a0 0x14 0x0
+				0x11a8 0x0f 0x0
+				0x0220 0x16 0x0
+				0x03c0 0x38 0x0
+				0x0a20 0x16 0x0
+				0x0bc0 0x38 0x0
+				0x0360 0x9a 0x0
+				0x0364 0xb0 0x0
+				0x0368 0x12 0x0
+				0x036c 0xf0 0x0
+				0x0370 0x42 0x0
+				0x0374 0x99 0x0
+				0x0378 0x29 0x0
+				0x037c 0x9a 0x0
+				0x0380 0xb0 0x0
+				0x0384 0x12 0x0
+				0x0388 0xf0 0x0
+				0x038c 0x43 0x0
+				0x0390 0xdd 0x0
+				0x0394 0x0d 0x0
+				0x0398 0xf3 0x0
+				0x039c 0xe7 0x0
+				0x03a0 0x5e 0x0
+				0x03a4 0xec 0x0
+				0x03a8 0x83 0x0
+				0x03ac 0xf5 0x0
+				0x03b0 0x5e 0x0
+				0x0b60 0x9a 0x0
+				0x0b64 0xb0 0x0
+				0x0b68 0x12 0x0
+				0x0b6c 0xf0 0x0
+				0x0b70 0x42 0x0
+				0x0b74 0x99 0x0
+				0x0b78 0x29 0x0
+				0x0b7c 0x9a 0x0
+				0x0b80 0xb0 0x0
+				0x0b84 0x12 0x0
+				0x0b88 0xf0 0x0
+				0x0b8c 0x43 0x0
+				0x0b90 0xdd 0x0
+				0x0b94 0x0d 0x0
+				0x0b98 0xf3 0x0
+				0x0b9c 0xe7 0x0
+				0x0ba0 0x5e 0x0
+				0x0ba4 0xec 0x0
+				0x0ba8 0x83 0x0
+				0x0bac 0xf5 0x0
+				0x0bb0 0x5e 0x0
+				0x03b4 0x20 0x0
+				0x022c 0x3f 0x0
+				0x0230 0x37 0x0
+				0x0bb4 0x20 0x0
+				0x0a2c 0x3f 0x0
+				0x0a30 0x37 0x0
+				0x0078 0x05 0x0
+				0x007c 0xf6 0x0
+				0x0080 0x0f 0x0
+				0x0878 0x05 0x0
+				0x087c 0xf6 0x0
+				0x0880 0x0f 0x0
+				0x0290 0x00 0x0
+				0x0a90 0x00 0x0
+				0x0284 0x38 0x0
+				0x0a84 0x38 0x0
+				0x0318 0x7f 0x0
+				0x0b18 0x7f 0x0
+				0x03f8 0x1f 0x0
+				0x0400 0x1f 0x0
+				0x0408 0x1f 0x0
+				0x0410 0x1f 0x0
+				0x0418 0x1f 0x0
+				0x0420 0x1f 0x0
+				0x03f4 0x1f 0x0
+				0x03fc 0x1f 0x0
+				0x0404 0x1f 0x0
+				0x0bf8 0x1f 0x0
+				0x0c00 0x1f 0x0
+				0x0c08 0x1f 0x0
+				0x0c10 0x1f 0x0
+				0x0c18 0x1f 0x0
+				0x0c20 0x1f 0x0
+				0x0bf4 0x1f 0x0
+				0x0bfc 0x1f 0x0
+				0x0c04 0x1f 0x0
+				0x0438 0x01 0x0
+				0x0c38 0x01 0x0
+				0x0208 0x0c 0x0
+				0x0a08 0x0c 0x0
+				0x020c 0x08 0x0
+				0x0a0c 0x08 0x0
+				0x021c 0x04 0x0
+				0x0a1c 0x04 0x0
+				0x02d4 0x04 0x0
+				0x0ad4 0x04 0x0
+				0x02dc 0x08 0x0
+				0x0adc 0x08 0x0
+				0x0308 0x0b 0x0
+				0x0b08 0x0b 0x0
+				0x027c 0x10 0x0
+				0x0a7c 0x10 0x0
+				0x02b4 0x00 0x0
+				0x0ab4 0x00 0x0
+				0x02ec 0x0f 0x0
+				0x0aec 0x0f 0x0
+				0x02c4 0x00 0x0
+				0x02c8 0x1f 0x0
+				0x0ac4 0x00 0x0
+				0x0ac8 0x1f 0x0
+				0x0030 0x1f 0x0
+				0x0034 0x07 0x0
+				0x0830 0x1f 0x0
+				0x0834 0x07 0x0
+				0x0318 0x7c 0x0
+				0x0b18 0x7c 0x0
+				0x0398 0xf3 0x0
+				0x039c 0xe7 0x0
+				0x03a0 0x5e 0x0
+				0x03a4 0xec 0x0
+				0x03a8 0x81 0x0
+				0x03ac 0xf5 0x0
+				0x03b0 0x5e 0x0
+				0x0b98 0xf3 0x0
+				0x0b9c 0xe7 0x0
+				0x0ba0 0x5e 0x0
+				0x0ba4 0xec 0x0
+				0x0ba8 0x81 0x0
+				0x0bac 0xf5 0x0
+				0x0bb0 0x5e 0x0
+				0x0078 0x05 0x0
+				0x007c 0xf6 0x0
+				0x0080 0x0e 0x0
+				0x0878 0x05 0x0
+				0x087c 0xf6 0x0
+				0x0880 0x0e 0x0
+				0x0290 0x00 0x0
+				0x0a90 0x00 0x0
+				0x0284 0x38 0x0
+				0x0a84 0x38 0x0
+				0x0318 0x7f 0x0
+				0x0b18 0x7f 0x0
+				0x0030 0x1f 0x0
+				0x0034 0x07 0x0
+				0x0830 0x1f 0x0
+				0x0834 0x07 0x0
+				0x0318 0x7c 0x0
+				0x0b18 0x7c 0x0
+				0x03a8 0x83 0x0
+				0x0ba8 0x83 0x0
+				0x0080 0x0f 0x0
+				0x0880 0x0f 0x0
+				0x141c 0xc1 0x0
+				0x1490 0x00 0x0
+				0x13e0 0x16 0x0
+				0x13e4 0x22 0x0
+				0x1508 0x02 0x0
+				0x14a0 0x16 0x0
+				0x1584 0x28 0x0
+				0x1370 0x2e 0x0
+				0x155c 0x2e 0x0
+				0x140c 0x1d 0x0
+				0x1388 0xaa 0x0
+				0x1e24 0x00 0x0
+				0x1e28 0x00 0x0
+				0x1828 0x00 0x0
+				0x1c28 0x00 0x0
+				0x1200 0x00 0x0
+				0x1244 0x03 0x0>;
 
 		pcie0_rp: pcie0_rp {
 			reg = <0 0 0 0 0>;
@@ -389,25 +439,20 @@
 			<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
 			<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
 			<&gcc GCC_PCIE_CLKREF_EN>,
-			<&gcc GCC_PCIE_1_AUX_CLK_SRC>,
 			<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
 			<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
-			<&gcc GCC_PCIE_1_PHY_RCHNG_CLK_SRC>,
-			<&gcc GCC_PCIE_1_PIPE_DIV_CLK_SRC>,
 			<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
 			<&gcc GCC_PCIE_1_PHY_AUX_CLK>,
 			<&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
-			<&gcc GCC_PCIE_1_PHY_AUX_CLK_SRC>,
 			<&pcie_1_pipe_clk>;
 
 		clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src",
 				"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
 				"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
-				"pcie_1_ldo", "pcie_1_aux_clk_src",
+				"pcie_1_ldo",
 				"pcie_1_slv_q2a_axi_clk", "pcie_phy_refgen_clk",
-				"pcie_phy_refgen_clk_src", "pcie_1_pipe_div_clk_src",
 				"pcie_pipe_clk_mux", "pcie_phy_aux_clk",
-				"pcie_1_pipediv2_clk", "pcie_phy_aux_clk_src",
+				"pcie_1_pipediv2_clk",
 				"pcie_pipe_clk_ext_src";
 
 		max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
@@ -452,6 +497,7 @@
 		qcom,phy-power-down-offset = <0x2240>;
 
 		qcom,phy-sequence = <0x2240 0x03 0x0
+				0x2010 0x00 0x0
 				0x201c 0x31 0x0
 				0x2020 0x01 0x0
 				0x2024 0xde 0x0
@@ -480,7 +526,7 @@
 				0x20d0 0x55 0x0
 				0x20d4 0x03 0x0
 				0x20d8 0x55 0x0
-				0x20dC 0x55 0x0
+				0x20dc 0x55 0x0
 				0x20e0 0x05 0x0
 				0x210c 0x02 0x0
 				0x2154 0x34 0x0
@@ -495,7 +541,7 @@
 				0x21a8 0x0f 0x0
 				0x3a2c 0x3f 0x0
 				0x3a30 0x37 0x0
-				0x3a90 0x05 0x0
+				0x3a90 0x00 0x0
 				0x3bc0 0x38 0x0
 				0x3ab4 0x00 0x0
 				0x3aec 0x0f 0x0
@@ -529,19 +575,53 @@
 				0x3b9c 0xb0 0x0
 				0x3ba0 0x64 0x0
 				0x3ba4 0xf0 0x0
-				0x3ba8 0xc3 0x0
+				0x3ba8 0x81 0x0
 				0x3bac 0xfd 0x0
 				0x3bb0 0x7f 0x0
 				0x3ac4 0x00 0x0
 				0x3ac8 0x1f 0x0
 				0x3a08 0x0c 0x0
-				0x3a0C 0x0a 0x0
+				0x3a0c 0x0a 0x0
 				0x3a20 0x16 0x0
 				0x3adc 0x0a 0x0
 				0x3878 0x05 0x0
-				0x387c 0x10 0x0
+				0x387c 0xf6 0x0
+				0x3880 0x0e 0x0
 				0x3834 0x0c 0x0
 				0x3830 0x1a 0x0
+				0x3b18 0x7c 0x0
+				0x02d4 0x04 0x0
+				0x0ad4 0x04 0x0
+				0x3a88 0x00 0x0
+				0x3a8c 0x00 0x0
+				0x3a90 0x00 0x0
+				0x3a84 0x3b 0x0
+				0x3b18 0x7f 0x0
+				0x3c38 0x01 0x0
+				0x3aec 0x19 0x0
+				0x3b98 0xf3 0x0
+				0x3b9c 0xe6 0x0
+				0x3ba0 0x5e 0x0
+				0x3ba4 0xec 0x0
+				0x3ba8 0x81 0x0
+				0x3bac 0xf9 0x0
+				0x3bb0 0x3d 0x0
+				0x3a0c 0x08 0x0
+				0x3a1c 0x04 0x0
+				0x3ad4 0x04 0x0
+				0x3ad8 0x00 0x0
+				0x3878 0x05 0x0
+				0x387c 0xf6 0x0
+				0x3880 0x0e 0x0
+				0x3834 0x07 0x0
+				0x3830 0x1f 0x0
+				0x3a84 0x38 0x0
+				0x3b18 0x7c 0x0
+				0x3ba8 0x83 0x0
+				0x3878 0x05 0x0
+				0x387c 0xf6 0x0
+				0x3880 0x0f 0x0
+				0x3a84 0x10 0x0
 				0x241c 0xc1 0x0
 				0x2490 0x00 0x0
 				0x23e0 0x16 0x0
@@ -553,6 +633,10 @@
 				0x255c 0x2e 0x0
 				0x2388 0x99 0x0
 				0x240c 0x1d 0x0
+				0x2e24 0x00 0x0
+				0x2e28 0x00 0x0
+				0x2828 0x00 0x0
+				0x2c28 0x00 0x0
 				0x2200 0x00 0x0
 				0x2244 0x03 0x0>;
 
diff --git a/qcom/lemans-pinctrl.dtsi b/qcom/lemans-pinctrl.dtsi
index 854a8a1f..4d18130d 100755
--- a/qcom/lemans-pinctrl.dtsi
+++ b/qcom/lemans-pinctrl.dtsi
@@ -1606,4 +1606,629 @@
 			};
 		};
 	};
+
+	sec_tdm_sck {
+		sec_tdm_sck_sleep: sec_tdm_sck_sleep {
+			mux {
+				pins = "gpio106";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio106";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		sec_tdm_sck_active: sec_tdm_sck_active {
+			mux {
+				pins = "gpio106";
+				function = "mi2s1_sck";
+			};
+
+			config {
+				pins = "gpio106";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	sec_tdm_ws {
+		sec_tdm_ws_sleep: sec_tdm_ws_sleep {
+			mux {
+				pins = "gpio107";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio107";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		sec_tdm_ws_active: sec_tdm_ws_active {
+			mux {
+				pins = "gpio107";
+				function = "mi2s1_ws";
+			};
+
+			config {
+				pins = "gpio107";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	sec_tdm_din {
+		sec_tdm_din_sleep: sec_tdm_din_sleep {
+			mux {
+				pins = "gpio108";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio108";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		sec_tdm_din_active: sec_tdm_din_active {
+			mux {
+				pins = "gpio108";
+				function = "mi2s1_data0";
+			};
+
+			config {
+				pins = "gpio108";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	sec_tdm_dout {
+		sec_tdm_dout_sleep: sec_tdm_dout_sleep {
+			mux {
+				pins = "gpio109";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio109";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		sec_tdm_dout_active: sec_tdm_dout_active {
+			mux {
+				pins = "gpio109";
+				function = "mi2s1_data1";
+			};
+
+			config {
+				pins = "gpio109";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	tert_tdm_sck {
+		tert_tdm_sck_sleep: tert_tdm_sck_sleep {
+			mux {
+				pins = "gpio110";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio110";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_tdm_sck_active: tert_tdm_sck_active {
+			mux {
+				pins = "gpio110";
+				function = "mi2s2_sck";
+			};
+
+			config {
+				pins = "gpio110";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	tert_tdm_ws {
+		tert_tdm_ws_sleep: tert_tdm_ws_sleep {
+			mux {
+				pins = "gpio111";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio111";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_tdm_ws_active: tert_tdm_ws_active {
+			mux {
+				pins = "gpio111";
+				function = "mi2s2_ws";
+			};
+
+			config {
+				pins = "gpio111";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	tert_tdm_din {
+		tert_tdm_din_sleep: tert_tdm_din_sleep {
+			mux {
+				pins = "gpio112";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio112";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_tdm_din_active: tert_tdm_din_active {
+			mux {
+				pins = "gpio112";
+				function = "mi2s2_data0";
+			};
+
+			config {
+				pins = "gpio112";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	tert_tdm_dout {
+		tert_tdm_dout_sleep: tert_tdm_dout_sleep {
+			mux {
+				pins = "gpio113";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio113";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_tdm_dout_active: tert_tdm_dout_active {
+			mux {
+				pins = "gpio113";
+				function = "mi2s2_data1";
+			};
+
+			config {
+				pins = "gpio113";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs0_i2s_sck {
+		hs0_i2s_sck_sleep: hs0_i2s_sck_sleep {
+			mux {
+				pins = "gpio114";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio114";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs0_i2s_sck_active: hs0_i2s_sck_active {
+			mux {
+				pins = "gpio114";
+				function = "hs0_mi2s";
+			};
+
+			config {
+				pins = "gpio114";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs0_i2s_ws {
+		hs0_i2s_ws_sleep: hs0_i2s_ws_sleep {
+			mux {
+				pins = "gpio115";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio115";
+				drive-strength = <2>;   /* 8 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs0_i2s_ws_active: hs0_i2s_ws_active {
+			mux {
+				pins = "gpio115";
+				function = "hs0_mi2s";
+			};
+
+			config {
+				pins = "gpio115";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs0_i2s_data0 {
+		hs0_i2s_data0_sleep: hs0_i2s_data0_sleep {
+			mux {
+				pins = "gpio116";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio116";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs0_i2s_data0_active: hs0_i2s_data0_active {
+			mux {
+				pins = "gpio116";
+				function = "hs0_mi2s";
+			};
+
+			config {
+				pins = "gpio116";
+				drive-strength = <8>;   /* 2 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	hs0_i2s_data1 {
+		hs0_i2s_data1_sleep: hs0_i2s_data1_sleep {
+			mux {
+				pins = "gpio117";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio117";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs0_i2s_data1_active: hs0_i2s_data1_active {
+			mux {
+				pins = "gpio117";
+				function = "hs0_mi2s";
+			};
+
+			config {
+				pins = "gpio117";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs1_i2s_sck {
+		hs1_i2s_sck_sleep: hs1_i2s_sck_sleep {
+			mux {
+				pins = "gpio118";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio118";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs1_i2s_sck_active: hs1_i2s_sck_active {
+			mux {
+				pins = "gpio118";
+				function = "hs1_mi2s";
+			};
+
+			config {
+				pins = "gpio118";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs1_i2s_ws {
+		hs1_i2s_ws_sleep: hs1_i2s_ws_sleep {
+			mux {
+				pins = "gpio119";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio119";
+				drive-strength = <2>;   /* 8 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs1_i2s_ws_active: hs1_i2s_ws_active {
+			mux {
+				pins = "gpio119";
+				function = "hs1_mi2s";
+			};
+
+			config {
+				pins = "gpio119";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs1_i2s_data0 {
+		hs1_i2s_data0_sleep: hs1_i2s_data0_sleep {
+			mux {
+				pins = "gpio120";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio120";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs1_i2s_data0_active: hs1_i2s_data0_active {
+			mux {
+				pins = "gpio120";
+				function = "hs1_mi2s";
+			};
+
+			config {
+				pins = "gpio120";
+				drive-strength = <8>;   /* 2 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	hs1_i2s_data1 {
+		hs1_i2s_data1_sleep: hs1_i2s_data1_sleep {
+			mux {
+				pins = "gpio121";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio121";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs1_i2s_data1_active: hs1_i2s_data1_active {
+			mux {
+				pins = "gpio121";
+				function = "hs1_mi2s";
+			};
+
+			config {
+				pins = "gpio121";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs2_i2s_sck {
+		hs2_i2s_sck_sleep: hs2_i2s_sck_sleep {
+			mux {
+				pins = "gpio122";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio122";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs2_i2s_sck_active: hs2_i2s_sck_active {
+			mux {
+				pins = "gpio122";
+				function = "hs2_mi2s";
+			};
+
+			config {
+				pins = "gpio122";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs2_i2s_ws {
+		hs2_i2s_ws_sleep: hs2_i2s_ws_sleep {
+			mux {
+				pins = "gpio123";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio123";
+				drive-strength = <2>;   /* 8 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs2_i2s_ws_active: hs2_i2s_ws_active {
+			mux {
+				pins = "gpio123";
+				function = "hs2_mi2s";
+			};
+
+			config {
+				pins = "gpio123";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs2_i2s_data0 {
+		hs2_i2s_data0_sleep: hs2_i2s_data0_sleep {
+			mux {
+				pins = "gpio124";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio124";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs2_i2s_data0_active: hs2_i2s_data0_active {
+			mux {
+				pins = "gpio124";
+				function = "hs2_mi2s";
+			};
+
+			config {
+				pins = "gpio124";
+				drive-strength = <8>;   /* 2 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	hs2_i2s_data1 {
+		hs2_i2s_data1_sleep: hs2_i2s_data1_sleep {
+			mux {
+				pins = "gpio125";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio125";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs2_i2s_data1_active: hs2_i2s_data1_active {
+			mux {
+				pins = "gpio125";
+				function = "hs2_mi2s";
+			};
+
+			config {
+				pins = "gpio125";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	audio_internal_mclk1 {
+		audio_internal_mclk1_sleep: audio_internal_mclk1_sleep {
+			mux {
+				pins = "gpio105";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio105";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+			};
+		};
+
+		audio_internal_mclk1_active: audio_internal_mclk1_active {
+			mux {
+				pins = "gpio105";
+				function = "mi2s_mclk0";
+			};
+
+			config {
+				pins = "gpio105";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
 };
diff --git a/qcom/lemans-qupv3.dtsi b/qcom/lemans-qupv3.dtsi
index 366f8b9b..1e09942d 100755
--- a/qcom/lemans-qupv3.dtsi
+++ b/qcom/lemans-qupv3.dtsi
@@ -7,7 +7,7 @@
 		qcom,msm-bus,vectors-bus-ids =
 			<MASTER_QUP_CORE_0 SLAVE_QUP_CORE_0>,
 			<MASTER_QUP_0 SLAVE_EBI1>;
-		iommus = <&apps_smmu 0x417 0x0>;
+		iommus = <&apps_smmu 0x403 0x0>;
 		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
 		qcom,iommu-geometry = <0x40000000 0x10000000>;
 		qcom,iommu-dma = "fastmap";
@@ -22,7 +22,7 @@
 		qcom,msm-bus,vectors-bus-ids =
 			<MASTER_QUP_CORE_1 SLAVE_QUP_CORE_1>,
 			<MASTER_QUP_1 SLAVE_EBI1>;
-		iommus = <&apps_smmu 0x457 0x0>;
+		iommus = <&apps_smmu 0x443 0x0>;
 		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
 		qcom,iommu-geometry = <0x40000000 0x10000000>;
 		qcom,iommu-dma = "fastmap";
@@ -37,7 +37,7 @@
 		qcom,msm-bus,vectors-bus-ids =
 			<MASTER_QUP_CORE_2 SLAVE_QUP_CORE_2>,
 			<MASTER_QUP_2 SLAVE_EBI1>;
-		iommus = <&apps_smmu 0x5b7 0x0>;
+		iommus = <&apps_smmu 0x5a3 0x0>;
 		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
 		qcom,iommu-geometry = <0x40000000 0x10000000>;
 		qcom,iommu-dma = "fastmap";
@@ -52,7 +52,7 @@
 		qcom,msm-bus,vectors-bus-ids =
 			<MASTER_QUP_CORE_3 SLAVE_QUP_CORE_3>,
 			<MASTER_QUP_3 SLAVE_EBI1>;
-		iommus = <&apps_smmu 0x57 0x0>;
+		iommus = <&apps_smmu 0x43 0x0>;
 		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
 		qcom,iommu-geometry = <0x40000000 0x10000000>;
 		qcom,iommu-dma = "fastmap";
diff --git a/qcom/lemans-thermal-overlay.dtsi b/qcom/lemans-thermal-overlay.dtsi
index 1d6f92b8..652887e4 100755
--- a/qcom/lemans-thermal-overlay.dtsi
+++ b/qcom/lemans-thermal-overlay.dtsi
@@ -1,6 +1,16 @@
 #include <dt-bindings/thermal/thermal_qti.h>
 
 &thermal_zones {
+	pm8775_1_tz {
+		cooling-maps {
+			pm8775_1_gpu {
+				trip = <&pm8775_1_trip0>;
+				cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
+							THERMAL_MAX_LIMIT>;
+			};
+		};
+	};
+
 	pm8775_2_tz {
 		cooling-maps {
 			pm8775_2_cdsp0 {
diff --git a/qcom/lemans-thermal.dtsi b/qcom/lemans-thermal.dtsi
index 7d5d7760..d3f23406 100755
--- a/qcom/lemans-thermal.dtsi
+++ b/qcom/lemans-thermal.dtsi
@@ -82,6 +82,10 @@
 	};
 };
 
+&msm_gpu {
+	#cooling-cells = <2>;
+};
+
 &cpufreq_hw {
 	qcom,cpu-isolation {
 		compatible = "qcom,cpu-isolate";
@@ -280,14 +284,14 @@
 	};
 
 	gpuss-0-step {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-governor = "step_wise";
 		thermal-sensors = <&tsens0 5>;
 		trips {
 			gpuss0_config: gpuss0-config {
-				temperature = <110000>;
-				hysteresis = <10000>;
+				temperature = <105000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
@@ -297,17 +301,25 @@
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			gpu0_cdev {
+				trip = <&gpuss0_config>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	gpuss-1-step {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-governor = "step_wise";
 		thermal-sensors = <&tsens0 6>;
 		trips {
 			gpuss1_config: gpuss1-config {
-				temperature = <110000>;
-				hysteresis = <10000>;
+				temperature = <105000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
@@ -317,17 +329,25 @@
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			gpu1_cdev {
+				trip = <&gpuss1_config>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	gpuss-2-step {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-governor = "step_wise";
 		thermal-sensors = <&tsens0 7>;
 		trips {
 			gpuss2_config: gpuss2-config {
-				temperature = <110000>;
-				hysteresis = <10000>;
+				temperature = <105000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
@@ -337,6 +357,14 @@
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			gpu2_cdev {
+				trip = <&gpuss2_config>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	cpu-0-0-1-step {
@@ -448,14 +476,14 @@
 	};
 
 	gpuss-3-step {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-governor = "step_wise";
 		thermal-sensors = <&tsens1 5>;
 		trips {
 			gpuss3_config: gpuss3-config {
-				temperature = <110000>;
-				hysteresis = <10000>;
+				temperature = <105000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
@@ -465,17 +493,25 @@
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			gpu3_cdev {
+				trip = <&gpuss3_config>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	gpuss-4-step {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-governor = "step_wise";
 		thermal-sensors = <&tsens1 6>;
 		trips {
 			gpuss4_config: gpuss4-config {
-				temperature = <110000>;
-				hysteresis = <10000>;
+				temperature = <105000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
@@ -485,17 +521,25 @@
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			gpu4_cdev {
+				trip = <&gpuss4_config>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	gpuss-5-step {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-governor = "step_wise";
 		thermal-sensors = <&tsens1 7>;
 		trips {
 			gpuss5_config: gpuss5-config {
-				temperature = <110000>;
-				hysteresis = <10000>;
+				temperature = <105000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
@@ -505,6 +549,14 @@
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			gpu5_cdev {
+				trip = <&gpuss5_config>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	cpu-1-0-0-step {
@@ -616,14 +668,14 @@
 	};
 
 	nsp-0-0-0-step {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-governor = "step_wise";
 		thermal-sensors = <&tsens2 5>;
 		trips {
 			nsp000_config: nsp000-config {
 				temperature = <105000>;
-				hysteresis = <10000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
@@ -644,14 +696,14 @@
 	};
 
 	nsp-0-1-0-step {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-governor = "step_wise";
 		thermal-sensors = <&tsens2 6>;
 		trips {
 			nsp010_config: nsp010-config {
 				temperature = <105000>;
-				hysteresis = <10000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
@@ -672,14 +724,14 @@
 	};
 
 	nsp-0-2-0-step {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-governor = "step_wise";
 		thermal-sensors = <&tsens2 7>;
 		trips {
 			nsp020_config: nsp020-config {
 				temperature = <105000>;
-				hysteresis = <10000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
@@ -700,14 +752,14 @@
 	};
 
 	nsp-1-0-0-step {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-governor = "step_wise";
 		thermal-sensors = <&tsens2 8>;
 		trips {
 			nsp100_config: nsp100-config {
 				temperature = <105000>;
-				hysteresis = <10000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
@@ -728,14 +780,14 @@
 	};
 
 	nsp-1-1-0-step {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-governor = "step_wise";
 		thermal-sensors = <&tsens2 9>;
 		trips {
 			nsp110_config: nsp110-config {
 				temperature = <105000>;
-				hysteresis = <10000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
@@ -756,14 +808,14 @@
 	};
 
 	nsp-1-2-0-step {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-governor = "step_wise";
 		thermal-sensors = <&tsens2 10>;
 		trips {
 			nsp120_config: nsp120-config {
 				temperature = <105000>;
-				hysteresis = <10000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
@@ -892,14 +944,14 @@
 	};
 
 	nsp-0-0-1-step {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-governor = "step_wise";
 		thermal-sensors = <&tsens3 5>;
 		trips {
 			nsp001_config: nsp001-config {
 				temperature = <105000>;
-				hysteresis = <10000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
@@ -920,14 +972,14 @@
 	};
 
 	nsp-0-1-1-step {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-governor = "step_wise";
 		thermal-sensors = <&tsens3 6>;
 		trips {
 			nsp011_config: nsp011-config {
 				temperature = <105000>;
-				hysteresis = <10000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
@@ -948,14 +1000,14 @@
 	};
 
 	nsp-0-2-1-step {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-governor = "step_wise";
 		thermal-sensors = <&tsens3 7>;
 		trips {
 			nsp021_config: nsp021-config {
 				temperature = <105000>;
-				hysteresis = <10000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
@@ -976,14 +1028,14 @@
 	};
 
 	nsp-1-0-1-step {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-governor = "step_wise";
 		thermal-sensors = <&tsens3 8>;
 		trips {
 			nsp101_config: nsp101-config {
 				temperature = <105000>;
-				hysteresis = <10000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
@@ -1004,14 +1056,14 @@
 	};
 
 	nsp-1-1-1-step {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-governor = "step_wise";
 		thermal-sensors = <&tsens3 9>;
 		trips {
 			nsp111_config: nsp111-config {
 				temperature = <105000>;
-				hysteresis = <10000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
@@ -1032,14 +1084,14 @@
 	};
 
 	nsp-1-2-1-step {
-		polling-delay-passive = <0>;
+		polling-delay-passive = <10>;
 		polling-delay = <0>;
 		thermal-governor = "step_wise";
 		thermal-sensors = <&tsens3 10>;
 		trips {
 			nsp121_config: nsp121-config {
 				temperature = <105000>;
-				hysteresis = <10000>;
+				hysteresis = <5000>;
 				type = "passive";
 			};
 
diff --git a/qcom/lemans-vm.dtsi b/qcom/lemans-vm.dtsi
index 081cee49..8a4c2fba 100755
--- a/qcom/lemans-vm.dtsi
+++ b/qcom/lemans-vm.dtsi
@@ -1,3 +1,4 @@
+#include <dt-bindings/interconnect/qcom,lemans.h>
 #include "quin-vm-common.dtsi"
 
 / {
@@ -7,17 +8,278 @@
 };
 
 &soc {
+	tlmm: pinctrl@f000000 {
+		compatible = "qcom,lemans-pinctrl";
+		reg = <0xf000000 0x1000000>;
+		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	apps_smmu: apps-smmu@15000000 {
+		compatible = "qcom,qsmmu-v500";
+		reg = <0x15000000 0x100000>,
+			<0x15182000 0x28>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,skip-init;
+		qcom,use-3-lvl-tables;
+		#global-interrupts = <2>;
+		#size-cells = <1>;
+		#address-cells = <1>;
+		#tcu-testbus-version = <1>;
+		ranges;
+		interrupts =	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	virtio_icc: virtio_icc@0x1cc00000 {
+		compatible = "virtio,mmio";
+		reg = <0x1cc00000 0x1000>;
+		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+		#interconnect-cells = <1>;
+
+		xm_usb3_0 {
+			node-name = "usb3_0";
+			node-id = /bits/ 16 <MASTER_USB3_0>;
+			node-num-links = /bits/ 16 <1>;
+			node-links = /bits/ 16 <SLAVE_EBI1>;
+		};
+
+		qhm_pcie_0 {
+			node-name = "pcie_0";
+			node-id = /bits/ 16 <MASTER_PCIE_0>;
+			node-num-links = /bits/ 16 <1>;
+			node-links = /bits/ 16 <SLAVE_EBI1>;
+		};
+
+		qhm_pcie_1 {
+			node-name = "pcie_1";
+			node-id = /bits/ 16 <MASTER_PCIE_1>;
+			node-num-links = /bits/ 16 <1>;
+			node-links = /bits/ 16 <SLAVE_EBI1>;
+		};
+
+		ebi {
+			node-name = "ebi1";
+			node-id = /bits/ 16 <SLAVE_EBI1>;
+			node-num-links = /bits/ 16 <0>;
+		};
+
+		chm_apps {
+			node-name = "appss_proc";
+			node-id = /bits/ 16 <MASTER_APPSS_PROC>;
+			node-num-links = /bits/ 16 <1>;
+			node-links = /bits/ 16 <SLAVE_USB3_0>;
+		};
+
+		qhs_usb3_0 {
+			node-name = "usb3_0";
+			node-id = /bits/ 16 <SLAVE_USB3_0>;
+			node-num-links = /bits/ 16 <0>;
+		};
+	};
+
+	pcie_0_pipe_clk: pcie_0_pipe_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <1000>;
+		clock-output-names = "pcie_0_pipe_clk";
+		#clock-cells = <0>;
+	};
+
+	pcie_1_pipe_clk: pcie_1_pipe_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <1000>;
+		clock-output-names = "pcie_1_pipe_clk";
+		#clock-cells = <0>;
+	};
+
+	rpmh_cxo_clk: rpmh_cxo_clk {
+		compatible = "qcom,dummycc";
+		clock-output-names = "bi_tcxo";
+		#clock-cells = <0>;
+	};
 };
 
-&gcc {
-	status = "disabled";
+&regulator {
+	gcc_usb30_prim_gdsc: gcc_usb30_prim_gdsc {
+		regulator-name = "gcc_usb30_prim_gdsc";
+	};
+
+	gcc_pcie_0_gdsc: gcc_pcie_0_gdsc {
+		regulator-name = "gcc_pcie_0_gdsc";
+	};
+
+	gcc_pcie_1_gdsc: gcc_pcie_1_gdsc {
+		regulator-name = "gcc_pcie_1_gdsc";
+	};
+
+	L5A: pm8775_a_l5: regulator-pm8775_a-l5 {
+		regulator-name = "ldoa5";
+		regulator-min-microvolt = <870000>;
+		regulator-max-microvolt = <950000>;
+	};
+
+	L7A: pm8775_a_l7: regulator-pm8775_a-l7 {
+		regulator-name = "ldoa7";
+		regulator-min-microvolt = <720000>;
+		regulator-max-microvolt = <950000>;
+	};
+
+	L9A: pm8775_a_l9: regulator-pm8775_a-l9 {
+		regulator-name = "ldoa9";
+		regulator-min-microvolt = <2970000>;
+		regulator-max-microvolt = <3544000>;
+	};
+
+	L1C: pm8775_c_l1: regulator-pm8775_c-l1 {
+		regulator-name = "ldoc1";
+		regulator-min-microvolt = <1140000>;
+		regulator-max-microvolt = <1260000>;
+	};
+
+	L6C: pm8775_c_l6: regulator-pm8775_c-l6 {
+		regulator-name = "ldoc6";
+		regulator-min-microvolt = <1620000>;
+		regulator-max-microvolt = <1980000>;
+	};
 };
 
-&scc {
+&gcc {
 	status = "disabled";
 };
 
-&regulator {
+&scc {
 	status = "disabled";
 };
 
diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi
index eaabd068..f1864b7f 100755
--- a/qcom/lemans.dtsi
+++ b/qcom/lemans.dtsi
@@ -14,6 +14,15 @@
 #include <dt-bindings/soc/qcom,ipcc.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,epss-l3.h>
+#include <dt-bindings/sound/qcom,gpr.h>
+
+#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
+#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
+#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\
+				opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\
+				opp-supported-hw = <ddrtype>;}
+#define DDR_TYPE_LPDDR5		8
 
 / {
 	model = "Qualcomm Technologies, Inc. Lemans";
@@ -32,6 +41,8 @@
 	aliases {
 		serial0 = &qupv3_se10_2uart;
 		ufshc1 = &ufshc_mem; /* Embedded UFS slot */
+		ufshc2 = &ufshc2_mem; /* Embedded 2nd UFS Slot */
+		hsuart0 = &qupv3_se17_4uart;
 	 };
 
 	soc: soc { };
@@ -1377,6 +1388,390 @@
 		};
 	};
 
+	llcc_pmu: llcc-pmu@9095000 {
+		compatible = "qcom,llcc-pmu-ver2";
+		reg = <0x09095000 0x300>;
+		reg-names = "lagg-base";
+	};
+
+	llcc_bw_opp_table: llcc-bw-opp-table {
+		compatible = "operating-points-v2";
+		BW_OPP_ENTRY(  600, 16);
+		BW_OPP_ENTRY(  806, 16);
+		BW_OPP_ENTRY(  933, 16);
+		BW_OPP_ENTRY( 1066, 16);
+	};
+
+	ddr_bw_opp_table: ddr-bw-opp-table {
+		compatible = "operating-points-v2";
+		BW_OPP_ENTRY_DDR(  200, 4, 0x180);
+		BW_OPP_ENTRY_DDR(  451, 4, 0x180);
+		BW_OPP_ENTRY_DDR(  547, 4, 0x180);
+		BW_OPP_ENTRY_DDR(  682, 4, 0x180);
+		BW_OPP_ENTRY_DDR(  768, 4, 0x180);
+		BW_OPP_ENTRY_DDR( 1555, 4, 0x180);
+		BW_OPP_ENTRY_DDR( 1708, 4, 0x180);
+		BW_OPP_ENTRY_DDR( 2093, 4, 0x180);
+		BW_OPP_ENTRY_DDR( 2736, 4, 0x180);
+		BW_OPP_ENTRY_DDR( 3197, 4, 0x180);
+	};
+
+	qoslat_opp_table: qoslat-opp-table {
+		compatible = "operating-points-v2";
+		opp-1 {
+			opp-hz = /bits/ 64 < 1 >;
+		};
+
+		opp-2 {
+			opp-hz = /bits/ 64 < 2 >;
+		};
+	};
+
+	cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw {
+		compatible = "qcom,devfreq-icc";
+		governor = "bw_hwmon";
+		interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
+		qcom,active-only;
+		operating-points-v2 = <&llcc_bw_opp_table>;
+	};
+
+	cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 {
+		compatible = "qcom,bimc-bwmon4";
+		reg = <0x90b6400 0x300>, <0x90b6300 0x200>;
+		reg-names = "base", "global_base";
+		interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,mport = <0>;
+		qcom,hw-timer-hz = <19200000>;
+		qcom,target-dev = <&cpu_cpu_llcc_bw>;
+		qcom,count-unit = <0x10000>;
+	};
+
+	cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw {
+		compatible = "qcom,devfreq-icc-ddr";
+		governor = "bw_hwmon";
+		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
+		qcom,active-only;
+		operating-points-v2 = <&ddr_bw_opp_table>;
+	};
+
+	cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@9091000 {
+		compatible = "qcom,bimc-bwmon5";
+		reg = <0x9091000 0x1000>;
+		reg-names = "base";
+		interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,hw-timer-hz = <19200000>;
+		qcom,target-dev = <&cpu_llcc_ddr_bw>;
+		qcom,count-unit = <0x10000>;
+	};
+
+	cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat {
+		compatible = "qcom,devfreq-icc-l3";
+		reg = <0x18590100 0xa0>;
+		reg-names = "ftbl-base";
+		governor = "mem_latency";
+		interconnects =
+			<&epss_l3_cpu MASTER_EPSS_L3_APPS
+			 &epss_l3_cpu SLAVE_EPSS_L3_CPU0>;
+	};
+
+	cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat {
+		compatible = "qcom,devfreq-icc-l3";
+		reg = <0x18590100 0xa0>;
+		reg-names = "ftbl-base";
+		governor = "mem_latency";
+		interconnects =
+			<&epss_l3_cpu MASTER_EPSS_L3_APPS
+			 &epss_l3_cpu SLAVE_EPSS_L3_CPU1>;
+	};
+
+	cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat {
+		compatible = "qcom,devfreq-icc-l3";
+		reg = <0x18590100 0xa0>;
+		reg-names = "ftbl-base";
+		governor = "mem_latency";
+		interconnects =
+			<&epss_l3_cpu MASTER_EPSS_L3_APPS
+			 &epss_l3_cpu SLAVE_EPSS_L3_CPU2>;
+	};
+
+	cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat {
+		compatible = "qcom,devfreq-icc-l3";
+		reg = <0x18590100 0xa0>;
+		reg-names = "ftbl-base";
+		governor = "mem_latency";
+		interconnects =
+			<&epss_l3_cpu MASTER_EPSS_L3_APPS
+			 &epss_l3_cpu SLAVE_EPSS_L3_CPU3>;
+	};
+
+	cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat {
+		compatible = "qcom,devfreq-icc-l3";
+		reg = <0x18590100 0xa0>;
+		reg-names = "ftbl-base";
+		governor = "mem_latency";
+		interconnects =
+			<&epss_l3_cpu MASTER_EPSS_L3_1_APPS
+			 &epss_l3_cpu SLAVE_EPSS_L3_CPU4>;
+	};
+
+	cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat {
+		compatible = "qcom,devfreq-icc-l3";
+		reg = <0x18590100 0xa0>;
+		reg-names = "ftbl-base";
+		governor = "mem_latency";
+		interconnects =
+			<&epss_l3_cpu MASTER_EPSS_L3_1_APPS
+			 &epss_l3_cpu SLAVE_EPSS_L3_CPU5>;
+	};
+
+	cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat {
+		compatible = "qcom,devfreq-icc-l3";
+		reg = <0x18590100 0xa0>;
+		reg-names = "ftbl-base";
+		governor = "mem_latency";
+		interconnects =
+			<&epss_l3_cpu MASTER_EPSS_L3_1_APPS
+			 &epss_l3_cpu SLAVE_EPSS_L3_CPU6>;
+	};
+
+	cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat {
+		compatible = "qcom,devfreq-icc-l3";
+		reg = <0x18590100 0xa0>;
+		reg-names = "ftbl-base";
+		governor = "mem_latency";
+		interconnects =
+			<&epss_l3_cpu MASTER_EPSS_L3_1_APPS
+			 &epss_l3_cpu SLAVE_EPSS_L3_CPU7>;
+	};
+
+	cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {
+		compatible = "qcom,devfreq-icc";
+		governor = "mem_latency";
+		interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
+		qcom,active-only;
+		operating-points-v2 = <&llcc_bw_opp_table>;
+	};
+
+	cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat {
+		compatible = "qcom,devfreq-icc";
+		governor = "mem_latency";
+		interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
+		qcom,active-only;
+		operating-points-v2 = <&llcc_bw_opp_table>;
+	};
+
+	cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {
+		compatible = "qcom,devfreq-icc-ddr";
+		governor = "mem_latency";
+		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
+		qcom,active-only;
+		operating-points-v2 = <&ddr_bw_opp_table>;
+	};
+
+	cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat {
+		compatible = "qcom,devfreq-icc-ddr";
+		governor = "mem_latency";
+		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
+		qcom,active-only;
+		operating-points-v2 = <&ddr_bw_opp_table>;
+	};
+
+	cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {
+		compatible = "qcom,devfreq-icc-ddr";
+		governor = "compute";
+		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
+		qcom,active-only;
+		operating-points-v2 = <&ddr_bw_opp_table>;
+	};
+
+	cpu4_cpu_llcc_latfloor: qcom,cpu4-cpu-llcc-latfloor {
+		compatible = "qcom,devfreq-icc";
+		governor = "compute";
+		interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
+		qcom,active-only;
+		operating-points-v2 = <&llcc_bw_opp_table>;
+	};
+
+	cpu4_cpu_ddr_qoslat: qcom,cpu4-cpu-ddr-qoslat {
+		compatible = "qcom,devfreq-qoslat";
+		governor = "mem_latency";
+		operating-points-v2 = <&qoslat_opp_table>;
+		mboxes = <&qmp_aop 0>;
+	};
+
+	cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl {
+		qcom,core-dev-table =
+			< 1286400 1094400000 >;
+	};
+
+	cpu4_cpu_l3_tbl: qcom,cpu4-cpu-l3-tbl {
+		qcom,core-dev-table =
+			< 1286400 1094400000 >;
+	};
+
+	memlat_cpugrp: qcom,memlat-cpugrp {
+		compatible = "qcom,arm-memlat-cpugrp";
+		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3
+				&CPU4 &CPU5 &CPU6 &CPU7>;
+
+		cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {
+			compatible = "qcom,arm-memlat-mon";
+			qcom,cpulist = <&CPU0>;
+			qcom,target-dev = <&cpu0_cpu_l3_lat>;
+			qcom,cachemiss-ev = <0x17>;
+			qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
+		};
+
+		cpu1_cpu_l3_latmon: qcom,cpu1-cpu-l3-latmon {
+			compatible = "qcom,arm-memlat-mon";
+			qcom,cpulist = <&CPU1>;
+			qcom,target-dev = <&cpu1_cpu_l3_lat>;
+			qcom,cachemiss-ev = <0x17>;
+			qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
+		};
+
+		cpu2_cpu_l3_latmon: qcom,cpu2-cpu-l3-latmon {
+			compatible = "qcom,arm-memlat-mon";
+			qcom,cpulist = <&CPU2>;
+			qcom,target-dev = <&cpu2_cpu_l3_lat>;
+			qcom,cachemiss-ev = <0x17>;
+			qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
+		};
+
+		cpu3_cpu_l3_latmon: qcom,cpu3-cpu-l3-latmon {
+			compatible = "qcom,arm-memlat-mon";
+			qcom,cpulist = <&CPU3>;
+			qcom,target-dev = <&cpu3_cpu_l3_lat>;
+			qcom,cachemiss-ev = <0x17>;
+			qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
+		};
+
+
+		cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {
+			compatible = "qcom,arm-memlat-mon";
+			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+			qcom,target-dev = <&cpu0_cpu_llcc_lat>;
+			qcom,cachemiss-ev = <0x2A>;
+			qcom,core-dev-table =
+				< 1268000 MHZ_TO_MBPS(  600, 16) >,
+				< 1632000 MHZ_TO_MBPS(  806, 16) >,
+				< 2112000 MHZ_TO_MBPS(  933, 16) >,
+				< 2362000 MHZ_TO_MBPS( 1066, 16) >;
+		};
+
+		cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {
+			compatible = "qcom,arm-memlat-mon";
+			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+			qcom,target-dev = <&cpu0_llcc_ddr_lat>;
+			qcom,cachemiss-ev = <0x1000>;
+
+			ddr-map {
+				qcom,ddr-type = <DDR_TYPE_LPDDR5>;
+				qcom,core-dev-table =
+					< 1268000 MHZ_TO_MBPS(  768, 4) >,
+					< 1632000 MHZ_TO_MBPS( 2092, 4) >,
+					< 2112000 MHZ_TO_MBPS( 2736, 4) >,
+					< 2362000 MHZ_TO_MBPS( 3196, 4) >;
+			};
+		};
+
+		cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon {
+			compatible = "qcom,arm-memlat-mon";
+			qcom,cpulist = <&CPU4>;
+			qcom,target-dev = <&cpu4_cpu_l3_lat>;
+			qcom,cachemiss-ev = <0x17>;
+			qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;
+		};
+
+		cpu5_cpu_l3_latmon: qcom,cpu5-cpu-l3-latmon {
+			compatible = "qcom,arm-memlat-mon";
+			qcom,cpulist = <&CPU5>;
+			qcom,target-dev = <&cpu5_cpu_l3_lat>;
+			qcom,cachemiss-ev = <0x17>;
+			qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;
+		};
+
+		cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon {
+			compatible = "qcom,arm-memlat-mon";
+			qcom,cpulist = <&CPU6>;
+			qcom,target-dev = <&cpu6_cpu_l3_lat>;
+			qcom,cachemiss-ev = <0x17>;
+			qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;
+		};
+
+		cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon {
+			compatible = "qcom,arm-memlat-mon";
+			qcom,cpulist = <&CPU7>;
+			qcom,target-dev = <&cpu7_cpu_l3_lat>;
+			qcom,cachemiss-ev = <0x17>;
+			qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;
+		};
+
+		cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon {
+			compatible = "qcom,arm-memlat-mon";
+			qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+			qcom,target-dev = <&cpu4_cpu_llcc_lat>;
+			qcom,cachemiss-ev = <0x2A>;
+			qcom,core-dev-table =
+				< 1268000 MHZ_TO_MBPS(  600, 16) >,
+				< 1632000 MHZ_TO_MBPS(  806, 16) >,
+				< 2112000 MHZ_TO_MBPS(  933, 16) >,
+				< 2362000 MHZ_TO_MBPS( 1066, 16) >;
+		};
+
+		cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon {
+			compatible = "qcom,arm-memlat-mon";
+			qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+			qcom,target-dev = <&cpu4_llcc_ddr_lat>;
+			qcom,cachemiss-ev = <0x1000>;
+
+			ddr-map {
+				qcom,ddr-type = <DDR_TYPE_LPDDR5>;
+				qcom,core-dev-table =
+					< 1268000 MHZ_TO_MBPS(  768, 4) >,
+					< 1632000 MHZ_TO_MBPS( 2092, 4) >,
+					< 2112000 MHZ_TO_MBPS( 2736, 4) >,
+					< 2362000 MHZ_TO_MBPS( 3196, 4) >;
+			};
+		};
+
+		cpu4_computemon: qcom,cpu4-computemon {
+			compatible = "qcom,arm-compute-mon";
+			qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+			qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
+
+			ddr-map {
+				qcom,ddr-type = <DDR_TYPE_LPDDR5>;
+				qcom,core-dev-table =
+					< 1268000 MHZ_TO_MBPS(  768, 4) >,
+					< 1632000 MHZ_TO_MBPS( 2092, 4) >,
+					< 2112000 MHZ_TO_MBPS( 2736, 4) >,
+					< 2362000 MHZ_TO_MBPS( 3196, 4) >;
+			};
+		};
+
+		cpu4_llcc_computemon: qcom,cpu4-llcc-computemon {
+			compatible = "qcom,arm-compute-mon";
+			qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+			qcom,target-dev = <&cpu4_cpu_llcc_latfloor>;
+			qcom,core-dev-table =
+				< 1268000 MHZ_TO_MBPS(  600, 16) >,
+				< 1632000 MHZ_TO_MBPS(  806, 16) >,
+				< 2112000 MHZ_TO_MBPS(  933, 16) >,
+				< 2362000 MHZ_TO_MBPS( 1066, 16) >;
+		};
+
+		cpu4_qoslatmon: qcom,cpu4-qoslatmon {
+			compatible = "qcom,arm-memlat-mon";
+			qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+			qcom,target-dev = <&cpu4_cpu_ddr_qoslat>;
+			qcom,cachemiss-ev = <0x1000>;
+			qcom,core-dev-table =
+				<  300000 1 >,
+				< 3000000 2 >;
+		};
+	};
+
 	ipcc_mproc: qcom,ipcc@408000 {
 		compatible = "qcom,ipcc";
 		reg = <0x408000 0x1000>;
@@ -1496,6 +1891,29 @@
 				qcom,notify-edges = <&glink_gpdsp0>,
 						    <&glink_gpdsp1>;
 			};
+
+			audio_gpr: qcom,gpr {
+				compatible = "qcom,gpr";
+				qcom,glink-channels = "adsp_apps";
+				qcom,intents = <0x200 20>;
+				reg = <GPR_DOMAIN_ADSP>;
+
+				spf_core {
+					compatible = "qcom,spf_core";
+					reg = <GPR_SVC_ADSP_CORE>;
+				};
+
+				audio-pkt {
+					compatible = "qcom,audio-pkt";
+					qcom,audiopkt-ch-name = "apr_audio_svc";
+					reg = <GPR_SVC_MAX>;
+				};
+
+				audio_prm {
+					compatible = "qcom,audio_prm";
+					reg = <GPR_SVC_ASM>;
+				};
+			};
 		};
 
 		glink_cdsp0: cdsp {
@@ -2062,6 +2480,151 @@
 		};
 	};
 
+	ufs2phy_mem: ufsphy2_mem@1da7000 {
+		reg = <0x1da7000 0xe10>;
+		reg-names = "phy_mem";
+		#phy-cells = <0>;
+
+		lanes-per-direction = <2>;
+		clock-names = "ref_clk_src",
+			"ref_clk",
+			"ref_aux_clk";
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_EDP_REF_CLKREF_EN>,
+			<&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
+		resets = <&ufshc2_mem 0>;
+		status = "disabled";
+	};
+
+	ufshc2_mem: ufshc2@1da4000 {
+		compatible = "qcom,ufshc";
+		reg = <0x1da4000 0x3000>;
+		reg-names = "ufs_mem";
+		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+		phys = <&ufs2phy_mem>;
+		phy-names = "ufsphy";
+		#reset-cells = <1>;
+
+		lanes-per-direction = <2>;
+		dev-ref-clk-freq = <0>; /* 19.2 MHz */
+
+		clock-names =
+			"core_clk",
+			"bus_aggr_clk",
+			"iface_clk",
+			"core_clk_unipro",
+			"core_clk_ice",
+			"ref_clk",
+			"tx_lane0_sync_clk",
+			"rx_lane0_sync_clk",
+			"rx_lane1_sync_clk";
+
+		clocks =
+			<&gcc GCC_UFS_CARD_AXI_CLK>,
+			<&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
+			<&gcc GCC_UFS_CARD_AHB_CLK>,
+			<&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
+			<&gcc GCC_UFS_CARD_ICE_CORE_CLK>,
+			<&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
+			<&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
+			<&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
+
+		freq-table-hz =
+			<75000000 300000000>,
+			<0 0>,
+			<0 0>,
+			<75000000 300000000>,
+			<75000000 300000000>,
+			<0 0>,
+			<0 0>,
+			<0 0>,
+			<0 0>;
+
+		interconnects = <&aggre2_noc MASTER_UFS_CARD &mc_virt SLAVE_EBI1>,
+		      <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_CARD_CFG>;
+		interconnect-names = "ufs-ddr", "cpu-ufs";
+
+		qcom,ufs-bus-bw,name = "ufshc_mem";
+		qcom,ufs-bus-bw,num-cases = <26>;
+		qcom,ufs-bus-bw,num-paths = <2>;
+		qcom,ufs-bus-bw,vectors-KBps =
+		/*
+		 * During HS G3 UFS runs at nominal voltage corner, vote
+		 * higher bandwidth to push other buses in the data path
+		 * to run at nominal to achieve max throughput.
+		 * 4GBps pushes BIMC to run at nominal.
+		 * 200MBps pushes CNOC to run at nominal.
+		 * Vote for half of this bandwidth for HS G3 1-lane.
+		 * For max bandwidth, vote high enough to push the buses
+		 * to run in turbo voltage corner.
+		 */
+		<0 0>, <0 0>,          /* No vote */
+		<922 0>, <1000 0>,     /* PWM G1 */
+		<1844 0>, <1000 0>,    /* PWM G2 */
+		<3688 0>, <1000 0>,    /* PWM G3 */
+		<7376 0>, <1000 0>,    /* PWM G4 */
+		<1844 0>, <1000 0>,    /* PWM G1 L2 */
+		<3688 0>, <1000 0>,    /* PWM G2 L2 */
+		<7376 0>, <1000 0>,    /* PWM G3 L2 */
+		<14752 0>, <1000 0>,   /* PWM G4 L2 */
+		<127796 0>, <1000 0>,  /* HS G1 RA */
+		<255591 0>, <1000 0>,  /* HS G2 RA */
+		<1492582 0>, <102400 0>,  /* HS G3 RA */
+		<2915200 0>, <204800 0>,  /* HS G4 RA */
+		<255591 0>, <1000 0>,  /* HS G1 RA L2 */
+		<511181 0>, <1000 0>,  /* HS G2 RA L2 */
+		<1492582 0>, <204800 0>, /* HS G3 RA L2 */
+		<2915200 0>, <409600 0>, /* HS G4 RA L2 */
+		<149422 0>, <1000 0>,  /* HS G1 RB */
+		<298189 0>, <1000 0>,  /* HS G2 RB */
+		<1492582 0>, <102400 0>,  /* HS G3 RB */
+		<2915200 0>, <204800 0>,  /* HS G4 RB */
+		<298189 0>, <1000 0>,  /* HS G1 RB L2 */
+		<596378 0>, <1000 0>,  /* HS G2 RB L2 */
+		/* As UFS working in HS G3 RB L2 mode, aggregated
+		 * bandwidth (AB) should take care of providing
+		 * optimum throughput requested. However, as tested,
+		 * in order to scale up CNOC clock, instantaneous
+		 * bindwidth (IB) needs to be given a proper value too.
+		 */
+		<1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */
+		<2915200 0>, <409600 409600>, /* HS G4 RB L2 */
+		<7643136 0>, <307200 0>; /* Max. bandwidth */
+
+		qcom,bus-vector-names = "MIN",
+		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
+		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
+		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
+		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
+		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
+		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
+		"MAX";
+
+		reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
+
+		resets = <&gcc GCC_UFS_CARD_BCR>;
+		reset-names = "rst";
+		iommus = <&apps_smmu 0x420 0x0>;
+		qcom,iommu-dma = "fastmap";
+		dma-coherent;
+
+		secondary-storage;
+
+		status = "disabled";
+
+		qos0 {
+			mask = <0xf0>;
+			vote = <44>;
+		};
+
+		qos1 {
+			mask = <0x0f>;
+			vote = <44>;
+		};
+
+	};
+
 	mtl_rx_setup: rx-queues-config {
 		snps,rx-queues-to-use = <1>;
 		snps,rx-sched-sp;
@@ -2249,6 +2812,7 @@
 #include "lemans-usb.dtsi"
 #include "lemans-smp2p.dtsi"
 #include "lemans-pm.dtsi"
+#include "lemans-audio.dtsi"
 
 &cam_cc_titan_top_gdsc {
 	reg = <0xadf31bc 0x4>;
@@ -2487,6 +3051,37 @@
 	status = "ok";
 };
 
-#include "lemans-thermal.dtsi"
+&ufs2phy_mem {
+	compatible = "qcom,ufs-phy-qmp-v4-waipio";
+
+	vdda-phy-supply = <&L4A>;
+	vdda-pll-supply = <&L1C>;
+	vdda-phy-max-microamp = <137000>;
+	vdda-pll-max-microamp = <18300>;
+
+	status = "ok";
+};
+
+&ufshc2_mem {
+	vdd-hba-supply = <&gcc_ufs_card_gdsc>;
+	vdd-hba-fixed-regulator;
+
+	vcc-supply = <&L8C>;
+	vcc-voltage-level = <2504000 2506000>;
+	vcc-max-microamp = <1100000>;
+
+	vccq-supply = <&L5C>;
+	vccq-max-microamp = <1200000>;
+
+	vccq2-supply = <&S4A>;
+	vccq2-max-microamp = <800000>;
+
+	qcom,vddp-ref-clk-supply = <&L5C>;
+	qcom,vddp-ref-clk-max-microamp = <100>;
+
+	status = "ok";
+};
+
 #include "lemans-pcie.dtsi"
 #include "lemans-gpu.dtsi"
+#include "lemans-thermal.dtsi"
diff --git a/qcom/monaco-amic-audio-overlay.dtsi b/qcom/monaco-amic-audio-overlay.dtsi
index 7f714137..bc7b6eda 100755
--- a/qcom/monaco-amic-audio-overlay.dtsi
+++ b/qcom/monaco-amic-audio-overlay.dtsi
@@ -11,13 +11,13 @@
 				<3 COMP_L 0x1>, <3 COMP_R 0x2>,
 				<4 LO 0x1>, <5 DSD_L 0x1>,
 				<5 DSD_R 0x2>,
-				<7 SWRM_RX_PCM_IN 0x3>;
+				<7 SWRM_TX1_CH1 0x1>, <7 SWRM_TX1_CH2 0x2>;
 	};
 };
 
 &besbev_codec {
 		qcom,swr_ch_map = <0 SPKR_L 0x1 0 LO>,
-				<2 ADC1 0x1 0 SWRM_RX_PCM_IN>, <2 ADC2 0x2 0 SWRM_RX_PCM_IN>;
+				<2 ADC1 0x1 0 SWRM_TX1_CH1>, <2 ADC2 0x2 0 SWRM_TX1_CH2>;
 
 };
 
diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi
index 148df7dd..0c5c6342 100755
--- a/qcom/monaco.dtsi
+++ b/qcom/monaco.dtsi
@@ -1665,6 +1665,18 @@ qcom,msm-adsprpc-mem {
 			qcom,glinkpkt-ch-name = "slate_bt_app";
 			qcom,glinkpkt-dev-name = "glink_pkt_slate_bt_app";
 		};
+
+		qcom,glinkpkt-dcf-bt-ctrl {
+			qcom,glinkpkt-edge = "slate";
+			qcom,glinkpkt-ch-name = "dcf_bt_ctrl";
+			qcom,glinkpkt-dev-name = "glink_pkt_dcf_bt_ctrl";
+			};
+
+		qcom,glinkpkt-dcf-bt-data {
+			qcom,glinkpkt-edge = "slate";
+			qcom,glinkpkt-ch-name = "dcf_bt_data";
+			qcom,glinkpkt-dev-name = "glink_pkt_dcf_bt_data";
+			};
 	};
 
 	qcom,smp2p-modem {
diff --git a/qcom/pm2250.dtsi b/qcom/pm2250.dtsi
index f6a57667..8210ed5b 100755
--- a/qcom/pm2250.dtsi
+++ b/qcom/pm2250.dtsi
@@ -167,6 +167,8 @@
 
 		pm2250_rtc: qcom,pm2250_rtc {
 			compatible = "qcom,pm8941-rtc";
+			reg = <0x6000>, <0x6100>;
+			reg-names = "rtc", "alarm";
 			interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
 		};
 
diff --git a/qcom/prairie-iot-idp.dtsi b/qcom/prairie-iot-idp.dtsi
index a936b0c9..ed8d909a 100755
--- a/qcom/prairie-iot-idp.dtsi
+++ b/qcom/prairie-iot-idp.dtsi
@@ -187,6 +187,21 @@
 	io-channel-names = "chg_type";
 };
 
+&qusb_phy0 {
+	reg = <0x88e2000 0x180>,
+		<0x01fcb250 0x4>,
+		<0x007801f8 0x4>,
+		<0x01fcb3e4 0x4>;
+	reg-names = "qusb_phy_base",
+		"tcsr_clamp_dig_n_1p8",
+		"tune2_efuse_addr",
+		"tcsr_conn_box_spare_0";
+};
+
+&usb1 {
+	status = "disabled";
+};
+
 &qupv3_se0_2uart {
 	status = "ok";
 };
diff --git a/qcom/qcs610-iot.dtsi b/qcom/qcs610-iot.dtsi
index c69038b0..30abcba1 100755
--- a/qcom/qcs610-iot.dtsi
+++ b/qcom/qcs610-iot.dtsi
@@ -144,8 +144,19 @@
 	status = "okay";
 };
 
+&qusb_phy0 {
+	reg = <0x88e2000 0x180>,
+		<0x01fcb250 0x4>,
+		<0x007801f8 0x4>,
+		<0x01fcb3e4 0x4>;
+	reg-names = "qusb_phy_base",
+		"tcsr_clamp_dig_n_1p8",
+		"tune2_efuse_addr",
+		"tcsr_conn_box_spare_0";
+};
+
 &usb1 {
-	status = "okay";
+	status = "disabled";
 	pinctrl-names = "default";
 	pinctrl-0 = <&usb_typea_host_en>;
 };
diff --git a/qcom/qrb5165-iot-rb5-pine.dts b/qcom/qrb5165-iot-rb5-pine.dts
new file mode 100755
index 00000000..0c869c4d
--- /dev/null
+++ b/qcom/qrb5165-iot-rb5-pine.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "qrb5165-pine.dtsi"
+#include "kona-v2.1-iot-rb5.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. qrb5165 IOT RB5 PINE";
+	compatible = "qcom,kona-iot", "qcom,kona", "qcom,iot";
+	qcom,board-id = <0x01010B 0x03>;
+};
diff --git a/qcom/qrb5165-pine.dtsi b/qcom/qrb5165-pine.dtsi
new file mode 100755
index 00000000..e2f9f9e7
--- /dev/null
+++ b/qcom/qrb5165-pine.dtsi
@@ -0,0 +1,148 @@
+#include "qrb5165.dtsi"
+
+&soc {
+	qcnwlan: qcom,qcn9000@b0000000 {
+		compatible = "qcom,cnss-qcn9000";
+		reg = <0xb0000000 0x10000>,
+		      <0xb2e5510 0x5c0>;
+		reg-names = "smmu_iova_ipa", "tcs_cmd";
+		base-addr = <0xb0000000>;
+		qcom,wlan-rc-num = <2>;
+		qcom,wlan-ramdump-dynamic = <0x420000>;
+		mhi,max-channels = <30>;
+		mhi,timeout = <10000>;
+		qrtr_node_id = <0x20>;
+		status="okay";
+
+		mhi_channels {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mhi_chan@0 {
+				label = "LOOPBACK";
+				mhi,chan-dir = <1>;
+				mhi,data-type = <0>;
+				mhi,doorbell-mode = <2>;
+				mhi,ee = <0x14>;
+				mhi,event-ring = <1>;
+				mhi,num-elements = <32>;
+				reg = <0>;
+			};
+
+			mhi_chan@1 {
+				label = "LOOPBACK";
+				mhi,chan-dir = <2>;
+				mhi,data-type = <0>;
+				mhi,doorbell-mode = <2>;
+				mhi,ee = <0x14>;
+				mhi,event-ring = <1>;
+				mhi,num-elements = <32>;
+				reg = <1>;
+			};
+
+			mhi_chan@20 {
+				label = "IPCR";
+				mhi,auto-start;
+				mhi,chan-dir = <1>;
+				mhi,data-type = <1>;
+				mhi,doorbell-mode = <2>;
+				mhi,ee = <0x14>;
+				mhi,event-ring = <1>;
+				mhi,num-elements = <32>;
+				reg = <20>;
+			};
+
+			mhi_chan@21 {
+				label = "IPCR";
+				mhi,auto-queue;
+				mhi,auto-start;
+				mhi,chan-dir = <2>;
+				mhi,data-type = <0>;
+				mhi,doorbell-mode = <2>;
+				mhi,ee = <0x14>;
+				mhi,event-ring = <1>;
+				mhi,num-elements = <32>;
+				reg = <21>;
+			};
+
+			mhi_chan@4 {
+				label = "DIAG";
+				mhi,chan-dir = <1>;
+				mhi,data-type = <0>;
+				mhi,doorbell-mode = <2>;
+				mhi,ee = <0x14>;
+				mhi,event-ring = <1>;
+				mhi,num-elements = <32>;
+				reg = <4>;
+			};
+
+			mhi_chan@5 {
+				label = "DIAG";
+				mhi,chan-dir = <2>;
+				mhi,data-type = <0>;
+				mhi,doorbell-mode = <2>;
+				mhi,ee = <0x14>;
+				mhi,event-ring = <1>;
+				mhi,num-elements = <32>;
+				reg = <5>;
+			};
+		};
+
+		mhi_events {
+			mhi_event@0 {
+				mhi,brstmode = <2>;
+				mhi,data-type = <1>;
+				mhi,intmod = <1>;
+				mhi,msi = <1>;
+				mhi,num-elements = <32>;
+				mhi,priority = <1>;
+			};
+
+			mhi_event@1 {
+				mhi,brstmode = <2>;
+				mhi,intmod = <1>;
+				mhi,msi = <2>;
+				mhi,num-elements = <256>;
+				mhi,priority = <1>;
+			};
+		};
+
+		mhi_devices {
+			mhi_qrtr {
+				mhi,chan = "IPCR";
+				qcom,net-id = <0>;
+			};
+		};
+	};
+};
+
+&pcie0_rp {
+	/delete-node/ cnss_pci;
+};
+
+&pcie2_rp {
+	#address-cells = <5>;
+	#size-cells = <0>;
+	status = "ok";
+
+	/delete-node/ qcom,mhi@0;
+
+	cnss2_pci: cnss2_pci {
+		reg = <0 0 0 0 0>;
+		qcom,iommu-group = <&cnss2_pci_iommu_group>;
+		memory-region = <&cnss_wlan_mem>;
+		qrtr_instance_id = <0x20>;
+		status = "ok";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cnss2_pci_iommu_group: cnss2_pci_iommu_group {
+			qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
+			qcom,iommu-dma = "fastmap";
+			qcom,iommu-pagetable = "coherent";
+			qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE",
+					    "non-fatal";
+		};
+	};
+};
diff --git a/qcom/qrb5165m-iot-rb5-pine.dts b/qcom/qrb5165m-iot-rb5-pine.dts
new file mode 100755
index 00000000..4541066a
--- /dev/null
+++ b/qcom/qrb5165m-iot-rb5-pine.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "qrb5165.dtsi"
+#include "qrb5165m-iot-rb5-pine.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. QRB5165M IOT RB5 PINE";
+	compatible = "qcom,kona-iot", "qcom,kona", "qcom,iot";
+	qcom,board-id = <0x04010B 0x03>;
+};
diff --git a/qcom/qrb5165m-iot-rb5-pine.dtsi b/qcom/qrb5165m-iot-rb5-pine.dtsi
new file mode 100755
index 00000000..d1dfc51e
--- /dev/null
+++ b/qcom/qrb5165m-iot-rb5-pine.dtsi
@@ -0,0 +1,2 @@
+#include "kona-v2.1-iot-rb5.dtsi"
+
diff --git a/qcom/sa415m-pm.dtsi b/qcom/sa415m-pm.dtsi
new file mode 100755
index 00000000..ac0fbde0
--- /dev/null
+++ b/qcom/sa415m-pm.dtsi
@@ -0,0 +1,104 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+	qcom,lpm-levels {
+		compatible = "qcom,lpm-levels";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,pm-cluster@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			idle-state-name = "system";
+			qcom,psci-mode-shift = <0>;
+			qcom,psci-mode-mask = <0xf>;
+
+			CX_ACTIVE: qcom,pm-cluster-level@0 {
+				reg = <0>;
+				idle-state-name = "cx-active";
+				compatible = "arm,idle-state";
+				qcom,psci-mode = <0>;
+				arm,psci-suspend-param = <0x40000004>;
+				entry-latency-us = <230>;
+				exit-latency-us = <270>;
+				min-residency-us = <6488>;
+			};
+
+			CX_MIN: qcom,pm-cluster-level@1 {/* C8=>XO off in f/w */
+				reg = <1>;
+				idle-state-name = "cx-min";
+				compatible = "arm,idle-state";
+				qcom,psci-mode = <0x4>;
+				arm,psci-suspend-param = <0x40000008>;
+				entry-latency-us = <255>;
+				exit-latency-us = <285>;
+				min-residency-us = <8000>;
+				local-timer-stop;
+				qcom,min-child-idx = <2>;
+				qcom,notify-rpm;
+				qcom,is-reset;
+			};
+
+			qcom,pm-cpu@0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				qcom,psci-mode-shift = <0>;
+				qcom,psci-mode-mask = <0xf>;
+				qcom,disable-ipi-prediction;
+				qcom,cpu = <&CPU0>;
+
+				qcom,pm-cpu-level@0 {
+					reg = <0>;
+					idle-state-name = "wfi";
+					compatible = "arm,idle-state";
+					qcom,psci-cpu-mode = <0x1>;
+					arm,psci-suspend-param = <0x1>;
+					entry-latency-us = <24>;
+					exit-latency-us = <1>;
+					min-residency-us = <419>;
+				};
+
+				A7_SPC: qcom,pm-cpu-level@1 {/* C3 */
+					reg = <1>;
+					idle-state-name ="standalone-pc";
+					compatible = "arm,idle-state";
+					qcom,psci-cpu-mode = <0x3>;
+					arm,psci-suspend-param = <0x40000003>;
+					entry-latency-us = <180>;
+					exit-latency-us = <240>;
+					min-residency-us = <3040>;
+					local-timer-stop;
+					qcom,use-broadcast-timer;
+					qcom,is-reset;
+				};
+
+				A7_PC: qcom,pm-cpu-level@2 { /* C4 */
+					reg = <2>;
+					idle-state-name = "pc";
+					compatible = "arm,idle-state";
+					qcom,psci-cpu-mode = <0x4>;
+					arm,psci-suspend-param = <0x40000004>;
+					entry-latency-us = <230>;
+					exit-latency-us = <270>;
+					min-residency-us = <6488>;
+					local-timer-stop;
+					qcom,use-broadcast-timer;
+					qcom,is-reset;
+				};
+
+			};
+		};
+	};
+
+	rpmh-master-stats@b211200 {
+		compatible = "qcom,rpmh-master-stats-v1";
+		reg = <0xb211200 0x60>;
+	};
+
+	soc-sleep-stats@C370000 {
+		compatible = "qcom,rpmh-sleep-stats";
+		reg = <0xc370000 0x400>;
+	};
+
+};
diff --git a/qcom/sa415m.dtsi b/qcom/sa415m.dtsi
index 16356c8c..ba3effda 100755
--- a/qcom/sa415m.dtsi
+++ b/qcom/sa415m.dtsi
@@ -105,6 +105,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			enable-method = "psci";
+			cpu-idle-states = <&A7_SPC &A7_PC &CX_MIN>;
 			reg = <0x0>;
 			#cooling-cells = <2>;
 		};
@@ -139,6 +140,10 @@
 				  <SLEEP_TCS   2>,
 				  <WAKE_TCS    2>,
 				  <CONTROL_TCS 1>;
+
+		system_pm {
+			compatible = "qcom,system-pm";
+		};
 	};
 
 	intc: interrupt-controller@17800000 {
@@ -173,6 +178,11 @@
 		clock-frequency = <19200000>;
 	};
 
+	qcom,sps {
+		compatible = "qcom,msm-sps-4k";
+		qcom,pipe-attr-ee;
+	};
+
 	timer@17820000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -283,6 +293,12 @@
 		compatible = "qcom,msm-rtb";
 		qcom,rtb-size = <0x100000>;
 	};
+
+	thermal_zones: thermal-zones {
+	};
 };
 
+#include "sdxpoorwills-regulator.dtsi"
 #include "sa415m-pinctrl.dtsi"
+#include "sa415m-pm.dtsi"
+#include "sdxpoorwills-thermal.dtsi"
diff --git a/qcom/sa515m-blsp.dtsi b/qcom/sa515m-blsp.dtsi
index 5abac944..1bc4614d 100755
--- a/qcom/sa515m-blsp.dtsi
+++ b/qcom/sa515m-blsp.dtsi
@@ -24,7 +24,7 @@
 		qcom,summing-threshold = <0x10>;
 	};
 
-	i2c_1: i2c@835000 { /* BLSP1 QUP1 */
+	i2c_1: i2c@835000 { /* BLSP1 QUP1: GPIO: 2,3 */
 		compatible = "qcom,i2c-msm-v2";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -47,7 +47,7 @@
 		status = "disabled";
 	};
 
-	i2c_2: i2c@836000 { /* BLSP1 QUP2 */
+	i2c_2: i2c@836000 { /* BLSP1 QUP2: GPIO: 6,7 */
 		compatible = "qcom,i2c-msm-v2";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -70,7 +70,7 @@
 		status = "disabled";
 	};
 
-	i2c_3: i2c@837000 { /* BLSP1 QUP3 */
+	i2c_3: i2c@837000 { /* BLSP1 QUP3: GPIO: 10,11 */
 		compatible = "qcom,i2c-msm-v2";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -93,7 +93,7 @@
 		status = "ok";
 	};
 
-	i2c_4: i2c@838000 { /* BLSP1 QUP4 */
+	i2c_4: i2c@838000 { /* BLSP1 QUP4: GPIO: 78,79 */
 		compatible = "qcom,i2c-msm-v2";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -116,7 +116,7 @@
 		status = "disabled";
 	};
 
-	i2c_5: i2c@835000 { /* BLSP1 QUP1 */
+	i2c_5: i2cb@835000 { /* BLSP1 QUP1: GPIO: 82,83 */
 		compatible = "qcom,i2c-msm-v2";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -139,7 +139,7 @@
 		status = "disabled";
 	};
 
-	i2c_6: i2c@836000 { /* BLSP1 QUP2 */
+	i2c_6: i2cb@836000 { /* BLSP1 QUP2: GPIO: 65,66 */
 		compatible = "qcom,i2c-msm-v2";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -162,7 +162,7 @@
 		status = "disabled";
 	};
 
-	i2c_7: i2c@838000 { /* BLSP1 QUP3 */
+	i2c_7: i2cb@838000 { /* BLSP1 QUP4: GPIO: 18,19 */
 		compatible = "qcom,i2c-msm-v2";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -178,7 +178,7 @@
 		qcom,clk-freq-in  = <19200000>;
 		clock-names = "iface_clk", "core_clk";
 		clocks = <&gcc GCC_BLSP1_AHB_CLK>,
-			<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+			<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 		pinctrl-names = "i2c_active", "i2c_sleep";
 		pinctrl-0 = <&i2c_7_active>;
 		pinctrl-1 = <&i2c_7_sleep>;
diff --git a/qcom/sa515m-ccard-cnss.dtsi b/qcom/sa515m-ccard-cnss.dtsi
index b048e24d..b1638b4f 100755
--- a/qcom/sa515m-ccard-cnss.dtsi
+++ b/qcom/sa515m-ccard-cnss.dtsi
@@ -315,6 +315,138 @@
 				};
 			};
 		};
+
+		chip_cfg@3 {
+			reg = <0xa0000000 0x10000000>,
+				<0xb0000000 0x10000>;
+			reg-names = "smmu_iova_base", "smmu_iova_ipa";
+
+			supported-ids = <0x1103>;
+			wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1",
+				"vdd-wlan-rfa3";
+
+			qcom,vdd-wlan-aon-info = <1000000 1000000 0 0>;
+			qcom,vdd-wlan-rfa1-info = <1370000 1370000 0 0>;
+			qcom,vdd-wlan-rfa3-info = <1904000 1904000 450000 0>;
+
+			qcom,wlan-ramdump-dynamic = <0x400000>;
+			mhi,max-channels = <30>;
+			mhi,buffer-len = <0x8000>;
+			mhi,timeout = <10000>;
+			qcom,smmu-s1-enable;
+			pcie-disable-l1ss;
+
+			mhi_channels {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				mhi_chan@0 {
+					reg = <0>;
+					label = "LOOPBACK";
+					mhi,num-elements = <32>;
+					mhi,event-ring = <1>;
+					mhi,chan-dir = <1>;
+					mhi,data-type = <0>;
+					mhi,doorbell-mode = <2>;
+					mhi,ee = <0x14>;
+				};
+
+				mhi_chan@1 {
+					reg = <1>;
+					label = "LOOPBACK";
+					mhi,num-elements = <32>;
+					mhi,event-ring = <1>;
+					mhi,chan-dir = <2>;
+					mhi,data-type = <0>;
+					mhi,doorbell-mode = <2>;
+					mhi,ee = <0x14>;
+				};
+
+				mhi_chan@4 {
+					reg = <4>;
+					label = "DIAG";
+					mhi,num-elements = <32>;
+					mhi,event-ring = <1>;
+					mhi,chan-dir = <1>;
+					mhi,data-type = <0>;
+					mhi,doorbell-mode = <2>;
+					mhi,ee = <0x14>;
+				};
+
+				mhi_chan@5 {
+					reg = <5>;
+					label = "DIAG";
+					mhi,num-elements = <32>;
+					mhi,event-ring = <1>;
+					mhi,chan-dir = <2>;
+					mhi,data-type = <0>;
+					mhi,doorbell-mode = <2>;
+					mhi,ee = <0x14>;
+				};
+
+				mhi_chan@20 {
+					reg = <20>;
+					label = "IPCR";
+					mhi,num-elements = <32>;
+					mhi,event-ring = <1>;
+					mhi,chan-dir = <1>;
+					mhi,data-type = <1>;
+					mhi,doorbell-mode = <2>;
+					mhi,ee = <0x14>;
+					mhi,auto-start;
+				};
+
+				mhi_chan@21 {
+					reg = <21>;
+					label = "IPCR";
+					mhi,num-elements = <32>;
+					mhi,event-ring = <1>;
+					mhi,chan-dir = <2>;
+					mhi,data-type = <0>;
+					mhi,doorbell-mode = <2>;
+					mhi,ee = <0x14>;
+					mhi,auto-queue;
+					mhi,auto-start;
+				};
+			};
+
+			mhi_events {
+				mhi_event@0 {
+					mhi,num-elements = <32>;
+					mhi,intmod = <1>;
+					mhi,msi = <1>;
+					mhi,priority = <1>;
+					mhi,brstmode = <2>;
+					mhi,data-type = <1>;
+				};
+
+				mhi_event@1 {
+					mhi,num-elements = <256>;
+					mhi,intmod = <1>;
+					mhi,msi = <2>;
+					mhi,priority = <1>;
+					mhi,brstmode = <2>;
+				};
+
+				mhi_event@2 {
+					mhi,num-elements = <32>;
+					mhi,intmod = <1>;
+					mhi,msi = <0>;
+					mhi,priority = <2>;
+					mhi,brstmode = <2>;
+					mhi,data-type = <3>;
+				};
+
+			};
+
+			mhi_devices {
+				mhi_qrtr {
+					mhi,chan = "IPCR";
+					qcom,net-id = <0>;
+					qcom,low-latency;
+					mhi,early-notify;
+				};
+			};
+		};
 	};
 };
 
diff --git a/qcom/sa515m-ccard-eth-phy-ep.dts b/qcom/sa515m-ccard-eth-phy-ep.dts
new file mode 100755
index 00000000..f055c0f3
--- /dev/null
+++ b/qcom/sa515m-ccard-eth-phy-ep.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "sa515m.dtsi"
+#include "sa515m-ccard.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SA515M CCARD ETH";
+	compatible = "qcom,sa515m-ccard",
+			"qcom,sa515m", "qcom,ccard";
+	qcom,board-id = <0x020019 5>;
+};
diff --git a/qcom/sa515m-v2-ccard-eth-phy-ep.dts b/qcom/sa515m-v2-ccard-eth-phy-ep.dts
new file mode 100755
index 00000000..a1ec4993
--- /dev/null
+++ b/qcom/sa515m-v2-ccard-eth-phy-ep.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "sa515m-v2.dtsi"
+#include "sa515m-ccard.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SA515M CCARD ETH V2 MAC SWT";
+	compatible = "qcom,sa515m-ccard",
+		"qcom,sa515m", "qcom,ccard";
+	qcom,board-id = <0x020019 5>;
+};
diff --git a/qcom/sa515m.dtsi b/qcom/sa515m.dtsi
index 4e01586e..836076d9 100755
--- a/qcom/sa515m.dtsi
+++ b/qcom/sa515m.dtsi
@@ -2,11 +2,15 @@
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
 #include <dt-bindings/interconnect/qcom,sdx55.h>
+#include <dt-bindings/clock/qcom,apsscc-sdxlemur.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 #include <dt-bindings/gpio/gpio.h>
 
+#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
+#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -158,6 +162,53 @@
 		method = "smc";
 	};
 
+	msm_cpufreq: qcom,msm-cpufreq {
+		compatible = "qcom,msm-cpufreq";
+		clocks = <&apsscc APCS_MUX_CLK>;
+		clock-names = "cpu0_clk";
+
+		qcom,cpufreq-table-0 =
+				<  153600 >,
+				<  300000 >,
+				<  345600 >,
+				<  576000 >,
+				<  1094400 >,
+				<  1555200 >;
+	};
+
+	ddr_bw_opp_table: ddr-bw-opp-table {
+		compatible = "operating-points-v2";
+		BW_OPP_ENTRY( 100, 4); /*  381 MB/s */
+		BW_OPP_ENTRY( 200, 4); /*  762 MB/s */
+		BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */
+		BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */
+		BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */
+		BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */
+		BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */
+		BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */
+		BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */
+		BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */
+		BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */
+	};
+
+	cpubw: qcom,cpubw {
+		compatible = "qcom,devfreq-icc";
+		governor = "cpufreq";
+		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
+		qcom,active-only;
+		operating-points-v2 = <&ddr_bw_opp_table>;
+	};
+
+	devfreq-cpufreq {
+		cpubw-cpufreq {
+			target-dev = <&cpubw>;
+			cpu-to-dev-map =
+				<  576000 MHZ_TO_MBPS( 300, 4) >,
+				< 1497600 MHZ_TO_MBPS(1017, 4) >,
+				< 1555200 MHZ_TO_MBPS(1804, 4) >;
+		};
+	};
+
 	apps_rsc: rsc@17830000 {
 		label = "apps_rsc";
 		compatible = "qcom,rpmh-rsc";
@@ -456,6 +507,30 @@
 		qcom,rtb-size = <0x100000>;
 	};
 
+	keepalive_opp_table: keepalive-opp-table {
+		compatible = "operating-points-v2";
+		opp-1 {
+			opp-hz = /bits/ 64 < 1 >;
+		};
+	};
+
+	snoc_pcnoc_keepalive: qcom,snoc_pcnoc_keepalive {
+		compatible = "qcom,devfreq-icc";
+		governor = "powersave";
+		interconnects = <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IMEM_CFG>;
+		qcom,active-only;
+		status = "ok";
+		operating-points-v2 = <&keepalive_opp_table>;
+	};
+
+	ddr_keepalive: qcom,ddr_keepalive {
+		compatible = "qcom,devfreq-icc";
+		governor = "powersave";
+		interconnects = <&mem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>;
+		qcom,active-only;
+		status = "ok";
+		operating-points-v2 = <&keepalive_opp_table>;
+	};
 
 	qnand_1: nand@1b00000 {
 		compatible = "qcom,msm-nand";
@@ -488,8 +563,8 @@
 		reg = <0x8804000 0x1000>;
 		reg-names = "hc_mem";
 
-		interrupts = <GIC_SPI 210 IRQ_TYPE_NONE>,
-			<GIC_SPI 227 IRQ_TYPE_NONE>;
+		interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "hc_irq", "pwr_irq";
 
 		bus-width = <4>;
@@ -609,6 +684,112 @@
 		};
 	};
 
+
+	qcom_tzlog: tz-log@0x1468f720 {
+		compatible = "qcom,tz-log";
+		reg = <0x1468f720 0x2000>;
+	};
+
+	qtee_shmbridge {
+		compatible = "qcom,tee-shared-memory-bridge";
+	};
+
+	qcom_rng: qrng@793000 {
+		compatible = "qcom,msm-rng";
+		reg = <0x793000 0x1000>;
+		qcom,no-qrng-config;
+		qcom,msm-bus,name = "msm-rng-noc";
+		qcom,msm-bus,num-cases = <2>;
+		qcom,msm-bus,num-paths = <1>;
+		qcom,msm-bus,vectors-KBps =
+			<1 618 0 0>,    /* No vote */
+			<1 618 0 300000>;  /* 75 MHz */
+		qcom,no-clock-support;
+	};
+
+	qcom_crypto: qcrypto@1de0000 {
+		compatible = "qcom,qcrypto";
+		reg = <0x1de0000 0x20000>,
+			<0x1dc4000 0x24000>;
+		reg-names = "crypto-base","crypto-bam-base";
+		interrupts = <0 252 0>;
+		qcom,bam-pipe-pair = <2>;
+		qcom,ce-hw-instance = <0>;
+		qcom,ce-device = <0>;
+		qcom,bam-ee = <0>;
+		qcom,ce-hw-shared;
+		qcom,msm-bus,name = "qcrypto-noc";
+		qcom,msm-bus,num-cases = <2>;
+		qcom,msm-bus,num-paths = <1>;
+		qcom,msm-bus,vectors-KBps =
+				<125 512 0 0>,
+				<125 512 393600 393600>;
+		qcom,use-sw-aes-cbc-ecb-ctr-algo;
+		qcom,use-sw-aes-xts-algo;
+		qcom,use-sw-aes-ccm-algo;
+		qcom,use-sw-aead-algo;
+		qcom,use-sw-ahash-algo;
+		qcom,use-sw-hmac-algo;
+		qcom,no-clock-support;
+		qcom,iommu-s1-enable;
+		interconnect-names = "data_path";
+		interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
+		iommus = <&apps_smmu 0x0064 0x0011>,
+			<&apps_smmu 0x0074 0x0011>;
+	};
+
+	qcom_cedev: qcedev@1de0000 {
+		compatible = "qcom,qcedev";
+		reg = <0x1de0000 0x20000>,
+			<0x1dc4000 0x24000>;
+		reg-names = "crypto-base","crypto-bam-base";
+		interrupts = <0 252 0>;
+		qcom,bam-pipe-pair = <3>;
+		qcom,ce-hw-instance = <0>;
+		qcom,ce-device = <0>;
+		qcom,bam-ee = <0>;
+		qcom,ce-hw-shared;
+		qcom,msm-bus,name = "qcedev-noc";
+		qcom,msm-bus,num-cases = <2>;
+		qcom,msm-bus,num-paths = <1>;
+		qcom,msm-bus,vectors-KBps =
+				<125 512 0 0>,
+				<125 512 393600 393600>;
+		qcom,no-clock-support;
+		qcom,iommu-s1-enable;
+		interconnect-names = "data_path";
+		interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
+		iommus = <&apps_smmu 0x0066 0x0011>,
+			<&apps_smmu 0x0076 0x0011>;
+	};
+
+	qcom_seecom: qseecom@90000000 {
+		compatible = "qcom,qseecom";
+		reg = <0x90000000 0x500000>;
+		reg-names = "secapp-region";
+		memory-region = <&qseecom_mem>;
+		qcom,hlos-num-ce-hw-instances = <1>;
+		qcom,hlos-ce-hw-instance = <0>;
+		qcom,qsee-ce-hw-instance = <0>;
+		qcom,no-clock-support;
+		qcom,msm-bus,name = "qseecom-noc";
+		qcom,msm-bus,num-cases = <4>;
+		qcom,msm-bus,num-paths = <1>;
+		qcom,msm-bus,vectors-KBps =
+			<125 512 0 0>,
+			<125 512 20000 40000>,
+			<125 512 30000 80000>,
+			<125 512 40000 100000>;
+		qcom,qsee-reentrancy-support = <2>;
+	};
+
+	qcom_smcinvoke: smcinvoke@90000000 {
+		compatible = "qcom,smcinvoke";
+		qcom,support-legacy_smc;
+		reg = <0x90000000 0x500000>;
+		reg-names = "secapp-region";
+	};
+
 	tcsr_mutex_block: syscon@1f40000 {
 		compatible = "syscon";
 		reg = <0x1f40000 0x20000>;
@@ -960,26 +1141,25 @@
 			snps,dcb-algorithm;
 			snps,map-to-dma-channel = <0x0>;
 			snps,route-up;
-			snps,route-ptp;
-			snps,route-dcbcp;
+			snps,priority = <0x1>;
 		};
 
 		queue1 {
 			snps,dcb-algorithm;
 			snps,map-to-dma-channel = <0x1>;
-			snps,route-avcp;
-			snps,route-multi-broad;
+			snps,route-ptp;
 		};
 
 		queue2 {
 			snps,avb-algorithm;
 			snps,map-to-dma-channel = <0x2>;
+			snps,route-avcp;
 		};
 
 		queue3 {
 			snps,avb-algorithm;
 			snps,map-to-dma-channel = <0x3>;
-			snps,priority = <0x0C>;
+			snps,priority = <0xC>;
 		};
 	};
 
@@ -1023,6 +1203,8 @@
 			<&gcc GCC_ETH_PTP_CLK>,
 			<&gcc GCC_ETH_RGMII_CLK>;
 		clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
+		snps,ptp-ref-clk-rate = <230400000>;
+		snps,ptp-req-clk-rate = <57600000>;
 		interrupts-extended = <&intc 0 62 4>, <&intc 0 60 4>,
 			<&tlmm 90 2>, <&intc 0 290 1>, <&intc 0 291 1>;
 		interrupt-names = "macirq", "eth_lpi",
@@ -1067,6 +1249,7 @@
 			dll-clock-dis = <1>;
 			ddr-traffic-init-sel = <0>;
 			ddr-traffic-init-sw = <0>;
+			rgmii-tx-drv = <1>;
 			};
 		};
 };
diff --git a/qcom/sa8155-vm-audio.dtsi b/qcom/sa8155-vm-audio.dtsi
index 34bc5d4f..f8b9cbc8 100755
--- a/qcom/sa8155-vm-audio.dtsi
+++ b/qcom/sa8155-vm-audio.dtsi
@@ -552,3 +552,11 @@
 	};
 };
 
+&soc {
+	spf_snd_8155: spf-sound-adp-star {
+		compatible = "qcom,8155-spf-asoc-snd-adp-star";
+		qcom,model = "gvmauto-8155-snd-card";
+		asoc-codec = <&stub_codec>;
+		asoc-codec-names = "msm-stub-codec.1";
+	};
+};
diff --git a/qcom/scuba-qrd.dtsi b/qcom/scuba-qrd.dtsi
index a1621464..b06b5766 100755
--- a/qcom/scuba-qrd.dtsi
+++ b/qcom/scuba-qrd.dtsi
@@ -223,7 +223,74 @@
 	status = "ok";
 };
 
+&tlmm {
+	key_vol_up {
+		key_vol_up_default: key_vol_up_default {
+			pins = "gpio96";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+			power-source = <0>;
+		};
+	};
+};
+
 &soc {
+	gpio_keys {
+		compatible = "gpio-keys";
+		label = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&key_vol_up_default>;
+
+		vol_up {
+			label = "volume_up";
+			gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+			linux,input-type = <1>;
+			linux,code = <KEY_VOLUMEUP>;
+			linux,can-disable;
+			debounce-interval = <15>;
+			gpio-key,wakeup;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		wifi_led {
+			label = "wifi-led_yellow";
+			gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		bt_led {
+			label = "bt-led_blue";
+			gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		user_led0 {
+			label = "user-led0_green";
+			gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+
+	pm2250_rg_leds: qcom,rg_leds {
+		compatible = "pwm-leds";
+		user_led1 {
+			label = "user-led1_green";
+			pwms = <&pm2250_pwm1 0 1000000>;
+			max-brightness = <255>;
+		};
+
+		user_led2 {
+			label = "user-led2_green";
+			pwms = <&pm2250_pwm2 0 1000000>;
+			max-brightness = <255>;
+		};
+	};
+
 	clk40M: can_clock {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
diff --git a/qcom/scuba.dtsi b/qcom/scuba.dtsi
index 9356174d..98bedd53 100755
--- a/qcom/scuba.dtsi
+++ b/qcom/scuba.dtsi
@@ -624,7 +624,6 @@
 
 		no-sd;
 		no-sdio;
-		max-frequency = <192000000>;
 
 		qcom,devfreq,freq-table = <50000000 200000000>;
 		qcom,scaling-lower-bus-speed-mode = "DDR52";
diff --git a/qcom/sdxpoorwills-regulator.dtsi b/qcom/sdxpoorwills-regulator.dtsi
new file mode 100755
index 00000000..fcb2fbd0
--- /dev/null
+++ b/qcom/sdxpoorwills-regulator.dtsi
@@ -0,0 +1,390 @@
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/gpio/gpio.h>
+
+&apps_rsc {
+	/* RPMh regulators */
+
+	/* pmxpoorwills S1 - VDD_MODEM supply */
+	rpmh-regulator-modemlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "mss.lvl";
+		VDD_MODEM_LEVEL:
+		S1A_LEVEL: pmxpoorwills_s1_level: regulator-pmxpoorwills-s1 {
+			regulator-name = "pmxpoorwills_s1_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt =
+					<RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+		};
+	};
+
+	rpmh-regulator-smpa4 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "smpa4";
+		S4A: pmxpoorwills_s4: regulator-pmxpoorwills-s4 {
+			 regulator-name = "pmxpoorwills_s4";
+			 qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			 regulator-min-microvolt = <1800000>;
+			 regulator-max-microvolt = <1800000>;
+			 qcom,init-voltage = <1800000>;
+		 };
+	};
+
+	/*  pmxpoorwills S5 - VDD_CX supply */
+	rpmh-regulator-cxlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "cx.lvl";
+		VDD_CX_LEVEL: S5A_LEVEL:
+		pmxpoorwills_s5_level: regulator-pmxpoorwills-s5-level {
+			regulator-name = "pmxpoorwills_s5_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			pmxpoorwills_s5_level-parent-supply = <&pmxpoorwills_l9_level>;
+			regulator-min-microvolt =
+						<RPMH_REGULATOR_LEVEL_LOW_SVS>;
+			regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,min-dropout-voltage-level = <(-1)>;
+		};
+
+		VDD_CX_LEVEL_AO: S5A_LEVEL_AO:
+		pmxpoorwills_s5_level_ao: regulator-pmxpoorwills-s5-level-ao {
+			regulator-name = "pmxpoorwills_s5_level_ao";
+			qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+			pmxpoorwills_s5_level_ao-parent-supply =
+						<&pmxpoorwills_l9_level_ao>;
+			regulator-min-microvolt =
+						<RPMH_REGULATOR_LEVEL_LOW_SVS>;
+			regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+			qcom,min-dropout-voltage-level = <(-1)>;
+		};
+
+		cx_cdev: regulator-cdev {
+			compatible = "qcom,rpmh-reg-cdev";
+			mboxes = <&qmp_aop 0>;
+			qcom,reg-resource-name = "cx";
+			#cooling-cells = <2>;
+		};
+	};
+
+	rpmh-regulator-ldoa1 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoa1";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L1A: pmxpoorwills_l1: regulator-pmxpoorwills-11 {
+			regulator-name = "pmxpoorwills_l1";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			qcom,init-voltage = <1200000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa2 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoa2";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L2A: pmxpoorwills_l2: regulator-pmxpoorwills-12 {
+			 regulator-name = "pmxpoorwills_l2";
+			 qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			 regulator-min-microvolt = <1128000>;
+			 regulator-max-microvolt = <1128000>;
+			 qcom,init-voltage = <1128000>;
+			 qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+		 };
+	};
+
+	rpmh-regulator-ldoa3 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoa3";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L3A: pmxpoorwills_l3: regulator-pmxpoorwills-l3 {
+			regulator-name = "pmxpoorwills_l3";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <800000>;
+			regulator-max-microvolt = <800000>;
+			qcom,init-voltage = <800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa4 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoa4";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L4A: pmxpoorwills_l4: regulator-pmxpoorwills-l4 {
+			regulator-name = "pmxpoorwills_l4";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <872000>;
+			regulator-max-microvolt = <872000>;
+			qcom,init-voltage = <872000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa5 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoa5";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L5A: pmxpoorwills_l5: regulator-pmxpoorwills-l5 {
+			regulator-name = "pmxpoorwills_l5";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1704000>;
+			regulator-max-microvolt = <1704000>;
+			qcom,init-voltage = <1704000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa7 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoa7";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L7A: pmxpoorwills_l7: regulator-pmxpoorwills-l7 {
+			regulator-name = "pmxpoorwills_l7";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2952000>;
+			qcom,init-voltage = <1800000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa8 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoa8";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L8A: pmxpoorwills_l8: regulator-pmxpoorwills-l8 {
+			regulator-name = "pmxpoorwills_l8";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <480000>;
+			regulator-max-microvolt = <900000>;
+			qcom,init-voltage = <480000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	/* pmxpoorwills L9 - VDD_MX supply */
+	rpmh-regulator-mxlvl {
+		compatible = "qcom,rpmh-arc-regulator";
+		qcom,resource-name = "mx.lvl";
+		VDD_MX_LEVEL: L9A_LEVEL:
+		pmxpoorwills_l9_level: regulator-pmxpoorwills-l9-level {
+			regulator-name = "pmxpoorwills_l9_level";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+		};
+
+		VDD_MX_LEVEL_AO: L9A_LEVEL_AO:
+		pmxpoorwills_l9_level_ao: regulator-pmxpoorwills-l9-level-ao {
+			regulator-name = "pmxpoorwills_l9_level_ao";
+			qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+			regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+			regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+		};
+
+		mx_cdev: mx-cdev-lvl {
+			compatible = "qcom,regulator-cooling-device";
+			regulator-cdev-supply = <&VDD_MX_LEVEL>;
+			regulator-levels =
+				<RPMH_REGULATOR_LEVEL_RETENTION
+				 RPMH_REGULATOR_LEVEL_NOM>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	rpmh-regulator-ldoa10 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoa10";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L10A: pmxpoorwills_l10: regulator-pmxpoorwills-l10 {
+			regulator-name = "pmxpoorwills_l10";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			regulator-min-microvolt = <3088000>;
+			regulator-max-microvolt = <3088000>;
+			qcom,init-voltage = <3088000>;
+			qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+		};
+	};
+
+	rpmh-regulator-ldoa11 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoa11";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L11A: pmxpoorwills_l11: regulator-pmxpoorwills-l11 {
+			  regulator-name = "pmxpoorwills_l11";
+			  qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			  regulator-min-microvolt = <1704000>;
+			  regulator-max-microvolt = <3000000>;
+			  qcom,init-voltage = <1704000>;
+			  qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+		  };
+	};
+
+	rpmh-regulator-ldoa12 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoa12";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L12A: pmxpoorwills_l12: regulator-pmxpoorwills-l12 {
+			  regulator-name = "pmxpoorwills_l12";
+			  qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			  regulator-min-microvolt = <2704000>;
+			  regulator-max-microvolt = <2704000>;
+			  qcom,init-voltage = <2704000>;
+			  qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+		  };
+	};
+
+	rpmh-regulator-ldoa13 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoa13";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L13A: pmxpoorwills_l13: regulator-pmxpoorwills-l13 {
+			  regulator-name = "pmxpoorwills_l13";
+			  qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			  regulator-min-microvolt = <1704000>;
+			  regulator-max-microvolt = <3000000>;
+			  qcom,init-voltage = <1704000>;
+			  qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+		  };
+	};
+
+	rpmh-regulator-ldoa14 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoa14";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L14A: pmxpoorwills_l14: regulator-pmxpoorwills-l14 {
+			  regulator-name = "pmxpoorwills_l14";
+			  qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			  regulator-min-microvolt = <600000>;
+			  regulator-max-microvolt = <800000>;
+			  qcom,init-voltage = <600000>;
+			  qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+		  };
+	};
+
+	rpmh-regulator-ldoa16 {
+		compatible = "qcom,rpmh-vrm-regulator";
+		qcom,resource-name = "ldoa16";
+		qcom,regulator-type = "pmic5-ldo";
+		qcom,supported-modes =
+			<RPMH_REGULATOR_MODE_LPM
+			 RPMH_REGULATOR_MODE_HPM>;
+		qcom,mode-threshold-currents = <0 1>;
+		L16A: pmxpoorwills_l16: regulator-pmxpoorwills-l16 {
+			  regulator-name = "pmxpoorwills_l16";
+			  qcom,set = <RPMH_REGULATOR_SET_ALL>;
+			  regulator-min-microvolt = <304000>;
+			  regulator-max-microvolt = <880000>;
+			  qcom,init-voltage = <304000>;
+			  qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+		  };
+	};
+
+	/* VREF_RGMII */
+	rpmh-regulator-rgmii {
+		compatible = "qcom,rpmh-xob-regulator";
+		qcom,resource-name = "vrefa2";
+		vreg_rgmii: regulator-rgmii {
+			regulator-name = "vreg_rgmii";
+			qcom,set = <RPMH_REGULATOR_SET_ALL>;
+		};
+	};
+
+	/* Stub regulators */
+
+	/*
+	 * RPMh does not provide support for pmxpoorwills L6 because it is
+	 * always on at 1.8 V.  Therefore, use a fixed regulator for L6.
+	 */
+	L6A: pmxpoorwills_l6: regulator-pmxpoorwills-l6 {
+		compatible = "regulator-fixed";
+		regulator-name = "pmxpoorwills_l6";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	vreg_sd_mmc: vreg_sd_mmc {
+		compatible = "regulator-fixed";
+		regulator-name = "vreg_sd_mmc";
+		startup-delay-us = <4000>;
+		enable-active-high;
+		gpio = <&tlmm 92 GPIO_ACTIVE_HIGH>;
+	};
+
+	vreg_emac_phy: emac_phy_regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "emac_phy";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-enable-ramp-delay = <100>;
+		gpio = <&tlmm 83 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vreg_rgmii_io_pads: rgmii_io_pads_regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "rgmii_io_pads";
+		regulator-min-microvolt = <2500000>;
+		regulator-max-microvolt = <2500000>;
+		regulator-enable-ramp-delay = <100>;
+		gpio = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vreg_wlan: vreg_wlan {
+		compatible = "regulator-fixed";
+		regulator-name = "vreg_wlan";
+		startup-delay-us = <4000>;
+		enable-active-high;
+	};
+};
diff --git a/qcom/sdxpoorwills-thermal.dtsi b/qcom/sdxpoorwills-thermal.dtsi
new file mode 100755
index 00000000..d6b0e3a7
--- /dev/null
+++ b/qcom/sdxpoorwills-thermal.dtsi
@@ -0,0 +1,176 @@
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/thermal/thermal_qti.h>
+
+&soc {
+	tsens0: tsens@c222000 {
+		compatible = "qcom,tsens24xx";
+		reg = <0xc222000 0x4>,
+		      <0xc263000 0x1ff>;
+		reg-names = "tsens_srot_physical",
+			    "tsens_tm_physical";
+		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "tsens-upper-lower", "tsens-critical";
+		#thermal-sensor-cells = <1>;
+	};
+
+	qmi-tmd-devices {
+		compatible = "qcom,qmi-cooling-devices";
+
+		modem {
+			qcom,instance-id = <QMI_MODEM_INST_ID>;
+
+			modem_pa: modem_pa {
+				qcom,qmi-dev-name = "pa";
+				#cooling-cells = <2>;
+			};
+
+			modem_proc: modem_proc {
+				qcom,qmi-dev-name = "modem";
+				#cooling-cells = <2>;
+			};
+
+			modem_current: modem_current {
+				qcom,qmi-dev-name = "modem_current";
+				#cooling-cells = <2>;
+			};
+
+			modem_skin: modem_skin {
+				qcom,qmi-dev-name = "modem_skin";
+				#cooling-cells = <2>;
+			};
+
+			modem_vdd: modem_vdd {
+				qcom,qmi-dev-name = "cpuv_restriction_cold";
+				#cooling-cells = <2>;
+			};
+		};
+
+		adsp {
+			qcom,instance-id = <QMI_ADSP_INST_ID>;
+
+			adsp_vdd: adsp_vdd {
+				qcom,qmi-dev-name = "cpuv_restriction_cold";
+				#cooling-cells = <2>;
+			};
+		};
+	};
+};
+
+&thermal_zones {
+	aoss-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&tsens0 0>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	mdm-q6-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&tsens0 1>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	ddrss-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&tsens0 2>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&tsens0 3>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	mdm-core-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&tsens0 4>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	mdm-vpe-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&tsens0 5>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	mdm-core-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&tsens0 4>;
+		trips {
+			mdm_step_trip0: mdm-step-trip-0 {
+				temperature = <95000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			mdm_step_trip1: mdm-step-trip-1 {
+				temperature = <105000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			modem_proc-lv11 {
+				trip = <&mdm_step_trip0>;
+				cooling-device = <&modem_proc 1 1>;
+			};
+
+			modem_proc_lvl3 {
+				trip = <&mdm_step_trip1>;
+				cooling-device = <&modem_proc 3 3>;
+			};
+		};
+	};
+};
diff --git a/qcom/slate.dtsi b/qcom/slate.dtsi
index 212b1a78..42cc37c8 100755
--- a/qcom/slate.dtsi
+++ b/qcom/slate.dtsi
@@ -214,6 +214,16 @@
 			qcom,intents = <0xF2F8 1>;
 		};
 
+		qcom,glin-dcf-bt-ctrl {
+			qcom,glink-channels = "dcf_bt_ctrl";
+			qcom,intents = <0x50 1>;
+		};
+
+		qcom,glink-dcf-bt-data {
+			qcom,glink-channels = "dcf_bt_data";
+			qcom,intents = <0x100 1>;
+		};
+
 		audio_ipc: qcom,audio_cc_ipc {
 			compatible = "qcom,audio_cc_ipc";
 			qcom,glink-channels = "gpr_cc_apps";
diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi
index 30852c60..cb3d6e46 100755
--- a/qcom/sm6150.dtsi
+++ b/qcom/sm6150.dtsi
@@ -1674,7 +1674,6 @@
 
 		resets = <&gcc GCC_UFS_PHY_BCR>;
 		reset-names = "rst";
-		non-removable;
 
 		status = "disabled";
 		qos0 {