diff options
| author | QC Publisher <qcpublisher@qti.qualcomm.com> | 2021-10-17 10:01:10 -0700 |
|---|---|---|
| committer | Andrew Evans <andrewevans@google.com> | 2022-02-15 14:56:20 -0800 |
| commit | ae3d046330003c3bea902480d8f0b523970a9b9a (patch) | |
| tree | 6ade780a7bca111628744879314db9be03b2d8be | |
| parent | 3b7ddf8debeeba4acdcabcbb4f42510d55341621 (diff) | |
| download | devicetree-ae3d046330003c3bea902480d8f0b523970a9b9a.tar.gz | |
Commit label r00088.2 - ES2 0.0.088.2
TRACKING-ID:db40d318-f9e4-4d1e-8ac6-41266717b2b8
117 files changed, 7122 insertions, 989 deletions
diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 42134d39..d359053a 100755 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -116,6 +116,9 @@ SoCs: - DIREWOLF compatible = "qcom,direwolf" +- LEMANS + compatible = "qcom,lemans" + Generic board variants: - CDP device: @@ -314,3 +317,6 @@ compatible = "qcom,direwolf-ivi-adp-star" compatible = "qcom,direwolf-adas" compatible = "qcom,direwolf-adas-rumi" compatible = "qcom,direwolf-adas-adp-star" +compatible = "qcom,lemans-rumi" +compatible = "qcom,lemans-adp-air" +compatible = "qcom,lemans-adp-star" diff --git a/bindings/arm/msm/sleepstate-hlos.txt b/bindings/arm/msm/sleepstate-hlos.txt new file mode 100755 index 00000000..38965153 --- /dev/null +++ b/bindings/arm/msm/sleepstate-hlos.txt @@ -0,0 +1,12 @@ +Qualcomm Technologies, Inc. hlos_sleep_state driver using SMSM framework. + +Required properties: +-compatible : should be one of the following: +- "qcom,smp2p-hlos_sleep_state" +-qcom,smem-states : the relevant outgoing smp2p entry + +Example: +qcom,hlos_sleep_state { + compatible = "qcom,smp2p-hlos_sleep_state"; + qcom,smem-states = <&hlos_sleep_state_out 0>; +}; diff --git a/bindings/arm/msm/subsystem-sleep-stats.yaml b/bindings/arm/msm/subsystem-sleep-stats.yaml index 53e03871..3e7c8e5f 100755 --- a/bindings/arm/msm/subsystem-sleep-stats.yaml +++ b/bindings/arm/msm/subsystem-sleep-stats.yaml @@ -23,9 +23,12 @@ properties: Value type: <string> Definition: Should be "qcom,subsystem-sleep-stats". + reg: + maxItems: 1 example: - | subsystem-sleep-stats { compatible = "qcom,subsystem-sleep-stats"; + reg = <0xc3f0000 0 0x400>; }; diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt index 6180b44c..3c2a4e69 100755 --- a/bindings/clock/qcom,gpucc.txt +++ b/bindings/clock/qcom,gpucc.txt @@ -17,6 +17,7 @@ Required properties : "qcom,scuba-gpucc" "qcom,bengal-gpucc" "qcom,direwolf-gpucc" + "qcom,direwolf-gpucc-v2" - reg: shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/bindings/clock/qcom,videocc.txt b/bindings/clock/qcom,videocc.txt index ea3973b0..6cfab423 100755 --- a/bindings/clock/qcom,videocc.txt +++ b/bindings/clock/qcom,videocc.txt @@ -15,6 +15,7 @@ Required properties : "qcom,sm6150-videocc" "qcom,sa6155-videocc" "qcom,direwolf-videocc" + "qcom,direwolf-videocc-v2" - reg : shall contain base register location and length - #clock-cells : from common clock binding, shall contain 1. diff --git a/bindings/interconnect/qcom,scuba.txt b/bindings/interconnect/qcom,scuba.txt new file mode 100755 index 00000000..4ae84f1b --- /dev/null +++ b/bindings/interconnect/qcom,scuba.txt @@ -0,0 +1,45 @@ +QTI SCUBA Network-On-Chip interconnect driver binding +----------------------------------------------------------- + +Required properties : +- compatible : shall contain only one of the following: + "qcom,scuba-bimc", + "qcom,scuba-sys_noc", + "qcom,scuba-config_noc", + "qcom,scuba-clk_virt", + "qcom,scuba-mmnrt_virt", + "qcom,scuba-mmrt_virt", +- #interconnect-cells : should contain 1 + +reg : specifies the physical base address and size of registers +clocks : list of phandles and specifiers to all interconnect bus clocks +clock-names : clock names should include both "bus" and "bus_a" + +The following are optional properties: + +qcom,util-factor : Parameter that represents the DDR utilization factor + to be used in aggregation scheme. It is represented as + actual util-factor * 100. + +Examples: + +soc { + ... + system_noc: interconnect@1880000 { + reg = <0x1880000 0x60200>; + compatible = "qcom,scuba-sys_noc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + + config_noc: interconnect@1900000 { + reg = <0x1900000 0x8200>; + compatible = "qcom,scuba-config_noc"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, + <&rpmcc RPM_SMD_CNOC_A_CLK>; + }; +}; diff --git a/bindings/net/qcom,ethqos-thin.txt b/bindings/net/qcom,ethqos-thin.txt new file mode 100755 index 00000000..f9a6b98d --- /dev/null +++ b/bindings/net/qcom,ethqos-thin.txt @@ -0,0 +1,55 @@ +* Qualcomm Technologies, Inc. Ethernet thin driver (GMAC) + +This documents dwmmac based ethernet device which supports Gigabit +ethernet for single TX and RX DMA channel pair. +There are 2 emac instances with DWMMAC HW version 0x30000000. +Either emac0 or emac1 instance is supported. +For emac0 instance, comaptible should be "qcom,stmmac-ethqos-emac0" + +Required properties: +- compatible: Should be "qcom,stmmac-ethqos-emac1", + +- reg: Address and length of the register set for the device + +- reg-names: Should contain register name "stmmaceth" + +- interrupts: Should contain the per channel interrupts + +- interrupt-names: Should contain per channel interrupt names + +- queue: queue index in MTL for this driver + +Rest of the properties are defined in stmmac.txt file in same directory + +Examples: + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + queue { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + snps,tx-sched-sp; + queue { + snps,dcb-algorithm; + }; + }; + + emacthin_hw: ethernet@00020000 { + compatible = "qcom,stmmac-ethqos-emac1"; + reg = <0x20000 0x10000>; + interrupts-extended = <&intc 0 945 1>; + interrupt-names = "tx_rx_ch1_intr"; + mac-address = [000000000000]; /* Filled in by U-Boot */ + + rx-fifo-depth = <16384>; + tx-fifo-depth = <16384>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + queue = <2> + }; diff --git a/bindings/power/supply/qcom/qpnp-smblite.txt b/bindings/power/supply/qcom/qpnp-smblite.txt index 370957dc..35c7ad4a 100755 --- a/bindings/power/supply/qcom/qpnp-smblite.txt +++ b/bindings/power/supply/qcom/qpnp-smblite.txt @@ -197,6 +197,12 @@ Charger specific properties: Definition: Specifies the step size of each step of FCC stepper algorithm. If left unspecified, the default value is 100mA. +- qcom,fc-step-start-ua + Usage: optional + Value type: <u32> + Definition: Specifies the initial current of FCC stepper algorithm. + If left unspecified, the default value is 500mA. + - qcom,concurrency-mode-enable Usage: optional Value type: bool @@ -209,6 +215,16 @@ Charger specific properties: Definition: Boolean flag to determine if FG is running on different processor. Its supported only on PM5100, By default this feature is disabled. +- qcom,float-option + Usage: optional + Value type: <u32> + Definition: Configures how the charger behaves when a float charger is + detected by APSD. + 1 - Treat as a DCP. + 2 - Treat as a SDP. + 3 - Disable charging. + 4 - Suspend USB input. + ================================================= Second Level Nodes - SMBLITE Charger Peripherals ================================================= diff --git a/bindings/regulator/max20411-regulator.txt b/bindings/regulator/max20411-regulator.txt new file mode 100755 index 00000000..76168d2a --- /dev/null +++ b/bindings/regulator/max20411-regulator.txt @@ -0,0 +1,49 @@ +Maxim MAX20411 voltage regulator + +MAX20411 regulator is a high-efficiency, synchronous step-down converter +that operates with a 3.0V to 5.5V input voltage range and provideds +a 0.05V to 1.275V output range. + +Properties: +- compatible + Usage: required + Value type: <string> + Definition: Must be "maxim,max20411". + +- reg + Usage: required + Value type: <u32> + Definition: I2C slave address. + +- enable-gpio: + Usage: required + Value type: <phandle> + Definition: Phandle to GPIO used to control enable status of regulator. + +- regulator-name + Usage: required + Value type: <string> + Definition: Specifies the name for this regulator. + +- regulator-min-microvolt + Usage: required + Value type: <u32> + Definition: This is the minimum supported voltage in microvolts. + +- regulator-max-microvolt + Usage: required + Value type: <u32> + Definition: This is the maximum supported voltage in microvolts. + + +Example: +&qupv3_se12_i2c { + VDD_GFX_LEVEL: max20411-regulator@39 { + reg = <0x39>; + compatible = "maxim,max20411"; + enable-gpio = <&pm8540_1_gpios 2 GPIO_ACTIVE_HIGH>; + regulator-name = "max20411-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <968750>; + }; +}; diff --git a/bindings/soc/qcom/qcom,glink-slatecom-xprt.txt b/bindings/soc/qcom/qcom,glink-slatecom-xprt.txt index 769317af..b49bc3c7 100755 --- a/bindings/soc/qcom/qcom,glink-slatecom-xprt.txt +++ b/bindings/soc/qcom/qcom,glink-slatecom-xprt.txt @@ -23,6 +23,19 @@ The following example reprsents a glink_slatecom node. label = "slate"; }; += AUDIO_CC_IPC_PLATFORM +This node is defined as the platform driver with cc codec as the child device. +- compatible: + Usage: required + Value type: <stringlist> + Definition: must be "qcom,audio-cc-ipc-platform" + += EXAMPLE + + qcom,audio-cc-ipc-platform { + compatible = "qcom,audio-cc-ipc-platform"; + }; + = AUDIO_CC_IPC_NODE Each subnode of the glink_slatecom_xprt is a device node exposed to user space by the audio-cc-ipc driver for sending ipc packets between the ipc clients. diff --git a/bindings/sound/qcom-audio-dev.txt b/bindings/sound/qcom-audio-dev.txt index 5c4fd50a..c581cdb3 100755 --- a/bindings/sound/qcom-audio-dev.txt +++ b/bindings/sound/qcom-audio-dev.txt @@ -1978,6 +1978,7 @@ Optional properties: - qcom,rxtx-bolero-codec: Property to specify RX-TX macros supported. - qcom,wsa-bolero-codec: Property to specify WSA macro supported. - qcom,visense-enable: Property to specify VISense need to enable or not. +- qcom,rx-wsa-enable: Property to specify wsa need to enable or not. Example: monaco_snd: sound { diff --git a/bindings/usb/dwc3.txt b/bindings/usb/dwc3.txt index d9963a22..06b78e11 100755 --- a/bindings/usb/dwc3.txt +++ b/bindings/usb/dwc3.txt @@ -123,6 +123,7 @@ Optional properties: compliance mode, pattern 14. - snps,gen2-tx-de-emph3: This register is for setting TX deemphasis used in compliance mode, pattern 16. + - snps,force-gen1: If present, limit the speed of Gen2 link to Gen1. - in addition all properties from usb-xhci.txt from the current directory are supported as well diff --git a/qcom/Makefile b/qcom/Makefile index dddaa2cf..6305b269 100755 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -268,12 +268,15 @@ dtbo-$(CONFIG_ARCH_MONACO) += \ monaco-standalone-idp-v1-overlay.dtbo \ monaco-standalone-idp-v2-overlay.dtbo \ monaco-standalone-idp-v3-overlay.dtbo \ + monacop-standalone-idp-v1-overlay.dtbo \ + monaco-standalone-atp-v1-overlay.dtbo \ monaco-idp-v1-overlay.dtbo \ monaco-idp-v2-overlay.dtbo \ monaco-idp-v3-overlay.dtbo \ monaco-idp-v1.1-overlay.dtbo \ monaco-idp-v2.1-overlay.dtbo \ monaco-idp-v3.1-overlay.dtbo \ + monaco-atp-v1-overlay.dtbo \ monaco-standalone-wdp-v1-overlay.dtbo \ monaco-wdp-v1-overlay.dtbo \ monaco-wdp-v1.1-overlay.dtbo @@ -282,12 +285,15 @@ monaco-rumi-overlay.dtbo-base := monaco.dtb monaco-standalone-idp-v1-overlay.dtbo-base := monaco-1gb.dtb monacop-1gb.dtb monaco-standalone-idp-v2-overlay.dtbo-base := monaco-1gb.dtb monacop-1gb.dtb monaco-standalone-idp-v3-overlay.dtbo-base := monaco-1gb.dtb monacop-1gb.dtb +monacop-standalone-idp-v1-overlay.dtbo-base := monaco-1gb.dtb +monaco-standalone-atp-v1-overlay.dtbo-base := monaco-1gb.dtb monacop-1gb.dtb monaco-idp-v1-overlay.dtbo-base := monaco.dtb monacop.dtb monaco-idp-v2-overlay.dtbo-base := monaco.dtb monacop.dtb monaco-idp-v3-overlay.dtbo-base := monaco.dtb monacop.dtb monaco-idp-v1.1-overlay.dtbo-base := monaco.dtb monacop.dtb monaco-idp-v2.1-overlay.dtbo-base := monaco.dtb monaco-idp-v3.1-overlay.dtbo-base := monaco.dtb +monaco-atp-v1-overlay.dtbo-base := monaco.dtb monacop.dtb monaco-standalone-wdp-v1-overlay.dtbo-base := monaco-1gb.dtb monacop-1gb.dtb monaco-wdp-v1-overlay.dtbo-base := monaco.dtb monacop.dtb monaco-wdp-v1.1-overlay.dtbo-base := monaco.dtb monacop.dtb @@ -300,6 +306,8 @@ dtb-$(CONFIG_ARCH_MONACO) += monaco-rumi.dtb \ monacop-standalone-idp-v2.dtb \ monaco-standalone-idp-v3.dtb \ monacop-standalone-idp-v3.dtb \ + monaco-standalone-atp-v1.dtb \ + monacop-standalone-atp-v1.dtb \ monaco-idp-v1.dtb \ monaco-idp-v2.dtb \ monaco-idp-v3.dtb \ @@ -309,6 +317,8 @@ dtb-$(CONFIG_ARCH_MONACO) += monaco-rumi.dtb \ monaco-idp-v1.1.dtb \ monaco-idp-v2.1.dtb \ monaco-idp-v3.1.dtb \ + monaco-atp-v1.dtb \ + monacop-atp-v1.dtb \ monaco-standalone-wdp-v1.dtb \ monaco-wdp-v1.dtb \ monacop-standalone-wdp-v1.dtb \ @@ -493,7 +503,9 @@ dtb-$(CONFIG_QTI_QUIN_GVM) += sa8155-vm-la.dtb \ sa6155p-vm-la.dtb \ sa6155p-vm-lv.dtb \ direwolf-vm-lv.dtb \ - direwolf-vm-la.dtb + direwolf-vm-la.dtb \ + direwolf-vm-la-mt.dtb \ + direwolf-vm-lv-mt.dtb ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_DIREWOLF) += direwolf-ivi-rumi-overlay.dtbo \ @@ -515,6 +527,10 @@ dtb-$(CONFIG_ARCH_DIREWOLF) += direwolf-ivi-rumi.dtb \ direwolf-adas-adp-star.dtb endif +dtb-$(CONFIG_ARCH_LEMANS) += lemans-rumi.dtb \ + lemans-adp-air.dtb \ + lemans-adp-star.dtb + always := $(dtb-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi index a78e4bcd..4fe63f0d 100755 --- a/qcom/blair.dtsi +++ b/qcom/blair.dtsi @@ -998,6 +998,7 @@ clk_virt: interconnect { compatible = "qcom,holi-clk_virt"; #interconnect-cells = <1>; + qcom,keepalive; clock-names = "bus", "bus_a"; clocks = <&rpmcc RPM_SMD_QUP_CLK>, <&rpmcc RPM_SMD_QUP_A_CLK>; diff --git a/qcom/direwolf-adp-common.dtsi b/qcom/direwolf-adp-common.dtsi index e972ad98..e661eef4 100755 --- a/qcom/direwolf-adp-common.dtsi +++ b/qcom/direwolf-adp-common.dtsi @@ -1,3 +1,4 @@ +#include <dt-bindings/gpio/gpio.h> #include "direwolf-cnss.dtsi" &soc { @@ -29,6 +30,9 @@ qcom,vddp-ref-clk-supply = <&L6C0>; qcom,vddp-ref-clk-max-microamp = <100>; + /* Disable Write Booster Feature */ + qcom,disable-wb-support; + status = "ok"; }; @@ -57,6 +61,9 @@ qcom,vddp-ref-clk-supply = <&L3C0>; qcom,vddp-ref-clk-max-microamp = <100>; + /* Disable Write Booster Feature */ + qcom,disable-wb-support; + status = "ok"; }; @@ -105,3 +112,32 @@ pinctrl-0 = <&usb20_vbus_boost_default &usb21_vbus_boost_default &usb22_vbus_boost_default &usb23_vbus_boost_default>; }; + +&qupv3_se12_i2c { + status = "ok"; +}; + +&pm8540_1_gpios { + vdd_gfx_en { + vdd_gfx_en_default: vdd_gfx_en_default { + pins = "gpio2"; + function = "normal"; + output-high; + }; + }; +}; + +&VDD_GFX_LEVEL { + enable-gpio = <&pm8540_1_gpios 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_gfx_en_default>; + status = "ok"; +}; + +/* + * Each QUP device that's a parent to PMIC must be listed as a critical device + * to GCC + */ +&gcc { + qcom,critical-devices = <&qupv3_se12_i2c>; +}; diff --git a/qcom/direwolf-audio.dtsi b/qcom/direwolf-audio.dtsi new file mode 100755 index 00000000..93d92ff5 --- /dev/null +++ b/qcom/direwolf-audio.dtsi @@ -0,0 +1,1298 @@ +#include "msm-audio-lpass.dtsi" + +/ { + aliases { + i2c4 = &qupv3_se21_i2c; + }; +}; + + +&msm_audio_ion { + iommus = <&apps_smmu 0x0c01 0x0>; + qcom,smmu-sid-mask = /bits/ 64 <0xf>; + /delete-property/ qcom,iommu-dma-addr-pool; +}; + + +&soc { + tdm_pri_rx: qcom,msm-dai-tdm-pri-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37120>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36864 36866 36868 36870>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pri_tdm_sck_active &pri_tdm_ws_active + &pri_tdm_din_active &pri_tdm_dout_active>; + pinctrl-1 = <&pri_tdm_sck_sleep &pri_tdm_ws_sleep + &pri_tdm_din_sleep &pri_tdm_dout_sleep>; + #gpio-cells = <0>; + dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36864>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_1: qcom,msm-dai-q6-tdm-pri-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36866>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_2: qcom,msm-dai-q6-tdm-pri-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36868>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_3: qcom,msm-dai-q6-tdm-pri-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36870>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_pri_tx: qcom,msm-dai-tdm-pri-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37121>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36865 36867 36869 36871>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36865>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_1: qcom,msm-dai-q6-tdm-pri-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36867>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_2: qcom,msm-dai-q6-tdm-pri-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36869>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_3: qcom,msm-dai-q6-tdm-pri-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36871>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sec_rx: qcom,msm-dai-tdm-sec-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36880 36882 36884 + 36886 36894>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <0>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36880>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_1: qcom,msm-dai-q6-tdm-sec-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36882>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_2: qcom,msm-dai-q6-tdm-sec-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36884>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_3: qcom,msm-dai-q6-tdm-sec-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36886>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_7: qcom,msm-dai-q6-tdm-sec-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36894>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sec_tx: qcom,msm-dai-tdm-sec-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37137>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36881 36883 36885 36887>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <0>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36881>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_1: qcom,msm-dai-q6-tdm-sec-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36883>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_2: qcom,msm-dai-q6-tdm-sec-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36885>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_3: qcom,msm-dai-q6-tdm-sec-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36887>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_tert_rx: qcom,msm-dai-tdm-tert-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37152>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36896 36898 36900 + 36902 36904>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&tert_tdm_sck_active &tert_tdm_ws_active + &tert_tdm_din_active &tert_tdm_dout_active>; + pinctrl-1 = <&tert_tdm_sck_sleep &tert_tdm_ws_sleep + &tert_tdm_din_sleep &tert_tdm_dout_sleep>; + #gpio-cells = <0>; + dai_tert_tdm_rx_0: qcom,msm-dai-q6-tdm-tert-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36896>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_1: qcom,msm-dai-q6-tdm-tert-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36898>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_2: qcom,msm-dai-q6-tdm-tert-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36900>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_3: qcom,msm-dai-q6-tdm-tert-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36902>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_4: qcom,msm-dai-q6-tdm-tert-rx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36904>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_tert_tx: qcom,msm-dai-tdm-tert-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37153>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36897 36899 36901 + 36903 36911>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <0>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + dai_tert_tdm_tx_0: qcom,msm-dai-q6-tdm-tert-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36897>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_1: qcom,msm-dai-q6-tdm-tert-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36899>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_2: qcom,msm-dai-q6-tdm-tert-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36901>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_3: qcom,msm-dai-q6-tdm-tert-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36903>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_7: qcom,msm-dai-q6-tdm-tert-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36911>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quat_rx: qcom,msm-dai-tdm-quat-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37168>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36912 36914 36916 + 36918 36926>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <10>; + dai_quat_tdm_rx_0: qcom,msm-dai-q6-tdm-quat-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36912>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_1: qcom,msm-dai-q6-tdm-quat-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36914>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_2: qcom,msm-dai-q6-tdm-quat-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36916>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_3: qcom,msm-dai-q6-tdm-quat-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36918>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_7: qcom,msm-dai-q6-tdm-quat-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36926>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quat_tx: qcom,msm-dai-tdm-quat-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37169>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36913 36915 36917 + 36919 36927>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <5>; + dai_quat_tdm_tx_0: qcom,msm-dai-q6-tdm-quat-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36913>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_1: qcom,msm-dai-q6-tdm-quat-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36915>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_2: qcom,msm-dai-q6-tdm-quat-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36917>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_3: qcom,msm-dai-q6-tdm-quat-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36919>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_7: qcom,msm-dai-q6-tdm-quat-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36927>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quin_rx: qcom,msm-dai-tdm-quin-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37184>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36928 36930 36932 + 36934 36942>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_quin_tdm_rx_0: qcom,msm-dai-q6-tdm-quin-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36928>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_1: qcom,msm-dai-q6-tdm-quin-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36930>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_2: qcom,msm-dai-q6-tdm-quin-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36932>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_3: qcom,msm-dai-q6-tdm-quin-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36934>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_7: qcom,msm-dai-q6-tdm-quin-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36942>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quin_tx: qcom,msm-dai-tdm-quin-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37185>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36929 36931 36933 + 36935 36943>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_quin_tdm_tx_0: qcom,msm-dai-q6-tdm-quin-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36929>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_1: qcom,msm-dai-q6-tdm-quin-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36931>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_2: qcom,msm-dai-q6-tdm-quin-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36933>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_3: qcom,msm-dai-q6-tdm-quin-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36935>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_7: qcom,msm-dai-q6-tdm-quin-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36943>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sen_rx: qcom,msm-dai-tdm-sen-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37200>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <36944 36946 36948 + 36950 36952 36954 36956 36958>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sen_tdm_rx_0: qcom,msm-dai-q6-tdm-sen-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36944>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_rx_1: qcom,msm-dai-q6-tdm-sen-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36946>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_rx_2: qcom,msm-dai-q6-tdm-sen-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36948>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_rx_3: qcom,msm-dai-q6-tdm-sen-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36950>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_rx_4: qcom,msm-dai-q6-tdm-sen-rx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36952>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_rx_5: qcom,msm-dai-q6-tdm-sen-rx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36954>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_rx_6: qcom,msm-dai-q6-tdm-sen-rx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36956>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_rx_7: qcom,msm-dai-q6-tdm-sen-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36958>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sen_tx: qcom,msm-dai-tdm-sen-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37201>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <36945 36947 36949 + 36951 36953 36955 36957 36959>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sen_tdm_tx_0: qcom,msm-dai-q6-tdm-sen-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36945>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_tx_1: qcom,msm-dai-q6-tdm-sen-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36947>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_tx_2: qcom,msm-dai-q6-tdm-sen-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36949>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_tx_3: qcom,msm-dai-q6-tdm-sen-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36951>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_tx_4: qcom,msm-dai-q6-tdm-sen-tx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36953>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_tx_5: qcom,msm-dai-q6-tdm-sen-tx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36955>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_tx_6: qcom,msm-dai-q6-tdm-sen-tx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36957>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sen_tdm_tx_7: qcom,msm-dai-q6-tdm-sen-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36959>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sep_rx: qcom,msm-dai-tdm-sep-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37216>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <36960 36962 36964 + 36966 36968 36970 36972 36974>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sep_tdm_rx_0: qcom,msm-dai-q6-tdm-sep-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36960>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_rx_1: qcom,msm-dai-q6-tdm-sep-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36962>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_rx_2: qcom,msm-dai-q6-tdm-sep-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36964>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_rx_3: qcom,msm-dai-q6-tdm-sep-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36966>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_rx_4: qcom,msm-dai-q6-tdm-sep-rx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36968>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_rx_5: qcom,msm-dai-q6-tdm-sep-rx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36970>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_rx_6: qcom,msm-dai-q6-tdm-sep-rx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36972>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_rx_7: qcom,msm-dai-q6-tdm-sep-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36974>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sep_tx: qcom,msm-dai-tdm-sep-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37217>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <36961 36963 36965 + 36967 36969 36971 36973 36975>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sep_tdm_tx_0: qcom,msm-dai-q6-tdm-sep-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36961>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_tx_1: qcom,msm-dai-q6-tdm-sep-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36963>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_tx_2: qcom,msm-dai-q6-tdm-sep-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36965>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_tx_3: qcom,msm-dai-q6-tdm-sep-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36967>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_tx_4: qcom,msm-dai-q6-tdm-sep-tx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36969>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_tx_5: qcom,msm-dai-q6-tdm-sep-tx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36971>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_tx_6: qcom,msm-dai-q6-tdm-sep-tx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36973>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sep_tdm_tx_7: qcom,msm-dai-q6-tdm-sep-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36975>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_hsif0_rx: qcom,msm-dai-tdm-hsif0-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37232>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <36976 36978 36980 + 36982 36984 36986 36988 36990>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_hsif0_tdm_rx_0: qcom,msm-dai-q6-tdm-hsif0-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36976>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_rx_1: qcom,msm-dai-q6-tdm-hsif0-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36978>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_rx_2: qcom,msm-dai-q6-tdm-hsif0-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36980>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_rx_3: qcom,msm-dai-q6-tdm-hsif0-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36982>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_rx_4: qcom,msm-dai-q6-tdm-hsif0-rx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36984>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_rx_5: qcom,msm-dai-q6-tdm-hsif0-rx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36986>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_rx_6: qcom,msm-dai-q6-tdm-hsif0-rx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36988>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_rx_7: qcom,msm-dai-q6-tdm-hsif0-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36990>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_hsif0_tx: qcom,msm-dai-tdm-hsif0-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37233>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <36977 36979 36981 + 36983 36985 36987 36989 36991>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_hsif0_tdm_tx_0: qcom,msm-dai-q6-tdm-hsif0-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36977>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_tx_1: qcom,msm-dai-q6-tdm-hsif0-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36979>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_tx_2: qcom,msm-dai-q6-tdm-hsif0-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36981>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_tx_3: qcom,msm-dai-q6-tdm-hsif0-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36983>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_tx_4: qcom,msm-dai-q6-tdm-hsif0-tx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36985>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_tx_5: qcom,msm-dai-q6-tdm-hsif0-tx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36987>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_tx_6: qcom,msm-dai-q6-tdm-hsif0-tx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36989>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif0_tdm_tx_7: qcom,msm-dai-q6-tdm-hsif0-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36991>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_hsif1_rx: qcom,msm-dai-tdm-hsif1-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37248>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <36992 36994 36996 + 36998 37000 37002 37004 37006>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_hsif1_tdm_rx_0: qcom,msm-dai-q6-tdm-hsif1-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36992>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_rx_1: qcom,msm-dai-q6-tdm-hsif1-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36994>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_rx_2: qcom,msm-dai-q6-tdm-hsif1-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36996>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_rx_3: qcom,msm-dai-q6-tdm-hsif1-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36998>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_rx_4: qcom,msm-dai-q6-tdm-hsif1-rx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37000>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_rx_5: qcom,msm-dai-q6-tdm-hsif1-rx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37002>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_rx_6: qcom,msm-dai-q6-tdm-hsif1-rx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37004>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_rx_7: qcom,msm-dai-q6-tdm-hsif1-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37006>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_hsif1_tx: qcom,msm-dai-tdm-hsif1-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37249>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <36993 36995 36997 + 36999 37001 37003 37005 37007>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_hsif1_tdm_tx_0: qcom,msm-dai-q6-tdm-hsif1-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36993>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_tx_1: qcom,msm-dai-q6-tdm-hsif1-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36995>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_tx_2: qcom,msm-dai-q6-tdm-hsif1-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36997>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_tx_3: qcom,msm-dai-q6-tdm-hsif1-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36999>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_tx_4: qcom,msm-dai-q6-tdm-hsif1-tx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37001>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_tx_5: qcom,msm-dai-q6-tdm-hsif1-tx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37003>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_tx_6: qcom,msm-dai-q6-tdm-hsif1-tx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37005>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif1_tdm_tx_7: qcom,msm-dai-q6-tdm-hsif1-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37007>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_hsif2_rx: qcom,msm-dai-tdm-hsif2-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37264>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <37008 37010 37012 + 37014 37016 37018 37020 37022>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_hsif2_tdm_rx_0: qcom,msm-dai-q6-tdm-hsif2-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37008>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_rx_1: qcom,msm-dai-q6-tdm-hsif2-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37010>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_rx_2: qcom,msm-dai-q6-tdm-hsif2-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37012>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_rx_3: qcom,msm-dai-q6-tdm-hsif2-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37014>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_rx_4: qcom,msm-dai-q6-tdm-hsif2-rx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37016>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_rx_5: qcom,msm-dai-q6-tdm-hsif2-rx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37018>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_rx_6: qcom,msm-dai-q6-tdm-hsif2-rx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37020>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_rx_7: qcom,msm-dai-q6-tdm-hsif2-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37022>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_hsif2_tx: qcom,msm-dai-tdm-hsif2-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37265>; + qcom,msm-cpudai-tdm-group-num-ports = <8>; + qcom,msm-cpudai-tdm-group-port-id = <37009 37011 37013 + 37015 37017 37019 37021 37023>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_hsif2_tdm_tx_0: qcom,msm-dai-q6-tdm-hsif2-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37009>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_tx_1: qcom,msm-dai-q6-tdm-hsif2-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37011>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_tx_2: qcom,msm-dai-q6-tdm-hsif2-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37013>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_tx_3: qcom,msm-dai-q6-tdm-hsif2-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37015>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_tx_4: qcom,msm-dai-q6-tdm-hsif2-tx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37017>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_tx_5: qcom,msm-dai-q6-tdm-hsif2-tx-5 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37019>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_tx_6: qcom,msm-dai-q6-tdm-hsif2-tx-6 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37021>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_hsif2_tdm_tx_7: qcom,msm-dai-q6-tdm-hsif2-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <37023>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + + afe_pcm_rx_1: qcom,msm-dai-q6-be-afe-pcm-rx-1 { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <226>; + }; + + afe_proxy_tx_1: qcom,msm-dai-q6-afe-proxy-tx-1 { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <242>; + }; + }; + + internal_mclk1: qcom,msm-internal-mclk1 { + compatible = "qcom,msm-pcm-routing"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&audio_internal_mclk1_active>; + pinctrl-1 = <&audio_internal_mclk1_sleep>; + #gpio-cells = <0>; + }; + +}; + + +&audio_apr { + q6core: qcom,q6core-audio { + compatible = "qcom,q6core-audio"; + }; +}; + +&q6core { + snd_8295: sound-adp-star { + compatible = "qcom,sa8295-asoc-snd-adp-star"; + qcom,model = "sa8295-adp-star-snd-card"; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; + + qcom,pri-tdm-gpios = <&tdm_pri_rx>; + qcom,tert-tdm-gpios = <&tdm_tert_rx>; + qcom,internal-mclk1-gpios = <&internal_mclk1>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>, <&loopback1>, <&pcm_dtmf>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", + "msm-pcm-dtmf"; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, + <&afe_proxy_rx>, <&afe_proxy_tx>, + <&afe_pcm_rx_1>, <&afe_proxy_tx_1>, + <&incall_record_rx>, <&incall_record_tx>, + <&incall_music_rx>, <&incall_music_2_rx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_rx_1>, + <&dai_pri_tdm_rx_2>, <&dai_pri_tdm_rx_3>, + <&dai_pri_tdm_tx_0>, <&dai_pri_tdm_tx_1>, + <&dai_pri_tdm_tx_2>, <&dai_pri_tdm_tx_3>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_rx_1>, + <&dai_sec_tdm_rx_2>, <&dai_sec_tdm_rx_3>, + <&dai_sec_tdm_rx_7>, <&dai_sec_tdm_tx_0>, + <&dai_sec_tdm_tx_1>, <&dai_sec_tdm_tx_2>, + <&dai_sec_tdm_tx_3>, <&dai_tert_tdm_rx_0>, + <&dai_tert_tdm_rx_1>, <&dai_tert_tdm_rx_2>, + <&dai_tert_tdm_rx_3>, <&dai_tert_tdm_rx_4>, + <&dai_tert_tdm_tx_0>, <&dai_tert_tdm_tx_1>, + <&dai_tert_tdm_tx_2>, <&dai_tert_tdm_tx_3>, + <&dai_tert_tdm_tx_7>, <&dai_quat_tdm_rx_0>, + <&dai_quat_tdm_rx_1>, <&dai_quat_tdm_rx_2>, + <&dai_quat_tdm_rx_3>, <&dai_quat_tdm_rx_7>, + <&dai_quat_tdm_tx_0>, <&dai_quat_tdm_tx_1>, + <&dai_quat_tdm_tx_2>, <&dai_quat_tdm_tx_3>, + <&dai_quat_tdm_tx_7>, <&dai_quin_tdm_rx_0>, + <&dai_quin_tdm_rx_1>, <&dai_quin_tdm_rx_2>, + <&dai_quin_tdm_rx_3>, <&dai_quin_tdm_rx_7>, + <&dai_quin_tdm_tx_0>, <&dai_quin_tdm_tx_1>, + <&dai_quin_tdm_tx_2>, <&dai_quin_tdm_tx_3>, + <&dai_quin_tdm_tx_7>, <&dai_sen_tdm_rx_0>, + <&dai_sen_tdm_rx_1>, <&dai_sen_tdm_rx_2>, + <&dai_sen_tdm_rx_3>, <&dai_sen_tdm_rx_4>, + <&dai_sen_tdm_rx_5>, <&dai_sen_tdm_rx_6>, + <&dai_sen_tdm_rx_7>, <&dai_sen_tdm_tx_0>, + <&dai_sen_tdm_tx_1>, <&dai_sen_tdm_tx_2>, + <&dai_sen_tdm_tx_3>, <&dai_sen_tdm_tx_4>, + <&dai_sen_tdm_tx_5>, <&dai_sen_tdm_tx_6>, + <&dai_sen_tdm_tx_7>, <&dai_sep_tdm_rx_0>, + <&dai_sep_tdm_rx_1>, <&dai_sep_tdm_rx_2>, + <&dai_sep_tdm_rx_3>, <&dai_sep_tdm_rx_4>, + <&dai_sep_tdm_rx_5>, <&dai_sep_tdm_rx_6>, + <&dai_sep_tdm_rx_7>, <&dai_sep_tdm_tx_0>, + <&dai_sep_tdm_tx_1>, <&dai_sep_tdm_tx_2>, + <&dai_sep_tdm_tx_3>, <&dai_sep_tdm_tx_4>, + <&dai_sep_tdm_tx_5>, <&dai_sep_tdm_tx_6>, + <&dai_sep_tdm_tx_7>, <&dai_hsif0_tdm_rx_0>, + <&dai_hsif0_tdm_rx_1>, <&dai_hsif0_tdm_rx_2>, + <&dai_hsif0_tdm_rx_3>, <&dai_hsif0_tdm_rx_4>, + <&dai_hsif0_tdm_rx_5>, <&dai_hsif0_tdm_rx_6>, + <&dai_hsif0_tdm_rx_7>, <&dai_hsif0_tdm_tx_0>, + <&dai_hsif0_tdm_tx_1>, <&dai_hsif0_tdm_tx_2>, + <&dai_hsif0_tdm_tx_3>, <&dai_hsif0_tdm_tx_4>, + <&dai_hsif0_tdm_tx_5>, <&dai_hsif0_tdm_tx_6>, + <&dai_hsif1_tdm_tx_7>, <&dai_hsif1_tdm_rx_0>, + <&dai_hsif1_tdm_rx_1>, <&dai_hsif1_tdm_rx_2>, + <&dai_hsif1_tdm_rx_3>, <&dai_hsif1_tdm_rx_4>, + <&dai_hsif1_tdm_rx_5>, <&dai_hsif1_tdm_rx_6>, + <&dai_hsif1_tdm_rx_7>, <&dai_hsif1_tdm_tx_0>, + <&dai_hsif1_tdm_tx_1>, <&dai_hsif1_tdm_tx_2>, + <&dai_hsif1_tdm_tx_3>, <&dai_hsif1_tdm_tx_4>, + <&dai_hsif1_tdm_tx_5>, <&dai_hsif1_tdm_tx_6>, + <&dai_hsif1_tdm_tx_7>, <&dai_hsif2_tdm_rx_0>, + <&dai_hsif2_tdm_rx_1>, <&dai_hsif2_tdm_rx_2>, + <&dai_hsif2_tdm_rx_3>, <&dai_hsif2_tdm_rx_4>, + <&dai_hsif2_tdm_rx_5>, <&dai_hsif2_tdm_rx_6>, + <&dai_hsif2_tdm_rx_7>, <&dai_hsif2_tdm_tx_0>, + <&dai_hsif2_tdm_tx_1>, <&dai_hsif2_tdm_tx_2>, + <&dai_hsif2_tdm_tx_3>, <&dai_hsif2_tdm_tx_4>, + <&dai_hsif2_tdm_tx_5>, <&dai_hsif2_tdm_tx_6>, + <&dai_hsif2_tdm_tx_7>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.0", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", + "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.226", "msm-dai-q6-dev.242", + "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", + "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36866", + "msm-dai-q6-tdm.36868", "msm-dai-q6-tdm.36870", + "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36867", + "msm-dai-q6-tdm.36869", "msm-dai-q6-tdm.36871", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36882", + "msm-dai-q6-tdm.36884", "msm-dai-q6-tdm.36886", + "msm-dai-q6-tdm.36894", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36883", "msm-dai-q6-tdm.36885", + "msm-dai-q6-tdm.36887", "msm-dai-q6-tdm.36896", + "msm-dai-q6-tdm.36898", "msm-dai-q6-tdm.36900", + "msm-dai-q6-tdm.36902", "msm-dai-q6-tdm.36904", + "msm-dai-q6-tdm.36897", "msm-dai-q6-tdm.36899", + "msm-dai-q6-tdm.36901", "msm-dai-q6-tdm.36903", + "msm-dai-q6-tdm.36911", "msm-dai-q6-tdm.36912", + "msm-dai-q6-tdm.36914", "msm-dai-q6-tdm.36916", + "msm-dai-q6-tdm.36918", "msm-dai-q6-tdm.36926", + "msm-dai-q6-tdm.36913", "msm-dai-q6-tdm.36915", + "msm-dai-q6-tdm.36917", "msm-dai-q6-tdm.36919", + "msm-dai-q6-tdm.36927", "msm-dai-q6-tdm.36928", + "msm-dai-q6-tdm.36930", "msm-dai-q6-tdm.36932", + "msm-dai-q6-tdm.36934", "msm-dai-q6-tdm.36942", + "msm-dai-q6-tdm.36929", "msm-dai-q6-tdm.36931", + "msm-dai-q6-tdm.36933", "msm-dai-q6-tdm.36935", + "msm-dai-q6-tdm.36943", "msm-dai-q6-tdm.36944", + "msm-dai-q6-tdm.36946", "msm-dai-q6-tdm.36948", + "msm-dai-q6-tdm.36950", "msm-dai-q6-tdm.36952", + "msm-dai-q6-tdm.36954", "msm-dai-q6-tdm.36956", + "msm-dai-q6-tdm.36958", "msm-dai-q6-tdm.36945", + "msm-dai-q6-tdm.36947", "msm-dai-q6-tdm.36949", + "msm-dai-q6-tdm.36951", "msm-dai-q6-tdm.36953", + "msm-dai-q6-tdm.36955", "msm-dai-q6-tdm.36957", + "msm-dai-q6-tdm.36959", "msm-dai-q6-tdm.36960", + "msm-dai-q6-tdm.36962", "msm-dai-q6-tdm.36964", + "msm-dai-q6-tdm.36966", "msm-dai-q6-tdm.36968", + "msm-dai-q6-tdm.36970", "msm-dai-q6-tdm.36972", + "msm-dai-q6-tdm.36974", "msm-dai-q6-tdm.36961", + "msm-dai-q6-tdm.36963", "msm-dai-q6-tdm.36965", + "msm-dai-q6-tdm.36967", "msm-dai-q6-tdm.36969", + "msm-dai-q6-tdm.36971", "msm-dai-q6-tdm.36973", + "msm-dai-q6-tdm.36975", "msm-dai-q6-tdm.36976", + "msm-dai-q6-tdm.36978", "msm-dai-q6-tdm.36980", + "msm-dai-q6-tdm.36982", "msm-dai-q6-tdm.36984", + "msm-dai-q6-tdm.36986", "msm-dai-q6-tdm.36988", + "msm-dai-q6-tdm.36990", "msm-dai-q6-tdm.36977", + "msm-dai-q6-tdm.36979", "msm-dai-q6-tdm.36981", + "msm-dai-q6-tdm.36983", "msm-dai-q6-tdm.36985", + "msm-dai-q6-tdm.36987", "msm-dai-q6-tdm.36989", + "msm-dai-q6-tdm.36991", "msm-dai-q6-tdm.36992", + "msm-dai-q6-tdm.36994", "msm-dai-q6-tdm.36996", + "msm-dai-q6-tdm.36998", "msm-dai-q6-tdm.37000", + "msm-dai-q6-tdm.37002", "msm-dai-q6-tdm.37004", + "msm-dai-q6-tdm.37006", "msm-dai-q6-tdm.36993", + "msm-dai-q6-tdm.36995", "msm-dai-q6-tdm.36997", + "msm-dai-q6-tdm.36999", "msm-dai-q6-tdm.37001", + "msm-dai-q6-tdm.37003", "msm-dai-q6-tdm.37005", + "msm-dai-q6-tdm.37007", "msm-dai-q6-tdm.37008", + "msm-dai-q6-tdm.37010", "msm-dai-q6-tdm.37012", + "msm-dai-q6-tdm.37014", "msm-dai-q6-tdm.37016", + "msm-dai-q6-tdm.37018", "msm-dai-q6-tdm.37020", + "msm-dai-q6-tdm.37022", "msm-dai-q6-tdm.37009", + "msm-dai-q6-tdm.37011", "msm-dai-q6-tdm.37013", + "msm-dai-q6-tdm.37015", "msm-dai-q6-tdm.37017", + "msm-dai-q6-tdm.37019", "msm-dai-q6-tdm.37021", + "msm-dai-q6-tdm.37023"; + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; + }; +}; + +&qupv3_se21_i2c { + status = "ok"; +}; + + +&qupv3_se22_spi { + status = "ok"; + spi_codec@0 { + compatible = "qcom,spi-msm-codec-slave"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-cpha; + }; +}; diff --git a/qcom/direwolf-gdsc.dtsi b/qcom/direwolf-gdsc.dtsi index 02b45262..ed4b03e8 100755 --- a/qcom/direwolf-gdsc.dtsi +++ b/qcom/direwolf-gdsc.dtsi @@ -378,4 +378,42 @@ qcom,retain-regs; status = "disabled"; }; + + /* GPU_CC GDSCs */ + gpu_cc_gx_domain_addr: syscon@3d9158c { + compatible = "syscon"; + reg = <0x3d9158c 0x4>; + }; + + gpu_cc_cx_gdsc_hw_ctrl: syscon@3d91540 { + compatible = "syscon"; + reg = <0x3d91540 0x4>; + }; + + gpu_cc_gx_sw_reset: syscon@3d91008 { + compatible = "syscon"; + reg = <0x3d91008 0x4>; + }; + + gpu_cc_cx_gdsc: qcom,gdsc@3d9106c { + compatible = "qcom,gdsc"; + reg = <0x3d9106c 0x4>; + regulator-name = "gpu_cc_cx_gdsc"; + hw-ctrl-addr = <&gpu_cc_cx_gdsc_hw_ctrl>; + qcom,no-status-check-on-disable; + qcom,retain-regs; + status = "disabled"; + }; + + gpu_cc_gx_gdsc: qcom,gdsc@3d9100c { + compatible = "qcom,gdsc"; + reg = <0x3d9100c 0x4>; + regulator-name = "gpu_cc_gx_gdsc"; + sw-reset = <&gpu_cc_gx_sw_reset>; + domain-addr = <&gpu_cc_gx_domain_addr>; + qcom,reset-aon-logic; + qcom,retain-regs; + status = "disabled"; + }; + }; diff --git a/qcom/direwolf-pinctrl.dtsi b/qcom/direwolf-pinctrl.dtsi index ffed88d3..b12cf5b2 100755 --- a/qcom/direwolf-pinctrl.dtsi +++ b/qcom/direwolf-pinctrl.dtsi @@ -2266,4 +2266,485 @@ }; + pri_tdm { + pri_tdm_sck_sleep: pri_tdm_sck_sleep { + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_sck_active: pri_tdm_sck_active { + mux { + pins = "gpio93"; + function = "mi2s0_sck"; + }; + + config { + pins = "gpio93"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + + pri_tdm_ws_sleep: pri_tdm_ws_sleep { + mux { + pins = "gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio94"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_ws_active: pri_tdm_ws_active { + mux { + pins = "gpio94"; + function = "mi2s0_ws"; + }; + + config { + pins = "gpio94"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_tdm_din { + pri_tdm_din_sleep: pri_tdm_din_sleep { + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_din_active: pri_tdm_din_active { + mux { + pins = "gpio95"; + function = "mi2s0_data0"; + }; + + config { + pins = "gpio95"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_tdm_dout { + pri_tdm_dout_sleep: pri_tdm_dout_sleep { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_dout_active: pri_tdm_dout_active { + mux { + pins = "gpio96"; + function = "mi2s0_data1"; + }; + + config { + pins = "gpio96"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + + tert_tdm { + tert_tdm_sck_sleep: tert_tdm_sck_sleep { + mux { + pins = "gpio212"; + function = "gpio"; + }; + + config { + pins = "gpio212"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_sck_active: tert_tdm_sck_active { + mux { + pins = "gpio212"; + function = "mi2s2_sck"; + }; + + config { + pins = "gpio212"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + + tert_tdm_ws_sleep: tert_tdm_ws_sleep { + mux { + pins = "gpio213"; + function = "gpio"; + }; + + config { + pins = "gpio213"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_ws_active: tert_tdm_ws_active { + mux { + pins = "gpio213"; + function = "mi2s2_ws"; + }; + + config { + pins = "gpio213"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_tdm_din { + tert_tdm_din_sleep: tert_tdm_din_sleep { + mux { + pins = "gpio214"; + function = "gpio"; + }; + + config { + pins = "gpio214"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_din_active: tert_tdm_din_active { + mux { + pins = "gpio214"; + function = "mi2s2_data0"; + }; + + config { + pins = "gpio214"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_tdm_dout { + tert_tdm_dout_sleep: tert_tdm_dout_sleep { + mux { + pins = "gpio215"; + function = "gpio"; + }; + + config { + pins = "gpio215"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_dout_active: tert_tdm_dout_active { + mux { + pins = "gpio215"; + function = "mi2s2_data1"; + }; + + config { + pins = "gpio215"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + audio_internal_mclk1_active: audio_internal_mclk1_active { + mux { + pins = "gpio80"; + function = "mi2s_mclk1"; + }; + + config { + pins = "gpio80"; + drive-strength = <8>; + bias-disable; + output-high; + }; + }; + + audio_internal_mclk1_sleep: audio_internal_mclk1_sleep { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio113","gpio114"; + function = "cci_i2c"; + }; + + config { + pins = "gpio113","gpio114"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio113","gpio114"; + function = "cci_i2c"; + }; + + config { + pins = "gpio113","gpio114"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio115","gpio116"; + function = "cci_i2c"; + }; + + config { + pins = "gpio115","gpio116"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio115","gpio116"; + function = "cci_i2c"; + }; + + config { + pins = "gpio115","gpio116"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_active: cci2_active { + mux { + /* CLK, DATA */ + pins = "gpio10","gpio11"; + function = "cci_i2c"; + }; + + config { + pins = "gpio10","gpio11"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_suspend: cci2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio10","gpio11"; + function = "cci_i2c"; + }; + + config { + pins = "gpio10","gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_active: cci3_active { + mux { + /* CLK, DATA */ + pins = "gpio12","gpio13"; + function = "cci_i2c"; + }; + + config { + pins = "gpio12","gpio13"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_suspend: cci3_suspend { + mux { + /* CLK, DATA */ + pins = "gpio12","gpio13"; + function = "cci_i2c"; + }; + + config { + pins = "gpio12","gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor0_active: cam_sensor0_active { + /* intr gpio for bridge chip 0 */ + mux { + pins = "gpio162"; + function = "gpio"; + }; + + config { + pins = "gpio162"; + bias-pull-up; /* PULL UP */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor0_suspend: cam_sensor0_suspend { + /* intr gpio for bridge chip 0 */ + mux { + pins = "gpio162"; + function = "gpio"; + }; + + config { + pins = "gpio162"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor1_active: cam_sensor1_active { + /* intr gpio for bridge chip 1 */ + mux { + pins = "gpio163"; + function = "gpio"; + }; + + config { + pins = "gpio163"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor1_suspend: cam_sensor1_suspend { + /* intr gpio for bridge chip 1 */ + mux { + pins = "gpio163"; + function = "gpio"; + }; + + config { + pins = "gpio163"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor2_active: cam_sensor2_active { + /* intr gpio for bridge chip 2 */ + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + bias-pull-up; /* PULL UP */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor2_suspend: cam_sensor2_suspend { + /* intr gpio for bridge chip 2 */ + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor3_active: cam_sensor3_active { + /* intr gpio for bridge chip 3 */ + mux { + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + bias-pull-up; /* PULL UP */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor3_suspend: cam_sensor3_suspend { + /* intr gpio for bridge chip 3 */ + mux { + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; }; diff --git a/qcom/direwolf-regulators.dtsi b/qcom/direwolf-regulators.dtsi index 722eafb5..8cec977e 100755 --- a/qcom/direwolf-regulators.dtsi +++ b/qcom/direwolf-regulators.dtsi @@ -777,3 +777,17 @@ regulator-enable-ramp-delay = <5>; }; }; + +&qupv3_se12_i2c { + VDD_GFX_LEVEL: max20411-regulator@39 { + reg = <0x39>; + compatible = "maxim,max20411"; + regulator-name = "max20411-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <968750>; + proxy-supply = <&VDD_GFX_LEVEL>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = <825000 968750>; + status = "disabled"; + }; +}; diff --git a/qcom/direwolf-usb.dtsi b/qcom/direwolf-usb.dtsi index 05673bf5..aaba8cdf 100755 --- a/qcom/direwolf-usb.dtsi +++ b/qcom/direwolf-usb.dtsi @@ -1,3 +1,6 @@ +#include <dt-bindings/phy/qcom,usb3-5nm-qmp-uni.h> +#include <dt-bindings/phy/qcom,usb4-5nm-qmp-combo.h> + &soc { usb0: ssusb@a600000 { compatible = "qcom,dwc-usb3-msm"; @@ -43,6 +46,7 @@ qcom,core-clk-rate-hs = <66666667>; qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + qcom,ignore-wakeup-src-in-hostmode; interconnect-names = "usb-ddr", "ddr-usb"; interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, @@ -52,17 +56,18 @@ compatible = "snps,dwc3"; reg = <0xa600000 0xd93c>; interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; - usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy0>; linux,sysdev_is_parent; snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; snps,ssp-u3-u0-quirk; snps,is-utmi-l1-suspend; + snps,usb2-gadget-lpm-disable; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; tx-fifo-resize; - maximum-speed = "high-speed"; + maximum-speed = "super-speed-plus"; dr_mode = "otg"; }; }; @@ -89,6 +94,194 @@ 0x17 0x74>; /* override x2 */ }; + /* Primary USB port related USB4-USB3-DP PHY */ + usb_qmp_dp_phy0: ssphy@88eb000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88eb000 0x4000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&L5A0>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L3A0>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB4_EUD_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB4_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + qcom,qmp-phy-reg-offset = + <USB3_PCS_PCS_STATUS1 + USB3_PCS_USB3_AUTONOMOUS_MODE_CTRL + USB3_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR + USB3_PCS_POWER_DOWN_CONTROL + USB3_PCS_SW_RESET + USB3_PCS_START_CONTROL + 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */ + USB43DP_COM_POWER_DOWN_CTRL + USB43DP_COM_SW_RESET + USB43DP_COM_RESET_OVRD_CTRL1 + USB43DP_COM_PHY_MODE_CTRL + USB43DP_COM_TYPEC_CTRL + USB3_PCS_CLAMP_ENABLE + USB43DP_COM_TYPEC_STATUS>; + + qcom,qmp-phy-init-seq = + /* <reg_offset, value, delay> */ + <USB3_QSERDES_PLL_SSC_EN_CENTER 0x01 0 + USB3_QSERDES_PLL_SSC_PER1 0x31 0 + USB3_QSERDES_PLL_SSC_PER2 0x01 0 + USB3_QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0xFD 0 + USB3_QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x0D 0 + USB3_QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0xFD 0 + USB3_QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x0D 0 + USB3_QSERDES_PLL_SYSCLK_BUF_ENABLE 0x0A 0 + USB3_QSERDES_PLL_CP_CTRL_MODE0 0x02 0 + USB3_QSERDES_PLL_CP_CTRL_MODE1 0x02 0 + USB3_QSERDES_PLL_PLL_RCTRL_MODE0 0x16 0 + USB3_QSERDES_PLL_PLL_RCTRL_MODE1 0x16 0 + USB3_QSERDES_PLL_PLL_CCTRL_MODE0 0x36 0 + USB3_QSERDES_PLL_PLL_CCTRL_MODE1 0x36 0 + USB3_QSERDES_PLL_SYSCLK_EN_SEL 0x1A 0 + USB3_QSERDES_PLL_LOCK_CMP_EN 0x04 0 + USB3_QSERDES_PLL_LOCK_CMP1_MODE0 0x14 0 + USB3_QSERDES_PLL_LOCK_CMP2_MODE0 0x34 0 + USB3_QSERDES_PLL_LOCK_CMP1_MODE1 0x34 0 + USB3_QSERDES_PLL_LOCK_CMP2_MODE1 0x82 0 + USB3_QSERDES_PLL_DEC_START_MODE0 0x04 0 + USB3_QSERDES_PLL_DEC_START_MSB_MODE0 0x01 0 + USB3_QSERDES_PLL_DEC_START_MODE1 0x04 0 + USB3_QSERDES_PLL_DEC_START_MSB_MODE1 0x01 0 + USB3_QSERDES_PLL_DIV_FRAC_START1_MODE0 0x55 0 + USB3_QSERDES_PLL_DIV_FRAC_START2_MODE0 0xD5 0 + USB3_QSERDES_PLL_DIV_FRAC_START3_MODE0 0x05 0 + USB3_QSERDES_PLL_DIV_FRAC_START1_MODE1 0x55 0 + USB3_QSERDES_PLL_DIV_FRAC_START2_MODE1 0xD5 0 + USB3_QSERDES_PLL_DIV_FRAC_START3_MODE1 0x05 0 + USB3_QSERDES_PLL_VCO_TUNE_MAP 0x02 0 + USB3_QSERDES_PLL_VCO_TUNE1_MODE0 0xD4 0 + USB3_QSERDES_PLL_VCO_TUNE2_MODE0 0x00 0 + USB3_QSERDES_PLL_VCO_TUNE1_MODE1 0xD4 0 + USB3_QSERDES_PLL_VCO_TUNE2_MODE1 0x00 0 + USB3_QSERDES_PLL_HSCLK_SEL 0x13 0 + USB3_QSERDES_PLL_HSCLK_HS_SWITCH_SEL 0x00 0 + USB3_QSERDES_PLL_CORECLK_DIV_MODE0 0x0A 0 + USB3_QSERDES_PLL_CORECLK_DIV_MODE1 0x04 0 + USB3_QSERDES_PLL_CORE_CLK_EN 0x60 0 + USB3_QSERDES_PLL_CMN_CONFIG 0x76 0 + USB3_QSERDES_PLL_PLL_IVCO 0xFF 0 + USB3_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x20 0 + USB3_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x20 0 + USB3_QSERDES_PLL_VCO_TUNE_INITVAL2 0x00 0 + USB3_QSERDES_PLL_VCO_TUNE_MAXVAL2 0x01 0 + USB3_QSERDES_PLL_SVS_MODE_CLK_SEL 0x0A 0 + USB43DP_QSERDES_TXA_LANE_MODE_1 0x05 0 + USB43DP_QSERDES_TXA_LANE_MODE_2 0xC2 0 + USB43DP_QSERDES_TXA_LANE_MODE_3 0x10 0 + USB43DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x1F 0 + USB43DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0A 0 + USB43DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0 + USB43DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0 + USB43DP_QSERDES_RXA_SIGDET_ENABLES 0x00 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B0 0xD2 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B1 0xD2 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B2 0xDB 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B3 0x21 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B4 0x3F 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B5 0x80 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B6 0x45 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B7 0x00 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B0 0x6B 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B1 0x63 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B2 0xB6 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B3 0x23 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B4 0x35 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B5 0x30 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B6 0x8E 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B7 0x00 0 + USB43DP_QSERDES_RXA_RX_IVCM_CAL_CODE_OVERRIDE 0x00 0 + USB43DP_QSERDES_RXA_RX_IVCM_CAL_CTRL2 0x80 0 + USB43DP_QSERDES_RXA_RX_SUMMER_CAL_SPD_MODE 0x1B 0 + USB43DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0 + USB43DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x15 0 + USB43DP_QSERDES_RXA_UCDR_SB2_GAIN2_RATE2 0x0A 0 + USB43DP_QSERDES_RXA_RX_IVCM_POSTCAL_OFFSET 0x7C 0 + USB43DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x00 0 + USB43DP_QSERDES_RXA_VGA_CAL_MAN_VAL 0x0D 0 + USB43DP_QSERDES_RXA_DFE_DAC_ENABLE1 0x00 0 + USB43DP_QSERDES_RXA_DFE_3 0x45 0 + USB43DP_QSERDES_RXA_GM_CAL 0x09 0 + USB43DP_QSERDES_RXA_UCDR_FO_GAIN_RATE2 0x09 0 + USB43DP_QSERDES_RXA_UCDR_SO_GAIN_RATE2 0x05 0 + USB43DP_QSERDES_RXA_Q_PI_INTRINSIC_BIAS_RATE32 0x3F 0 + USB43DP_QSERDES_TXB_LANE_MODE_1 0x05 0 + USB43DP_QSERDES_TXB_LANE_MODE_2 0xC2 0 + USB43DP_QSERDES_TXB_LANE_MODE_3 0x10 0 + USB43DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x1F 0 + USB43DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0A 0 + USB43DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0 + USB43DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0 + USB43DP_QSERDES_RXB_SIGDET_ENABLES 0x00 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B0 0xD2 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B1 0xD2 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B2 0xDB 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B3 0x21 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B4 0x3F 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B5 0x80 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B6 0x45 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B7 0x00 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B0 0x6B 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B1 0x63 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B2 0xB6 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B3 0x23 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B4 0x35 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B5 0x30 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B6 0x8E 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B7 0x00 0 + USB43DP_QSERDES_RXB_RX_IVCM_CAL_CODE_OVERRIDE 0x00 0 + USB43DP_QSERDES_RXB_RX_IVCM_CAL_CTRL2 0x80 0 + USB43DP_QSERDES_RXB_RX_SUMMER_CAL_SPD_MODE 0x1B 0 + USB43DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0 + USB43DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x15 0 + USB43DP_QSERDES_RXB_UCDR_SB2_GAIN2_RATE2 0x0A 0 + USB43DP_QSERDES_RXB_RX_IVCM_POSTCAL_OFFSET 0x7C 0 + USB43DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x00 0 + USB43DP_QSERDES_RXB_VGA_CAL_MAN_VAL 0x0D 0 + USB43DP_QSERDES_RXB_DFE_DAC_ENABLE1 0x00 0 + USB43DP_QSERDES_RXB_DFE_3 0x45 0 + USB43DP_QSERDES_RXB_GM_CAL 0x09 0 + USB43DP_QSERDES_RXB_UCDR_FO_GAIN_RATE2 0x09 0 + USB43DP_QSERDES_RXB_UCDR_SO_GAIN_RATE2 0x05 0 + USB43DP_QSERDES_RXB_Q_PI_INTRINSIC_BIAS_RATE32 0x3F 0 + USB3_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0 + USB3_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0 + USB3_PCS_LOCK_DETECT_CONFIG1 0xD0 0 + USB3_PCS_LOCK_DETECT_CONFIG2 0x07 0 + USB3_PCS_LOCK_DETECT_CONFIG3 0x20 0 + USB3_PCS_LOCK_DETECT_CONFIG6 0x13 0 + USB3_PCS_REFGEN_REQ_CONFIG1 0x21 0 + USB3_PCS_RX_SIGDET_LVL 0xAA 0 + USB3_PCS_RX_CONFIG 0x0A 0 + USB3_PCS_ALIGN_DETECT_CONFIG1 0x88 0 + USB3_PCS_ALIGN_DETECT_CONFIG2 0x13 0 + USB3_PCS_PCS_TX_RX_CONFIG 0x0C 0 + USB3_PCS_EQ_CONFIG1 0x4B 0 + USB3_PCS_EQ_CONFIG5 0x10 0 + USB3_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0 + USB3_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0 + 0xffffffff 0xffffffff 0x00>; + }; + usb_nop_phy: usb_nop_phy { compatible = "usb-nop-xceiv"; }; @@ -137,6 +330,7 @@ qcom,core-clk-rate-hs = <66666667>; qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + qcom,ignore-wakeup-src-in-hostmode; qcom,default-mode-host; interconnect-names = "usb-ddr", "ddr-usb"; @@ -147,17 +341,18 @@ compatible = "snps,dwc3"; reg = <0xa800000 0xd93c>; interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; - usb-phy = <&usb2_phy1>, <&usb_nop_phy>; + usb-phy = <&usb2_phy1>, <&usb_qmp_dp_phy1>; linux,sysdev_is_parent; snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; snps,ssp-u3-u0-quirk; snps,is-utmi-l1-suspend; + snps,usb2-gadget-lpm-disable; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; tx-fifo-resize; - maximum-speed = "high-speed"; + maximum-speed = "super-speed-plus"; dr_mode = "otg"; }; }; @@ -184,6 +379,194 @@ 0x17 0x74>; /* override x2 */ }; + /* Secondary USB port related USB4-USB3-DP PHY */ + usb_qmp_dp_phy1: ssphy@8903000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x8903000 0x4000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&L1C0>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L4C0>; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, + <&usb3_uni_phy_sec_gcc_usb30_pipe_clk>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB4_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + qcom,qmp-phy-reg-offset = + <USB3_PCS_PCS_STATUS1 + USB3_PCS_USB3_AUTONOMOUS_MODE_CTRL + USB3_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR + USB3_PCS_POWER_DOWN_CONTROL + USB3_PCS_SW_RESET + USB3_PCS_START_CONTROL + 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */ + USB43DP_COM_POWER_DOWN_CTRL + USB43DP_COM_SW_RESET + USB43DP_COM_RESET_OVRD_CTRL1 + USB43DP_COM_PHY_MODE_CTRL + USB43DP_COM_TYPEC_CTRL + USB3_PCS_CLAMP_ENABLE + USB43DP_COM_TYPEC_STATUS>; + + qcom,qmp-phy-init-seq = + /* <reg_offset, value, delay> */ + <USB3_QSERDES_PLL_SSC_EN_CENTER 0x01 0 + USB3_QSERDES_PLL_SSC_PER1 0x31 0 + USB3_QSERDES_PLL_SSC_PER2 0x01 0 + USB3_QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0xFD 0 + USB3_QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x0D 0 + USB3_QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0xFD 0 + USB3_QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x0D 0 + USB3_QSERDES_PLL_SYSCLK_BUF_ENABLE 0x0A 0 + USB3_QSERDES_PLL_CP_CTRL_MODE0 0x02 0 + USB3_QSERDES_PLL_CP_CTRL_MODE1 0x02 0 + USB3_QSERDES_PLL_PLL_RCTRL_MODE0 0x16 0 + USB3_QSERDES_PLL_PLL_RCTRL_MODE1 0x16 0 + USB3_QSERDES_PLL_PLL_CCTRL_MODE0 0x36 0 + USB3_QSERDES_PLL_PLL_CCTRL_MODE1 0x36 0 + USB3_QSERDES_PLL_SYSCLK_EN_SEL 0x1A 0 + USB3_QSERDES_PLL_LOCK_CMP_EN 0x04 0 + USB3_QSERDES_PLL_LOCK_CMP1_MODE0 0x14 0 + USB3_QSERDES_PLL_LOCK_CMP2_MODE0 0x34 0 + USB3_QSERDES_PLL_LOCK_CMP1_MODE1 0x34 0 + USB3_QSERDES_PLL_LOCK_CMP2_MODE1 0x82 0 + USB3_QSERDES_PLL_DEC_START_MODE0 0x04 0 + USB3_QSERDES_PLL_DEC_START_MSB_MODE0 0x01 0 + USB3_QSERDES_PLL_DEC_START_MODE1 0x04 0 + USB3_QSERDES_PLL_DEC_START_MSB_MODE1 0x01 0 + USB3_QSERDES_PLL_DIV_FRAC_START1_MODE0 0x55 0 + USB3_QSERDES_PLL_DIV_FRAC_START2_MODE0 0xD5 0 + USB3_QSERDES_PLL_DIV_FRAC_START3_MODE0 0x05 0 + USB3_QSERDES_PLL_DIV_FRAC_START1_MODE1 0x55 0 + USB3_QSERDES_PLL_DIV_FRAC_START2_MODE1 0xD5 0 + USB3_QSERDES_PLL_DIV_FRAC_START3_MODE1 0x05 0 + USB3_QSERDES_PLL_VCO_TUNE_MAP 0x02 0 + USB3_QSERDES_PLL_VCO_TUNE1_MODE0 0xD4 0 + USB3_QSERDES_PLL_VCO_TUNE2_MODE0 0x00 0 + USB3_QSERDES_PLL_VCO_TUNE1_MODE1 0xD4 0 + USB3_QSERDES_PLL_VCO_TUNE2_MODE1 0x00 0 + USB3_QSERDES_PLL_HSCLK_SEL 0x13 0 + USB3_QSERDES_PLL_HSCLK_HS_SWITCH_SEL 0x00 0 + USB3_QSERDES_PLL_CORECLK_DIV_MODE0 0x0A 0 + USB3_QSERDES_PLL_CORECLK_DIV_MODE1 0x04 0 + USB3_QSERDES_PLL_CORE_CLK_EN 0x60 0 + USB3_QSERDES_PLL_CMN_CONFIG 0x76 0 + USB3_QSERDES_PLL_PLL_IVCO 0xFF 0 + USB3_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x20 0 + USB3_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x20 0 + USB3_QSERDES_PLL_VCO_TUNE_INITVAL2 0x00 0 + USB3_QSERDES_PLL_VCO_TUNE_MAXVAL2 0x01 0 + USB3_QSERDES_PLL_SVS_MODE_CLK_SEL 0x0A 0 + USB43DP_QSERDES_TXA_LANE_MODE_1 0x05 0 + USB43DP_QSERDES_TXA_LANE_MODE_2 0xC2 0 + USB43DP_QSERDES_TXA_LANE_MODE_3 0x10 0 + USB43DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x1F 0 + USB43DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0A 0 + USB43DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0 + USB43DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0 + USB43DP_QSERDES_RXA_SIGDET_ENABLES 0x00 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B0 0xD2 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B1 0xD2 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B2 0xDB 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B3 0x21 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B4 0x3F 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B5 0x80 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B6 0x45 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B7 0x00 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B0 0x6B 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B1 0x63 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B2 0xB6 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B3 0x23 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B4 0x35 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B5 0x30 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B6 0x8E 0 + USB43DP_QSERDES_RXA_RX_MODE_RATE2_B7 0x00 0 + USB43DP_QSERDES_RXA_RX_IVCM_CAL_CODE_OVERRIDE 0x00 0 + USB43DP_QSERDES_RXA_RX_IVCM_CAL_CTRL2 0x80 0 + USB43DP_QSERDES_RXA_RX_SUMMER_CAL_SPD_MODE 0x1B 0 + USB43DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0 + USB43DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x15 0 + USB43DP_QSERDES_RXA_UCDR_SB2_GAIN2_RATE2 0x0A 0 + USB43DP_QSERDES_RXA_RX_IVCM_POSTCAL_OFFSET 0x7C 0 + USB43DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x00 0 + USB43DP_QSERDES_RXA_VGA_CAL_MAN_VAL 0x0D 0 + USB43DP_QSERDES_RXA_DFE_DAC_ENABLE1 0x00 0 + USB43DP_QSERDES_RXA_DFE_3 0x45 0 + USB43DP_QSERDES_RXA_GM_CAL 0x09 0 + USB43DP_QSERDES_RXA_UCDR_FO_GAIN_RATE2 0x09 0 + USB43DP_QSERDES_RXA_UCDR_SO_GAIN_RATE2 0x05 0 + USB43DP_QSERDES_RXA_Q_PI_INTRINSIC_BIAS_RATE32 0x3F 0 + USB43DP_QSERDES_TXB_LANE_MODE_1 0x05 0 + USB43DP_QSERDES_TXB_LANE_MODE_2 0xC2 0 + USB43DP_QSERDES_TXB_LANE_MODE_3 0x10 0 + USB43DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x1F 0 + USB43DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0A 0 + USB43DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0 + USB43DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0 + USB43DP_QSERDES_RXB_SIGDET_ENABLES 0x00 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B0 0xD2 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B1 0xD2 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B2 0xDB 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B3 0x21 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B4 0x3F 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B5 0x80 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B6 0x45 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B7 0x00 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B0 0x6B 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B1 0x63 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B2 0xB6 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B3 0x23 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B4 0x35 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B5 0x30 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B6 0x8E 0 + USB43DP_QSERDES_RXB_RX_MODE_RATE2_B7 0x00 0 + USB43DP_QSERDES_RXB_RX_IVCM_CAL_CODE_OVERRIDE 0x00 0 + USB43DP_QSERDES_RXB_RX_IVCM_CAL_CTRL2 0x80 0 + USB43DP_QSERDES_RXB_RX_SUMMER_CAL_SPD_MODE 0x1B 0 + USB43DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0 + USB43DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x15 0 + USB43DP_QSERDES_RXB_UCDR_SB2_GAIN2_RATE2 0x0A 0 + USB43DP_QSERDES_RXB_RX_IVCM_POSTCAL_OFFSET 0x7C 0 + USB43DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x00 0 + USB43DP_QSERDES_RXB_VGA_CAL_MAN_VAL 0x0D 0 + USB43DP_QSERDES_RXB_DFE_DAC_ENABLE1 0x00 0 + USB43DP_QSERDES_RXB_DFE_3 0x45 0 + USB43DP_QSERDES_RXB_GM_CAL 0x09 0 + USB43DP_QSERDES_RXB_UCDR_FO_GAIN_RATE2 0x09 0 + USB43DP_QSERDES_RXB_UCDR_SO_GAIN_RATE2 0x05 0 + USB43DP_QSERDES_RXB_Q_PI_INTRINSIC_BIAS_RATE32 0x3F 0 + USB3_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0 + USB3_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0 + USB3_PCS_LOCK_DETECT_CONFIG1 0xD0 0 + USB3_PCS_LOCK_DETECT_CONFIG2 0x07 0 + USB3_PCS_LOCK_DETECT_CONFIG3 0x20 0 + USB3_PCS_LOCK_DETECT_CONFIG6 0x13 0 + USB3_PCS_REFGEN_REQ_CONFIG1 0x21 0 + USB3_PCS_RX_SIGDET_LVL 0xAA 0 + USB3_PCS_RX_CONFIG 0x0A 0 + USB3_PCS_ALIGN_DETECT_CONFIG1 0x88 0 + USB3_PCS_ALIGN_DETECT_CONFIG2 0x13 0 + USB3_PCS_PCS_TX_RX_CONFIG 0x0C 0 + USB3_PCS_EQ_CONFIG1 0x4B 0 + USB3_PCS_EQ_CONFIG5 0x10 0 + USB3_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0 + USB3_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0 + 0xffffffff 0xffffffff 0x00>; + }; + /* Tertiary USB port related controller */ usb2: ssusb@a400000 { compatible = "qcom,dwc-usb3-msm"; @@ -235,6 +618,7 @@ reset-names = "core_reset"; qcom,core-clk-rate = <200000000>; + qcom,ignore-wakeup-src-in-hostmode; interconnect-names = "usb-ddr", "ddr-usb"; interconnects = <&aggre1_noc MASTER_USB3_MP &mc_virt SLAVE_EBI1>, @@ -244,8 +628,8 @@ compatible = "snps,dwc3"; reg = <0xa400000 0xd93c>; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; - usb-phy = <&usb2_phy2>, <&usb_nop_phy>, - <&usb2_phy3>, <&usb_nop_phy>, + usb-phy = <&usb2_phy2>, <&usb_qmp_phy0>, + <&usb2_phy3>, <&usb_qmp_phy1>, <&usb2_phy4>, <&usb_nop_phy>, <&usb2_phy5>, <&usb_nop_phy>; linux,sysdev_is_parent; @@ -254,10 +638,8 @@ snps,hird-threshold = /bits/ 8 <0x0>; snps,ssp-u3-u0-quirk; snps,is-utmi-l1-suspend; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; snps,dis_u3_susphy_quirk; - maximum-speed = "high-speed"; + maximum-speed = "super-speed-plus"; dr_mode = "host"; }; }; @@ -284,6 +666,140 @@ 0x17 0x74>; /* override x2 */ }; + /* Tertiary USB port 0 related QMP PHY */ + usb_qmp_phy0: ssphy@88ef000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88ef000 0x2000>, + <0x088ef28c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&L5A0>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L3A0>; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK_SRC>, + <&usb3_uni_phy_mp_gcc_usb30_pipe_0_clk>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP0_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + + qcom,qmp-phy-reg-offset = + <USB3_UNI_PCS_PCS_STATUS1 + USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL + USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR + USB3_UNI_PCS_POWER_DOWN_CONTROL + USB3_UNI_PCS_SW_RESET + USB3_UNI_PCS_START_CONTROL>; + + qcom,qmp-phy-init-seq = + /* <reg_offset, value, delay> */ + <USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0 + USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0 + USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0 + USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x06 0 + USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0 + USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0 + USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0 + USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0 + USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0 + USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0 + USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0 + USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0 + USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0 + USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0 + USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0 + USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0 + USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0 + USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0 + USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0 + USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0 + USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0 + USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0 + USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0 + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0 + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0 + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0 + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0 + USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xDC 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xBD 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xFF 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7F 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xFF 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xA9 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7B 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0xE4 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0x24 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0x64 0 + USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0 + USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x08 0 + USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0 + USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x00 0 + USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x04 0 + USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2F 0 + USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xFF 0 + USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0 + USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A 0 + USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0 + USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0F 0 + USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0F 0 + USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0A 0 + USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0 + USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0 + USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0 + USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0E 0 + USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38 0 + USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x05 0 + USB3_UNI_QSERDES_RX_GM_CAL 0x00 0 + USB3_UNI_QSERDES_RX_SIGDET_ENABLES 0x00 0 + USB3_UNI_QSERDES_TX_LANE_MODE_1 0xA5 0 + USB3_UNI_QSERDES_TX_LANE_MODE_2 0x82 0 + USB3_UNI_QSERDES_TX_LANE_MODE_3 0x3F 0 + USB3_UNI_QSERDES_TX_LANE_MODE_4 0x3F 0 + USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x21 0 + USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10 0 + USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x0E 0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xD0 0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0 + USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0 + USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0 + USB3_UNI_PCS_RX_SIGDET_LVL 0xAA 0 + USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0C 0 + USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0 + USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0 + USB3_UNI_PCS_CDR_RESET_TIME 0x0A 0 + USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0 + USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0 + USB3_UNI_PCS_EQ_CONFIG1 0x4B 0 + USB3_UNI_PCS_EQ_CONFIG5 0x10 0 + USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0 + 0xffffffff 0xffffffff 0x00>; + }; + /* Tertiary USB port 1 related High Speed PHY */ usb2_phy3: hsphy@88e8000 { compatible = "qcom,usb-hsphy-snps-femto"; @@ -306,6 +822,140 @@ 0x17 0x74>; /* override x2 */ }; + /* Tertiary USB port 1 related QMP PHY */ + usb_qmp_phy1: ssphy@88f1000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88f1000 0x2000>, + <0x088f128c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&L5A0>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L3A0>; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK_SRC>, + <&usb3_uni_phy_mp_gcc_usb30_pipe_1_clk>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP1_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + + qcom,qmp-phy-reg-offset = + <USB3_UNI_PCS_PCS_STATUS1 + USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL + USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR + USB3_UNI_PCS_POWER_DOWN_CONTROL + USB3_UNI_PCS_SW_RESET + USB3_UNI_PCS_START_CONTROL>; + + qcom,qmp-phy-init-seq = + /* <reg_offset, value, delay> */ + <USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0 + USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0 + USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0 + USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x06 0 + USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0 + USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0 + USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0 + USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0 + USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0 + USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0 + USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0 + USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0 + USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0 + USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0 + USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0 + USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0 + USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0 + USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0 + USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0 + USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0 + USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0 + USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0 + USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0 + USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0 + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0 + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0 + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0 + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0 + USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xDC 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xBD 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xFF 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7F 0 + USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xFF 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xA9 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7B 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0xE4 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0x24 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0x64 0 + USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0 + USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x08 0 + USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0 + USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x00 0 + USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x04 0 + USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2F 0 + USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xFF 0 + USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0 + USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A 0 + USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0 + USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0F 0 + USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0F 0 + USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0A 0 + USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0 + USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0 + USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0 + USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0E 0 + USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38 0 + USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x05 0 + USB3_UNI_QSERDES_RX_GM_CAL 0x00 0 + USB3_UNI_QSERDES_RX_SIGDET_ENABLES 0x00 0 + USB3_UNI_QSERDES_TX_LANE_MODE_1 0xA5 0 + USB3_UNI_QSERDES_TX_LANE_MODE_2 0x82 0 + USB3_UNI_QSERDES_TX_LANE_MODE_3 0x3F 0 + USB3_UNI_QSERDES_TX_LANE_MODE_4 0x3F 0 + USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x21 0 + USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10 0 + USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x0E 0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xD0 0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0 + USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0 + USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0 + USB3_UNI_PCS_RX_SIGDET_LVL 0xAA 0 + USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0C 0 + USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0 + USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0 + USB3_UNI_PCS_CDR_RESET_TIME 0x0A 0 + USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0 + USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0 + USB3_UNI_PCS_EQ_CONFIG1 0x4B 0 + USB3_UNI_PCS_EQ_CONFIG5 0x10 0 + USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0 + 0xffffffff 0xffffffff 0x00>; + }; + /* Tertiary USB port 2 related High Speed PHY */ usb2_phy4: hsphy@88e9000 { compatible = "qcom,usb-hsphy-snps-femto"; diff --git a/qcom/direwolf-vm-la-mt.dts b/qcom/direwolf-vm-la-mt.dts new file mode 100755 index 00000000..c8b79758 --- /dev/null +++ b/qcom/direwolf-vm-la-mt.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "direwolf-vm.dtsi" +#include "direwolf-vm-la-mt.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Direwolf Multi LA Virtual Machine"; + compatible = "qcom,direwolf"; + qcom,board-id = <0x2000001 0>; +}; + diff --git a/qcom/direwolf-vm-la-mt.dtsi b/qcom/direwolf-vm-la-mt.dtsi new file mode 100755 index 00000000..8f017361 --- /dev/null +++ b/qcom/direwolf-vm-la-mt.dtsi @@ -0,0 +1,57 @@ +&reserved_memory { + pmem_shared: pmem_shared_region { + reg = <0x1 0x6a500000 0x0 0x51400000>; + label = "pmem_shared_mem"; + }; +}; + +#include "display/quin-vm-display-la.dtsi" +#include "direwolf-cnss.dtsi" + +/ { + rename_blk: rename_blk { + compatible = "qcom,blkdev-rename"; + actual-dev = "vda", "vdb", "vdc", + "vdd", "vde", "vdf", + "vdg", "vdh"; + rename-dev = "system", "userdata", "vendor", + "persist", "modem", "bluetooth", + "misc", "vbmeta"; + }; +}; + +&usb0 { + status = "okay"; +}; + +&usb2_phy0 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb2_phy2 { + status = "okay"; +}; + +&usb2_phy3 { + status = "okay"; +}; + +&usb2_phy4 { + status = "okay"; +}; + +&usb2_phy5 { + status = "okay"; +}; + +&pcie4 { + status = "okay"; +}; + +&pcie4_msi_snps { + status = "okay"; +}; diff --git a/qcom/direwolf-vm-la.dtsi b/qcom/direwolf-vm-la.dtsi index 7cc58f95..41aa3b3b 100755 --- a/qcom/direwolf-vm-la.dtsi +++ b/qcom/direwolf-vm-la.dtsi @@ -26,3 +26,23 @@ "misc", "vbmeta"; }; }; + +&usb2 { + status = "okay"; +}; + +&usb2_phy2 { + status = "okay"; +}; + +&usb2_phy3 { + status = "okay"; +}; + +&usb2_phy4 { + status = "okay"; +}; + +&usb2_phy5 { + status = "okay"; +}; diff --git a/qcom/direwolf-vm-lv-mt.dts b/qcom/direwolf-vm-lv-mt.dts new file mode 100755 index 00000000..97e0bf4d --- /dev/null +++ b/qcom/direwolf-vm-lv-mt.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "direwolf-vm.dtsi" +#include "direwolf-vm-lv-mt.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Direwolf Multi LV Virtual Machine"; + compatible = "qcom,direwolf"; + qcom,board-id = <0x2000002 0>; +}; + diff --git a/qcom/direwolf-vm-lv-mt.dtsi b/qcom/direwolf-vm-lv-mt.dtsi new file mode 100755 index 00000000..def95592 --- /dev/null +++ b/qcom/direwolf-vm-lv-mt.dtsi @@ -0,0 +1,28 @@ +&hab { + vmid = <3>; +}; + +&reserved_memory { + pmem_shared: pmem_shared_region { + reg = <0x1 0x66500000 0x0 0x51400000>; + label = "pmem_shared_mem"; + }; +}; + +#include "display/quin-vm-display-lxc.dtsi" + +&usb1 { + status = "okay"; +}; + +&usb2_phy1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie2a_msi_snps { + status = "okay"; +}; diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index 144d9443..cabf6936 100755 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -3,7 +3,7 @@ / { model = "Qualcomm Technologies, Inc. Direwolf Virtual Machine"; - qcom,msm-name = "Direwolf V1"; + qcom,msm-name = "SA_DIREWOLF_IVI"; qcom,msm-id = <460 0x10000>; aliases { @@ -190,8 +190,14 @@ clock-names = "km_clk_src"; }; + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + }; + qtee_shmbridge { compatible = "qcom,tee-shared-memory-bridge"; + /*Boolean property to disable shmbridge*/ + qcom,disable-shmbridge-support; }; qcom_qseecom: qseecom@c1800000 { @@ -287,6 +293,92 @@ clock-output-names = "pcie_4_pipe_clk"; #clock-cells = <0>; }; + + emac_ctrl_fe: emac_ctrl_drv@0x1d000000 { + compatible = "virtio,mmio"; + reg =<0x1d000000 0x1000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + + queue { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + snps,tx-sched-sp; + queue { + snps,dcb-algorithm; + }; + }; + + emac0_hw: qcom,ethernet@00020000 { + compatible = "qcom,stmmac-ethqos-emac0"; + emac-core-version = <0x30000000>; + qcom,arm-smmu; + reg = <0x2A000 0x1000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc 0 945 4>, <&intc 0 944 4>, + <&intc 0 943 4>, <&intc 0 942 4>, + <&intc 0 941 4>, <&intc 0 940 4>, + <&intc 0 939 4>, <&intc 0 938 4>; + interrupt-names = "tx_rx_ch0_intr", "tx_rx_ch1_intr", + "tx_rx_ch2_intr", "tx_rx_ch3_intr", + "tx_rx_ch4_intr", "tx_rx_ch5_intr", + "tx_rx_ch6_intr", "tx_rx_ch7_intr"; + + snps,tso; + snps,pbl = <32>; + mac-address = [00 55 7B B5 7D f7]; + rx-fifo-depth = <4096>; + tx-fifo-depth = <4096>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + queue = <2>; + + emac0_emb_smmu: emac0_emb_smmu { + compatible = "qcom,emac-smmu-embedded"; + iommus = <&apps_smmu 0x4C4 0x1>; + qcom,iommu-dma-addr-pool = <0x80000000 0x40000000>; + }; + }; + + emac1_hw: qcom,ethernet@23000000 { + compatible = "qcom,stmmac-ethqos-emac1"; + emac-core-version = <0x30000000>; + qcom,arm-smmu; + reg = <0x2300A000 0x1000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc 0 772 4>, <&intc 0 773 4>, + <&intc 0 774 4>, <&intc 0 775 4>, + <&intc 0 776 4>, <&intc 0 777 4>, + <&intc 0 778 4>, <&intc 0 937 4>; + interrupt-names = "tx_rx_ch0_intr", "tx_rx_ch1_intr", + "tx_rx_ch2_intr", "tx_rx_ch3_intr", + "tx_rx_ch4_intr", "tx_rx_ch5_intr", + "tx_rx_ch6_intr", "tx_rx_ch7_intr"; + + snps,tso; + snps,pbl = <32>; + mac-address = [00 55 7B B5 7D f7]; + rx-fifo-depth = <4096>; + tx-fifo-depth = <4096>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + queue = <2>; + + emac1_emb_smmu: emac1_emb_smmu { + compatible = "qcom,emac-smmu-embedded"; + iommus = <&apps_smmu 0x44 0x1>; + qcom,iommu-dma-addr-pool = <0x80000000 0x40000000>; + }; + }; }; ®ulator { diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 1a08dcdb..af0acd7b 100755 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/clock/qcom,camcc-direwolf.h> #include <dt-bindings/clock/qcom,dispcc-direwolf.h> #include <dt-bindings/clock/qcom,gcc-direwolf.h> +#include <dt-bindings/clock/qcom,gpucc-direwolf.h> #include <dt-bindings/clock/qcom,videocc-direwolf.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> @@ -42,6 +43,7 @@ pci-domain2 = &pcie2; /* PCIe2 domain */ pci-domain3 = &pcie3; /* PCIe3 domain */ pci-domain4 = &pcie4; /* PCIe4 domain */ + spi22 = &qupv3_se22_spi; }; cpus { @@ -373,7 +375,7 @@ alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>; reusable; alignment = <0x0 0x400000>; - size = <0x0 0x2000000>; + size = <0x0 0x3c00000>; linux,cma-default; }; }; @@ -956,6 +958,24 @@ #reset-cells = <1>; }; + gpucc: clock-controller@3d90000 { + compatible = "qcom,direwolf-gpucc", "syscon"; + reg = <0x3d90000 0x9000>; + reg-name = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src", + "iface"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + apsscc: syscon@182a0000 { compatible = "syscon"; reg = <0x182a0000 0x1c>; @@ -971,6 +991,7 @@ qcom,apsscc = <&apsscc>; qcom,camcc = <&camcc>; qcom,gcc = <&gcc>; + qcom,gpucc = <&gpucc>; qcom,dispcc0 = <&dispcc0>; qcom,dispcc1 = <&dispcc1>; qcom,mccc = <&mccc>; @@ -2429,16 +2450,19 @@ }; #include "direwolf-pinctrl.dtsi" +#include "direwolf-qupv3.dtsi" #include "direwolf-regulators.dtsi" #include "direwolf-pm.dtsi" #include "direwolf-gdsc.dtsi" #include "direwolf-ion.dtsi" #include "msm-arm-smmu-direwolf.dtsi" -#include "direwolf-qupv3.dtsi" #include "direwolf-usb.dtsi" #include "direwolf-smp2p.dtsi" #include "direwolf-pcie.dtsi" #include "display/direwolf-sde.dtsi" +#include "direwolf-audio.dtsi" +#include "camera/direwolf-camera.dtsi" +#include "camera/direwolf-camera-sensor.dtsi" &gcc_emac0_gdsc { status = "ok"; @@ -2659,6 +2683,23 @@ status = "ok"; }; +&gpu_cc_cx_gdsc { + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; + status = "ok"; +}; + +&gpu_cc_gx_gdsc { + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "ahb_clk"; + parent-supply = <&VDD_GFX_LEVEL>; + qcom,retain-regs; + qcom,skip-disable-before-sw-enable; + status = "ok"; +}; + &qupv3_se17_2uart { status = "ok"; }; diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index cd8d005b..fdf4ef50 100755 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1013,6 +1013,7 @@ clk_virt: interconnect { compatible = "qcom,holi-clk_virt"; #interconnect-cells = <1>; + qcom,keepalive; clock-names = "bus", "bus_a"; clocks = <&rpmcc RPM_SMD_QUP_CLK>, <&rpmcc RPM_SMD_QUP_A_CLK>; diff --git a/qcom/lemans-adp-air.dts b/qcom/lemans-adp-air.dts new file mode 100755 index 00000000..9f58cd5b --- /dev/null +++ b/qcom/lemans-adp-air.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +#include "lemans-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans ADP AIR"; + compatible = "qcom,lemans", "qcom,adp-air", "qcom,lemans-adp-air"; +}; diff --git a/qcom/lemans-adp-air.dtsi b/qcom/lemans-adp-air.dtsi new file mode 100755 index 00000000..ca6ccc52 --- /dev/null +++ b/qcom/lemans-adp-air.dtsi @@ -0,0 +1 @@ + #include "lemans-adp-common.dtsi" diff --git a/qcom/lemans-adp-common.dtsi b/qcom/lemans-adp-common.dtsi new file mode 100755 index 00000000..612056c7 --- /dev/null +++ b/qcom/lemans-adp-common.dtsi @@ -0,0 +1,7 @@ +#include "lemans.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans ADP"; + compatible = "qcom,lemans", "qcom,adp"; + qcom,board-id = <25 0>; +}; diff --git a/qcom/lemans-adp-star.dts b/qcom/lemans-adp-star.dts new file mode 100755 index 00000000..6babf5b4 --- /dev/null +++ b/qcom/lemans-adp-star.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +#include "lemans-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans ADP STAR"; + compatible = "qcom,lemans", "qcom,adp-star", "qcom,lemans-adp-star"; +}; diff --git a/qcom/lemans-adp-star.dtsi b/qcom/lemans-adp-star.dtsi new file mode 100755 index 00000000..689bf563 --- /dev/null +++ b/qcom/lemans-adp-star.dtsi @@ -0,0 +1 @@ +#include "lemans-adp-common.dtsi" diff --git a/qcom/lemans-rumi.dts b/qcom/lemans-rumi.dts new file mode 100755 index 00000000..223c7f04 --- /dev/null +++ b/qcom/lemans-rumi.dts @@ -0,0 +1,10 @@ +/dts-v1/; +/memreserve/ 0x90000000 0x00000100; + +#include "lemans-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans RUMI"; + compatible = "qcom,lemans", "qcom,rumi", "qcom,lemans-rumi"; + qcom,board-id = <15 0>; +}; diff --git a/qcom/lemans-rumi.dtsi b/qcom/lemans-rumi.dtsi new file mode 100755 index 00000000..e77b64ca --- /dev/null +++ b/qcom/lemans-rumi.dtsi @@ -0,0 +1,9 @@ +#include "lemans.dtsi" + +&arch_timer { + clock-frequency = <500000>; +}; + +&memtimer { + clock-frequency = <500000>; +}; diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi new file mode 100755 index 00000000..09f3e780 --- /dev/null +++ b/qcom/lemans.dtsi @@ -0,0 +1,289 @@ +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Qualcomm Technologies, Inc. Lemans"; + compatible = "qcom,lemans"; + qcom,msm-id = <532 0x10000>, <534 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + chosen: chosen { }; + + aliases { }; + + soc: soc { }; + + firmware: firmware { }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x90000000>; + cache-size = <0x20000>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + cache-size = <0x80000>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-level = <3>; + cache-size = <0x200000>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x90000000>; + cache-size = <0x20000>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + cache-size = <0x80000>; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x90000000>; + cache-size = <0x20000>; + next-level-cache = <&L2_2>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + cache-size = <0x80000>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x90000000>; + cache-size = <0x20000>; + next-level-cache = <&L2_3>; + L2_3: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + cache-size = <0x80000>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "spin-table"; + cache-size = <0x20000>; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_4>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + cache-size = <0x80000>; + next-level-cache = <&L3_1>; + L3_1: l3-cache { + compatible = "arm,arch-cache"; + cache-level = <3>; + cache-size = <0x200000>; + }; + + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x90000000>; + cache-size = <0x20000>; + next-level-cache = <&L2_5>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + cache-size = <0x80000>; + next-level-cache = <&L3_1>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x90000000>; + cache-size = <0x20000>; + next-level-cache = <&L2_6>; + L2_6: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + cache-size = <0x80000>; + next-level-cache = <&L3_1>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x90000000>; + cache-size = <0x20000>; + next-level-cache = <&L2_7>; + L2_7: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + cache-size = <0x80000>; + next-level-cache = <&L3_1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <19200000>; + }; + + memtimer: timer@17c20000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17c20000 0x1000>; + clock-frequency = <19200000>; + + frame@17c21000 { + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c27000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/monaco-1gb.dtsi b/qcom/monaco-1gb.dtsi index 18dde94f..7c26c724 100755 --- a/qcom/monaco-1gb.dtsi +++ b/qcom/monaco-1gb.dtsi @@ -1 +1,11 @@ #include "monaco.dtsi" + +/ { + reserved-memory { + /delete-node/deepsleep_region@45700000; + }; +}; + +&removed_region { + reg = <0x0 0x61000000 0x0 0x0B00000>; +}; diff --git a/qcom/monaco-amic-audio-overlay.dtsi b/qcom/monaco-amic-audio-overlay.dtsi index 0ba74f47..01f0e1d7 100755 --- a/qcom/monaco-amic-audio-overlay.dtsi +++ b/qcom/monaco-amic-audio-overlay.dtsi @@ -3,201 +3,22 @@ #include <dt-bindings/sound/audio-codec-port-types.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -&spf_core_platform { - rx_swr_gpios: rx_swr_clk_data_pinctrl { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active>; - pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep>; - qcom,lpi-gpios; - }; - - bolero: bolero-cdc { - compatible = "qcom,bolero-codec"; - clock-names = "lpass_audio_hw_vote"; - clocks = <&lpass_audio_hw_vote 0>; - bolero-clk-rsc-mngr { - compatible = "qcom,bolero-clk-rsc-mngr"; - }; - - va_macro: va-macro@0a730000 { - swr0: va_swr_master { - }; - }; - tx_macro: tx-macro@0a620000 { - }; - - rx_macro: rx-macro@0a600000 { - swr1: rx_swr_master { - }; - }; - }; - - monaco_snd: sound { - qcom,mi2s-audio-intf = <0>; - qcom,cc-va-intf-enable = <0>; - qcom,auxpcm-audio-intf = <0>; - qcom,tdm-audio-intf = <0>; - qcom,wcn-btfm = <0>; - qcom,afe-rxtx-lb = <0>; - - asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, - <&loopback>, <&compress>, <&hostless>, - <&afe>, <&lsm>, <&routing>, <&compr>, - <&pcm_noirq>; - asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", - "msm-pcm-dsp.2", "msm-voip-dsp", - "msm-pcm-voice", "msm-pcm-loopback", - "msm-compress-dsp", "msm-pcm-hostless", - "msm-pcm-afe", "msm-lsm-client", - "msm-pcm-routing", "msm-compr-dsp", - "msm-pcm-dsp-noirq"; - asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_pri_auxpcm>, - <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, - <&dai_quat_auxpcm>, - <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, - <&afe_proxy_tx>, <&incall_record_rx>, - <&incall_record_tx>, <&incall_music_rx>, - <&incall_music_2_rx>, - <&proxy_rx>, <&proxy_tx>, - <&usb_audio_rx>, <&usb_audio_tx>, - <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, - <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>, - <&va_cdc_dma_2_tx>, - <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>, - <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>, - <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>, - <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>, - <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>, - <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>, - <&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>, - <&afe_loopback_tx>; - asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", - "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-auxpcm.1", - "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", - "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.224", - "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", - "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", - "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", - "msm-dai-q6-dev.32770", - "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195", - "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", - "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", - "msm-dai-q6-dev.16401", - "msm-dai-cdc-dma-dev.45089", - "msm-dai-cdc-dma-dev.45091", - "msm-dai-cdc-dma-dev.45093", - "msm-dai-cdc-dma-dev.45104", - "msm-dai-cdc-dma-dev.45105", - "msm-dai-cdc-dma-dev.45106", - "msm-dai-cdc-dma-dev.45107", - "msm-dai-cdc-dma-dev.45108", - "msm-dai-cdc-dma-dev.45109", - "msm-dai-cdc-dma-dev.45110", - "msm-dai-cdc-dma-dev.45111", - "msm-dai-cdc-dma-dev.45112", - "msm-dai-cdc-dma-dev.45113", - "msm-dai-cdc-dma-dev.45114", - "msm-dai-cdc-dma-dev.45115", - "msm-dai-cdc-dma-dev.45116", - "msm-dai-cdc-dma-dev.45118", - "msm-dai-q6-dev.24577"; - }; -}; - -&bolero { - qcom,num-macros = <2>; - qcom,bolero-version = <6>; - bolero-clk-rsc-mngr { - compatible = "qcom,bolero-clk-rsc-mngr"; - qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>, - <0x3004 0x3 0x1>, <0x3080 0x2 0x2>; - qcom,rx_mclk_mode_muxsel = <0x0a5640d8>; - qcom,va_mclk_mode_muxsel = <0x0a7a0000>; - clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk"; - clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>, - <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>; - }; - - tx_macro: tx-macro@0a620000 { - compatible = "qcom,tx-macro"; - reg = <0x0a620000 0x0>; - clock-names = "tx_core_clk", "tx_npl_clk"; - clocks = <&clock_audio_tx_1 0>, - <&clock_audio_tx_2 0>; - qcom,is-used-swr-gpio = <0>; - }; - - rx_macro: rx-macro@0a600000 { - compatible = "qcom,rx-macro"; - reg = <0x0a600000 0x0>; - clock-names = "rx_core_clk", "rx_npl_clk"; - clocks = <&clock_audio_rx_1 0>, - <&clock_audio_rx_2 0>; - qcom,rx-swr-gpios = <&rx_swr_gpios>; - qcom,rx_mclk_mode_muxsel = <0x0a5640d8>; - qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>; - qcom,default-clk-id = <TX_CORE_CLK>; - swr1: rx_swr_master { - compatible = "qcom,swr-mstr"; - #address-cells = <2>; - #size-cells = <0>; - clock-names = "lpass_audio_hw_vote"; - clocks = <&lpass_audio_hw_vote 0>; - qcom,swr_master_id = <2>; - qcom,swrm-hctl-reg = <0x0a6a9098>; - qcom,mipi-sdw-block-packing-mode = <1>; - swrm-io-base = <0x0a610000 0x0>; - interrupts = <0 297 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "swr_master_irq"; - qcom,swr-num-ports = <7>; - qcom,disable-div2-clk-switch = <1>; - qcom,swr-port-mapping = <1 HPH_L 0x1>, +&rx_macro { + swr1: rx_swr_master { + qcom,swr-port-mapping = <1 HPH_L 0x1>, <1 HPH_R 0x2>, <2 CLSH 0x1>, <3 COMP_L 0x1>, <3 COMP_R 0x2>, <4 LO 0x1>, <5 DSD_L 0x1>, <5 DSD_R 0x2>, - <7 SWRM_RX_PCM_IN 0xF>; - qcom,swr-num-dev = <1>; - qcom,swr-clock-stop-mode0 = <1>; - besbev_rx_slave: besbev-rx-slave { - compatible = "qcom,besbev-slave"; - reg = <0x03 0x02170223>; - }; - }; + <7 SWRM_RX_PCM_IN 0x3>; }; +}; - besbev_codec: besbev-codec { - compatible = "qcom,besbev-codec"; - qcom,split-codec = <1>; - qcom,pmic-spmi-node = <&pm5100_cdc>; - qcom,wcd-reset-reg = <0x0000FCDB>; - qcom,foundry-id-reg = <0x000001F2>; +&besbev_codec { qcom,swr_ch_map = <0 SPKR_L 0x1 0 LO>, <2 ADC1 0x1 0 SWRM_RX_PCM_IN>, <2 ADC2 0x2 0 SWRM_RX_PCM_IN>; - qcom,besbev-slave = <&besbev_rx_slave>; - qcom,speaker-present = <1>; - qcom,comp-support = <0>; - - cdc-mic-bias-supply = <&L28A>; - qcom,cdc-mic-bias-voltage = <2904000 2904000>; - qcom,cdc-mic-bias-current = <1180>; - - cdc-vdd-spkr-supply = <&SPKR_BOOST>; - qcom,cdc-vdd-spkr-voltage = <5500000 5500000>; - qcom,cdc-vdd-spkr-current = <700000>; - - qcom,cdc-micbias1-mv = <1800>; - qcom,cdc-micbias2-mv = <1800>; - - qcom,cdc-static-supplies = "cdc-mic-bias"; - qcom,cdc-on-demand-supplies = "cdc-vdd-spkr"; - }; }; &monaco_snd { @@ -237,45 +58,3 @@ "besbev_codec"; qcom,msm_audio_ssr_devs = <&audio_gpr>, <&bolero>, <&lpi_tlmm>; }; - -&soc { - audio_pkt_core_platform: qcom,audio-pkt-core-platform { - compatible = "qcom,audio-pkt-core-platform"; - }; - - clock_audio_rx_1: rx_core_clk { - compatible = "qcom,audio-ref-clk"; - qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>; - qcom,codec-lpass-ext-clk-freq = <22579200>; - qcom,codec-lpass-clk-id = <0x30E>; - #clock-cells = <1>; - }; - - clock_audio_rx_2: rx_npl_clk { - compatible = "qcom,audio-ref-clk"; - qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_5>; - qcom,codec-lpass-ext-clk-freq = <22579200>; - qcom,codec-lpass-clk-id = <0x30F>; - #clock-cells = <1>; - }; - - clock_audio_tx_1: tx_core_clk { - compatible = "qcom,audio-ref-clk"; - qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>; - qcom,codec-lpass-ext-clk-freq = <19200000>; - qcom,codec-lpass-clk-id = <0x30C>; - #clock-cells = <1>; - }; - - clock_audio_tx_2: tx_npl_clk { - compatible = "qcom,audio-ref-clk"; - qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_7>; - qcom,codec-lpass-ext-clk-freq = <19200000>; - qcom,codec-lpass-clk-id = <0x30D>; - #clock-cells = <1>; - }; -}; - -&va_cdc_dma_0_tx { - qcom,msm-dai-is-island-supported = <1>; -}; diff --git a/qcom/monaco-atp-v1-overlay.dts b/qcom/monaco-atp-v1-overlay.dts new file mode 100755 index 00000000..acea30f5 --- /dev/null +++ b/qcom/monaco-atp-v1-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-atp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco ATP V1.0"; + qcom,board-id = <0x010021 0x0>; +}; diff --git a/qcom/monaco-atp-v1.dts b/qcom/monaco-atp-v1.dts new file mode 100755 index 00000000..1cd23c6d --- /dev/null +++ b/qcom/monaco-atp-v1.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "monaco.dtsi" +#include "monaco-atp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco ATP V1.0"; + compatible = "qcom,monaco", "qcom,atp"; + qcom,board-id = <0x010021 0x0>; +}; diff --git a/qcom/monaco-atp-v1.dtsi b/qcom/monaco-atp-v1.dtsi new file mode 100755 index 00000000..6fea5bc4 --- /dev/null +++ b/qcom/monaco-atp-v1.dtsi @@ -0,0 +1 @@ +#include "monaco-idp-v1.dtsi" diff --git a/qcom/monaco-coresight.dtsi b/qcom/monaco-coresight.dtsi index ca2d02f8..f512df06 100755 --- a/qcom/monaco-coresight.dtsi +++ b/qcom/monaco-coresight.dtsi @@ -36,6 +36,7 @@ qcom,perflsheot-set-support; qcom,blk-size = <1>; + qcom,flushperiod = <8>; }; swao_csr: csr@8a03000 { @@ -255,6 +256,8 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; + + qcom,cmb-msr-skip; out-ports { port { tpdm_dcc_out_tpda12: endpoint { @@ -275,6 +278,8 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; + + qcom,cmb-msr-skip; out-ports { port { tpdm_prng_out_tpda14: endpoint { @@ -335,6 +340,8 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; + + qcom,cmb-msr-skip; out-ports { port { tpdm_pimem_out_tpda21: endpoint { @@ -355,6 +362,8 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; + + qcom,cmb-msr-skip; out-ports { port { tpdm_mapss_out_tpda_mapss: endpoint { @@ -422,6 +431,7 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; + qcom,cmb-msr-skip; out-ports { port { tpdm_spdm_out_tpda18: endpoint { @@ -579,6 +589,8 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; + + qcom,cmb-msr-skip; out-ports { port { tpdm_actpm_out_tpda_actpm: endpoint { @@ -600,6 +612,7 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; + qcom,cmb-msr-cnt = <12>; out-ports { port { tpdm_llm_silver_out_tpda_llm_silver: endpoint { diff --git a/qcom/monaco-haptics-fifo-data.dtsi b/qcom/monaco-haptics-fifo-data.dtsi new file mode 100755 index 00000000..ad4fbf0d --- /dev/null +++ b/qcom/monaco-haptics-fifo-data.dtsi @@ -0,0 +1,299 @@ +#include <dt-bindings/input/qcom,hv-haptics.h> + +&pm5100_haptics { + effect_6 { + qcom,effect-id = <17>; + qcom,wf-vmax-mv = <4800>; + qcom,wf-fifo-data = [ + 00 00 00 00 00 00 00 00 00 00 + 00 01 01 01 01 01 01 01 01 01 + 02 02 02 02 02 03 03 03 04 04 + 04 05 05 05 06 06 07 08 08 09 + 0a 0b 0c 0c 0d 0e 0f 0f 0f 0f + 0f 0f 0e 0e 0d 0c 0b 0a 09 08 + 06 05 03 01 00 ff fd fa f8 f6 + f3 f1 ee ec e9 e6 e3 e0 dc d9 + d5 d1 cd c8 c4 bf bb b9 b7 b6 + b7 b8 ba bd c1 c5 cb d1 d7 de + e5 ed f5 fd 04 0d 15 1e 26 2e + 36 3d 44 4b 51 56 5b 5f 62 64 + 65 65 64 63 5f 5b 56 50 4a 45 + 3f 3a 34 2f 29 24 1f 1a 14 0f + 0a 05 00 fc f8 f3 ef ea e6 e2 + df dc d9 d6 d4 d3 d2 d1 d1 d1 + d2 d4 d7 da de e2 e8 ee f6 fd + 02 08 0d 12 16 1a 1d 20 23 26 + 28 2a 2b 2d 2e 2f 30 30 30 31 + 31 31 31 30 30 2f 2f 2e 2d 2c + 2c 2b 2a 29 28 26 25 24 23 22 + 21 20 1e 1d 1c 1b 1a 19 17 16 + 15 14 13 12 11 10 0f 0e 0d 0c + 0b 0a 0a 09 08 07 07 06 05 04 + 04 03 03 02 02 01 01 00 00 00 + 00 00 ff ff ff ff fe fe fe fe + fd fd fd fd fd fd fd fd fd fc + fc fc fc fc fc fc fc fc fc fc + fc fd fd fd fd fd fd fd fd fd + fd fd fd fd fd fe fe fe fe fe + fe fe fe fe fe fe ff ff ff ff + ff ff ff ff ff ff ff ff ff ff + 00 00 00 00 00 00 00 00 00 00 + 00 01 01 01 01 01 01 01 01 01 + 02 02 02 02 02 03 03 03 04 04 + 04 05 05 05 06 06 07 08 08 09 + 0a 0b 0c 0c 0d 0e 0f 0f 0f 0f + 0f 0f 0e 0e 0d 0c 0b 0a 09 08 + 06 05 03 01 00 ff fd fa f8 f6 + f3 f1 ee ec e9 e6 e3 e0 dc d9 + d5 d1 cd c8 c4 bf bb b9 b7 b6 + b7 b8 ba bd c1 c5 cb d1 d7 de + e5 ed f5 fd 04 0d 15 1e 26 2e + 36 3d 44 4b 51 56 5b 5f 62 64 + 65 65 64 63 5f 5b 56 50 4a 45 + 3f 3a 34 2f 29 24 1f 1a 14 0f + 0a 05 00 fc f8 f3 ef ea e6 e2 + df dc d9 d6 d4 d3 d2 d1 d1 d1 + d2 d4 d7 da de e2 e8 ee f6 fd + 02 08 0d 12 16 1a 1d 20 23 26 + 28 2a 2b 2d 2e 2f 30 30 30 31 + 31 31 31 30 30 2f 2f 2e 2d 2c + 2c 2b 2a 29 28 26 25 24 23 22 + 21 20 1e 1d 1c 1b 1a 19 17 16 + 15 14 13 12 11 10 0f 0e 0d 0c + 0b 0a 0a 09 08 07 07 06 05 04 + 04 03 03 02 02 01 01 00 00 00 + 00 00 ff ff ff ff fe fe fe fe + fd fd fd fd fd fd fd fd fd fc + fc fc fc fc fc fc fc fc fc fc + fc fd fd fd fd fd fd fd fd fd + fd fd fd fd fd fe fe fe fe fe + fe fe fe fe fe fe ff ff ff ff + ff ff ff ff ff ff ff ff ff ff + ]; + qcom,wf-fifo-period = <S_PERIOD_T_LRA_X_8>; + qcom,wf-brake-disable; + qcom,wf-auto-res-disable; + }; + + effect_7 { + qcom,effect-id = <18>; + qcom,wf-vmax-mv = <4800>; + qcom,wf-fifo-data = [ + 00 00 00 00 00 00 00 00 00 00 + 00 01 01 01 01 01 01 01 01 01 + 02 02 02 02 02 03 03 03 04 04 + 04 05 05 05 06 06 07 08 08 09 + 0a 0b 0c 0c 0d 0e 0f 0f 0f 0f + 0f 0f 0e 0e 0d 0c 0b 0a 09 08 + 06 05 03 01 00 ff fd fa f8 f6 + f3 f1 ee ec e9 e6 e3 e0 dc d9 + d5 d1 cd c8 c4 bf bb b9 b7 b6 + b7 b8 ba bd c1 c5 cb d1 d7 de + e5 ed f5 fd 04 0d 15 1e 26 2e + 36 3d 44 4b 51 56 5b 5f 62 64 + 65 65 64 63 5f 5b 56 50 4a 45 + 3f 3a 34 2f 29 24 1f 1a 14 0f + 0a 05 00 fc f8 f3 ef ea e6 e2 + df dc d9 d6 d4 d3 d2 d1 d1 d1 + d2 d4 d7 da de e2 e8 ee f6 fd + 02 08 0d 12 16 1a 1d 20 23 26 + 28 2a 2b 2d 2e 2f 30 30 30 31 + 31 31 31 30 30 2f 2f 2e 2d 2c + 2c 2b 2a 29 28 26 25 24 23 22 + 21 20 1e 1d 1c 1b 1a 19 17 16 + 15 14 13 12 11 10 0f 0e 0d 0c + 0b 0a 0a 09 08 07 07 06 05 04 + 04 03 03 02 02 01 01 00 00 00 + 00 00 ff ff ff ff fe fe fe fe + fd fd fd fd fd fd fd fd fd fc + fc fc fc fc fc fc fc fc fc fc + fc fd fd fd fd fd fd fd fd fd + fd fd fd fd fd fe fe fe fe fe + fe fe fe fe fe fe ff ff ff ff + ff ff ff ff ff ff ff ff ff ff + 00 00 00 00 00 00 00 00 00 00 + 00 01 01 01 01 01 01 01 01 01 + 02 02 02 02 02 03 03 03 04 04 + 04 05 05 05 06 06 07 08 08 09 + 0a 0b 0c 0c 0d 0e 0f 0f 0f 0f + 0f 0f 0e 0e 0d 0c 0b 0a 09 08 + 06 05 03 01 00 ff fd fa f8 f6 + f3 f1 ee ec e9 e6 e3 e0 dc d9 + d5 d1 cd c8 c4 bf bb b9 b7 b6 + b7 b8 ba bd c1 c5 cb d1 d7 de + e5 ed f5 fd 04 0d 15 1e 26 2e + 36 3d 44 4b 51 56 5b 5f 62 64 + 65 65 64 63 5f 5b 56 50 4a 45 + 3f 3a 34 2f 29 24 1f 1a 14 0f + 0a 05 00 fc f8 f3 ef ea e6 e2 + df dc d9 d6 d4 d3 d2 d1 d1 d1 + d2 d4 d7 da de e2 e8 ee f6 fd + 02 08 0d 12 16 1a 1d 20 23 26 + 28 2a 2b 2d 2e 2f 30 30 30 31 + 31 31 31 30 30 2f 2f 2e 2d 2c + 2c 2b 2a 29 28 26 25 24 23 22 + 21 20 1e 1d 1c 1b 1a 19 17 16 + 15 14 13 12 11 10 0f 0e 0d 0c + 0b 0a 0a 09 08 07 07 06 05 04 + 04 03 03 02 02 01 01 00 00 00 + 00 00 ff ff ff ff fe fe fe fe + fd fd fd fd fd fd fd fd fd fc + fc fc fc fc fc fc fc fc fc fc + fc fd fd fd fd fd fd fd fd fd + fd fd fd fd fd fe fe fe fe fe + fe fe fe fe fe fe ff ff ff ff + ff ff ff ff ff ff ff ff ff ff + ]; + qcom,wf-fifo-period = <S_PERIOD_T_LRA_X_8>; + qcom,wf-brake-disable; + qcom,wf-auto-res-disable; + }; + + effect_8 { + qcom,effect-id = <19>; + qcom,wf-vmax-mv = <4800>; + qcom,wf-fifo-data = [ + 00 00 00 00 00 00 00 00 00 00 + 00 01 01 01 01 01 01 01 01 01 + 02 02 02 02 02 03 03 03 04 04 + 04 05 05 05 06 06 07 08 08 09 + 0a 0b 0c 0c 0d 0e 0f 0f 0f 0f + 0f 0f 0e 0e 0d 0c 0b 0a 09 08 + 06 05 03 01 00 ff fd fa f8 f6 + f3 f1 ee ec e9 e6 e3 e0 dc d9 + d5 d1 cd c8 c4 bf bb b9 b7 b6 + b7 b8 ba bd c1 c5 cb d1 d7 de + e5 ed f5 fd 04 0d 15 1e 26 2e + 36 3d 44 4b 51 56 5b 5f 62 64 + 65 65 64 63 5f 5b 56 50 4a 45 + 3f 3a 34 2f 29 24 1f 1a 14 0f + 0a 05 00 fc f8 f3 ef ea e6 e2 + df dc d9 d6 d4 d3 d2 d1 d1 d1 + d2 d4 d7 da de e2 e8 ee f6 fd + 02 08 0d 12 16 1a 1d 20 23 26 + 28 2a 2b 2d 2e 2f 30 30 30 31 + 31 31 31 30 30 2f 2f 2e 2d 2c + 2c 2b 2a 29 28 26 25 24 23 22 + 21 20 1e 1d 1c 1b 1a 19 17 16 + 15 14 13 12 11 10 0f 0e 0d 0c + 0b 0a 0a 09 08 07 07 06 05 04 + 04 03 03 02 02 01 01 00 00 00 + 00 00 ff ff ff ff fe fe fe fe + fd fd fd fd fd fd fd fd fd fc + fc fc fc fc fc fc fc fc fc fc + fc fd fd fd fd fd fd fd fd fd + fd fd fd fd fd fe fe fe fe fe + fe fe fe fe fe fe ff ff ff ff + ff ff ff ff ff ff ff ff ff ff + 00 00 00 00 00 00 00 00 00 00 + 00 01 01 01 01 01 01 01 01 01 + 02 02 02 02 02 03 03 03 04 04 + 04 05 05 05 06 06 07 08 08 09 + 0a 0b 0c 0c 0d 0e 0f 0f 0f 0f + 0f 0f 0e 0e 0d 0c 0b 0a 09 08 + 06 05 03 01 00 ff fd fa f8 f6 + f3 f1 ee ec e9 e6 e3 e0 dc d9 + d5 d1 cd c8 c4 bf bb b9 b7 b6 + b7 b8 ba bd c1 c5 cb d1 d7 de + e5 ed f5 fd 04 0d 15 1e 26 2e + 36 3d 44 4b 51 56 5b 5f 62 64 + 65 65 64 63 5f 5b 56 50 4a 45 + 3f 3a 34 2f 29 24 1f 1a 14 0f + 0a 05 00 fc f8 f3 ef ea e6 e2 + df dc d9 d6 d4 d3 d2 d1 d1 d1 + d2 d4 d7 da de e2 e8 ee f6 fd + 02 08 0d 12 16 1a 1d 20 23 26 + 28 2a 2b 2d 2e 2f 30 30 30 31 + 31 31 31 30 30 2f 2f 2e 2d 2c + 2c 2b 2a 29 28 26 25 24 23 22 + 21 20 1e 1d 1c 1b 1a 19 17 16 + 15 14 13 12 11 10 0f 0e 0d 0c + 0b 0a 0a 09 08 07 07 06 05 04 + 04 03 03 02 02 01 01 00 00 00 + 00 00 ff ff ff ff fe fe fe fe + fd fd fd fd fd fd fd fd fd fc + fc fc fc fc fc fc fc fc fc fc + fc fd fd fd fd fd fd fd fd fd + fd fd fd fd fd fe fe fe fe fe + fe fe fe fe fe fe ff ff ff ff + ff ff ff ff ff ff ff ff ff ff + ]; + qcom,wf-fifo-period = <S_PERIOD_T_LRA_X_8>; + qcom,wf-brake-disable; + qcom,wf-auto-res-disable; + }; + + effect_9 { + qcom,effect-id = <20>; + qcom,wf-vmax-mv = <4800>; + qcom,wf-fifo-data = [ + 00 00 00 00 00 00 00 00 00 00 + 00 01 01 01 01 01 01 01 01 01 + 02 02 02 02 02 03 03 03 04 04 + 04 05 05 05 06 06 07 08 08 09 + 0a 0b 0c 0c 0d 0e 0f 0f 0f 0f + 0f 0f 0e 0e 0d 0c 0b 0a 09 08 + 06 05 03 01 00 ff fd fa f8 f6 + f3 f1 ee ec e9 e6 e3 e0 dc d9 + d5 d1 cd c8 c4 bf bb b9 b7 b6 + b7 b8 ba bd c1 c5 cb d1 d7 de + e5 ed f5 fd 04 0d 15 1e 26 2e + 36 3d 44 4b 51 56 5b 5f 62 64 + 65 65 64 63 5f 5b 56 50 4a 45 + 3f 3a 34 2f 29 24 1f 1a 14 0f + 0a 05 00 fc f8 f3 ef ea e6 e2 + df dc d9 d6 d4 d3 d2 d1 d1 d1 + d2 d4 d7 da de e2 e8 ee f6 fd + 02 08 0d 12 16 1a 1d 20 23 26 + 28 2a 2b 2d 2e 2f 30 30 30 31 + 31 31 31 30 30 2f 2f 2e 2d 2c + 2c 2b 2a 29 28 26 25 24 23 22 + 21 20 1e 1d 1c 1b 1a 19 17 16 + 15 14 13 12 11 10 0f 0e 0d 0c + 0b 0a 0a 09 08 07 07 06 05 04 + 04 03 03 02 02 01 01 00 00 00 + 00 00 ff ff ff ff fe fe fe fe + fd fd fd fd fd fd fd fd fd fc + fc fc fc fc fc fc fc fc fc fc + fc fd fd fd fd fd fd fd fd fd + fd fd fd fd fd fe fe fe fe fe + fe fe fe fe fe fe ff ff ff ff + ff ff ff ff ff ff ff ff ff ff + 00 00 00 00 00 00 00 00 00 00 + 00 01 01 01 01 01 01 01 01 01 + 02 02 02 02 02 03 03 03 04 04 + 04 05 05 05 06 06 07 08 08 09 + 0a 0b 0c 0c 0d 0e 0f 0f 0f 0f + 0f 0f 0e 0e 0d 0c 0b 0a 09 08 + 06 05 03 01 00 ff fd fa f8 f6 + f3 f1 ee ec e9 e6 e3 e0 dc d9 + d5 d1 cd c8 c4 bf bb b9 b7 b6 + b7 b8 ba bd c1 c5 cb d1 d7 de + e5 ed f5 fd 04 0d 15 1e 26 2e + 36 3d 44 4b 51 56 5b 5f 62 64 + 65 65 64 63 5f 5b 56 50 4a 45 + 3f 3a 34 2f 29 24 1f 1a 14 0f + 0a 05 00 fc f8 f3 ef ea e6 e2 + df dc d9 d6 d4 d3 d2 d1 d1 d1 + d2 d4 d7 da de e2 e8 ee f6 fd + 02 08 0d 12 16 1a 1d 20 23 26 + 28 2a 2b 2d 2e 2f 30 30 30 31 + 31 31 31 30 30 2f 2f 2e 2d 2c + 2c 2b 2a 29 28 26 25 24 23 22 + 21 20 1e 1d 1c 1b 1a 19 17 16 + 15 14 13 12 11 10 0f 0e 0d 0c + 0b 0a 0a 09 08 07 07 06 05 04 + 04 03 03 02 02 01 01 00 00 00 + 00 00 ff ff ff ff fe fe fe fe + fd fd fd fd fd fd fd fd fd fc + fc fc fc fc fc fc fc fc fc fc + fc fd fd fd fd fd fd fd fd fd + fd fd fd fd fd fe fe fe fe fe + fe fe fe fe fe fe ff ff ff ff + ff ff ff ff ff ff ff ff ff ff + ]; + qcom,wf-fifo-period = <S_PERIOD_T_LRA_X_8>; + qcom,wf-brake-disable; + qcom,wf-auto-res-disable; + }; +}; diff --git a/qcom/monaco-idp-v1-common.dtsi b/qcom/monaco-idp-v1-common.dtsi index 53c2de53..f643efea 100755 --- a/qcom/monaco-idp-v1-common.dtsi +++ b/qcom/monaco-idp-v1-common.dtsi @@ -1,4 +1,5 @@ #include "monaco-thermal-overlay.dtsi" +#include "monaco-haptics-fifo-data.dtsi" &dsi_rm69090_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; diff --git a/qcom/monaco-idp-v1.1.dtsi b/qcom/monaco-idp-v1.1.dtsi index 7cf2c867..9c1f29e7 100755 --- a/qcom/monaco-idp-v1.1.dtsi +++ b/qcom/monaco-idp-v1.1.dtsi @@ -4,43 +4,6 @@ #include <dt-bindings/regulator/qcom,rpm-smd-regulator.h> #include "camera/monaco-camera.dtsi" #include "camera/monaco-camera-sensor-idp.dtsi" +#include "monaco-idp-v1.dtsi" -#include "monaco-idp-v1-common.dtsi" -#include "slate.dtsi" -#include "monaco-slate-audio-overlay.dtsi" -&sdhc_1 { - status = "ok"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; - - vdd-supply = <&L25A>; - qcom,vdd-voltage-level = <3080000 3080000>; - qcom,vdd-current-level = <0 250000>; - - vdd-io-supply = <&L15A>; - qcom,vdd-io-always-on; - qcom,vdd-io-lpm-sup; - qcom,vdd-io-voltage-level = <1800000 1800000>; - qcom,vdd-io-current-level = <0 250000>; -}; - -&pm5100_charger { - qcom,batteryless-platform; -}; - -&soc { - bluetooth: bt_wcn3990 { - compatible = "qcom,qcc5100"; - qcom,bt-vdd-pa-supply = <&L23A>; /* CH0 */ - - qcom,bt-vdd-pa-config = <1800000 1890000 10000 0>; - status = "ok"; - }; -}; - -&qupv3_se5_4uart { - status = "ok"; -}; diff --git a/qcom/monaco-idp-v1.dtsi b/qcom/monaco-idp-v1.dtsi index 0e62e779..6aa7602c 100755 --- a/qcom/monaco-idp-v1.dtsi +++ b/qcom/monaco-idp-v1.dtsi @@ -36,17 +36,8 @@ status = "ok"; }; -&soc { - monaco_batterydata: qcom,battery-data { - qcom,batt-id-range-pct = <15>; - #include "qbg-battery-profile-alium-860-89032-0000-3600mAh.dtsi" - #include "qbg-battery-profile-qrd-zwd-520mAh.dtsi" - }; -}; - &pm5100_charger { qcom,remote-fg; - qcom,battery-data = <&monaco_batterydata>; #io-channel-cells = <1>; io-channels = <&pm5100_adc PM5100_ADC5_GEN3_USB_SNS_V_16>, <&pm5100_adc PM5100_ADC5_GEN3_USB_IN_I>, @@ -55,7 +46,7 @@ <&pm5100_adc PM5100_ADC5_GEN3_VPH_PWR>, <&pm5100_adc PM5100_ADC5_GEN3_BAT_ID_100K_PU>, <&pm5100_adc PM5100_ADC5_GEN3_BATT_THM_100K_PU>, - <&pm5100_adc PM5100_ADC5_GEN3_AMUX1_THM_100K_PU>; + <&pm5100_adc PM5100_ADC5_GEN3_VBAT_SNS_QBG>; io-channel-names = "usb_in_voltage", "usb_in_current", @@ -66,3 +57,12 @@ "batt-temp", "batt-volt"; }; + +&spmi_bus { + qcom,pm5100@0 { + pmic_lpm: qti,pmic-lpm@7200 { + compatible = "qti,pmic-lpm"; + reg = <0x7200>; + }; + }; +}; diff --git a/qcom/monaco-pinctrl.dtsi b/qcom/monaco-pinctrl.dtsi index f37e63f6..5709e882 100755 --- a/qcom/monaco-pinctrl.dtsi +++ b/qcom/monaco-pinctrl.dtsi @@ -65,6 +65,68 @@ }; }; + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* NFC Read Interrupt */ + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* NFC Read Interrupt */ + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active: nfc_enable_active { + /* active state */ + mux { + /* Enable, Firmware gpios */ + pins = "gpio6", "gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio8"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + /* sleep state */ + mux { + /* Enable, Firmware gpios */ + pins = "gpio6", "gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio8"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + qupv3_se0_spi_pins: qupv3_se0_spi_pins { qupv3_se0_spi_active: qupv3_se0_spi_active { mux { diff --git a/qcom/monaco-pmic.dtsi b/qcom/monaco-pmic.dtsi index b4b36e59..fcedc97a 100755 --- a/qcom/monaco-pmic.dtsi +++ b/qcom/monaco-pmic.dtsi @@ -164,11 +164,24 @@ nvmem-cells = <&restart_reason>; nvmem-cell-names = "restart_reason"; }; + + monaco_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qbg-battery-profile-alium-860-89032-0000-3600mAh.dtsi" + #include "qbg-battery-profile-qrd-zwd-520mAh.dtsi" + }; }; &pm5100_charger { status = "okay"; + qcom,battery-data = <&monaco_batterydata>; dpdm-supply = <&usb2_phy0>; qcom,auto-recharge-soc = <98>; qcom,suspend-input-on-debug-batt; + qcom,chg-term-src = <1>; + qcom,chg-term-current-ma = <(-20)>; + qcom,fcc-stepping-enable; + qcom,fcc-step-delay-ms = <100>; + qcom,fcc-step-size-ua = <100000>; + qcom,fcc-step-start-ua = <500000>; }; diff --git a/qcom/monaco-slate-audio-overlay.dtsi b/qcom/monaco-slate-audio-overlay.dtsi index 9e6bd238..36bbdf3d 100755 --- a/qcom/monaco-slate-audio-overlay.dtsi +++ b/qcom/monaco-slate-audio-overlay.dtsi @@ -13,4 +13,5 @@ asoc-codec-names = "cc_codec"; qcom,quat-mi2s-gpios = <&cc_quat_mi2s_gpios>; qcom,pri-mi2s-gpios = <&cc_pri_mi2s_gpios>; + qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>; }; diff --git a/qcom/monaco-standalone-atp-v1-overlay.dts b/qcom/monaco-standalone-atp-v1-overlay.dts new file mode 100755 index 00000000..fdd0c502 --- /dev/null +++ b/qcom/monaco-standalone-atp-v1-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monaco-standalone-atp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco standalone ATP V1.0"; + qcom,board-id = <0x010021 0x1>; +}; diff --git a/qcom/monaco-standalone-atp-v1.dts b/qcom/monaco-standalone-atp-v1.dts new file mode 100755 index 00000000..86a39057 --- /dev/null +++ b/qcom/monaco-standalone-atp-v1.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "monaco-1gb.dtsi" +#include "monaco-standalone-atp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco standalone ATP V1.0"; + compatible = "qcom,monaco", "qcom,atp"; + qcom,board-id = <0x010021 0x1>; +}; diff --git a/qcom/monaco-standalone-atp-v1.dtsi b/qcom/monaco-standalone-atp-v1.dtsi new file mode 100755 index 00000000..d8a5c8c6 --- /dev/null +++ b/qcom/monaco-standalone-atp-v1.dtsi @@ -0,0 +1 @@ +#include "monaco-standalone-idp-v1.dtsi" diff --git a/qcom/monaco-standalone-idp-v1.dtsi b/qcom/monaco-standalone-idp-v1.dtsi index 8f0719bb..6cd284d9 100755 --- a/qcom/monaco-standalone-idp-v1.dtsi +++ b/qcom/monaco-standalone-idp-v1.dtsi @@ -1,4 +1,5 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/clock/qcom,gcc-monaco.h> #include <dt-bindings/interconnect/qcom,monaco.h> #include <dt-bindings/regulator/qcom,rpm-smd-regulator.h> @@ -56,14 +57,6 @@ status = "ok"; }; -&soc { - monaco_batterydata: qcom,battery-data { - qcom,batt-id-range-pct = <15>; - #include "qbg-battery-profile-alium-860-89032-0000-3600mAh.dtsi" - #include "qbg-battery-profile-qrd-zwd-520mAh.dtsi" - }; -}; - &pm5100_qbg { status = "ok"; qcom,battery-data = <&monaco_batterydata>; @@ -120,3 +113,35 @@ "charge_full_design", "time_to_full_now"; }; + +&pm5100_gpios { + nfc_clk { + nfc_clk_default: nfc_clk_default { + pins = "gpio4"; + function = "normal"; + input-enable; + power-source = <1>; + }; + }; +}; + +&qupv3_se0_i2c { + status = "ok"; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 7 0x00>; + qcom,sn-ven = <&tlmm 6 0x00>; + qcom,sn-firm = <&tlmm 8 0x00>; + qcom,sn-clkreq = <&pm5100_gpios 4 0x00>; + interrupt-parent = <&tlmm>; + qcom,clk-src = "LNBBCLK3"; + interrupts = <7 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active &nfc_clk_default>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK3_PIN>; + clock-names = "ref_clk"; + }; +}; diff --git a/qcom/monaco-standalone-idp-v2.dtsi b/qcom/monaco-standalone-idp-v2.dtsi index d8a5c8c6..0c27de59 100755 --- a/qcom/monaco-standalone-idp-v2.dtsi +++ b/qcom/monaco-standalone-idp-v2.dtsi @@ -1 +1,3 @@ + #include "monaco-standalone-idp-v1.dtsi" +#include "monaco-amic-audio-overlay.dtsi" diff --git a/qcom/monaco-standalone-idp-v3.dtsi b/qcom/monaco-standalone-idp-v3.dtsi index d8a5c8c6..9f97c8fa 100755 --- a/qcom/monaco-standalone-idp-v3.dtsi +++ b/qcom/monaco-standalone-idp-v3.dtsi @@ -1 +1,2 @@ #include "monaco-standalone-idp-v1.dtsi" +#include "monaco-wsa-audio-overlay.dtsi" diff --git a/qcom/monaco-wdp-v1.1.dtsi b/qcom/monaco-wdp-v1.1.dtsi index 3473a563..c41375f6 100755 --- a/qcom/monaco-wdp-v1.1.dtsi +++ b/qcom/monaco-wdp-v1.1.dtsi @@ -1,2 +1,2 @@ -#include "monaco-idp-v1.dtsi" +#include "monaco-idp-v1.1.dtsi" #include "monaco-wdp.dtsi" diff --git a/qcom/monaco-wsa-audio-overlay.dtsi b/qcom/monaco-wsa-audio-overlay.dtsi index 85d6d27a..84d129fc 100755 --- a/qcom/monaco-wsa-audio-overlay.dtsi +++ b/qcom/monaco-wsa-audio-overlay.dtsi @@ -1,178 +1,15 @@ -#include <dt-bindings/clock/qcom,audio-ext-clk.h> -#include <dt-bindings/sound/qcom,bolero-clk-rsc.h> -#include <dt-bindings/sound/audio-codec-port-types.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -&spf_core_platform { - cdc_dmic01_gpios: cdc_dmic01_pinctrl { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>; - pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>; - qcom,lpi-gpios; - }; - - cdc_dmic23_gpios: cdc_dmic23_pinctrl { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>; - pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>; - qcom,lpi-gpios; - }; - - rx_swr_gpios: rx_swr_clk_data_pinctrl { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active>; - pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep>; - qcom,lpi-gpios; - }; - - va_swr_gpios: va_swr_clk_data_pinctrl { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&tx_swr_clk_active &tx_swr_data1_active - &tx_swr_data2_active>; - pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data1_sleep - &tx_swr_data2_sleep>; - qcom,lpi-gpios; - qcom,chip-wakeup-reg = <0x003ca064>; - qcom,chip-wakeup-maskbit = <0>; - qcom,chip-wakeup-default-val = <0x1>; - }; - - bolero: bolero-cdc { - compatible = "qcom,bolero-codec"; - clock-names = "lpass_audio_hw_vote"; - clocks = <&lpass_audio_hw_vote 0>; - bolero-clk-rsc-mngr { - compatible = "qcom,bolero-clk-rsc-mngr"; - }; - - va_macro: va-macro@0a730000 { - swr0: va_swr_master { - }; - }; - - tx_macro: tx-macro@0a620000 { - }; - - rx_macro: rx-macro@0a600000 { - swr1: rx_swr_master { - }; - }; - }; - - monaco_snd: sound { - qcom,mi2s-audio-intf = <0>; - qcom,cc-va-intf-enable = <0>; - qcom,auxpcm-audio-intf = <0>; - qcom,tdm-audio-intf = <0>; - qcom,wcn-btfm = <0>; - qcom,afe-rxtx-lb = <0>; - - asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, - <&loopback>, <&compress>, <&hostless>, - <&afe>, <&lsm>, <&routing>, <&compr>, - <&pcm_noirq>; - asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", - "msm-pcm-dsp.2", "msm-voip-dsp", - "msm-pcm-voice", "msm-pcm-loopback", - "msm-compress-dsp", "msm-pcm-hostless", - "msm-pcm-afe", "msm-lsm-client", - "msm-pcm-routing", "msm-compr-dsp", - "msm-pcm-dsp-noirq"; - asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_pri_auxpcm>, - <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, - <&dai_quat_auxpcm>, - <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, - <&afe_proxy_tx>, <&incall_record_rx>, - <&incall_record_tx>, <&incall_music_rx>, - <&incall_music_2_rx>, - <&proxy_rx>, <&proxy_tx>, - <&usb_audio_rx>, <&usb_audio_tx>, - <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, - <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, - <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, - <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, - <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, - <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>, - <&va_cdc_dma_2_tx>, - <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>, - <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>, - <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>, - <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>, - <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>, - <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>, - <&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>, - <&afe_loopback_tx>; - asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", - "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-auxpcm.1", - "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", - "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.224", - "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", - "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", - "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", - "msm-dai-q6-dev.32770", - "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195", - "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", - "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", - "msm-dai-q6-dev.16401", - "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", - "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", - "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", - "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", - "msm-dai-cdc-dma-dev.45089", - "msm-dai-cdc-dma-dev.45091", - "msm-dai-cdc-dma-dev.45093", - "msm-dai-cdc-dma-dev.45104", - "msm-dai-cdc-dma-dev.45105", - "msm-dai-cdc-dma-dev.45106", - "msm-dai-cdc-dma-dev.45107", - "msm-dai-cdc-dma-dev.45108", - "msm-dai-cdc-dma-dev.45109", - "msm-dai-cdc-dma-dev.45110", - "msm-dai-cdc-dma-dev.45111", - "msm-dai-cdc-dma-dev.45112", - "msm-dai-cdc-dma-dev.45113", - "msm-dai-cdc-dma-dev.45114", - "msm-dai-cdc-dma-dev.45115", - "msm-dai-cdc-dma-dev.45116", - "msm-dai-cdc-dma-dev.45118", - "msm-dai-q6-dev.24577"; - }; +&soc { +wsa_spkr_en: wsa_spkr_en_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; +}; }; -&bolero { - qcom,num-macros = <3>; - qcom,bolero-version = <6>; - bolero-clk-rsc-mngr { - compatible = "qcom,bolero-clk-rsc-mngr"; - qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>, - <0x3004 0x3 0x1>, <0x3080 0x2 0x2>; - qcom,rx_mclk_mode_muxsel = <0x0a5640d8>; - qcom,va_mclk_mode_muxsel = <0x0a7a0000>; - clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk", - "va_core_clk", "va_npl_clk"; - clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>, - <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>, - <&clock_audio_va_1 0>, <&clock_audio_va_2 0>; - }; - - tx_macro: tx-macro@0a620000 { - compatible = "qcom,tx-macro"; - reg = <0x0a620000 0x0>; - clock-names = "tx_core_clk", "tx_npl_clk"; - clocks = <&clock_audio_tx_1 0>, - <&clock_audio_tx_2 0>; - qcom,tx-dmic-sample-rate = <2400000>; - qcom,is-used-swr-gpio = <0>; - }; - rx_macro: rx-macro@0a600000 { +&rx_macro { compatible = "qcom,rx-macro"; reg = <0x0a600000 0x0>; clock-names = "rx_core_clk", "rx_npl_clk"; @@ -182,6 +19,7 @@ qcom,rx_mclk_mode_muxsel = <0x0a5640d8>; qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>; qcom,default-clk-id = <TX_CORE_CLK>; + qcom,rx-wsa-enable = <1>; swr1: rx_swr_master { compatible = "qcom,swr-mstr"; #address-cells = <2>; @@ -220,60 +58,12 @@ }; }; - va_macro: va-macro@0a730000 { - compatible = "qcom,va-macro"; - reg = <0x0a730000 0x0>; - clock-names = "lpass_audio_hw_vote"; - clocks = <&lpass_audio_hw_vote 0>; - qcom,va-dmic-sample-rate = <600000>; - qcom,va-clk-mux-select = <1>; - qcom,va-island-mode-muxsel = <0x0a7a0000>; - qcom,default-clk-id = <TX_CORE_CLK>; - qcom,is-used-swr-gpio = <1>; - qcom,va-swr-gpios = <&va_swr_gpios>; - swr0: va_swr_master { - compatible = "qcom,swr-mstr"; - #address-cells = <2>; - #size-cells = <0>; - clock-names = "lpass_audio_hw_vote"; - clocks = <&lpass_audio_hw_vote 0>; - qcom,swr_master_id = <3>; - qcom,swrm-hctl-reg = <0x0a7ec100>; - qcom,mipi-sdw-block-packing-mode = <1>; - swrm-io-base = <0x0a740000 0x0>; - interrupts = - <0 296 IRQ_TYPE_LEVEL_HIGH>, - <0 79 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "swr_master_irq", "swr_wake_irq"; - qcom,swr-wakeup-required = <1>; - qcom,swr-num-ports = <3>; - qcom,swr-port-mapping = <1 ADC1 0x1>, <1 ADC2 0x2>, - <1 ADC3 0x4>, <1 ADC4 0x8>, - <2 DMIC0 0x1>, <2 DMIC1 0x2>, - <2 DMIC2 0x4>, <2 DMIC3 0x8>, - <3 DMIC4 0x1>, <3 DMIC5 0x2>, - <3 DMIC6 0x4>, <3 DMIC7 0x8>; - qcom,swr-num-dev = <1>; - qcom,swr-clock-stop-mode0 = <1>; - qcom,swr-mstr-irq-wakeup-capable = <1>; - }; - }; -}; - &monaco_snd { qcom,model = "monaco-idp-wsa-snd-card"; qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; qcom,wcn-btfm = <1>; qcom,va-bolero-codec = <1>; qcom,audio-routing = - "TX DMIC0", "Digital Mic0", - "Digital Mic0", "MIC BIAS1", - "TX DMIC1", "Digital Mic1", - "Digital Mic1", "MIC BIAS1", - "TX DMIC2", "Digital Mic2", - "Digital Mic2", "MIC BIAS2", - "TX DMIC3", "Digital Mic3", - "Digital Mic3", "MIC BIAS2", "SpkrLeft IN", "AUX_OUT", "TX SWR_INPUT", "VA_TX_SWR_CLK", "RX_TX DEC0_INP", "TX DEC0 MUX", @@ -286,18 +76,7 @@ "VA SWR_INPUT", "VA_SWR_CLK", "VA_AIF1 CAP", "VA_SWR_CLK", "VA_AIF2 CAP", "VA_SWR_CLK", - "VA_AIF3 CAP", "VA_SWR_CLK", - "VA DMIC0", "Digital Mic0", - "VA DMIC1", "Digital Mic1", - "VA DMIC2", "Digital Mic2", - "VA DMIC3", "Digital Mic3", - "VA DMIC0", "VA MIC BIAS1", - "VA DMIC1", "VA MIC BIAS1", - "VA DMIC2", "VA MIC BIAS2", - "VA DMIC3", "VA MIC BIAS2"; - - qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; - qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + "VA_AIF3 CAP", "VA_SWR_CLK"; nvmem-cells = <&adsp_variant>; nvmem-cell-names = "adsp_variant"; @@ -310,67 +89,3 @@ qcom,msm_audio_ssr_devs = <&audio_gpr>, <&bolero>, <&lpi_tlmm>; }; -&soc { - audio_pkt_core_platform: qcom,audio-pkt-core-platform { - compatible = "qcom,audio-pkt-core-platform"; - }; - - wsa_spkr_en: wsa_spkr_en_pinctrl { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&spkr_1_sd_n_active>; - pinctrl-1 = <&spkr_1_sd_n_sleep>; - }; - - clock_audio_rx_1: rx_core_clk { - compatible = "qcom,audio-ref-clk"; - qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>; - qcom,codec-lpass-ext-clk-freq = <22579200>; - qcom,codec-lpass-clk-id = <0x30E>; - #clock-cells = <1>; - }; - - clock_audio_rx_2: rx_npl_clk { - compatible = "qcom,audio-ref-clk"; - qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_5>; - qcom,codec-lpass-ext-clk-freq = <22579200>; - qcom,codec-lpass-clk-id = <0x30F>; - #clock-cells = <1>; - }; - - clock_audio_tx_1: tx_core_clk { - compatible = "qcom,audio-ref-clk"; - qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>; - qcom,codec-lpass-ext-clk-freq = <19200000>; - qcom,codec-lpass-clk-id = <0x30C>; - #clock-cells = <1>; - }; - - clock_audio_tx_2: tx_npl_clk { - compatible = "qcom,audio-ref-clk"; - qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_7>; - qcom,codec-lpass-ext-clk-freq = <19200000>; - qcom,codec-lpass-clk-id = <0x30D>; - #clock-cells = <1>; - }; - - clock_audio_va_1: va_core_clk { - compatible = "qcom,audio-ref-clk"; - qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>; - qcom,codec-lpass-ext-clk-freq = <19200000>; - qcom,codec-lpass-clk-id = <0x307>; - #clock-cells = <1>; - }; - - clock_audio_va_2: va_npl_clk { - compatible = "qcom,audio-ref-clk"; - qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_8>; - qcom,codec-lpass-ext-clk-freq = <19200000>; - qcom,codec-lpass-clk-id = <0x308>; - #clock-cells = <1>; - }; -}; - -&va_cdc_dma_0_tx { - qcom,msm-dai-is-island-supported = <1>; -}; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 11dc8234..166939dd 100755 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -167,14 +167,14 @@ #size-cells = <2>; ranges; - hyp_region: hyp_region@45700000 { + deepsleep_region: deepsleep_region@45700000 { no-map; - reg = <0x0 0x45700000 0x0 0x600000>; + reg = <0x0 0x45700000 0x0 0x400000>; }; - rpmbackup_mem: rpmbackup_mem@45D00000 { + hyp_region: hyp_region@45B00000 { no-map; - reg = <0x0 0x45D00000 0x0 0x100000>; + reg = <0x0 0x45B00000 0x0 0x300000>; }; xbl_aop_mem: xbl_aop_mem@45e00000 { @@ -192,44 +192,49 @@ reg = <0x0 0x46000000 0x0 0x200000>; }; + wlan_msa_mem: wlan_msa_region@46200000 { + no-map; + reg = <0x0 0x46200000 0x0 0x100000>; + }; + pil_modem_mem: modem_region@4ab00000 { no-map; - reg = <0x0 0x4ab00000 0x0 0x6900000>; + reg = <0x0 0x4ab00000 0x0 0x5E00000>; }; - pil_video_mem: pil_video_region@51400000 { + pil_video_mem: pil_video_region@50900000 { no-map; - reg = <0x0 0x51400000 0x0 0x500000>; + reg = <0x0 0x50900000 0x0 0x500000>; }; - wlan_msa_mem: wlan_msa_region@51900000 { + pil_adsp_mem: adsp_regions@50E00000 { no-map; - reg = <0x0 0x51900000 0x0 0x100000>; + reg = <0x0 0x50E00000 0x0 0x1900000>; }; - pil_adsp_mem: adsp_regions@51a00000 { + pil_ipa_fw_mem: ips_fw_region@52700000 { no-map; - reg = <0x0 0x51a00000 0x0 0x1c00000>; + reg = <0x0 0x52700000 0x0 0x10000>; }; - pil_ipa_fw_mem: ips_fw_region@53600000 { + pil_ipa_gsi_mem: ipa_gsi_region@52710000 { no-map; - reg = <0x0 0x53600000 0x0 0x10000>; + reg = <0x0 0x52710000 0x0 0x5000>; }; - pil_ipa_gsi_mem: ipa_gsi_region@53610000 { + pil_gpu_mem: gpu_region@52715000 { no-map; - reg = <0x0 0x53610000 0x0 0x5000>; + reg = <0x0 0x52715000 0x0 0x2000>; }; - pil_gpu_mem: gpu_region@53615000 { + stats_region: stats_region@60000000 { no-map; - reg = <0x0 0x53615000 0x0 0x2000>; + reg = <0x0 0x60000000 0x0 0x100000>; }; - removed_region: removed_region@60000000 { + removed_region: removed_region@60100000 { no-map; - reg = <0x0 0x60000000 0x0 0x1f00000>; + reg = <0x0 0x60100000 0x0 0x1E00000>; }; dump_mem: mem_dump_region { @@ -1450,14 +1455,12 @@ qcom,msm-adsprpc-mem { qcom,glinkpkt-edge = "slate"; qcom,glinkpkt-ch-name = "display-ctrl"; qcom,glinkpkt-dev-name = "glink_pkt_slate_display_ctrl"; - qcom,glinkpkt-enable-ch-close; }; qcom,glinkpkt-slate-display-data { qcom,glinkpkt-edge = "slate"; qcom,glinkpkt-ch-name = "display-data"; qcom,glinkpkt-dev-name = "glink_pkt_slate_display_data"; - qcom,glinkpkt-enable-ch-close; }; qcom,glinkpkt-slate-ssc-usta { @@ -1613,6 +1616,12 @@ qcom,msm-adsprpc-mem { qcom,glinkpkt-dev-name = "slate_adsp_data"; qcom,glinkpkt-fragmented-read; }; + + qcom,glinkpkt-haptics-offload-ctrl { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "slate-haptics-offload"; + qcom,glinkpkt-dev-name = "glinkpkt_slate_haptics_offload"; + }; }; qcom,smp2p-modem { @@ -1677,22 +1686,41 @@ qcom,msm-adsprpc-mem { #interrupt-cells = <2>; }; - sleepstate_smp2p_out: sleepstate-out { + sleepstate_smp2p_out_sensor: sleepstate-out-sensor { qcom,entry-name = "sleepstate"; #qcom,smem-state-cells = <1>; }; - sleepstate_smp2p_in: qcom,sleepstate-in { + sleepstate_smp2p_in_sensor: qcom,sleepstate-in-sensor { qcom,entry-name = "sleepstate_see"; interrupt-controller; #interrupt-cells = <2>; }; + + sleepstate_smp2p_out_ult: sleepstate-out-ult { + qcom,entry-name = "sleepstate_ult"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in_ult: qcom,sleepstate-in-ult { + qcom,entry-name = "sleepstate_ult_in"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p_sleepstate_sensor { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out_sensor 0>; + interrupt-parent = <&sleepstate_smp2p_in_sensor>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; }; - qcom,smp2p_sleepstate { + qcom,smp2p_sleepstate_ult { compatible = "qcom,smp2p-sleepstate"; - qcom,smem-states = <&sleepstate_smp2p_out 0>; - interrupt-parent = <&sleepstate_smp2p_in>; + qcom,smem-states = <&sleepstate_smp2p_out_ult 0>; + interrupt-parent = <&sleepstate_smp2p_in_ult>; interrupts = <0 0>; interrupt-names = "smp2p-sleepstate-in"; }; @@ -2002,7 +2030,7 @@ qcom,msm-adsprpc-mem { /* SVS2 */ qcom,svs2 = - <80000 2720000 80000 560000 80000 120000>; + <80000 2160000 80000 560000 80000 120000>; /* SVS */ qcom,svs = @@ -2159,7 +2187,7 @@ qcom,msm-adsprpc-mem { parade,core { parade,name = "pt_core"; - parade,irq_gpio = <&tlmm 13 0x2008>; + parade,irq_gpio = <&tlmm 13 0x00>; parade,rst_gpio = <&tlmm 12 0x00>; parade,hid_desc_register = <1>; /* @@ -2171,7 +2199,7 @@ qcom,msm-adsprpc-mem { * PT_CORE_FLAG_SKIP_RUNTIME = 0x20 * PT_CORE_FLAG_SKIP_RESUME = 0x40 */ - parade,flags = <4>; + parade,flags = <6>; /* PT_CORE_EWG_NONE */ parade,easy_wakeup_gesture = <0>; /* 0:AUTO 1:PIP1_ONLY 2:PIP2_CAPABLE*/ diff --git a/qcom/monacop-1gb.dtsi b/qcom/monacop-1gb.dtsi index 337a655e..eb34fbc7 100755 --- a/qcom/monacop-1gb.dtsi +++ b/qcom/monacop-1gb.dtsi @@ -19,3 +19,23 @@ &pil_modem_mem { reg = <0x0 0x4ab00000 0x0 0x3600000>; }; + +&pil_video_mem { + reg = <0x0 0x4E100000 0x0 0x500000>; +}; + +&pil_adsp_mem { + reg = <0x0 0x4E600000 0x0 0x1900000>; +}; + +&pil_ipa_fw_mem { + reg = <0x0 0x4FF00000 0x0 0x10000>; +}; + +&pil_ipa_gsi_mem { + reg = <0x0 0x4FF10000 0x0 0x5000>; +}; + +&pil_gpu_mem { + reg = <0x0 0x4FF15000 0x0 0x2000>; +}; diff --git a/qcom/monacop-atp-v1.dts b/qcom/monacop-atp-v1.dts new file mode 100755 index 00000000..cb1216e4 --- /dev/null +++ b/qcom/monacop-atp-v1.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "monacop.dtsi" +#include "monaco-atp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MonacoP ATP V1.0"; + compatible = "qcom,monaco", "qcom,atp"; + qcom,board-id = <0x010021 0x0>; +}; diff --git a/qcom/monacop-standalone-atp-v1.dts b/qcom/monacop-standalone-atp-v1.dts new file mode 100755 index 00000000..f9487ae0 --- /dev/null +++ b/qcom/monacop-standalone-atp-v1.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "monacop-1gb.dtsi" +#include "monaco-standalone-atp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco standalone ATP V1.0"; + compatible = "qcom,monaco", "qcom,atp"; + qcom,board-id = <0x010021 0x1>; +}; diff --git a/qcom/monacop-standalone-idp-v1-overlay.dts b/qcom/monacop-standalone-idp-v1-overlay.dts new file mode 100755 index 00000000..92a84a9b --- /dev/null +++ b/qcom/monacop-standalone-idp-v1-overlay.dts @@ -0,0 +1,9 @@ +/dts-v1/; +/plugin/; + +#include "monacop-standalone-idp-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monacop standalone IDP V1.0"; + qcom,board-id = <0x010122 0x1>; +}; diff --git a/qcom/monacop-standalone-idp-v1.dtsi b/qcom/monacop-standalone-idp-v1.dtsi new file mode 100755 index 00000000..63defdc0 --- /dev/null +++ b/qcom/monacop-standalone-idp-v1.dtsi @@ -0,0 +1,35 @@ +#include "monaco-standalone-idp-v1.dtsi" + +&soc { + qcom,rmnet-ipa { + status = "disabled"; + }; +}; + +&ipa_hw { + status = "disabled"; +}; + +&pil_modem_mem { + reg = <0x0 0x4ab00000 0x0 0x3600000>; +}; + +&pil_video_mem { + reg = <0x0 0x4E100000 0x0 0x500000>; +}; + +&pil_adsp_mem { + reg = <0x0 0x4E600000 0x0 0x1900000>; +}; + +&pil_ipa_fw_mem { + reg = <0x0 0x4FF00000 0x0 0x10000>; +}; + +&pil_ipa_gsi_mem { + reg = <0x0 0x4FF10000 0x0 0x5000>; +}; + +&pil_gpu_mem { + reg = <0x0 0x4FF15000 0x0 0x2000>; +}; diff --git a/qcom/monacop.dtsi b/qcom/monacop.dtsi index 538fd85e..cb40c32a 100755 --- a/qcom/monacop.dtsi +++ b/qcom/monacop.dtsi @@ -19,3 +19,23 @@ &pil_modem_mem { reg = <0x0 0x4ab00000 0x0 0x3600000>; }; + +&pil_video_mem { + reg = <0x0 0x4E100000 0x0 0x500000>; +}; + +&pil_adsp_mem { + reg = <0x0 0x4E600000 0x0 0x1900000>; +}; + +&pil_ipa_fw_mem { + reg = <0x0 0x4FF00000 0x0 0x10000>; +}; + +&pil_ipa_gsi_mem { + reg = <0x0 0x4FF10000 0x0 0x5000>; +}; + +&pil_gpu_mem { + reg = <0x0 0x4FF15000 0x0 0x2000>; +}; diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi index 02d215df..3043ea33 100755 --- a/qcom/pm5100.dtsi +++ b/qcom/pm5100.dtsi @@ -42,6 +42,8 @@ #size-cells = <1>; #cooling-cells = <2>; + qcom,thermal-mitigation = <1500000 + 1000000 500000>; qcom,chgr@2600 { reg = <0x1000>; interrupts = diff --git a/qcom/pm8008.dtsi b/qcom/pm8008.dtsi index fbde2891..52ab93f2 100755 --- a/qcom/pm8008.dtsi +++ b/qcom/pm8008.dtsi @@ -67,7 +67,7 @@ pm8008_9: qcom,pm8008@9 { regulator-min-microvolt = <528000>; regulator-max-microvolt = <1504000>; qcom,min-dropout-voltage = <225000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L2P: qcom,pm8008-l2@4100 { @@ -76,7 +76,7 @@ pm8008_9: qcom,pm8008@9 { regulator-min-microvolt = <528000>; regulator-max-microvolt = <1504000>; qcom,min-dropout-voltage = <225000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L3P: qcom,pm8008-l3@4200 { @@ -85,7 +85,7 @@ pm8008_9: qcom,pm8008@9 { regulator-min-microvolt = <1500000>; regulator-max-microvolt = <3400000>; qcom,min-dropout-voltage = <200000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L4P: qcom,pm8008-l4@4300 { @@ -94,7 +94,7 @@ pm8008_9: qcom,pm8008@9 { regulator-min-microvolt = <1500000>; regulator-max-microvolt = <3400000>; qcom,min-dropout-voltage = <200000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L5P: qcom,pm8008-l5@4400 { @@ -103,7 +103,7 @@ pm8008_9: qcom,pm8008@9 { regulator-min-microvolt = <1500000>; regulator-max-microvolt = <3400000>; qcom,min-dropout-voltage = <300000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L6P: qcom,pm8008-l6@4400 { @@ -112,7 +112,7 @@ pm8008_9: qcom,pm8008@9 { regulator-min-microvolt = <1500000>; regulator-max-microvolt = <3400000>; qcom,min-dropout-voltage = <300000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L7P: qcom,pm8008-l7@4400 { @@ -121,7 +121,7 @@ pm8008_9: qcom,pm8008@9 { regulator-min-microvolt = <1500000>; regulator-max-microvolt = <3400000>; qcom,min-dropout-voltage = <300000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; }; }; diff --git a/qcom/pm8010-rpm-regulator.dtsi b/qcom/pm8010-rpm-regulator.dtsi index 996a138b..bb498fe7 100755 --- a/qcom/pm8010-rpm-regulator.dtsi +++ b/qcom/pm8010-rpm-regulator.dtsi @@ -39,7 +39,7 @@ qcom,resource-id = <3>; qcom,regulator-type = <0>; qcom,regulator-hw-type = "pmic5-ldo"; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; status = "disabled"; regulator-l3 { @@ -56,7 +56,7 @@ qcom,resource-id = <4>; qcom,regulator-type = <0>; qcom,regulator-hw-type = "pmic5-ldo"; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; status = "disabled"; regulator-l4 { @@ -73,7 +73,7 @@ qcom,resource-id = <5>; qcom,regulator-type = <0>; qcom,regulator-hw-type = "pmic5-ldo"; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; status = "disabled"; regulator-l5 { @@ -90,7 +90,7 @@ qcom,resource-id = <6>; qcom,regulator-type = <0>; qcom,regulator-hw-type = "pmic5-ldo"; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; status = "disabled"; regulator-l6 { @@ -107,7 +107,7 @@ qcom,resource-id = <7>; qcom,regulator-type = <0>; qcom,regulator-hw-type = "pmic5-ldo"; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; status = "disabled"; regulator-l7 { diff --git a/qcom/pm8150.dtsi b/qcom/pm8150.dtsi index bde21fc7..8baf9aa8 100755 --- a/qcom/pm8150.dtsi +++ b/qcom/pm8150.dtsi @@ -115,7 +115,7 @@ compatible = "qcom,adc-tm5"; reg = <0x3500>; interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "thr-int-en"; + interrupt-names = "threshold"; #address-cells = <1>; #size-cells = <0>; #thermal-sensor-cells = <1>; diff --git a/qcom/pmi632.dtsi b/qcom/pmi632.dtsi index 0464d01e..2f403322 100755 --- a/qcom/pmi632.dtsi +++ b/qcom/pmi632.dtsi @@ -319,7 +319,7 @@ }; pmi632_qg: qpnp,qg { - compatible = "qcom,qpnp-qg"; + compatible = "qcom,pmi632-qg"; #address-cells = <1>; #size-cells = <0>; diff --git a/qcom/qbg-battery-profile-qrd-zwd-520mAh.dtsi b/qcom/qbg-battery-profile-qrd-zwd-520mAh.dtsi index 6bc3a433..b217c961 100755 --- a/qcom/qbg-battery-profile-qrd-zwd-520mAh.dtsi +++ b/qcom/qbg-battery-profile-qrd-zwd-520mAh.dtsi @@ -2,8 +2,10 @@ qcom,qbg-battery-profile-qrd-zwd-520mAh { qcom,battery-type = "QRD_ZWD_520MAH"; qcom,batt-id-kohm = <33>; qcom,capacity = <503>; + qcom,battery-beta = <4250>; + qcom,battery-therm-kohm = <100>; qcom,max-voltage-uv = <4350000>; - qcom,fastchg-current-ma = <520>; + qcom,fastchg-current-ma = <1040>; qcom,checksum = <4295719>; /*@5, 0.005V, 4% */ qcom,soh-range = <0 100>; /* Nominal_Impedance in 10nohm @ SOC 50% 25C* 0:fresh cell, 1: aged cell */ @@ -17,6 +19,23 @@ qcom,qbg-battery-profile-qrd-zwd-520mAh { /* Termination current (in mA) in recharge */ qcom,recharge-iterm-ma = <10>; + qcom,jeita-fcc-ranges = <0 150 156000 + 151 420 1040000 + 421 450 520000>; + + qcom,jeita-fv-ranges = <0 150 4300000 + 151 420 4350000 + 421 450 4300000>; + + /* COOL = 15 DegC, WARM = 42 DegC */ + qcom,jeita-soft-thresholds = <0x27c1 0x1444>; + /* COLD = 0 DegC, HOT = 45 DegC */ + qcom,jeita-hard-thresholds = <0x3257 0x128c>; + /* COOL = 18 DegC, WARM = 39 DegC*/ + qcom,jeita-soft-hys-thresholds = <0x256e 0x161b>; + qcom,jeita-soft-fcc-ua = <156000 520000>; + qcom,jeita-soft-fv-uv = <4300000 4300000>; + qcom,bp-c-table-0 { qcom,temperature = <25>; qcom,soc = < 0 39 78 97 136>, diff --git a/qcom/qcs405-blsp.dtsi b/qcom/qcs405-blsp.dtsi new file mode 100755 index 00000000..9e8d5182 --- /dev/null +++ b/qcom/qcs405-blsp.dtsi @@ -0,0 +1,513 @@ +#include "qcs405-pinctrl.dtsi" + +/ { + aliases { + spi1 = &spi_1; + spi2 = &spi_2; + spi3 = &spi_3; + spi4 = &spi_4; + spi5 = &spi_5; + spi6 = &spi_6; + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + }; +}; + +&soc { + dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0x7884000 0x25000>; + interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>; + qcom,summing-threshold = <0x10>; + }; + + dma_blsp2: qcom,sps-dma@7ac4000 { /* BLSP2 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0x7ac4000 0x17000>; + interrupts = <0 239 IRQ_TYPE_LEVEL_HIGH>; + qcom,summing-threshold = <0x10>; + }; + + i2c_1: i2c@78b5000 { /* BLSP1 QUP0 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x78b5000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 8 64 0x20000020 0x20>, + <&dma_blsp1 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <MASTER_BLSP_1>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_1_active>; + pinctrl-1 = <&i2c_1_sleep>; + status = "disabled"; + }; + + + i2c_2: i2c@78b6000 { /* BLSP1 QUP1 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x78b6000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 10 64 0x20000020 0x20>, + <&dma_blsp1 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <MASTER_BLSP_1>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_2_active>; + pinctrl-1 = <&i2c_2_sleep>; + status = "disabled"; + }; + + i2c_3: i2c@78b7000 { /* BLSP1 QUP2 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x78b7000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 12 64 0x20000020 0x20>, + <&dma_blsp1 13 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <MASTER_BLSP_1>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_3_sda_active>, <&i2c_3_scl_active>; + pinctrl-1 = <&i2c_3_sleep>; + status = "disabled"; + }; + + i2c_4: i2c@78b8000 { /* BLSP1 QUP3 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x78b8000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 14 64 0x20000020 0x20>, + <&dma_blsp1 15 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <MASTER_BLSP_1>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_4_active>; + pinctrl-1 = <&i2c_4_sleep>; + status = "disabled"; + }; + + i2c_5: i2c@78b9000 { /* BLSP1 QUP4 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x78b9000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 16 64 0x20000020 0x20>, + <&dma_blsp1 17 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <MASTER_BLSP_1>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_5_active>; + pinctrl-1 = <&i2c_5_sleep>; + status = "disabled"; + }; + + i2c_6: i2c@7af5000 { /* BLSP2 QUP1 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7af5000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 299 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp2 2 64 0x20000020 0x20>, + <&dma_blsp2 3 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <MASTER_BLSP_2>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_6_active>; + pinctrl-1 = <&i2c_6_sleep>; + status = "disabled"; + }; + + spi_1: spi@78b5000 { /* BLSP1 QUP0 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x78b5000 0x600>, + <0x7884000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>, + <0 238 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <8>; + qcom,bam-producer-pipe-index = <9>; + qcom,master-id = <MASTER_BLSP_1>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_1_active>; + pinctrl-1 = <&spi_1_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_2: spi@78b6000 { /* BLSP1 QUP1 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x78b6000 0x600>, + <0x7884000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>, + <0 238 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <10>; + qcom,bam-producer-pipe-index = <11>; + qcom,master-id = <MASTER_BLSP_1>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_2_mosi_a1_active + &spi_2_miso_a1_active + &spi_2_cs_n_a1_active + &spi_2_clk_a1_active>; + pinctrl-1 = <&spi_2_mosi_a1_sleep + &spi_2_miso_a1_sleep + &spi_2_cs_n_a1_sleep + &spi_2_clk_a1_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_3: spi@78b7000 { /* BLSP1 QUP2 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x78b7000 0x600>, + <0x7884000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>, + <0 238 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <12>; + qcom,bam-producer-pipe-index = <13>; + qcom,master-id = <MASTER_BLSP_1>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_3_active>; + pinctrl-1 = <&spi_3_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_4: spi@78b8000 { /* BLSP1 QUP3 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x78b8000 0x600>, + <0x7884000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>, + <0 238 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <14>; + qcom,bam-producer-pipe-index = <15>; + qcom,master-id = <MASTER_BLSP_1>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_4_active>; + pinctrl-1 = <&spi_4_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_5: spi@78b9000 { /* BLSP1 QUP4 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x78b9000 0x600>, + <0x7884000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>, + <0 238 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <16>; + qcom,bam-producer-pipe-index = <17>; + qcom,master-id = <MASTER_BLSP_1>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_5_active>; + pinctrl-1 = <&spi_5_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_6: spi@7af5000 { /* BLSP2 QUP1 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x7af5000 0x600>, + <0x7ac4000 0x17000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 299 IRQ_TYPE_LEVEL_HIGH>, + <0 239 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <2>; + qcom,bam-producer-pipe-index = <3>; + qcom,master-id = <MASTER_BLSP_2>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_6_active>; + pinctrl-1 = <&spi_6_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>; + status = "disabled"; + }; + + blsp1_uart1_hs: uart@78af000 { /* BLSP1 UART0 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x78af000 0x200>, + <0x7884000 0x25000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart1_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 107 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 238 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 31 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + + qcom,master-id = <MASTER_BLSP_1>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART0_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart1_sleep>; + pinctrl-1 = <&blsp1_uart1_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; + status = "disabled"; + + }; + + blsp1_uart2_hs: uart@78b0000 { /* BLSP1 UART1 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x78b0000 0x200>, + <0x7884000 0x25000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart2_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 108 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 238 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 23 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <2>; + qcom,bam-rx-ep-pipe-index = <3>; + + qcom,master-id = <MASTER_BLSP_1>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart2_sleep>; + pinctrl-1 = <&blsp1_uart2_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; + + status = "disabled"; + }; + + blsp1_uart3_hs: uart@78b1000 { /* BLSP1 UART2 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x78b1000 0x200>, + <0x7884000 0x25000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart3_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 118 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 238 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 18 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <4>; + qcom,bam-rx-ep-pipe-index = <5>; + + qcom,master-id = <MASTER_BLSP_1>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART2_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart3_sleep>; + pinctrl-1 = <&blsp1_uart3_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; + + status = "disabled"; + }; + + blsp1_uart4_hs: uart@78b2000 { /* BLSP1 UART3 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x78b2000 0x200>, + <0x7884000 0x25000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart4_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 119 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 238 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 83 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <6>; + qcom,bam-rx-ep-pipe-index = <7>; + + qcom,master-id = <MASTER_BLSP_1>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART3_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart4_sleep>; + pinctrl-1 = <&blsp1_uart4_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; + + status = "disabled"; + }; + + blsp2_uart1_hs: uart@7aef000 { /* BLSP2 UART0 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x7aef000 0x200>, + <0x7ac4000 0x17000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp2_uart1_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 297 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 239 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 27 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + + qcom,master-id = <MASTER_BLSP_2>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_UART0_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp2_uart1_sleep>; + pinctrl-1 = <&blsp2_uart1_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; + + status = "disabled"; + }; + +}; diff --git a/qcom/qcs405-cpu.dtsi b/qcom/qcs405-cpu.dtsi index 07c83a54..eac0ce39 100755 --- a/qcom/qcs405-cpu.dtsi +++ b/qcom/qcs405-cpu.dtsi @@ -32,6 +32,7 @@ compatible = "arm,cortex-a53"; reg = <0x100>; enable-method = "psci"; + cpu-idle-states = <&CORE_PC>; capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; #cooling-cells = <2>; @@ -58,6 +59,7 @@ compatible = "arm,cortex-a53"; reg = <0x101>; enable-method = "psci"; + cpu-idle-states = <&CORE_PC>; capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; #cooling-cells = <2>; @@ -77,6 +79,7 @@ compatible = "arm,cortex-a53"; reg = <0x102>; enable-method = "psci"; + cpu-idle-states = <&CORE_PC>; capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; #cooling-cells = <2>; @@ -96,6 +99,7 @@ compatible = "arm,cortex-a53"; reg = <0x103>; enable-method = "psci"; + cpu-idle-states = <&CORE_PC>; capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; #cooling-cells = <2>; diff --git a/qcom/qcs405-pinctrl.dtsi b/qcom/qcs405-pinctrl.dtsi index 520b66e9..8eb34fcd 100755 --- a/qcom/qcs405-pinctrl.dtsi +++ b/qcom/qcs405-pinctrl.dtsi @@ -11,6 +11,7 @@ gpio-ranges = <&tlmm 0 0 120>; gpio-controller; #gpio-cells = <2>; + wakeup-parent = <&wakegic>; blsp1_uart2_default: blsp1-uart2-default { rx { @@ -208,5 +209,617 @@ input-enable; }; }; + + /* UART configuration */ + blsp1_uart1 { + blsp1_uart1_active: blsp1_uart1_active { + mux { + pins = "gpio30", "gpio31"; + function = "blsp_uart0"; + }; + + config { + pins = "gpio30", "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1_sleep: blsp1_uart1_sleep { + mux { + pins = "gpio30", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + blsp1_uart2 { + blsp1_uart2_active: blsp1_uart2_active { + mux { + pins = "gpio22", "gpio23"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2_sleep: blsp1_uart2_sleep { + mux { + pins = "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + blsp1_uart3 { + blsp1_uart3_active: blsp1_uart3_active { + mux { + pins = "gpio17", "gpio18", + "gpio19", "gpio20"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio17", "gpio18", + "gpio19", "gpio20"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_sleep: blsp1_uart3_sleep { + mux { + pins = "gpio17", "gpio18", + "gpio19", "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio17", "gpio18", + "gpio19", "gpio20"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + blsp1_uart4 { + blsp1_uart4_active: blsp1_uart4_active { + mux { + pins = "gpio82", "gpio83"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio82", "gpio83"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4_sleep: blsp1_uart4_sleep { + mux { + pins = "gpio82", "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio82", "gpio83"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + blsp2_uart1 { + blsp2_uart1_active: blsp2_uart1_active { + mux { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + function = "blsp_uart5"; + }; + + config { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart1_sleep: blsp2_uart1_sleep { + mux { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + /* SPI CONFIGURATION */ + spi_1 { + spi_1_active: spi_1_active { + mux { + pins = "gpio30", "gpio31", + "gpio32", "gpio33"; + function = "blsp_spi0"; + }; + + config { + pins = "gpio30", "gpio31", + "gpio32", "gpio33"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_1_sleep: spi_1_sleep { + mux { + pins = "gpio30", "gpio31", + "gpio32", "gpio33"; + function = "blsp_spi0"; + }; + + config { + pins = "gpio30", "gpio31", + "gpio32", "gpio33"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_2 { + spi_2_mosi_a1_active: spi_2_mosi_a1_active { + mux { + pins = "gpio22"; + function = "blsp_spi_mosi_a1"; + }; + + config { + pins = "gpio22"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_2_mosi_a1_sleep: spi_2_mosi_a1_sleep { + mux { + pins = "gpio22"; + function = "blsp_spi_mosi_a1"; + }; + + config { + pins = "gpio22"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_2_miso_a1_active: spi_2_miso_a1_active { + mux { + pins = "gpio23"; + function = "blsp_spi_miso_a1"; + }; + + config { + pins = "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_2_miso_a1_sleep: spi_2_miso_a1_sleep { + mux { + pins = "gpio23"; + function = "blsp_spi_miso_a1"; + }; + + config { + pins = "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_2_cs_n_a1_active: spi_2_cs_n_a1_active { + mux { + pins = "gpio24"; + function = "blsp_spi_cs_n_a1"; + }; + + config { + pins = "gpio24"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_2_cs_n_a1_sleep: spi_2_cs_n_a1_sleep { + mux { + pins = "gpio24"; + function = "blsp_spi_cs_n_a1"; + }; + + config { + pins = "gpio24"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_2_clk_a1_active: spi_2_clk_a1_active { + mux { + pins = "gpio25"; + function = "blsp_spi_clk_a1"; + }; + + config { + pins = "gpio25"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_2_clk_a1_sleep: spi_2_clk_a1_sleep { + mux { + pins = "gpio25"; + function = "blsp_spi_clk_a1"; + }; + + config { + pins = "gpio25"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_3 { + spi_3_active: spi_3_active { + mux { + pins = "gpio17", "gpio18", + "gpio19", "gpio20"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio17", "gpio18", + "gpio19", "gpio20"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_3_sleep: spi_3_sleep { + mux { + pins = "gpio17", "gpio18", + "gpio19", "gpio20"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio17", "gpio18", + "gpio19", "gpio20"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_4 { + spi_4_active: spi_4_active { + mux { + pins = "gpio82", "gpio83", + "gpio84", "gpio85"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio82", "gpio83", + "gpio84", "gpio85"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_4_sleep: spi_4_sleep { + mux { + pins = "gpio82", "gpio83", + "gpio84", "gpio85"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio82", "gpio83", + "gpio84", "gpio85"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_5 { + spi_5_active: spi_5_active { + mux { + pins = "gpio37", "gpio38", + "gpio117", "gpio118"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio37", "gpio38", + "gpio117", "gpio118"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_5_sleep: spi_5_sleep { + mux { + pins = "gpio37", "gpio38", + "gpio117", "gpio118"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio37", "gpio38", + "gpio117", "gpio118"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_6 { + spi_6_active: spi_6_active { + mux { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + function = "blsp_spi5"; + }; + + config { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_6_sleep: spi_6_sleep { + mux { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + function = "blsp_spi5"; + }; + + config { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* I2C configuration */ + i2c_1 { + i2c_1_active: i2c_1_active { + /* active state */ + mux { + pins = "gpio32", "gpio33"; + function = "blsp_i2c0"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_1_sleep: i2c_1_sleep { + /* suspended state */ + mux { + pins = "gpio32", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_2 { + i2c_2_active: i2c_2_active { + /* active state */ + mux { + pins = "gpio24", "gpio25"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_2_sleep: i2c_2_sleep { + /* suspended state */ + mux { + pins = "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_3 { + i2c_3_sda_active: i2c_3_sda_active { + /* active state */ + mux { + pins = "gpio19"; + function = "blsp_i2c_sda_a2"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_3_scl_active: i2c_3_scl_active { + /* active state */ + mux { + pins = "gpio20"; + function = "blsp_i2c_scl_a2"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_3_sleep: i2c_3_sleep { + /* suspended state */ + mux { + pins = "gpio19", "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio19", "gpio20"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_4 { + i2c_4_active: i2c_4_active { + /* active state */ + mux { + pins = "gpio84", "gpio85"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_4_sleep: i2c_4_sleep { + /* suspended state */ + mux { + pins = "gpio84", "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_5 { + i2c_5_active: i2c_5_active { + /* active state */ + mux { + pins = "gpio117", "gpio118"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio117", "gpio118"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_5_sleep: i2c_5_sleep { + /* suspended state */ + mux { + pins = "gpio117", "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio117", "gpio118"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_6 { + i2c_6_active: i2c_6_active { + /* active state */ + mux { + pins = "gpio28", "gpio29"; + function = "blsp_i2c5"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_6_sleep: i2c_6_sleep { + /* suspended state */ + mux { + pins = "gpio28", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + }; }; diff --git a/qcom/qcs405-pm.dtsi b/qcom/qcs405-pm.dtsi new file mode 100755 index 00000000..6b74107a --- /dev/null +++ b/qcom/qcs405-pm.dtsi @@ -0,0 +1,107 @@ +&soc { + qcom,spm@b012000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb012000 0x1000>; + qcom,name = "perf-l2"; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x14>; + qcom,saw2-spm-dly= <0x3C11840A>; + qcom,saw2-spm-ctl = <0xe>; + qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,vctl-timeout-us = <500>; + qcom,vctl-port = <0x0>; + qcom,vctl-port-ub = <0x1>; + qcom,pfm-port = <0x02>; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + idle-state-name = "L2"; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xf>; + + CLUSTER_WFI: qcom,pm-cluster-level@0 { /* D1 */ + reg = <0>; + compatible = "arm,idle-state"; + idle-state-name = "l2-wfi"; + entry-latency-us = <125>; + exit-latency-us = <180>; + min-residency-us = <305>; + arm,psci-suspend-param = <0x10>; + qcom,psci-mode = <0x1>; + }; + + CLUSTER_OFF: qcom,pm-cluster-level@1 { /* D4 */ + reg = <1>; + compatible = "arm,idle-state"; + idle-state-name = "l2-rail-pc"; + entry-latency-us = <700>; + exit-latency-us = <1000>; + min-residency-us = <6500>; + arm,psci-suspend-param = <0x40>; + qcom,psci-mode = <0x4>; + qcom,notify-rpm; + qcom,min-child-idx = <1>; + qcom,is-reset; + }; + + qcom,pm-cpu@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + label = "pwr"; + qcom,disable-ipi-prediction; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; + + CORE_WFI: qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + compatible = "arm,idle-state"; + idle-state-name = "wfi"; + entry-latency-us = <13>; + exit-latency-us = <12>; + min-residency-us = <25>; + arm,psci-suspend-param = <0x1>; + qcom,psci-cpu-mode = <0x1>; + }; + + CORE_PC: qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <125>; + exit-latency-us = <180>; + min-residency-us = <595>; + qcom,psci-cpu-mode = <0x3>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + }; + }; + + rpm_sleep_stats: soc-sleep-stats@200000 { + compatible = "qcom,rpm-sleep-stats"; + reg = <0x200000 0x1000>; + }; + + subsystem-sleep-stats { + compatible = "qcom,subsystem-sleep-stats"; + }; + + rpmh-master-stats { + compatible = "qcom,rpmh-master-stats-v1"; + }; +}; diff --git a/qcom/qcs405.dtsi b/qcom/qcs405.dtsi index 9b4b16fc..3e3765e3 100755 --- a/qcom/qcs405.dtsi +++ b/qcom/qcs405.dtsi @@ -26,6 +26,7 @@ sdhc0 = &sdhc_1; sdhc1 = &sdhc_2; pci-domain0 = &pcie0; /* PCIe0 domain */ + qpic_nand1 = &qnand_1; }; chosen { @@ -94,16 +95,18 @@ qseecom_mem: qseecom_region { compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; - alignment = <0 0x400000>; - size = <0 0x1000000>; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; }; qseecom_ta_mem: qseecom_ta_region { compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; reusable; - alignment = <0 0x400000>; - size = <0 0x400000>; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; }; adsp_mem: adsp_region { @@ -132,7 +135,7 @@ soc: soc { }; }; - +#include "qcs405-ion.dtsi" &soc { #address-cells = <1>; #size-cells = <1>; @@ -160,6 +163,10 @@ #interrupt-cells = <2>; }; + system_pm_rpm { + compatible = "qcom,system-pm-rpm"; + }; + arch_timer: timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, @@ -728,6 +735,122 @@ qcom,wakeup-enable; status = "okay"; }; + qcom_crypto: qcrypto@720000 { + compatible = "qcom,qcrypto"; + reg = <0x720000 0x20000>, + <0x704000 0x20000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 206 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 393600 393600>; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-hmac-algo; + qcom,use-sw-aead-algo; + qcom,smmu-s1-enable; + iommus = <&apps_smmu 0x0064 0x0011>, + <&apps_smmu 0x0074 0x0011>; + }; + + qcom_cedev: qcedev@720000 { + compatible = "qcom,qcedev"; + reg = <0x720000 0x20000>, + <0x704000 0x20000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 206 0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,bam-pipe-pair = <3>; + qcom,ce-hw-instance = <0>; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 393600 393600>; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>; + qcom,smmu-s1-enable; + iommus = <&apps_smmu 0x0066 0x0011>, + <&apps_smmu 0x0076 0x0011>; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; + + qcom_qseecom: qseecom@85900000 { + compatible = "qcom,qseecom"; + reg = <0x85900000 0x500000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,fde-key-size; + qcom,no-clock-support; + qcom,appsbl-qseecom-support; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,ce-opp-freq = <171430000>; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_smcinvoke: smcinvoke@85900000 { + compatible = "qcom,smcinvoke"; + reg = <0x85900000 0x500000>; + reg-names = "secapp-region"; + }; + + qcom_rng: qrng@e3000 { + compatible = "qcom,msm-rng"; + reg = <0xe3000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 618 0 0>, /* No vote */ + <1 618 0 800>; /* 100 MB/s */ + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "km_clk_src"; + }; + + qcom_tzlog: tz-log@8600720 { + compatible = "qcom,tz-log"; + reg = <0x08600720 0x2000>; + }; mem_dump { compatible = "qcom,mem-dump"; @@ -958,6 +1081,33 @@ }; }; + qnand_1: nand@4c0000 { + compatible = "qcom,msm-nand"; + reg = <0x004c0000 0x1000>, + <0x004c4000 0x1a000>; + reg-names = "nand_phys", "bam_phys"; + qcom,reg-adjustment-offset = <0x4000>; + + interrupts = <0 49 0>; + interrupt-names = "bam_irq"; + + interconnects = <&pc_noc MASTER_QPIC &bimc SLAVE_EBI_CH0>; + interconnect-names = "nand-ddr"; + qcom,msm-bus,name = "qpic_nand"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + + qcom,msm-bus,vectors-KBps = + <0 0>, + /* Voting for max b/w on PNOC bus for now */ + <400000 400000>; + + clock-names = "core_clk"; + clocks = <&rpmcc RPM_SMD_QPIC_CLK>; + + status = "disabled"; + }; + msm_cpufreq: qcom,msm-cpufreq { compatible = "qcom,msm-cpufreq"; clock-names = "cpu0_clk"; @@ -1027,6 +1177,7 @@ }; #include "qcs405-pinctrl.dtsi" +#include "qcs405-pm.dtsi" #include "qcs405-cpu.dtsi" #include "pms405-rpm-regulator.dtsi" #include "qcs405-regulator.dtsi" @@ -1037,6 +1188,7 @@ #include "qcs405-thermal.dtsi" #include "qcs405-pcie.dtsi" #include "qcs405-usb.dtsi" +#include "qcs405-blsp.dtsi" &gdsc_mdss { status = "ok"; diff --git a/qcom/qrb2210-rb1-audio-overlay.dtsi b/qcom/qrb2210-rb1-audio-overlay.dtsi index 7bb1e656..b6d5747e 100755 --- a/qcom/qrb2210-rb1-audio-overlay.dtsi +++ b/qcom/qrb2210-rb1-audio-overlay.dtsi @@ -179,8 +179,7 @@ "Digital Mic3", "MIC BIAS1", "IN1_HPHL", "HPHL_OUT", "IN2_HPHR", "HPHR_OUT", - "SpkrRight WSA_IN", "EAR", - "SpkrLeft WSA_IN", "LO", + "SpkrMono WSA_IN", "LO", "TX SWR_INPUT", "VA_TX_SWR_CLK", "TX SWR_INPUT", "ADC1_OUTPUT", "TX SWR_INPUT", "ADC2_OUTPUT", @@ -214,13 +213,9 @@ nvmem-cells = <&adsp_variant>; nvmem-cell-names = "adsp_variant"; asoc-codec = <&stub_codec>, <&bolero>, - <&rouleur_codec>, <&wsa881x_i2c_e>, - <&wsa881x_i2c_f>; + <&rouleur_codec>, <&wsa881x_i2c_e>; asoc-codec-names = "msm-stub-codec.1", "bolero_codec", - "rouleur_codec", "wsa-codec0", - "wsa-codec1"; - qcom,wsa-max-devs = <2>; - qcom,codec-max-aux-devs = <0>; + "rouleur_codec", "wsa-codec0"; qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&bolero>, <&lpi_tlmm>; }; @@ -233,28 +228,13 @@ clocks = <&wsa881x_analog_clk 0>; qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>; qcom,wsa-analog-reset-gpio = <&wsa881x_analog_reset_gpio>; - qcom,wsa-prefix = "SpkrLeft"; + qcom,wsa-prefix = "SpkrMono"; }; wsa881x_i2c_44: wsa881x-i2c-codec@44 { compatible = "qcom,wsa881x-i2c-codec"; reg = <0x044>; }; - - wsa881x_i2c_f: wsa881x-i2c-codec@f { - compatible = "qcom,wsa881x-i2c-codec"; - reg = <0x0f>; - clock-names = "wsa_mclk"; - clocks = <&wsa881x_analog_clk 0>; - qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>; - qcom,wsa-analog-reset-gpio = <&wsa881x_analog_reset_gpio>; - qcom,wsa-prefix = "SpkrRight"; - }; - - wsa881x_i2c_45: wsa881x-i2c-codec@45 { - compatible = "qcom,wsa881x-i2c-codec"; - reg = <0x045>; - }; }; &soc { diff --git a/qcom/qrb2210-rb1.dts b/qcom/qrb2210-rb1.dts index e2eccb3a..44fabbe4 100755 --- a/qcom/qrb2210-rb1.dts +++ b/qcom/qrb2210-rb1.dts @@ -1,11 +1,11 @@ /dts-v1/; -#include "qrb2210-rb1.dtsi" -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include "qrb2210-rb1-idp.dtsi" +//#include "qrb2210-rb1.dtsi" +//#include <dt-bindings/interrupt-controller/arm-gic.h> +//#include "qrb2210-rb1-idp.dtsi" / { - model = "Qualcomm Technologies, Inc. QRB2210 RB1"; + model = "Qualcomm Technologies, Inc. Scuba IOT SoC"; compatible = "qcom,scuba-iot"; - qcom,board-id = <34 0>; + qcom,board-id = <0 0>; }; diff --git a/qcom/qrb4210-rb2-pinctrl.dtsi b/qcom/qrb4210-rb2-pinctrl.dtsi index 9185a59c..4db15621 100755 --- a/qcom/qrb4210-rb2-pinctrl.dtsi +++ b/qcom/qrb4210-rb2-pinctrl.dtsi @@ -409,99 +409,6 @@ }; }; - nfc { - nfc_int_active: nfc_int_active { - /* active state */ - mux { - /* GPIO 70 NFC Read Interrupt */ - pins = "gpio70"; - function = "gpio"; - }; - - config { - pins = "gpio70"; - drive-strength = <2>; /* 2 MA */ - bias-pull-up; - }; - }; - - nfc_int_suspend: nfc_int_suspend { - /* sleep state */ - mux { - /* GPIO 70 NFC Read Interrupt */ - pins = "gpio70"; - function = "gpio"; - }; - - config { - pins = "gpio70"; - drive-strength = <2>; /* 2 MA */ - bias-pull-up; - }; - }; - - nfc_enable_active: nfc_enable_active { - /* active state */ - mux { - /* 69: Enable 31: Firmware */ - pins = "gpio69", "gpio31"; - function = "gpio"; - }; - - config { - pins = "gpio69", "gpio31"; - drive-strength = <2>; /* 2 MA */ - bias-pull-up; - }; - }; - - nfc_enable_suspend: nfc_enable_suspend { - /* sleep state */ - mux { - /* 69: Enable 31: Firmware */ - pins = "gpio69", "gpio31"; - function = "gpio"; - }; - - config { - pins = "gpio69", "gpio31"; - drive-strength = <2>; /* 2 MA */ - bias-disable; - }; - }; - - nfc_clk_req_active: nfc_clk_req_active { - /* active state */ - mux { - /* GPIO 86: NFC CLOCK REQUEST */ - pins = "gpio86"; - function = "gpio"; - }; - - config { - pins = "gpio86"; - drive-strength = <2>; /* 2 MA */ - bias-pull-up; - }; - }; - - nfc_clk_req_suspend: nfc_clk_req_suspend { - /* sleep state */ - mux { - /* GPIO 86: NFC CLOCK REQUEST */ - pins = "gpio86"; - function = "gpio"; - }; - - config { - pins = "gpio86"; - drive-strength = <2>; /* 2 MA */ - bias-disable; - }; - }; - }; - - qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { qupv3_se2_i2c_active: qupv3_se2_i2c_active { mux { diff --git a/qcom/qrb4210-rb2-qrd.dtsi b/qcom/qrb4210-rb2-qrd.dtsi index fe04071c..f215d28c 100755 --- a/qcom/qrb4210-rb2-qrd.dtsi +++ b/qcom/qrb4210-rb2-qrd.dtsi @@ -1,6 +1,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/iio/qcom,spmi-vadc.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/iio/qti_power_supply_iio.h> &qupv3_se1_i2c { status = "ok"; @@ -10,11 +11,26 @@ &soc { qrd_batterydata: qcom,battery-data { qcom,batt-id-range-pct = <15>; - #include "qg-batterydata-atl466271_3300mAh.dtsi" + #include "qg-batterydata-alium-3600mah.dtsi" }; }; &pmi632_qg { + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pmi632_vadc ADC5_BAT_THERM_100K_PU>, + <&pmi632_vadc ADC5_BAT_ID_100K_PU>, + <&pmi632_charger PSY_IIO_INPUT_CURRENT_LIMITED>, + <&pmi632_charger PSY_IIO_RECHARGE_SOC>, + <&pmi632_charger PSY_IIO_FORCE_RECHARGE>, + <&pmi632_charger PSY_IIO_CHARGE_DONE>; + io-channel-names = "batt-therm", + "batt-id", + "input_current_limited", + "recharge_soc", + "force_recharge", + "charge_done", + "cp_charging_enabled"; qcom,battery-data = <&qrd_batterydata>; qcom,qg-iterm-ma = <100>; qcom,hold-soc-while-full; @@ -23,7 +39,42 @@ }; &pmi632_charger { - qcom,battery-data = <&qrd_batterydata>; + status = "ok"; + #io-channel-cells = <1>; + io-channels = <&pmi632_qg PSY_IIO_RESISTANCE_ID>, + <&pmi632_qg PSY_IIO_VOLTAGE_NOW>, + <&pmi632_qg PSY_IIO_TEMP>, + <&pmi632_qg PSY_IIO_CAPACITY>, + <&pmi632_qg PSY_IIO_VOLTAGE_OCV>, + <&pmi632_qg PSY_IIO_VOLTAGE_AVG>, + <&pmi632_qg PSY_IIO_DEBUG_BATTERY>, + <&pmi632_qg PSY_IIO_REAL_CAPACITY>, + <&pmi632_qg PSY_IIO_CC_SOC>, + <&pmi632_qg PSY_IIO_CURRENT_NOW>, + <&pmi632_qg PSY_IIO_VOLTAGE_MAX>, + <&pmi632_qg PSY_IIO_CHARGE_FULL>, + <&pmi632_qg PSY_IIO_CHARGE_COUNTER>, + <&pmi632_qg PSY_IIO_CYCLE_COUNT>, + <&pmi632_qg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pmi632_qg PSY_IIO_TIME_TO_FULL_NOW>; + io-channel-names = "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "real_capacity", + "cc_soc", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now"; + qcom,batteryless-platform; + qcom,lpd-disable; qcom,suspend-input-on-debug-batt; qcom,sw-jeita-enable; qcom,step-charging-enable; @@ -119,6 +170,34 @@ gpio-key,wakeup; }; }; + + leds { + compatible = "gpio-leds"; + + gpio52 { + label = "user4-led_green"; + gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + gpio47 { + label = "wifi-led_yellow"; + gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + gpio45 { + label = "bt-led_blue"; + gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pm6125_pwm 0 100000>; + cooling-levels = <0 32 64 128 170 230 255>; + }; }; &sdhc_1 { @@ -147,14 +226,13 @@ qcom,vdd-io-voltage-level = <1800000 2960000>; qcom,vdd-io-current-level = <0 22000>; - vdd-io-bias-supply = <&L7A>; - qcom,vdd-io-bias-voltage-level = <1256000 1256000>; - qcom,vdd-io-bias-current-level = <0 6000>; - + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>; - status = "disabled"; + status = "ok"; }; &tlmm { @@ -177,7 +255,7 @@ pinctrl-0 = <&smb_int_default>; interrupt-parent = <&tlmm>; interrupts = <105 IRQ_TYPE_LEVEL_LOW>; - status = "ok"; + status = "disabled"; }; &smb1355_charger { @@ -186,7 +264,7 @@ qcom,parallel-mode = <1>; qcom,disable-ctm; qcom,hw-die-temp-mitigation; - status = "ok"; + status = "disabled"; }; &pm6125_pwm { diff --git a/qcom/qrb4210-rb2-vidc.dtsi b/qcom/qrb4210-rb2-vidc.dtsi new file mode 100755 index 00000000..6b220a29 --- /dev/null +++ b/qcom/qrb4210-rb2-vidc.dtsi @@ -0,0 +1,89 @@ +&soc { + msm_vidc: qcom,vidc@5a00000 { + compatible = "qcom,msm-vidc", "qcom,bengal-vidc"; + status = "ok"; + reg = <0x5a00000 0x200000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + + /* Supply */ + venus-supply = <&gcc_venus_gdsc>; + venus-core0-supply = <&gcc_vcodec0_gdsc>; + + /* Clocks */ + clock-names = "core_clk", "iface_clk", "bus_clk", + "core0_clk", "core0_bus_clk", "throttle_clk"; + clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>, + <&gcc GCC_VENUS_CTL_AXI_CLK>, + <&gcc GCC_VIDEO_VCODEC0_SYS_CLK>, + <&gcc GCC_VCODEC0_AXI_CLK>, + <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>; + qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk", + "core0_clk", "core0_bus_clk", "throttle_clk"; + qcom,clock-configs = <0x1 0x0 0x0 0x1 0x0 0x0>; + qcom,allowed-clock-rates = <133330000 240000000 300000000 + 384000000>; + + /* Bus Interconnects */ + interconnect-names = "venus-cnoc", "venus-ddr"; + interconnects = <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_VENUS_CFG>, + <&mmnrt_virt MASTER_VIDEO_P0 + &bimc SLAVE_EBI_CH0>; + + /* Bus BW range (low, high) for each bus */ + qcom,bus-range-kbps = <1000 1000 + 1000 2128000>; + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = + <&apps_smmu 0x860 0x00>, + <&apps_smmu 0x880 0x00>; + qcom,iommu-dma-addr-pool = <0x70800000 0x6f800000>; + qcom,iommu-faults = "non-fatal"; + buffer-types = <0xfff>; + virtual-addr-pool = <0x70800000 0x6f800000>; + }; + + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = + <&apps_smmu 0x861 0x04>; + qcom,iommu-dma-addr-pool = <0x4b000000 0x25800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/ + buffer-types = <0x241>; + virtual-addr-pool = <0x4b000000 0x25800000>; + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = + <&apps_smmu 0x863 0x0>; + qcom,iommu-dma-addr-pool = <0x25800000 0x25800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/ + buffer-types = <0x106>; + virtual-addr-pool = <0x25800000 0x25800000>; + qcom,secure-context-bank; + }; + + secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = + <&apps_smmu 0x804 0xE0>; + qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/ + buffer-types = <0x480>; + virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-context-bank; + }; + }; +}; diff --git a/qcom/qrb4210-rb2.dtsi b/qcom/qrb4210-rb2.dtsi index f4ad8858..87390ad6 100755 --- a/qcom/qrb4210-rb2.dtsi +++ b/qcom/qrb4210-rb2.dtsi @@ -271,25 +271,25 @@ }; &firmware { - android { - compatible = "android,firmware"; - vbmeta { - compatible="android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo,recovery"; - }; - - fstab { - compatible = "android,fstab"; - vendor { - compatible = "android,vendor"; - dev = "/dev/block/platform/soc/4744000.sdhci/by-name/vendor"; - type = "ext4"; - mnt_flags = "ro,barrier=1,discard"; - fsmgr_flags = "wait,slotselect,avb"; - status = "ok"; - }; + android { + compatible = "android,firmware"; + vbmeta { + compatible="android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo,recovery"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/4744000.sdhci/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; }; }; + }; }; &reserved_memory { @@ -462,7 +462,7 @@ redistributor-stride = <0x0 0x20000>; reg = <0xf200000 0x10000>, /* GICD */ <0xf300000 0x100000>; /* GICR * 8 */ - interrupts = <1 9 4>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <0>; }; @@ -772,14 +772,10 @@ interrupt-names = "hc_irq", "pwr_irq"; qcom,bus-width = <4>; - qcom,large-address-bus; - qcom,clk-rates = <400000 20000000 25000000 - 50000000 100000000 202000000>; - qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", - "SDR104"; - - qcom,devfreq,freq-table = <50000000 202000000>; + interconnects = <&system_noc MASTER_SDCC_2 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; qcom,msm-bus,name = "sdhc2"; qcom,msm-bus,num-cases = <8>; @@ -811,21 +807,27 @@ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100750000 200000000 4294967295>; - /* PM QoS */ - qcom,pm-qos-irq-type = "affine_irq"; - qcom,pm-qos-irq-latency = <26 26>; - qcom,pm-qos-cpu-groups = <0x0f 0xf0>; - qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>; + qcom,devfreq,freq-table = <50000000 202000000>; + no-mmc; + no-sdio; + max-frequency = <202000000>; + iommus = <&apps_smmu 0xA0 0x0>; + qcom,iommu-dma = "bypass"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>; - clock-names = "iface_clk", "core_clk"; + clock-names = "iface", "core"; /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */ qcom,dll-hsr-list = <0x0007642c 0x0 0x0 0x00010800 0x80040868>; - status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <43>; + }; + }; bluetooth: bt_wcn3990 { @@ -844,10 +846,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 1 0xf08>, - <1 2 0xf08>, - <1 3 0xf08>, - <1 0 0xf08>; + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; clock-frequency = <19200000>; }; @@ -869,50 +871,50 @@ frame@f121000 { frame-number = <0>; - interrupts = <0 8 0x4>, - <0 7 0x4>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf121000 0x1000>, <0xf122000 0x1000>; }; frame@f123000 { frame-number = <1>; - interrupts = <0 9 0x4>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf123000 0x1000>; status = "disabled"; }; frame@f124000 { frame-number = <2>; - interrupts = <0 10 0x4>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf124000 0x1000>; status = "disabled"; }; frame@f125000 { frame-number = <3>; - interrupts = <0 11 0x4>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf125000 0x1000>; status = "disabled"; }; frame@f126000 { frame-number = <4>; - interrupts = <0 12 0x4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf126000 0x1000>; status = "disabled"; }; frame@f127000 { frame-number = <5>; - interrupts = <0 13 0x4>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf127000 0x1000>; status = "disabled"; }; frame@f128000 { frame-number = <6>; - interrupts = <0 14 0x4>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; reg = <0xf128000 0x1000>; status = "disabled"; }; @@ -966,6 +968,10 @@ }; }; + dload_mode { + compatible = "qcom,dload-mode"; + }; + restart@440b000 { compatible = "qcom,pshold"; reg = <0x440b000 0x4>, @@ -1116,7 +1122,7 @@ cpu_pmu: cpu-pmu { compatible = "arm,armv8-pmuv3"; qcom,irq-is-percpu; - interrupts = <1 6 4>; + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; }; eud: qcom,msm-eud@1610000 { @@ -2247,12 +2253,9 @@ qcom,ahb-freq = <240000000>; qcom,pas-id = <9>; - qcom,msm-bus,name = "pil-venus"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <63 512 0 0>, - <63 512 0 304000>; + interconnect-names = "pil-venus"; + interconnects = <&mmnrt_virt MASTER_VIDEO_P0 + &bimc SLAVE_EBI_CH0>; qcom,proxy-timeout-ms = <100>; qcom,firmware-name = "venus"; memory-region = <&pil_video_mem>; @@ -2598,6 +2601,7 @@ #include "qrb4210-rb2-gdsc.dtsi" #include "qrb4210-rb2-usb.dtsi" #include "qrb4210-rb2-ion.dtsi" +#include "qrb4210-rb2-vidc.dtsi" #include "qrb4210-rb2-gpu.dtsi" #include "qrb4210-rb2-coresight.dtsi" #include "pmi632.dtsi" @@ -2809,6 +2813,58 @@ }; }; +&pmi632_vadc { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&conn_therm_default &skin_therm_default>; + + conn_therm { + reg = <ADC5_GPIO1_100K_PU>; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_therm { + reg = <ADC5_GPIO3_100K_PU>; + label = "skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pmi632_gpios { + conn_therm { + conn_therm_default: conn_therm_default { + pins = "gpio1"; + bias-high-impedance; + }; + }; + + skin_therm { + skin_therm_default: skin_therm_default { + pins = "gpio3"; + bias-high-impedance; + }; + }; +}; + +&pmi632_adc_tm { + #address-cells = <1>; + #size-cells = <0>; + io-channels = <&pmi632_vadc ADC5_GPIO3_100K_PU>; + + /* Channel nodes */ + skin_therm { + reg = <ADC5_GPIO3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + &pm6125_adc_tm { #address-cells = <1>; #size-cells = <0>; diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index 91880f64..6ad519ce 100755 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -61,7 +61,7 @@ firmware: firmware { android { compatible = "android,firmware"; - boot_devices = "vdevs/1c140000.virtio_blk,vdevs/1c0b0000.virtio_blk,vdevs/1c0f0000.virtio_blk"; + boot_devices = "vdevs/1c140000.virtio_blk,vdevs/1c0b0000.virtio_blk,vdevs/1c0f0000.virtio_blk,vdevs/1c160000.virtio_blk,vdevs/1c130000.virtio_blk"; vbmeta { compatible = "android,vbmeta"; diff --git a/qcom/sa2150p-ccard.dtsi b/qcom/sa2150p-ccard.dtsi index dadd5b30..877eac7e 100755 --- a/qcom/sa2150p-ccard.dtsi +++ b/qcom/sa2150p-ccard.dtsi @@ -191,3 +191,23 @@ &usb3 { extcon = <&usb3_extcon>; }; + +&qnand_1 { + status = "ok"; +}; + +&spi_6 { + status = "okay"; +}; + +&i2c_5 { + status = "okay"; +}; + +&blsp1_uart4_hs { + status = "okay"; +}; + +&blsp1_uart1_hs { + status = "okay"; +}; diff --git a/qcom/sa410m-gdsc.dtsi b/qcom/sa410m-gdsc.dtsi new file mode 100755 index 00000000..34a178aa --- /dev/null +++ b/qcom/sa410m-gdsc.dtsi @@ -0,0 +1,111 @@ +&soc { + /* GDSCs in GCC */ + gcc_camss_top_gdsc: qcom,gdsc@1458004 { + compatible = "qcom,gdsc"; + reg = <0x1458004 0x4>; + regulator-name = "gcc_camss_top_gdsc"; + status = "disabled"; + }; + + gcc_usb30_prim_gdsc: qcom,gdsc@141a004 { + compatible = "qcom,gdsc"; + reg = <0x141a004 0x4>; + regulator-name = "gcc_usb30_prim_gdsc"; + status = "disabled"; + }; + + gcc_vcodec0_gdsc: qcom,gdsc@1458098 { + compatible = "qcom,gdsc"; + reg = <0x1458098 0x4>; + regulator-name = "gcc_vcodec0_gdsc"; + status = "disabled"; + }; + + gcc_venus_gdsc: qcom,gdsc@145807c { + compatible = "qcom,gdsc"; + reg = <0x145807c 0x4>; + regulator-name = "gcc_venus_gdsc"; + status = "disabled"; + }; + + hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@147d074 { + compatible = "qcom,gdsc"; + reg = <0x147d074 0x4>; + regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@147d078 { + compatible = "qcom,gdsc"; + reg = <0x147d078 0x4>; + regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@147d060 { + compatible = "qcom,gdsc"; + reg = <0x147d060 0x4>; + regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@147d07c { + compatible = "qcom,gdsc"; + reg = <0x147d07c 0x4>; + regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + /* GDSCs in DISPCC */ + mdss_core_gdsc: qcom,gdsc@5f03000 { + compatible = "qcom,gdsc"; + reg = <0x5f03000 0x4>; + regulator-name = "mdss_core_gdsc"; + proxy-supply = <&mdss_core_gdsc>; + qcom,proxy-consumer-enable; + status = "disabled"; + }; + + /* GDSCs in GPUCC */ + gpu_cx_hw_ctrl: syscon@5991540 { + compatible = "syscon"; + reg = <0x5991540 0x4>; + }; + + gpu_gx_sw_reset: syscon@5991008 { + compatible = "syscon"; + reg = <0x5991008 0x4>; + }; + + gpu_gx_domain_addr: syscon@5991508 { + compatible = "syscon"; + reg = <0x5991508 0x4>; + }; + + gpu_cx_gdsc: qcom,gdsc@599106c { + compatible = "qcom,gdsc"; + reg = <0x599106c 0x4>; + regulator-name = "gpu_cx_gdsc"; + hw-ctl-addr = <&gpu_cx_hw_ctrl>; + qcom,no-status-check-on-disable; + status = "disabled"; + }; + + gpu_gx_gdsc: qcom,gdsc@599100c { + compatible = "qcom,gdsc"; + reg = <0x599100c 0x4>; + regulator-name = "gpu_gx_gdsc"; + sw-reset = <&gpu_gx_sw_reset>; + domain-addr = <&gpu_gx_domain_addr>; + qcom,reset-aon-logic; + status = "disabled"; + }; +}; diff --git a/qcom/sa410m.dtsi b/qcom/sa410m.dtsi index 2dbf24c6..f8212a93 100755 --- a/qcom/sa410m.dtsi +++ b/qcom/sa410m.dtsi @@ -1,5 +1,11 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/qcom,gcc-scuba.h> +#include <dt-bindings/clock/qcom,dispcc-scuba.h> +#include <dt-bindings/clock/qcom,gpucc-scuba.h> +#include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/interconnect/qcom,icc.h> +#include <dt-bindings/interconnect/qcom,scuba.h> / { #address-cells = <2>; @@ -442,6 +448,11 @@ qcom,rtb-size = <0x100000>; }; + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + cpu_pmu: cpu-pmu { compatible = "arm,armv8-pmuv3"; qcom,irq-is-percpu; @@ -496,6 +507,13 @@ status = "disabled"; }; + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + mem_dump { compatible = "qcom,mem-dump"; memory-region = <&dump_mem>; @@ -581,18 +599,166 @@ }; }; + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "chip_sleep_clk"; + #clock-cells = <0>; + }; + }; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-scuba"; + #clock-cells = <1>; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,scuba-gcc", "syscon"; + reg = <0x1400000 0x1f0000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@5f00000 { + compatible = "qcom,scuba-dispcc", "syscon"; + reg = <0x5f00000 0x20000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", + "gcc_disp_gpll0_div_clk_src", + "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@5990000 { + compatible = "qcom,scuba-gpucc", "syscon"; + reg = <0x5990000 0x9000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", "gpll0_out_main", + "gpll0_out_main_div"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cpucc: syscon@f11101c { + compatible = "syscon"; + reg = <0xf11101c 0x4>; + }; + + mccc: syscon@447d200 { + compatible = "syscon"; + reg = <0x447d200 0x100>; + }; + + debugcc: clock-controller@0 { + compatible = "qcom,blair-debugcc"; + qcom,gcc = <&gcc>; + qcom,dispcc = <&dispcc>; + qcom,gpucc = <&gpucc>; + qcom,cpucc = <&cpucc>; + qcom,mccc = <&mccc>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo_clk_src"; + #clock-cells = <1>; + }; + cpufreq_hw: qcom,cpufreq-hw { compatible = "qcom,cpufreq-hw"; reg = <0xf521000 0x1400>; reg-names = "freq-domain0"; - //clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; - //clock-names = "xo", "alternate"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; qcom,no-accumulative-counter; qcom,max-lut-entries = <12>; #freq-domain-cells = <2>; status = "ok"; }; + clk_virt: interconnect@0 { + compatible = "qcom,scuba-clk_virt"; + qcom,keepalive; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_QUP_CLK>, + <&rpmcc RPM_SMD_QUP_A_CLK>; + }; + + system_noc: interconnect0@1880000 { + reg = <0x1880000 0x60200>; + compatible = "qcom,scuba-sys_noc"; + qcom,keepalive; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + + mmnrt_virt: interconnect1@1880000 { + reg = <0x1880000 0x60200>; + compatible = "qcom,scuba-mmnrt_virt"; + qcom,util-factor = <142>; + qcom,keepalive; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_MMNRT_CLK>, + <&rpmcc RPM_SMD_MMNRT_A_CLK>; + }; + + mmrt_virt: interconnect2@1880000 { + reg = <0x1880000 0x60200>; + compatible = "qcom,scuba-mmrt_virt"; + qcom,util-factor = <139>; + qcom,keepalive; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_MMRT_CLK>, + <&rpmcc RPM_SMD_MMRT_A_CLK>; + }; + + config_noc: interconnect@1900000 { + reg = <0x1900000 0x9200>; + compatible = "qcom,scuba-config_noc"; + qcom,keepalive; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, + <&rpmcc RPM_SMD_CNOC_A_CLK>; + }; + + bimc: interconnect@4480000 { + reg = <0x4480000 0x80000>; + compatible = "qcom,scuba-bimc"; + qcom,util-factor = <153>; + qcom,keepalive; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + pil_scm_pas { compatible = "qcom,pil-tz-scm-pas"; //interconnects = <&clk_virt MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI_CH0>; @@ -690,8 +856,305 @@ qcom_scm: qcomscm { compatible = "qcom,scm"; }; + + tcsr_mutex_block: syscon@00340000 { + compatible = "syscon"; + reg = <0x340000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + //memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + apcs_glb: mailbox@0f111000 { + compatible = "qcom,scuba-apcs-hmss-global"; + reg = <0xF111000 0x1000>; + + #mbox-cells = <1>; + }; + + rpm_msg_ram: memory@045f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x45f0000 0x7000>; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + qcom,rpm_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>; + }; + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apcs_glb 12>; + mbox-names = "mpss_smem"; + interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 2>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apcs_glb 8>; + mbox-names = "adsp_smem"; + interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; + mboxes = <&apcs_glb 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; + mboxes = <&apcs_glb 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + }; #include "sa410m-pinctrl.dtsi" +#include "pm2250-rpm-regulator.dtsi" +#include "scuba-regulator.dtsi" #include "scuba-ion.dtsi" #include "msm-arm-smmu-scuba.dtsi" +#include "sa410m-gdsc.dtsi" + +&gcc_camss_top_gdsc { + status = "ok"; +}; + +&gcc_usb30_prim_gdsc { + status = "ok"; +}; + +&gcc_vcodec0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&gcc_venus_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu0_gdsc { + status = "ok"; +}; + +&mdss_core_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&gpu_cx_gdsc { + status = "ok"; +}; + +&gpu_gx_gdsc { + status = "ok"; +}; diff --git a/qcom/sa6155-adp-air.dtsi b/qcom/sa6155-adp-air.dtsi index 71e34236..e2a29af5 100755 --- a/qcom/sa6155-adp-air.dtsi +++ b/qcom/sa6155-adp-air.dtsi @@ -23,12 +23,12 @@ vdd-min-voltage = <1800000>; vdd-max-voltage = <1900000>; interrupt-parent = <&tlmm>; - interrupts = <22 4>; + interrupts = <122 4>; st,drdy-int-pin= <1>; pinctrl-names = "default"; pinctrl-0 = <&sensor_int1_default>; sensor_int1_default: sensor_int1_default { - pins = "gpio22"; + pins = "gpio122"; drive-strength = <16>; bias-pull-up; }; diff --git a/qcom/sa6155-adp-common.dtsi b/qcom/sa6155-adp-common.dtsi index edddba30..7413f4b1 100755 --- a/qcom/sa6155-adp-common.dtsi +++ b/qcom/sa6155-adp-common.dtsi @@ -181,6 +181,33 @@ qcom,iommu-dma = "fastmap"; qcom,iommu-dma-addr-pool = <0x80000000 0x40000000>; }; + + rgmii-io-macro-info { + config-cdr-en = <1>; + mclk-gating-en = <1>; + cdr-fine-phase = <1>; + skip-calc-traffic = <1>; + data-divide-clk-sel = <0>; + prg-rclk-dly = <1000>; + loopback-en = <1>; + rx-prog-swap = <1>; + tx-clk-phase-shift-en = <1>; + + dll-clock-dis = <0>; + mclk-freq-calc = <0x1A>; + ddr-traffic-init-sel = <0>; + ddr-traffic-init-sw = <0>; + ddr-cal-en = <0>; + + tcx0-cycles-dly-line = <64>; + tcx0-cycles-cnt = <4>; + + test-ctl = <0xC1800000>; + usr-ctl = <0x2C010800>; + + pps-create = <1>; + }; + }; }; diff --git a/qcom/sa6155.dtsi b/qcom/sa6155.dtsi index 9a1a1854..7e1eda93 100755 --- a/qcom/sa6155.dtsi +++ b/qcom/sa6155.dtsi @@ -153,10 +153,6 @@ q6-hvx-step { trips { - q6-hvx-config { - temperature = <105000>; - }; - q6-hvx-trip1 { temperature = <105000>; }; @@ -530,6 +526,36 @@ #address-cells = <1>; #size-cells = <0>; + qcom,speed-bin = <91>; + + qcom,initial-pwrlevel = <0>; + qcom,ca-target-pwrlevel = <0>; + + /* SVS */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <435000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_SVS>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* XO */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <0>; + qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-6 { + #address-cells = <1>; + #size-cells = <0>; + qcom,speed-bin = <73>; qcom,initial-pwrlevel = <0>; diff --git a/qcom/sa6155p-vm-cnss.dtsi b/qcom/sa6155p-vm-cnss.dtsi index 720ef687..1acebc7b 100755 --- a/qcom/sa6155p-vm-cnss.dtsi +++ b/qcom/sa6155p-vm-cnss.dtsi @@ -111,6 +111,7 @@ qcom,wlan-ramdump-dynamic = <0x400000>; mhi,max-channels = <30>; mhi,timeout = <10000>; + mhi,buffer-len = <0x8000>; mhi_channels { mhi_chan@0 { diff --git a/qcom/sa6155p-vm.dtsi b/qcom/sa6155p-vm.dtsi index a30a3417..1a079d65 100755 --- a/qcom/sa6155p-vm.dtsi +++ b/qcom/sa6155p-vm.dtsi @@ -5,7 +5,7 @@ / { model = "Qualcomm Technologies, Inc. SA6155P Virtual Machine"; qcom,msm-name = "SA6155P"; - qcom,msm-id = <377 0x0>; + qcom,msm-id = <377 0x10000>; aliases { hsuart0 = &qupv3_se7_4uart; diff --git a/qcom/sa6155p.dtsi b/qcom/sa6155p.dtsi index 80232eb6..90384e31 100755 --- a/qcom/sa6155p.dtsi +++ b/qcom/sa6155p.dtsi @@ -482,6 +482,36 @@ #address-cells = <1>; #size-cells = <0>; + qcom,speed-bin = <91>; + + qcom,initial-pwrlevel = <0>; + qcom,ca-target-pwrlevel = <0>; + + /* SVS */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <435000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_SVS>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* XO */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <0>; + qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-6 { + #address-cells = <1>; + #size-cells = <0>; + qcom,speed-bin = <73>; qcom,initial-pwrlevel = <0>; @@ -515,3 +545,125 @@ }; #include "sa6155-audio.dtsi" + +&thermal_zones { + cpuss-0-step { + trips { + cpu45-config { + temperature = <115000>; + }; + }; + }; + + cpuss-1-step { + trips { + cpu23-config { + temperature = <115000>; + }; + }; + }; + + cpuss-2-step { + trips { + cpu01-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-0-step { + trips { + cpu6-0-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-1-step { + trips { + cpu6-1-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-2-step { + trips { + cpu7-0-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-3-step { + trips { + cpu7-1-config { + temperature = <115000>; + }; + }; + }; + + gpu-step { + trips { + gpu-trip { + temperature = <105000>; + }; + + gpu-cx-mon { + temperature = <110000>; + }; + }; + }; + + q6-hvx-step { + trips { + q6-hvx-trip1 { + temperature = <105000>; + }; + + q6-hvx-cx-mon { + temperature = <110000>; + }; + }; + }; + + mdm-core-step { + trips { + mdm-core-cx-mon { + temperature = <110000>; + }; + }; + }; + + camera-step { + trips { + camera-cx-mon { + temperature = <110000>; + }; + }; + }; + + wlan-step { + trips { + wlan-cx-mon { + temperature = <110000>; + }; + }; + }; + + display-step { + trips { + display-cx-mon { + temperature = <110000>; + }; + }; + }; + + video-step { + trips { + video-cx-mon { + temperature = <110000>; + }; + }; + }; +}; diff --git a/qcom/sa8155-pmic-overlay.dtsi b/qcom/sa8155-pmic-overlay.dtsi index 8fec3354..a4191ceb 100755 --- a/qcom/sa8155-pmic-overlay.dtsi +++ b/qcom/sa8155-pmic-overlay.dtsi @@ -15,6 +15,26 @@ pm8150_1_rtc: &pm8150_rtc { pm8150_1_gpios: &pm8150_gpios { }; +pm8150_1_vadc: &pm8150_vadc { + xo_therm { + reg = <ADC5_XO_THERM_100K_PU>; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <1>; + qcom,pre-scaling = <1 1>; + }; +}; + +pm8150_1_adc_tm: &pm8150_adc_tm { + io-channels = <&pm8150_1_vadc ADC5_XO_THERM_100K_PU>; + + xo_therm { + reg = <ADC5_XO_THERM_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <1>; + }; +}; + /* PM8150_2: */ &spmi_bus { #address-cells = <2>; @@ -90,6 +110,46 @@ pm8150_1_gpios: &pm8150_gpios { label = "die_temp"; qcom,pre-scaling = <1 1>; }; + + ufs_therm { + reg = <ADC5_XO_THERM_100K_PU>; + label = "ufs_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + soc_therm { + reg = <ADC5_AMUX_THM1_100K_PU>; + label = "soc_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + }; + + pm8150_2_adc_tm: adc_tm@3500 { + compatible = "qcom,adc-tm5"; + reg = <0x3500 0x100>; + interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "threshold"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + io-channels = <&pm8150_2_vadc ADC5_XO_THERM_100K_PU>, + <&pm8150_2_vadc ADC5_AMUX_THM1_100K_PU>; + + ufs_therm { + reg = <ADC5_XO_THERM_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + soc_therm { + reg = <ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; }; }; @@ -253,4 +313,46 @@ pm8150_1_gpios: &pm8150_gpios { }; }; }; + + xo-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_1_adc_tm ADC5_XO_THERM_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + ufs-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_2_adc_tm ADC5_XO_THERM_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + soc-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_2_adc_tm ADC5_AMUX_THM1_100K_PU>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; }; diff --git a/qcom/sa8155-v2.dtsi b/qcom/sa8155-v2.dtsi index 76d5a1b6..811ff357 100755 --- a/qcom/sa8155-v2.dtsi +++ b/qcom/sa8155-v2.dtsi @@ -257,88 +257,96 @@ /* GPU power level overrides */ &msm_gpu { + + /* Feature Id to get the SKU */ + qcom,feature-id = <0x4130 20 0xff>; + /delete-property/qcom,initial-pwrlevel; - qcom,initial-pwrlevel = <4>; /delete-node/qcom,gpu-pwrlevels; /delete-node/qcom,gpu-pwrlevel-bins; - qcom,gpu-pwrlevels { - compatible = "qcom,gpu-pwrlevels"; - #address-cells = <1>; - #size-cells = <0>; + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <700000000>; - qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>; - qcom,bus-freq = <10>; - qcom,bus-min = <8>; - qcom,bus-max = <11>; - }; + compatible="qcom,gpu-pwrlevel-bins"; + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <675000000>; - qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>; - qcom,bus-freq = <8>; - qcom,bus-min = <7>; - qcom,bus-max = <9>; - }; + qcom,speed-bin = <0>; + qcom,initial-pwrlevel = <4>; - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <585000000>; - qcom,level = <RPMH_REGULATOR_LEVEL_NOM>; - qcom,bus-freq = <7>; - qcom,bus-min = <6>; - qcom,bus-max = <11>; - }; + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <700000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>; + qcom,bus-freq = <10>; + qcom,bus-min = <8>; + qcom,bus-max = <11>; + }; - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <500000000>; - qcom,level = <RPMH_REGULATOR_LEVEL_NOM>; - qcom,bus-freq = <7>; - qcom,bus-min = <6>; - qcom,bus-max = <11>; - }; + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <675000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <427000000>; - qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>; - qcom,bus-freq = <6>; - qcom,bus-min = <5>; - qcom,bus-max = <9>; - }; + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <585000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_NOM>; + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <11>; + }; - /* Vote for SVS_L1 voltage for 345MHz instead of SVS */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <345000000>; - qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>; - qcom,bus-freq = <3>; - qcom,bus-min = <3>; - qcom,bus-max = <8>; - }; + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <500000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_NOM>; + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <11>; + }; - /* Vote for SVS_L1 voltage for 257MHz instead of LOW_SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <257000000>; - qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>; - qcom,bus-freq = <2>; - qcom,bus-min = <1>; - qcom,bus-max = <8>; + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <427000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + qcom,bus-freq = <6>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + }; }; - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <0>; - qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>; - qcom,bus-freq = <0>; - qcom,bus-min = <0>; - qcom,bus-max = <0>; + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <1>; + qcom,initial-pwrlevel = <1>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <500000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_NOM>; + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <427000000>; + qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + qcom,bus-freq = <6>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + }; }; }; }; diff --git a/qcom/sa8155-vm-la-mt.dtsi b/qcom/sa8155-vm-la-mt.dtsi index 1bce6154..a7d9ce57 100755 --- a/qcom/sa8155-vm-la-mt.dtsi +++ b/qcom/sa8155-vm-la-mt.dtsi @@ -12,14 +12,34 @@ compatible = "qcom,blkdev-rename"; actual-dev = "vda", "vdb", "vdc", "vdd", "vde", "vdf", - "vdg", "vdh", "vdj"; + "vdg", "vdh", "vdi"; rename-dev = "system", "userdata", "vendor", "persist", "modem", "bluetooth", "misc", "vbmeta"; - rename-dev-ab = "super", "userdata", "vbmeta_system_a", + rename-dev-ab = "super", "userdata", "metadata", "persist", "modem_a", "bluetooth_a", - "misc", "vbmeta_a", "metadata"; + "misc", "vbmeta_a", "vbmeta_b"; }; /delete-node/ cpus; }; + +&usb0 { + status = "ok"; +}; + +&usb2_phy0 { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; diff --git a/qcom/sa8155-vm-lv-mt.dtsi b/qcom/sa8155-vm-lv-mt.dtsi index 2ce638aa..8257a238 100755 --- a/qcom/sa8155-vm-lv-mt.dtsi +++ b/qcom/sa8155-vm-lv-mt.dtsi @@ -16,21 +16,21 @@ #include "display/quin-vm-display-lv.dtsi" &usb0 { - status = "ok"; + status = "disabled"; }; &usb2_phy0 { - status = "ok"; + status = "disabled"; }; &pcie0_msi { - status = "ok"; + status = "disabled"; }; &pcie0 { - status = "ok"; + status = "disabled"; }; &qupv3_se13_4uart { - status = "ok"; + status = "disabled"; }; diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 6006aa10..a409f1fb 100755 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -5,7 +5,7 @@ / { model = "Qualcomm Technologies, Inc. SA8155 Virtual Machine"; - qcom,msm-name = "SA8155 V2"; + qcom,msm-name = "SA8155"; qcom,msm-id = <362 0x20000>; aliases { diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index bd6b53a2..fe9921a6 100755 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -196,6 +196,30 @@ qcom,iommu-dma = "fastmap"; qcom,iommu-dma-addr-pool = <0x80000000 0x40000000>; }; + + rgmii-io-macro-info { + prg-rclk-dly = <1000>; + config-cdr-en = <1>; + mclk-gating-en = <1>; + cdr-fine-phase = <1>; + skip-calc-traffic = <1>; + data-divide-clk-sel = <1>; + loopback-en = <0>; + rx-prog-swap = <1>; + tx-clk-phase-shift-en = <1>; + + dll-clock-dis = <0>; + mclk-freq-calc = <0x1A>; + ddr-traffic-init-sel = <0>; + ddr-traffic-init-sw = <0>; + ddr-cal-en = <0>; + + tcx0-cycles-dly-line = <64>; + tcx0-cycles-cnt = <4>; + + test-ctl = <0xC1800000>; + usr-ctl = <0x2C010800>; + }; }; aop-set-ddr-freq { diff --git a/qcom/sa8195-ssc-qupv3.dtsi b/qcom/sa8195-ssc-qupv3.dtsi index 03788ace..7ebad580 100755 --- a/qcom/sa8195-ssc-qupv3.dtsi +++ b/qcom/sa8195-ssc-qupv3.dtsi @@ -8,6 +8,10 @@ qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-bus-ids = <MASTER_SENSORS_AHB SLAVE_EBI1>; + qcom,subsys-name = "slpi"; + clock-names = "corex", "core2x"; + clocks = <&scc SCC_QUPV3_CORE_CLK>, + <&scc SCC_QUPV3_2XCORE_CLK>; iommus = <&apps_smmu 0x4e3 0x0>; qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; qcom,iommu-dma = "fastmap"; diff --git a/qcom/sa8195-usb.dtsi b/qcom/sa8195-usb.dtsi index e0af3a9f..881bd846 100755 --- a/qcom/sa8195-usb.dtsi +++ b/qcom/sa8195-usb.dtsi @@ -57,6 +57,7 @@ snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; snps,is-utmi-l1-suspend; + snps,usb2-gadget-lpm-disable; maximum-speed = "high-speed"; dr_mode = "otg"; }; @@ -174,6 +175,7 @@ snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; snps,is-utmi-l1-suspend; + snps,usb2-gadget-lpm-disable; maximum-speed = "high-speed"; dr_mode = "otg"; }; @@ -248,7 +250,7 @@ dwc3@a400000 { compatible = "snps,dwc3"; - reg = <0x0a400000 0xcd00>; + reg = <0x0a400000 0xd941>; interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; usb-phy = <&usb2_phy2>, <&usb_qmp_phy0>, <&usb2_phy3>, <&usb_qmp_phy1>; @@ -261,7 +263,8 @@ snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; snps,dis_u3_susphy_quirk; - maximum-speed = "super-speed-plus"; + snps,force-gen1; + maximum-speed = "super-speed"; dr_mode = "host"; }; }; diff --git a/qcom/sa8195-vm-la-mt.dtsi b/qcom/sa8195-vm-la-mt.dtsi index d955fb2c..285c980c 100755 --- a/qcom/sa8195-vm-la-mt.dtsi +++ b/qcom/sa8195-vm-la-mt.dtsi @@ -12,13 +12,13 @@ compatible = "qcom,blkdev-rename"; actual-dev = "vda", "vdb", "vdc", "vdd", "vde", "vdf", - "vdg", "vdh", "vdj"; + "vdg", "vdh", "vdi"; rename-dev = "system", "userdata", "vendor", "persist", "modem", "bluetooth", "misc", "vbmeta"; - rename-dev-ab = "super", "userdata", "vbmeta_system_a", + rename-dev-ab = "super", "userdata", "metadata", "persist", "modem_a", "bluetooth_a", - "misc", "vbmeta_a", "metadata"; + "misc", "vbmeta_a", "vbmeta_b"; }; /delete-node/ cpus; diff --git a/qcom/sa8195-vm-lv-lxc.dtsi b/qcom/sa8195-vm-lv-lxc.dtsi index 63602523..dd186e6d 100755 --- a/qcom/sa8195-vm-lv-lxc.dtsi +++ b/qcom/sa8195-vm-lv-lxc.dtsi @@ -7,10 +7,26 @@ reg = <0x0 0xa0000000 0x0 0x20000000>; label = "pmem_shared_mem"; }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + no-map; + alignment = <0x0 0x400000>; + size = <0x0 0x0a000000>; + }; }; #include "display/quin-vm-display-lxc.dtsi" +&msm_ion { + qcom,ion-heap@10 { + reg = <ION_SECURE_DISPLAY_HEAP_ID>; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; +}; + &usb0 { status = "ok"; }; diff --git a/qcom/sa8195-vm-lv-mt.dtsi b/qcom/sa8195-vm-lv-mt.dtsi index de02b75a..52243be1 100755 --- a/qcom/sa8195-vm-lv-mt.dtsi +++ b/qcom/sa8195-vm-lv-mt.dtsi @@ -16,21 +16,21 @@ #include "display/quin-vm-display-lv.dtsi" &usb0 { - status = "ok"; + status = "disabled"; }; &usb2_phy0 { - status = "ok"; + status = "disabled"; }; &qupv3_se13_4uart { - status = "ok"; + status = "disabled"; }; &pcie0_msi { - status = "ok"; + status = "disabled"; }; &pcie0 { - status = "ok"; + status = "disabled"; }; diff --git a/qcom/sa8195-vm-lv.dtsi b/qcom/sa8195-vm-lv.dtsi index 59646d3c..ae5ad563 100755 --- a/qcom/sa8195-vm-lv.dtsi +++ b/qcom/sa8195-vm-lv.dtsi @@ -34,3 +34,7 @@ &pcie0 { status = "ok"; }; + +&cnss_pcie { + status = "disabled"; +}; diff --git a/qcom/sa8195p-adp-common.dtsi b/qcom/sa8195p-adp-common.dtsi index 83d57d15..9cf35272 100755 --- a/qcom/sa8195p-adp-common.dtsi +++ b/qcom/sa8195p-adp-common.dtsi @@ -209,5 +209,29 @@ status = "ok"; qcom,iommu-dma = "fastmap"; qcom,iommu-dma-addr-pool = <0x80000000 0x40000000>; }; + + rgmii-io-macro-info { + config-cdr-en = <1>; + mclk-gating-en = <1>; + cdr-fine-phase = <1>; + skip-calc-traffic = <1>; + data-divide-clk-sel = <1>; + prg-rclk-dly = <1000>; + loopback-en = <1>; + rx-prog-swap = <1>; + tx-clk-phase-shift-en = <1>; + + dll-clock-dis = <0>; + mclk-freq-calc = <0x1A>; + ddr-traffic-init-sel = <0>; + ddr-traffic-init-sw = <0>; + ddr-cal-en = <0>; + + tcx0-cycles-dly-line = <64>; + tcx0-cycles-cnt = <4>; + + test-ctl = <0xC1800000>; + usr-ctl = <0x2C010800>; + }; }; }; diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index 0c3a88a0..1745280e 100755 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -1125,7 +1125,7 @@ dcc: dcc_v2@1be2000 { regulator-min-microvolt = <528000>; regulator-max-microvolt = <1256000>; qcom,min-dropout-voltage = <75000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L2P: qcom,pm8008-l2@4100 { @@ -1134,7 +1134,7 @@ dcc: dcc_v2@1be2000 { regulator-min-microvolt = <528000>; regulator-max-microvolt = <1144000>; qcom,min-dropout-voltage = <187500>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L3P: qcom,pm8008-l3@4200 { @@ -1143,7 +1143,7 @@ dcc: dcc_v2@1be2000 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2896000>; qcom,min-dropout-voltage = <200000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L4P: qcom,pm8008-l4@4300 { @@ -1152,7 +1152,7 @@ dcc: dcc_v2@1be2000 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2896000>; qcom,min-dropout-voltage = <200000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L5P: qcom,pm8008-l5@4400 { @@ -1161,7 +1161,7 @@ dcc: dcc_v2@1be2000 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2896000>; qcom,min-dropout-voltage = <300000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L6P: qcom,pm8008-l6@4500 { @@ -1170,7 +1170,7 @@ dcc: dcc_v2@1be2000 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2896000>; qcom,min-dropout-voltage = <300000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; L7P: qcom,pm8008-l7@4600 { @@ -1179,7 +1179,7 @@ dcc: dcc_v2@1be2000 { regulator-min-microvolt = <1656000>; regulator-max-microvolt = <1896000>; qcom,min-dropout-voltage = <300000>; - qcom,hpm-min-load = <10000>; + qcom,hpm-min-load = <0>; }; }; }; diff --git a/qcom/sdmshrike-coresight.dtsi b/qcom/sdmshrike-coresight.dtsi index 5ae041ac..cce30d8e 100755 --- a/qcom/sdmshrike-coresight.dtsi +++ b/qcom/sdmshrike-coresight.dtsi @@ -1,4 +1,3 @@ - &soc { replicator_qdss: replicator@6046000 { compatible = "arm,coresight-dynamic-replicator", @@ -35,6 +34,7 @@ in-ports { port { replicator0_in_tmc_etf: endpoint { + slave-mode; remote-endpoint= <&tmc_etf_out_replicator0>; }; @@ -66,6 +66,7 @@ in-ports { port { replicator1_in_replicator0_out: endpoint { + slave-mode; remote-endpoint= <&replicator0_out_replicator1_in>; }; @@ -75,7 +76,7 @@ tmc_etr: tmc@6048000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb961>; + arm,primecell-periphid = <0x0003b961>; reg = <0x6048000 0x1000>, <0x6064000 0x15000>; @@ -105,6 +106,7 @@ in-ports { port { tmc_etr_in_replicator0: endpoint { + slave-mode; remote-endpoint = <&replicator0_out_tmc_etr>; }; }; @@ -113,7 +115,7 @@ tmc_etf: tmc@6047000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb961>; + arm,primecell-periphid = <0x0003b961>; reg = <0x6047000 0x1000>; reg-names = "tmc-base"; @@ -140,6 +142,7 @@ port { reg = <0>; tmc_etf_in_funnel_merg: endpoint { + slave-mode; remote-endpoint = <&funnel_merg_out_tmc_etf>; }; @@ -149,7 +152,7 @@ funnel_merg: funnel@6045000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb908>; + arm,primecell-periphid = <0x0003b908>; reg = <0x6045000 0x1000>; reg-names = "funnel-base"; @@ -176,6 +179,7 @@ port@0 { reg = <0>; funnel_merg_in_funnel_in0: endpoint { + slave-mode; remote-endpoint = <&funnel_in0_out_funnel_merg>; }; @@ -184,6 +188,7 @@ port@1 { reg = <1>; funnel_merg_in_funnel_in1: endpoint { + slave-mode; remote-endpoint = <&funnel_in1_out_funnel_merg>; }; @@ -220,7 +225,7 @@ funnel_in0: funnel@6041000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb908>; + arm,primecell-periphid = <0x0003b908>; reg = <0x6041000 0x1000>; reg-names = "funnel-base"; @@ -246,6 +251,7 @@ port@6 { reg = <6>; funnel_in0_in_funnel_qatb: endpoint { + slave-mode; remote-endpoint = <&funnel_qatb_out_funnel_in0>; }; @@ -254,6 +260,7 @@ port@7 { reg = <7>; funnel_in0_in_stm: endpoint { + slave-mode; remote-endpoint = <&stm_out_funnel_in0>; }; }; @@ -262,7 +269,7 @@ funnel_in1: funnel@0x6042000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb908>; + arm,primecell-periphid = <0x0003b908>; reg = <0x6042000 0x1000>; reg-names = "funnel-base"; @@ -289,6 +296,7 @@ port@0 { reg = <0>; funnel_in1_in_modem_etm0: endpoint { + slave-mode; remote-endpoint = <&modem_etm0_out_funnel_in1>; }; @@ -297,6 +305,7 @@ port@1 { reg = <1>; funnel_in1_in_replicator_swao: endpoint { + slave-mode; remote-endpoint = <&replicator_swao_out_funnel_in1>; }; @@ -305,6 +314,7 @@ port@4 { reg = <4>; funnel_in1_in_funnel_apss_merg: endpoint { + slave-mode; remote-endpoint = <&funnel_apss_merg_out_funnel_in1>; }; @@ -313,6 +323,7 @@ port@6 { reg = <6>; funnel_in1_in_tpda_modem: endpoint { + slave-mode; remote-endpoint = <&tpda_modem_in_tpdm_modem>; }; @@ -362,6 +373,7 @@ port@1 { reg = <0>; replicator_swao_in_tmc_etf_swao: endpoint { + slave-mode; remote-endpoint = <&tmc_etf_swao_out_replicator_swao>; }; @@ -378,6 +390,7 @@ in-ports { port { dummy_eud_in_replicator_swao: endpoint { + slave-mode; remote-endpoint = <&replicator_swao_out_eud>; }; @@ -411,6 +424,7 @@ port { reg = <0>; tmc_etf_swao_in_funnel_swao: endpoint { + slave-mode; remote-endpoint= <&funnel_swao_out_tmc_etf_swao>; }; @@ -420,7 +434,7 @@ funnel_swao:funnel@6b08000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb908>; + arm,primecell-periphid = <0x0003b908>; reg = <0x6b08000 0x1000>; reg-names = "funnel-base"; @@ -448,6 +462,7 @@ port@0 { reg = <5>; funnel_swao_in_ssc_etm0: endpoint { + slave-mode; remote-endpoint= <&ssc_etm0_out_funnel_swao>; }; @@ -456,6 +471,7 @@ port@1 { reg = <6>; funnel_swao_in_replicator1_out: endpoint { + slave-mode; remote-endpoint= <&replicator1_out_funnel_swao>; }; @@ -464,6 +480,7 @@ port@2 { reg = <7>; funnel_swao_in_tpda_swao: endpoint { + slave-mode; remote-endpoint= <&tpda_swao_out_funnel_swao>; }; @@ -505,6 +522,7 @@ port@0 { reg = <0>; tpda_swao_in_tpdm_swao0: endpoint { + slave-mode; remote-endpoint = <&tpdm_swao0_out_tpda_swao>; }; @@ -513,6 +531,7 @@ port@1 { reg = <1>; tpda_swao_in_tpdm_swao1: endpoint { + slave-mode; remote-endpoint = <&tpdm_swao1_out_tpda_swao>; }; @@ -604,6 +623,7 @@ in-ports { port { tpda_modem_in_tpdm_modem: endpoint { + slave-mode; remote-endpoint = <&tpdm_modem_out_tpda_modem>; }; @@ -647,7 +667,7 @@ funnel_dl_mm: funnel@6c0b000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb908>; + arm,primecell-periphid = <0x0003b908>; reg = <0x6c0b000 0x1000>; reg-names = "funnel-base"; @@ -673,6 +693,7 @@ port { reg = <0>; funnel_dl_mm_in_tpdm_qm: endpoint { + slave-mode; remote-endpoint = <&tpdm_qm_out_funnel_dl_mm>; }; @@ -702,10 +723,10 @@ funnel_dl_mm1: funnel_1@6c0b000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb908>; + arm,primecell-periphid = <0x0003b908>; - reg = <0x6c0c000 0x1000>, - <0x6c0b000 0x1000>; + reg = <0x6867000 0x10>, + <0x6c0b000 0x1000>; reg-names = "funnel-base-dummy", "funnel-base-real"; coresight-name = "coresight-funnel-dl-mm1"; @@ -732,6 +753,7 @@ port { reg = <1>; funnel_dl_mm1_in_tpdm_mm: endpoint { + slave-mode; remote-endpoint = <&tpdm_mm_out_funnel_dl_mm1>; }; @@ -741,7 +763,7 @@ tpdm_mm: tpdm@6c08000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb968>; + arm,primecell-periphid = <0x0003b968>; reg = <0x6c08000 0x1000>; reg-names = "tpdm-base"; @@ -763,7 +785,7 @@ funnel_turing: funnel@6861000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb908>; + arm,primecell-periphid = <0x0003b908>; reg = <0x6861000 0x1000>; reg-names = "funnel-base"; @@ -790,6 +812,7 @@ port { reg = <0>; funnel_turing_in_tpdm_turing: endpoint { + slave-mode; remote-endpoint = <&tpdm_turing_out_funnel_turing>; }; @@ -820,12 +843,12 @@ }; }; - funnel_turing_1: funnel_1@6862000 { + funnel_turing_1: funnel_1@6861000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb908>; + arm,primecell-periphid = <0x0003b908>; - reg = <0x6862000 0x10>, - <0x6861000 0x1000>; + reg = <0x6867010 0x10>, + <0x6861000 0x1000>; reg-names = "funnel-base-dummy", "funnel-base-real"; coresight-name = "coresight-funnel-turing-1"; @@ -852,6 +875,7 @@ port { reg = <1>; funnel_turing_1_in_turing_etm0: endpoint { + slave-mode; remote-endpoint = <&turing_etm0_out_funnel_turing_1>; }; @@ -877,7 +901,7 @@ funnel_apss_merg: funnel@7810000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb908>; + arm,primecell-periphid = <0x0003b908>; reg = <0x7810000 0x1000>; reg-names = "funnel-base"; @@ -889,6 +913,7 @@ out-ports { port { + reg = <0>; funnel_apss_merg_out_funnel_in1: endpoint { remote-endpoint = <&funnel_in1_in_funnel_apss_merg>; @@ -903,6 +928,7 @@ port@0 { reg = <0>; funnel_apss_merg_in_funnel_apss: endpoint { + slave-mode; remote-endpoint = <&funnel_apss_out_funnel_apss_merg>; }; @@ -911,6 +937,7 @@ port@1 { reg = <2>; funnel_apss_merg_in_tpda_olc: endpoint { + slave-mode; remote-endpoint = <&tpda_olc_out_funnel_apss_merg>; }; @@ -919,6 +946,7 @@ port@2 { reg = <3>; funnel_apss_merg_in_tpda_llm_silver: endpoint { + slave-mode; remote-endpoint = <&tpda_llm_silver_out_funnel_apss_merg>; }; @@ -927,6 +955,7 @@ port@3 { reg = <4>; funnel_apss_merg_in_tpda_llm_gold: endpoint { + slave-mode; remote-endpoint = <&tpda_llm_gold_out_funnel_apss_merg>; }; @@ -935,6 +964,7 @@ port@4 { reg = <5>; funnel_apss_merg_in_tpda_apss: endpoint { + slave-mode; remote-endpoint = <&tpda_apss_out_funnel_apss_merg>; }; @@ -970,6 +1000,7 @@ port { reg = <0>; tpda_olc_in_tpdm_olc: endpoint { + slave-mode; remote-endpoint = <&tpdm_olc_out_tpda_olc>; }; @@ -1025,6 +1056,7 @@ port { reg = <0>; tpda_apss_in_tpdm_apss: endpoint { + slave-mode; remote-endpoint = <&tpdm_apss_out_tpda_apss>; }; @@ -1083,6 +1115,7 @@ port { reg = <0>; tpda_llm_silver_in_tpdm_llm_silver: endpoint { + slave-mode; remote-endpoint = <&tpdm_llm_silver_out_tpda_llm_silver>; }; @@ -1142,6 +1175,7 @@ port { reg = <0>; tpda_llm_gold_in_tpdm_llm_gold: endpoint { + slave-mode; remote-endpoint = <&tpdm_llm_gold_out_tpda_llm_gold>; }; @@ -1172,7 +1206,7 @@ funnel_apss: funnel@7800000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb908>; + arm,primecell-periphid = <0x0003b908>; reg = <0x7800000 0x1000>; reg-names = "funnel-base"; @@ -1197,6 +1231,7 @@ port@0 { reg = <0>; funnel_apss_in_etm0: endpoint { + slave-mode; remote-endpoint = <&etm0_out_funnel_apss>; }; @@ -1205,6 +1240,7 @@ port@1 { reg = <1>; funnel_apss_in_etm1: endpoint { + slave-mode; remote-endpoint = <&etm1_out_funnel_apss>; }; @@ -1213,6 +1249,7 @@ port@2 { reg = <2>; funnel_apss_in_etm2: endpoint { + slave-mode; remote-endpoint = <&etm2_out_funnel_apss>; }; @@ -1221,6 +1258,7 @@ port@3 { reg = <3>; funnel_apss_in_etm3: endpoint { + slave-mode; remote-endpoint = <&etm3_out_funnel_apss>; }; @@ -1229,6 +1267,7 @@ port@4 { reg = <4>; funnel_apss_in_etm4: endpoint { + slave-mode; remote-endpoint = <&etm4_out_funnel_apss>; }; @@ -1237,6 +1276,7 @@ port@5 { reg = <5>; funnel_apss_in_etm5: endpoint { + slave-mode; remote-endpoint = <&etm5_out_funnel_apss>; }; @@ -1245,6 +1285,7 @@ port@6 { reg = <6>; funnel_apss_in_etm6: endpoint { + slave-mode; remote-endpoint = <&etm6_out_funnel_apss>; }; @@ -1253,6 +1294,7 @@ port@7 { reg = <7>; funnel_apss_in_etm7: endpoint { + slave-mode; remote-endpoint = <&etm7_out_funnel_apss>; }; @@ -1835,7 +1877,6 @@ reg-names = "cti-base"; coresight-name = "coresight-cti-titan"; - status = "disabled"; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; @@ -1848,7 +1889,6 @@ reg-names = "cti-base"; coresight-name = "coresight-cti-venus-arm9"; - status = "disabled"; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; @@ -2022,7 +2062,7 @@ funnel_qatb: funnel@6005000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb908>; + arm,primecell-periphid = <0x0003b908>; reg = <0x6005000 0x1000>; reg-names = "funnel-base"; @@ -2050,14 +2090,16 @@ port@0 { reg = <0>; funnel_qatb_in_tpda: endpoint { + slave-mode; remote-endpoint = <&tpda_out_funnel_qatb>; }; }; port@1 { - reg = <7>; + reg = <5>; funnel_qatb_in_funnel_turing_1: endpoint { + slave-mode; remote-endpoint = <&funnel_turing_1_out_funnel_qatb>; }; @@ -2066,6 +2108,7 @@ port@2 { reg = <6>; funnel_qatb_in_funnel_lpass_1: endpoint { + slave-mode; remote-endpoint = <&funnel_lpass_1_out_funnel_qatb>; }; @@ -2116,6 +2159,7 @@ port@1 { reg = <0>; tpda_in_funnel_dl_mm: endpoint { + slave-mode; remote-endpoint = <&funnel_dl_mm_out_tpda>; }; @@ -2124,6 +2168,7 @@ port@2 { reg = <1>; tpda_in_funnel_dl_mm1: endpoint { + slave-mode; remote-endpoint = <&funnel_dl_mm1_out_tpda>; }; @@ -2132,6 +2177,7 @@ port@3 { reg = <2>; tpda_in_tpdm_center: endpoint { + slave-mode; remote-endpoint = <&tpdm_center_out_tpda>; }; @@ -2141,6 +2187,7 @@ port@5 { reg = <5>; tpda_in_funnel_ddr_0: endpoint { + slave-mode; remote-endpoint = <&funnel_ddr_0_out_tpda>; }; @@ -2149,6 +2196,7 @@ port@6 { reg = <8>; tpda_in_funnel_dl_south: endpoint { + slave-mode; remote-endpoint = <&funnel_dl_south_out_tpda>; }; @@ -2157,6 +2205,7 @@ port@7 { reg = <9>; tpda_in_funnel_lpass: endpoint { + slave-mode; remote-endpoint = <&funnel_lpass_out_tpda>; }; @@ -2165,6 +2214,7 @@ port@8 { reg = <10>; tpda_in_funnel_turing: endpoint { + slave-mode; remote-endpoint = <&funnel_turing_out_tpda>; }; @@ -2174,6 +2224,7 @@ port@9 { reg = <11>; tpda_in_tpdm_vsense: endpoint { + slave-mode; remote-endpoint = <&tpdm_vsense_out_tpda>; }; @@ -2182,6 +2233,7 @@ port@10 { reg = <13>; tpda_in_tpdm_prng: endpoint { + slave-mode; remote-endpoint = <&tpdm_prng_out_tpda>; }; @@ -2190,6 +2242,7 @@ port@11 { reg = <16>; tpda_in_tpdm_pimem: endpoint { + slave-mode; remote-endpoint = <&tpdm_pimem_out_tpda>; }; @@ -2199,7 +2252,7 @@ funnel_lpass: funnel@6846000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb908>; + arm,primecell-periphid = <0x0003b908>; reg = <0x6846000 0x1000>; reg-names = "funnel-base"; @@ -2222,6 +2275,7 @@ in-ports { port { funnel_lpass_in_tpdm_lpass: endpoint { + slave-mode; remote-endpoint = <&tpdm_lpass_out_funnel_lpass>; }; @@ -2253,10 +2307,10 @@ funnel_lpass_1: funnel_1@6846000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb908>; + arm,primecell-periphid = <0x0003b908>; - reg = <0x6847000 0x1000>, - <0x6846000 0x1000>; + reg = <0x6867020 0x10>, + <0x6846000 0x1000>; reg-names = "funnel-base-dummy", "funnel-base-real"; coresight-name = "coresight-funnel-lpass-1"; @@ -2279,6 +2333,7 @@ in-ports { port { funnel_lpass_1_in_audio_etm0: endpoint { + slave-mode; remote-endpoint = <&audio_etm0_out_funnel_lpass_1>; }; @@ -2304,7 +2359,7 @@ funnel_dl_south: funnel@69c2000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb908>; + arm,primecell-periphid = <0x0003b908>; reg = <0x69c2000 0x1000>; reg-names = "funnel-base"; @@ -2330,6 +2385,7 @@ port@0 { reg = <1>; funnel_dl_south_in_tpdm_dl_south: endpoint { + slave-mode; remote-endpoint = <&tpdm_dl_south_out_funnel_dl_south>; }; @@ -2338,6 +2394,7 @@ port@1 { reg = <3>; funnel_dl_south_in_funnel_wcss: endpoint { + slave-mode; remote-endpoint = <&funnel_wcss_out_funnel_dl_south>; }; @@ -2368,7 +2425,7 @@ funnel_wcss: funnel@6ac2000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb908>; + arm,primecell-periphid = <0x0003b908>; reg = <0x6ac2000 0x1000>; reg-names = "funnel-base"; @@ -2390,6 +2447,7 @@ in-ports { port { funnel_wcss_in_tpdm_wcss: endpoint { + slave-mode; remote-endpoint = <&tpdm_wcss_out_funnel_wcss>; }; @@ -2414,7 +2472,7 @@ funnel_ddr_0: funnel@6a05000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb908>; + arm,primecell-periphid = <0x0003b908>; reg = <0x6a05000 0x1000>; reg-names = "funnel-base"; @@ -2436,6 +2494,7 @@ in-ports { port { funnel_ddr_0_in_tpdm_ddr: endpoint { + slave-mode; remote-endpoint = <&tpdm_ddr_out_funnel_ddr_0>; }; @@ -2450,7 +2509,6 @@ reg-names = "tpdm-base"; coresight-name = "coresight-tpdm-ddr"; - status = "disabled"; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; @@ -2515,10 +2573,10 @@ reg-names = "tpdm-base"; coresight-name = "coresight-tpdm-vsense"; - status = "disabled"; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; + out-ports { port { tpdm_vsense_out_tpda: endpoint { @@ -2549,7 +2607,7 @@ stm: stm@6002000 { compatible = "arm,primecell"; - arm,primecell-periphid = <0x000bb962>; + arm,primecell-periphid = <0x0003b962>; reg = <0x6002000 0x1000>, <0x16280000 0x180000>, diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 24c2b86a..470a6f07 100755 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -12,6 +12,7 @@ #include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,scshrike.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/qcom,dcc_v2.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h> #include <dt-bindings/spmi/spmi.h> @@ -599,6 +600,15 @@ }; }; + dcc: dcc_v2@010a2000 { + compatible = "qcom,dcc-v2"; + reg = <0x10a2000 0x1000>, + <0x10ac000 0x4000>; + reg-names = "dcc-base", "dcc-ram-base"; + + dcc-ram-offset = <0xC000>; + }; + llcc_pmu: llcc-pmu@90cc000 { compatible = "qcom,llcc-pmu-ver2"; reg = <0x090cc000 0x300>, <0x09648000 0x200>; @@ -874,6 +884,46 @@ compatible = "qcom,mem-dump"; memory-region = <&dump_mem>; + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c200_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c300_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c400_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c500_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c600_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c700_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + rpmh { qcom,dump-size = <0x2000000>; qcom,dump-id = <0xec>; diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index 38cdf380..fc447a1f 100755 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -33,11 +33,11 @@ regulator-enable-ramp-delay = <2400>; }; - ioss_qps615_rx: qps615_rx@eth { + ioss_aqr_rx: qps615_rx@eth { qcom,dir-rx; qcom,rx-filter-ip; - qcom,ring-size = <128>; + qcom,ring-size = <1023>; qcom,buff-size = <2048>; qcom,mod-count-min = <64>; @@ -46,9 +46,33 @@ qcom,mod-usecs-max = <60>; }; - ioss_qps615_tx: qps615_tx@eth { + ioss_aqr_tx: qps615_tx@eth { qcom,dir-tx; - qcom,ring-size = <512>; + qcom,ring-size = <1023>; + qcom,buff-size = <2048>; + + qcom,mod-count-min = <64>; + qcom,mod-count-max = <64>; + qcom,mod-usecs-min = <30>; + qcom,mod-usecs-max = <60>; + }; + + ioss_napa_rx: qps615_rx@eth { + qcom,dir-rx; + qcom,rx-filter-ip; + + qcom,ring-size = <127>; + qcom,buff-size = <2048>; + + qcom,mod-count-min = <64>; + qcom,mod-count-max = <64>; + qcom,mod-usecs-min = <30>; + qcom,mod-usecs-max = <60>; + }; + + ioss_napa_tx: qps615_tx@eth { + qcom,dir-tx; + qcom,ring-size = <511>; qcom,buff-size = <2048>; qcom,mod-count-min = <64>; @@ -62,17 +86,17 @@ qcom,ioss_instance = <0>; qcom,ioss_channels = - <&ioss_qps615_rx>, - <&ioss_qps615_tx>; + <&ioss_aqr_rx>, + <&ioss_aqr_tx>; }; ioss_qps615_eth1: qps615@eth1 { qcom,name = "eth1"; - qcom,ioss_instance = <0>; + qcom,ioss_instance = <1>; qcom,ioss_channels = - <&ioss_qps615_rx>, - <&ioss_qps615_tx>; + <&ioss_napa_rx>, + <&ioss_napa_tx>; }; }; @@ -86,6 +110,15 @@ ep-reset-reg = <0x801210>; ep-reset-gpio-mask = <0xf>; dump-regs = <0x801330 0x801350 0x801370>; + reg_update = <0x82c030 0x1 + 0x828000 0x3 + 0x82bd00 0x8 + 0x82c030 0x2 + 0x828000 0x3 + 0x82bd00 0x8 + 0x82c030 0x8 + 0x828000 0x1 + 0x82bd00 0x8>; }; }; @@ -166,7 +199,7 @@ qcom,ioss_interfaces = <&ioss_qps615_eth1>; /* ipa shares this group */ - qcom,iommu-group = <&ipa_eth_group1>; + qcom,iommu-group = <&ipa_eth_group2>; #address-cells = <1>; #size-cells = <1>; diff --git a/qcom/sdxlemur-mtp-mbb-emmc.dtsi b/qcom/sdxlemur-mtp-mbb-emmc.dtsi index 8cb25786..ea6d71dc 100755 --- a/qcom/sdxlemur-mtp-mbb-emmc.dtsi +++ b/qcom/sdxlemur-mtp-mbb-emmc.dtsi @@ -14,7 +14,6 @@ reg = <0x08804000 0x1000>, <0x08805000 0x1000>; reg-names = "hc_mem", "cqhci_mem"; - qcom,restore-after-cx-collapse; mmc-ddr-1_8v; mmc-hs200-1_8v; diff --git a/qcom/sdxlemur-v2.dtsi b/qcom/sdxlemur-v2.dtsi index 3740fd2d..43abbcc5 100755 --- a/qcom/sdxlemur-v2.dtsi +++ b/qcom/sdxlemur-v2.dtsi @@ -150,6 +150,14 @@ qcom,iommu-dma = "fastmap"; }; +&apsscc { + qcom,speed0-bin-v0 = + < 345600000 RPMH_REGULATOR_LEVEL_LOW_SVS>, + < 576000000 RPMH_REGULATOR_LEVEL_SVS>, + < 1094400000 RPMH_REGULATOR_LEVEL_NOM>, + < 1804800000 RPMH_REGULATOR_LEVEL_TURBO>; +}; + &cpufreq { qcom,cpufreq-table = < 345600 >, diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 54e53dbd..96cb90e6 100755 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -579,6 +579,7 @@ clock-names = "core", "iface"; bus-width = <4>; + qcom,restore-after-cx-collapse; /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */ qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; @@ -1178,6 +1179,7 @@ qcom,ipa-hw-mode = <0>; qcom,platform-type = <0>; /* MDM platform */ qcom,ee = <0>; + qcom,entire-ipa-block-size = <0x200000>; qcom,use-ipa-tethering-bridge; qcom,use-tput-estmation-pipe; qcom,mhi-event-ring-id-limits = <9 15>; /* start and end */ @@ -1195,6 +1197,9 @@ qcom,ipa-holb-monitor-poll-period = <5>; qcom,ipa-holb-monitor-max-cnt-wlan = <10>; qcom,ipa-holb-monitor-max-cnt-usb = <10>; + qcom,register-collection-on-crash; + qcom,testbus-collection-on-crash; + qcom,non-tn-collection-on-crash; qcom,lan-rx-napi; clock-names = "core_clk"; clocks = <&rpmhcc RPMH_IPA_CLK>; diff --git a/qcom/slate.dtsi b/qcom/slate.dtsi index f477d272..d621f8ff 100755 --- a/qcom/slate.dtsi +++ b/qcom/slate.dtsi @@ -27,6 +27,19 @@ compatible = "qcom,slate-daemon"; }; + qcom,audio-cc-ipc-platform { + compatible = "qcom,audio-cc-ipc-platform"; + cc_codec: qcom,cc-codec { + compatible = "qcom,cc-codec"; + qcom,service-id = <3>; + qcom,channel-name = "custom_cc_apps"; + qcom,src-domain-id = <3>; + qcom,dst-domain-id = <6>; + qcom,src-port = <3>; + qcom,dst-port = <0x0F>; + }; + }; + qcom,glink-slatecom-xprt-slate { compatible = "qcom,glink-slatecom-xprt"; label = "slate"; @@ -41,6 +54,11 @@ qcom,intents = <0x0C 1>; }; + qcom,glink-slate-rsb { + qcom,glink-channels = "slate-rsb-ctl"; + qcom,intents = <0x0C 1>; + }; + qcom,glinkpkt-slate-ssc-hal { qcom,glink-channels = "ssc_hal"; qcom,intents = <0x2710 2 @@ -179,16 +197,6 @@ qcom,intents = <0x2000 2>; reg = <GPR_DOMAIN_CC_DSP>; cdev_name = "nongpr_channel"; - - cc_codec: qcom,cc-codec { - compatible = "qcom,cc-codec"; - qcom,service-id = <3>; - qcom,channel-name = "custom_cc_apps"; - qcom,src-domain-id = <3>; - qcom,dst-domain-id = <6>; - qcom,src-port = <3>; - qcom,dst-port = <0x0F>; - }; }; }; @@ -219,7 +227,7 @@ qcom,slatersb-rpmsg { compatible = "qcom,slatersb-rpmsg"; - qcom,glink-channels = "RSB_CTRL"; + qcom,glink-channels = "slate-rsb-ctl"; qcom,glinkpkt-edge = "slate"; intents = <0x200 1>; }; diff --git a/qcom/sm6150-ssc-qupv3.dtsi b/qcom/sm6150-ssc-qupv3.dtsi index 1395eb41..139e6b21 100755 --- a/qcom/sm6150-ssc-qupv3.dtsi +++ b/qcom/sm6150-ssc-qupv3.dtsi @@ -10,6 +10,10 @@ qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-bus-ids = <MASTER_LPASS_ANOC SLAVE_EBI1>; + qcom,subsys-name = "adsp"; + clock-names = "corex", "core2x"; + clocks = <&scc SCC_QUPV3_CORE_CLK>, + <&scc SCC_QUPV3_2XCORE_CLK>; iommus = <&apps_smmu 0x1783 0x0>; qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; diff --git a/qcom/sm6150-usb.dtsi b/qcom/sm6150-usb.dtsi index 471a6f58..d6fb911f 100755 --- a/qcom/sm6150-usb.dtsi +++ b/qcom/sm6150-usb.dtsi @@ -62,6 +62,7 @@ snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; snps,is-utmi-l1-suspend; + snps,usb2-gadget-lpm-disable; snps,usb3_lpm_capable; maximum-speed = "super-speed"; dr_mode = "otg"; @@ -344,6 +345,7 @@ snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; snps,is-utmi-l1-suspend; + snps,usb2-gadget-lpm-disable; maximum-speed = "high-speed"; dr_mode = "otg"; }; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 73413982..a132a473 100755 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -847,7 +847,7 @@ clock-output-names = "scc_pll_out_aux"; clocks = <&scc_pll>; clock-mult = <1>; - clock-div = <2>; + clock-div = <3>; #clock-cells = <0>; }; }; @@ -948,6 +948,46 @@ compatible = "qcom,mem-dump"; memory-region = <&dump_mem>; + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c200_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c300_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c400_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c500_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c600_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c700_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + rpmh { qcom,dump-size = <0x2000000>; qcom,dump-id = <0xec>; @@ -1538,9 +1578,6 @@ status = "disabled"; }; - thermal_zones: thermal-zones { - }; - ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000>, @@ -2063,6 +2100,11 @@ }; }; + qcom,hlos_sleep_state { + compatible = "qcom,smp2p-hlos_sleep_state"; + qcom,smem-states = <&hlos_sleep_state_out 0>; + }; + qcom,smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; @@ -2102,6 +2144,11 @@ interrupt-controller; #interrupt-cells = <2>; }; + + hlos_sleep_state_out: hlos_sleep_state-out { + qcom,entry-name = "hlos_sleep_state"; + #qcom,smem-state-cells = <1>; + }; }; qcom,smp2p-cdsp { diff --git a/qcom/sm8150-ssc-qupv3.dtsi b/qcom/sm8150-ssc-qupv3.dtsi index 17308b8b..69a6698c 100755 --- a/qcom/sm8150-ssc-qupv3.dtsi +++ b/qcom/sm8150-ssc-qupv3.dtsi @@ -10,6 +10,10 @@ qcom,msm-bus,vectors-bus-ids = <MASTER_SENSORS_AHB SLAVE_EBI1>; iommus = <&apps_smmu 0x4e3 0x0>; + qcom,subsys-name = "slpi"; + clock-names = "corex", "core2x"; + clocks = <&scc SCC_QUPV3_CORE_CLK>, + <&scc SCC_QUPV3_2XCORE_CLK>; qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; qcom,iommu-dma = "fastmap"; status = "disabled"; diff --git a/qcom/sm8150-usb.dtsi b/qcom/sm8150-usb.dtsi index 811be8a1..2288de1a 100755 --- a/qcom/sm8150-usb.dtsi +++ b/qcom/sm8150-usb.dtsi @@ -61,6 +61,7 @@ snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; snps,is-utmi-l1-suspend; + snps,usb2-gadget-lpm-disable; maximum-speed = "high-speed"; dr_mode = "otg"; }; @@ -167,7 +168,7 @@ dwc3@a800000 { compatible = "snps,dwc3"; - reg = <0x0a800000 0xcd00>; + reg = <0x0a800000 0xd941>; interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; usb-phy = <&usb2_phy1>, <&usb_qmp_phy>; linux,sysdev_is_parent; @@ -176,11 +177,13 @@ snps,hird-threshold = /bits/ 8 <0x0>; snps,ssp-u3-u0-quirk; snps,is-utmi-l1-suspend; + snps,usb2-gadget-lpm-disable; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; snps,dis_u3_susphy_quirk; + snps,force-gen1; tx-fifo-resize; - maximum-speed = "super-speed-plus"; + maximum-speed = "super-speed"; dr_mode = "otg"; }; }; |