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| author | QC Publisher <qcpublisher@qti.qualcomm.com> | 2023-04-28 04:07:36 -0700 |
|---|---|---|
| committer | Daniel Price <danielprice@google.com> | 2023-05-01 20:29:45 +0000 |
| commit | 2f02eb8c808e7a89e7f88651228ddad13b616d0a (patch) | |
| tree | ae90f12a4f0eaf076a610ddebf81ca00a2285786 | |
| parent | 94f4a4876813f7ba58f764866f9e3705527601d4 (diff) | |
| download | devicetree-2f02eb8c808e7a89e7f88651228ddad13b616d0a.tar.gz | |
Commit label r00078.3a - ES6 0.0.078.3a
TRACKING-ID:002deea6-3cac-4530-9032-57124bf93566
144 files changed, 7862 insertions, 304 deletions
diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 5aa5cebd..d2b9a021 100755 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -134,6 +134,9 @@ SoCs: - MONACO_AUTO compatible = "qcom,monaco_auto" +- TRINKET + compatible = "qcom,trinket", "qcom,trinket-iot" + Generic board variants: - CDP device: @@ -376,3 +379,7 @@ compatible = "qcom,lemans-adas-high-qam-star" compatible = "qcom,lemans-ivi-adas-adp-star" compatible = "qcom,lemans-ivi-adas-qam-star" compatible = "qcom,monaco_auto-rumi" +compatible = "qcom,trinket-iot" +compatible = "qcom,trinketp-iot" +compatible = "qcom,trinket-iot-idp" +compatible = "qcom,trinketp-iot-idp" diff --git a/bindings/clock/qcom,cmn-blk-pll.txt b/bindings/clock/qcom,cmn-blk-pll.txt new file mode 100755 index 00000000..ae6ae72b --- /dev/null +++ b/bindings/clock/qcom,cmn-blk-pll.txt @@ -0,0 +1,26 @@ +Qualcomm Technologies, Inc. Common Block PLL Controller Binding +--------------------------------------------------------------- + +Required properties : +- compatible : shall contain only the following: + "qcom,cmn_blk_pll" + +- reg : shall contain base register location and size. +- reg-names : "cmn_blk". +- clock-names : Shall contain "misc_reset", "ahb_clk", "aon_clk". +- clocks : phandle + clock reference to misc_reset, ahb and aon clock. +- #clock-cells : shall contain 1. + +Example : + clock_cmn_blk_pll@2f780 { + compatible = "qcom,cmn_blk_pll"; + reg = <0x2f780 0x4>; + reg-names = "cmn_blk"; + clocks = <&clock_gcc GCC_BIAS_PLL_MISC_RESET_CLK>, + <&clock_gcc GCC_BIAS_PLL_AHB_CLK>, + <&clock_gcc GCC_BIAS_PLL_AON_CLK>; + clock-names = "misc_reset_clk", "ahb_clk", "aon_clk"; + resets = <&clock_gcc GCC_BIAS_PLL_BCR>; + reset-names = "cmn_blk_pll_reset"; + #clock-cells = <1>; + }; diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt index 61e8d7e3..e327e7ef 100755 --- a/bindings/clock/qcom,debugcc.txt +++ b/bindings/clock/qcom,debugcc.txt @@ -23,6 +23,7 @@ Required properties : "qcom,lemans-debugcc" "qcom,sa410m-debugcc" "qcom,sm8250-debugcc" + "qcom,qcs404-debugcc" - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. diff --git a/bindings/crypto/msm/ice.txt b/bindings/crypto/msm/ice.txt deleted file mode 100755 index acafaebd..00000000 --- a/bindings/crypto/msm/ice.txt +++ /dev/null @@ -1,51 +0,0 @@ -* Inline Crypto Engine (ICE) - -Required properties: - - compatible : should be "qcom,ice" - - reg : <register mapping> - -Optional properties: - - interrupt-names : name describing the interrupts for ICE IRQ - - interrupts : <interrupt mapping for ICE IRQ> - - qcom,enable-ice-clk : should enable clocks for ICE HW - - clocks : List of phandle and clock specifier pairs - - clock-names : List of clock input name strings sorted in the same - order as the clocks property. - - qocm,op-freq-hz : max clock speed sorted in the same order as the clocks - property. - - qcom,instance-type : describe the storage type for which ICE node is defined - currently, only "ufs" and "sdcc" are supported storage type - - vdd-hba-supply : regulated supply to be used by ICE HW - - qcom,bus-vector-names : bus vectors mapping - -Example: - ufs_ice: ufsice@630000 { - compatible = "qcom,ice"; - reg = <0x630000 0x8000>; - interrupt-names = "ufs_ice_nonsec_level_irq", "ufs_ice_sec_level_irq"; - interrupts = <0 258 0>, <0 257 0>; - qcom,enable-ice-clk; - clock-names = "ice_core_clk_src", "ice_core_clk"; - clocks = <&clock_gcc clk_ufs_ice_core_clk_src>, - <&clock_gcc clk_gcc_ufs_ice_core_clk>; - qcom,op-freq-hz = <300000000>, <0>; - qcom,instance-type = "ufs"; - status = "disabled"; - }; - - ufs_card_ice: ufscardice@1db0000 { - compatible = "qcom,ice_card"; - reg = <0x1db0000 0x8000>; - qcom,enable-ice-clk; - clock-names = "ufs_core_clk", "bus_clk", - "iface_clk", "ice_core_clk"; - clocks = <&clock_gcc GCC_UFS_CARD_AXI_CLK>, - <&clock_gcc GCC_UFS_CARD_CLKREF_CLK>, - <&clock_gcc GCC_UFS_CARD_AHB_CLK>, - <&clock_gcc GCC_UFS_CARD_ICE_CORE_CLK>; - qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; - vdd-hba-supply = <&ufs_card_gdsc>; - qcom,bus-vector-names = "MIN", - "MAX"; - qcom,instance-type = "ufs_card"; - }; diff --git a/bindings/iio/adc/aks,ti-ads1015.yaml b/bindings/iio/adc/aks,ti-ads1015.yaml new file mode 100755 index 00000000..9ed335ee --- /dev/null +++ b/bindings/iio/adc/aks,ti-ads1015.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/aks,ti-ads1015.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI ADS1015 4 channel I2C analog to digital converter for AKSys joystick scenario, And this file's original contents comes from ti,ads1015.yaml + +maintainers: + - Daniel <daniel@aksys.co.kr> + +description: | + Datasheet at: https://www.ti.com/lit/gpn/ads1015 + Supports both single ended and differential channels. + +properties: + compatible: + const: aks,ti-ads1015 + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "#io-channel-cells": + const: 1 + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +patternProperties: + "^channel@[0-7]+$": + type: object + description: + Child nodes needed for each channel that the platform uses. + + properties: + reg: + description: | + 0: Voltage over AIN0 and AIN1. + 1: Voltage over AIN0 and AIN3. + 2: Voltage over AIN1 and AIN3. + 3: Voltage over AIN2 and AIN3. + 4: Voltage over AIN0 and GND. + 5: Voltage over AIN1 and GND. + 6: Voltage over AIN2 and GND. + 7: Voltage over AIN3 and GND. + items: + - minimum: 0 + maximum: 7 + + ti,gain: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 5 + description: | + pga is the programmable gain amplifier (values are full scale) + 0: +/- 6.144 V + 1: +/- 4.096 V + 2: +/- 2.048 V (default) + 3: +/- 1.024 V + 4: +/- 0.512 V + 5: +/- 0.256 V + + ti,datarate: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 6 + description: | + Data acquisition rate in samples per second + 0: 128 + 1: 250 + 2: 490 + 3: 920 + 4: 1600 (default) + 5: 2400 + 6: 3300 + + required: + - reg + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + adc@49 { + compatible = "aks,ti-ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + channel@0 { + reg = <0>; + }; + channel@4 { + reg = <4>; + ti,gain = <3>; + ti,datarate = <5>; + }; + }; + }; +... diff --git a/bindings/iio/proximity/inv_ch101.txt b/bindings/iio/proximity/inv_ch101.txt new file mode 100755 index 00000000..cf3e490c --- /dev/null +++ b/bindings/iio/proximity/inv_ch101.txt @@ -0,0 +1,29 @@ +TDK/InvenSense CH101 UltraSonic device + +https://invensense.tdk.com/products/ch101/ + +Required properties: + - compatible : should be one of + "invensense,ch101" + "invensense,ch201" + - reg : the I2C address of the sensor + - rst-gpios: reset pin + - rtc_rst-gpios: rtc reset + - prg-gpios: program pin. + - interrupts: interrupt mapping for IRQ. It should be configured with flags + IRQ_TYPE_EDGE_RISING, or IRQ_TYPE_EDGE_FALLING. + + Refer to interrupt-controller/interrupts.txt for generic interrupt client node + bindings. + +Example: + + ch101_0: ch101_1@45 { + compatible = "invensense,ch101"; + reg = <0x45>; + rst-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>; + rtc_rst-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + prg-gpios = <0 1 2>; + int-gpios = <&tlmm 122 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>, + } diff --git a/bindings/iio/temperature/tdktherm.txt b/bindings/iio/temperature/tdktherm.txt new file mode 100755 index 00000000..57a671a1 --- /dev/null +++ b/bindings/iio/temperature/tdktherm.txt @@ -0,0 +1,21 @@ +TDK/InvenSense temperature sensor + + +Required properties: + - compatible : "tdktherm" + - reg : chip select ID + - spi-max-frequency: support up to 24Mhz. + - rtc_rst-gpios: rtc reset + - spi-cpol: SPI mode + - spi-cpha: SPI mode + + +Example: + temp_sensor@0 { + compatible = "tdktherm"; + reg = <0>; // Chip select ID + spi-max-frequency = <10000000>; // Can support up to 24 MHz + spi-cpol; + spi-cpha; + status = "okay"; + }; diff --git a/bindings/input/aks,adc-joystick.yaml b/bindings/input/aks,adc-joystick.yaml new file mode 100755 index 00000000..3f608f46 --- /dev/null +++ b/bindings/input/aks,adc-joystick.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019-2022 AKSys.co.kr +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/input/aks,adc-joystick.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: support ADC attached joystick and gpio keys also + +maintainers: + - Daniel.G <daniel@aksys.co.kr> + +description: | + Bindings for joystick devices connected to ADC controllers supporting the Industrial I/O subsystem. + Support GPIO keys input also + +properties: + status: + description: | + enable('ok') or disable('disable') this section + + compatible: + const: aks,joystick_mt + + label: + const: aks,joystick_mt + + pinctrl-names: + description: | + list the pre-defined pinctrl arrays names + + pinctrl-0: + description: | + the pre-defined pinctrl arrays for active status + + pinctrl-1: + description: | + the pre-defined pinctrl arrays for sleep status + + io-channels: + minItems: 1 + maxItems: 1024 + description: | + List of phandle and IIO specifier pairs. + Each pair defines one ADC channel to which a joystick axis is connected. + See + https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml + for details. + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +required: + - compatible + - pinctrl-names + - pinctrl-0 + - pinctrl-1 + - io-channels + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +patternProperties: + "^axis@[0-9a-f]+$": + type: object + description: | + Represents a joystick axis bound to the given ADC channel. + For each entry in the io-channels list, one axis subnode with a matching + reg property must be specified. + + "^axis@[0-9a-f]+$": + type: object + description: | + Represents a joystick axis bound to the given ADC channel. + For each entry in the io-channels list, one axis subnode with a matching + reg property must be specified. + + properties: + reg: + minimum: 0 + maximum: 1023 + description: Index of an io-channels list entry bound to this axis. + + linux,code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: EV_ABS specific event code generated by the axis. + + abs-range: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - items: + - description: minimum value + - description: maximum value + description: | + Minimum and maximum values produced by the axis. + For an ABS_X axis this will be the left-most and right-most + inclination of the joystick. If min > max, it is left to userspace to + treat the axis as inverted. + This property is interpreted as two signed 32 bit values. + + abs-fuzz: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Amount of noise in the input value. + Omitting this property indicates the axis is precise. + + abs-flat: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Axial "deadzone", or area around the center position, where the axis + is considered to be at rest. + Omitting this property indicates the axis always returns to exactly + the center position. + + required: + - reg + - linux,code + - abs-range + + additionalProperties: false + +examples: + - | + #include <dt-bindings/iio/adc/ingenic,adc.h> + #include <dt-bindings/input/input.h> + + aks_joystick_mt: aks_joystick_mt { + status = "ok"; + compatible = "aks,joystick_mt"; + label = "aks-joystick-mt"; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&gpio_key_active>; + pinctrl-1 = <&gpio_key_suspend>; + io-channels = <&adcl 4>, <&adcl 5>, <&adcl 6>, <&adcr 4>, <&adcr 5>, <&adcr 6>; + #address-cells = <1>; + #size-cells = <0>; + + btn_mode { + label = "btn_mode"; + gpios = <&gpios 15 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <BTN_MODE>; + debounce-interval = <15>; + }; + + axis@0 { + reg = <0>; + index = <0>; + linux,code = <ABS_X>; + abs-range = <580 2040>; + abs-fuzz = <5>; + abs-flat = <5>; + }; + + axis@1 { + reg = <1>; + index = <1>; + linux,code = <ABS_Y>; + abs-range = <630 2040>; + abs-fuzz = <5>; + abs-flat = <5>; + }; + }; diff --git a/bindings/interconnect/qcom,crow.txt b/bindings/interconnect/qcom,crow.txt new file mode 100755 index 00000000..8235a590 --- /dev/null +++ b/bindings/interconnect/qcom,crow.txt @@ -0,0 +1,32 @@ +Qualcomm Technologies, Inc. Crow Network-On-Chip interconnect driver binding +----------------------------------------------------------- + +Crow interconnect providers support system bandwidth requirements through +RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is +able to communicate with the BCM through the Resource State Coordinator (RSC) +associated with each execution environment. Provider nodes must point to at +least one RPMh device child node pertaining to their RSC and each provider +can map to multiple RPMh resources. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,crow-aggre1_noc", + "qcom,crow-aggre2_noc", + "qcom,crow-clk_virt", + "qcom,crow-cnoc_cfg", + "qcom,crow-cnoc_main", + "qcom,crow-gem_noc", + "qcom,crow-lpass_ag_noc", + "qcom,crow-mc_virt", + "qcom,crow-mmss_noc", + "qcom,crow-pcie_anoc", + "qcom,crow-nsp_noc", + "qcom,crow-system_noc", +- #interconnect-cells : should contain 1 + +Examples: + +system_noc: interconnect@1680000 { + compatible = "qcom,crow-system_noc"; + #interconnect-cells = <1>; +}; diff --git a/bindings/pci/msm_ep_pcie.txt b/bindings/pci/msm_ep_pcie.txt index 351eb34c..8ae3634c 100755 --- a/bindings/pci/msm_ep_pcie.txt +++ b/bindings/pci/msm_ep_pcie.txt @@ -76,6 +76,13 @@ Optional Properties: - qcom,pcie-m2-autonomous: Enable L1ss sleep/exit to support M2 autonomous mode. - qcom,mhi-soc-reset-offset: AXI register offset to initiate a SOC reset. - qcom,override-disable-sriov: Set to report as SRIOV capability disable with client (MHI) driver. + - nvmem-cells: Phandle of nvmem cell containing the address for boot_config. + - nvmem-cell-names: nvmem cell name for boot_config. + - qcom,fast-boot-mask: Bitmask to read fast_boot value from boot_config cell. + - qcom,host-bypass-mask: Bitmask to read host_bypass value from boot_config cell. + Will work only when host_bypass is 1 bit in boot_config. + - qcom,fast-boot-values: fast_boot values to check against boot_config based value for confirming + that host-interface is PCIe. Example: diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index 4879cc92..3430ef7d 100755 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -275,6 +275,11 @@ interconnects: Value type: <bool> Definition: Apss based L1ss sleep is supported +- qcom,no-client-based-bw-voting: + Usage: optional + Value type: <bool> + Definition: client based bw voting is not supported + - qcom,no-aux-clk-sync: Usage: optional Value type: <bool> diff --git a/bindings/pinctrl/qcom,trinket-pinctrl.yaml b/bindings/pinctrl/qcom,trinket-pinctrl.yaml new file mode 100755 index 00000000..9a0f6ee5 --- /dev/null +++ b/bindings/pinctrl/qcom,trinket-pinctrl.yaml @@ -0,0 +1,187 @@ +Qualcomm Technologies, Inc. TRINKET TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +TRINKET platform. + +- compatible: + Usage: required + Value type: <string> + Definition: must be "qcom,trinket-pinctrl" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: <none> + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/interrupt-controller/irq.h> + +- gpio-controller: + Usage: required + Value type: <none> + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/gpio/gpio.h> + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: <string-array> + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins are: + gpio0-gpio112 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + +- function: + Usage: required + Value type: <string> + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + + blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio + +- bias-disable: + Usage: optional + Value type: <none> + Definition: The specified pins should be configured as no pull. + +- bias-pull-down: + Usage: optional + Value type: <none> + Definition: The specified pins should be configured as pull down. + +- bias-pull-up: + Usage: optional + Value type: <none> + Definition: The specified pins should be configured as pull up. + +- output-high: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + high. + Not valid for sdc pins. + +- output-low: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + low. + Not valid for sdc pins. + +- drive-strength: + Usage: optional + Value type: <u32> + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + tlmm: pinctrl@400000 { + compatible = "qcom,trinket-pinctrl"; + reg = <0x400000 0xc00000>; + interrupts = <0 227 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/bindings/remoteproc/qcom,adsp.txt b/bindings/remoteproc/qcom,adsp.txt index aa535e6c..4f50d2c8 100755 --- a/bindings/remoteproc/qcom,adsp.txt +++ b/bindings/remoteproc/qcom,adsp.txt @@ -42,6 +42,7 @@ on the Qualcomm Technologies inc ADSP Hexagon core. "qcom,khaje-modem-pas" "qcom,sdmshrike-adsp-pas" "qcom,sdmshrike-cdsp-pas" + "qcom,sdmshrike-mpss-pas" "qcom,scuba_auto-modem-pas" "qcom,scuba_auto-lpass-pas" "qcom,monaco-adsp-pas" diff --git a/bindings/spmi/qcom,spmi-glink-debug.txt b/bindings/soc/qcom/qcom,pmic-glink-debug.txt index 454ea8b6..454ea8b6 100755 --- a/bindings/spmi/qcom,spmi-glink-debug.txt +++ b/bindings/soc/qcom/qcom,pmic-glink-debug.txt diff --git a/bindings/vendor-prefixes.yaml b/bindings/vendor-prefixes.yaml index 8d67b6ae..d811eb65 100755 --- a/bindings/vendor-prefixes.yaml +++ b/bindings/vendor-prefixes.yaml @@ -59,6 +59,8 @@ patternProperties: description: Aeroflex Gaisler AB "^aesop,.*": description: AESOP Embedded Forum + "^aks,.*": + description: AKSys Co., Ltd. "^al,.*": description: Annapurna Labs "^alcatel,.*": diff --git a/qcom/Makefile b/qcom/Makefile index 384bba0c..bbac8b9e 100755 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -133,20 +133,26 @@ bengal-dtb-$(CONFIG_ARCH_KHAJE) += \ bengal-overlays-dtb-$(CONFIG_ARCH_KHAJE) += $(KHAJE_BOARDS) $(KHAJE_BASE_DTB) dtb-y += $(bengal-dtb-y) -KONA_BASE_DTB += kona-iot.dtb kona-iot-v2.dtb kona-iot-v2.1.dtb kona-7230-iot-v2.1.dtb qrb5165-iot.dtb qrb5165n-iot.dtb qrb3165-iot.dtb qrb3165n-iot.dtb +KONA_BASE_DTB += kona-iot.dtb kona-iot-v2.dtb kona-iot-v2.1.dtb kona-7230-iot-v2.1.dtb +KONA_LE_BASE_DTB += kona-7230-iot-v2.1.dtb qrb5165-iot.dtb qrb5165n-iot.dtb qrb3165-iot.dtb qrb3165n-iot.dtb KONA_BOARDS += \ - kona-iot-v2.1-rb5-overlay.dtbo \ - kona-iot-v2-rb5-overlay.dtbo \ kona-hdk-overlay.dtbo \ kona-rb5-HDMI-overlay.dtbo \ kona-iot-v2.1-vc-overlay.dtbo \ - kona-rb5-overlay.dtbo + kona-rb5-overlay.dtbo \ + kona-iot-v2.1-rb5-overlay.dtbo + + +KONA_LE_BOARDS += \ + kona-iot-v2.1-rb5-overlay.dtbo \ + kona-iot-v2-rb5-overlay.dtbo kona-dtb-$(CONFIG_ARCH_KONA) += \ - $(call add-overlays, $(KONA_BOARDS) ,$(KONA_BASE_DTB)) + $(call add-overlays, $(KONA_BOARDS) ,$(KONA_BASE_DTB)) \ + $(call add-overlays, $(KONA_LE_BOARDS) ,$(KONA_LE_BASE_DTB)) kona-overlays-dtb-$(CONFIG_ARCH_KONA) += $(KONA_BOARDS) $(KONA_BASE_DTB) -kona_le-overlays-dtb-$(CONFIG_ARCH_KONA) += $(KONA_BOARDS) $(KONA_BASE_DTB) +kona_le-overlays-dtb-$(CONFIG_ARCH_KONA) += $(KONA_LE_BOARDS) $(KONA_LE_BASE_DTB) dtb-y += $(kona-dtb-y) MONACO_BASE_DTB += monaco.dtb monacop.dtb @@ -206,6 +212,25 @@ qcs405-dtb-$(CONFIG_ARCH_QCS405) += \ qcs405-overlays-dtb-$(CONFIG_ARCH_QCS405) += $(QCS405_BOARDS) $(QCS405_BASE_DTB) dtb-y += $(qcs405-dtb-y) +TRINKET_BASE_DTB += trinket-iot.dtb trinketp-iot.dtb + +TRINKET_BOARDS += \ + trinket-iot-idp-overlay.dtbo \ + trinketp-iot-idp-overlay.dtbo \ + trinket-iot-dp-idp-overlay.dtbo \ + trinket-iot-external-codec-idp-overlay.dtbo \ + trinket-iot-usbc-external-codec-idp-overlay.dtbo \ + trinket-iot-usbc-idp-overlay.dtbo \ + trinketp-iot-dp-idp-overlay.dtbo \ + trinketp-iot-external-codec-idp-overlay.dtbo \ + trinketp-iot-usbc-external-codec-idp-overlay.dtbo \ + trinketp-iot-usbc-idp-overlay.dtbo + +trinket-dtb-$(CONFIG_ARCH_TRINKET) += \ + $(call add-overlays, $(TRINKET_BOARDS) ,$(TRINKET_BASE_DTB)) +trinket-overlays-dtb-$(CONFIG_ARCH_TRINKET) += $(TRINKET_BOARDS) $(TRINKET_BASE_DTB) +dtb-y += $(trinket-dtb-y) + kaka-dtb-$(CONFIG_ARCH_KAKA) += kaka-rumi.dtb dtb-y += $(kaka-dtb-y) @@ -382,8 +407,8 @@ kalama_tuivm-dtb-$(CONFIG_ARCH_QTI_VM) += kalama-vm-rumi.dtb \ kalama-vm-mtp.dtb \ kalama-vm-cdp.dtb \ kalama-vm-qrd.dtb \ - kalamap-vm-hdk.dtb \ - kalamap-vm-hhg.dtb \ + kalama-vm-hdk.dtb \ + kalama-vm-hhg.dtb \ kalama-oemvm-cdp.dtb \ kalama-oemvm-mtp.dtb \ kalama-oemvm-qrd.dtb \ diff --git a/qcom/cinder-du-hireg-4gb.dtsi b/qcom/cinder-du-hireg-4gb.dtsi new file mode 100755 index 00000000..e3a9de2c --- /dev/null +++ b/qcom/cinder-du-hireg-4gb.dtsi @@ -0,0 +1,31 @@ +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ecc_meta_data_reserved_mem: ecc_meta_data_reserved_region@f0000000 { + no-map; + reg = <0x0 0xf0000000 0x0 0x10000000>; + }; + + harq_buffer_mem: harq_buffer_region@800000000 { + no-map; + reg = <0x8 0x0 0x0 0x40000000>; + }; + + tenx_sp_buffer_mem: tenx_sp_buffer_region@880000000 { + no-map; + reg = <0x8 0x40000000 0x0 0x27100000>; + }; + + fapi_buffer_mem: fapi_buffer_region@867100000 { + no-map; + reg = <0x8 0x67100000 0x0 0xc800000>; + }; + + tenx_purge_area_mem: tenx_purge_area_region@87ba00000 { + no-map; + reg = <0x8 0x7ba00000 0x0 0x100000>; + }; + +}; diff --git a/qcom/cinder-du-hireg.dtsi b/qcom/cinder-du-hireg.dtsi new file mode 100755 index 00000000..8350d94f --- /dev/null +++ b/qcom/cinder-du-hireg.dtsi @@ -0,0 +1,26 @@ +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ecc_meta_data_reserved_mem: ecc_meta_data_reserved_region@e0000000 { + no-map; + reg = <0x0 0xe0000000 0x0 0x20000000>; + }; + + harq_buffer_mem: harq_buffer_region@800000000 { + no-map; + reg = <0x8 0x0 0x0 0x80000000>; + }; + + tenx_sp_buffer_mem: tenx_sp_buffer_region@880000000 { + no-map; + reg = <0x8 0x80000000 0x0 0x50000000>; + }; + + fapi_buffer_mem: fapi_buffer_region@8d0000000 { + no-map; + reg = <0x8 0xd0000000 0x0 0x20000000>; + }; + +}; diff --git a/qcom/cinder-du-idp.dts b/qcom/cinder-du-idp.dts index f9de1c7e..adeb6c2a 100755 --- a/qcom/cinder-du-idp.dts +++ b/qcom/cinder-du-idp.dts @@ -1,6 +1,8 @@ /dts-v1/; +#include "cinder.dtsi" #include "cinder-du.dtsi" +#include "cinder-du-hireg.dtsi" #include "cinder-idp.dtsi" / { diff --git a/qcom/cinder-du-rumi.dts b/qcom/cinder-du-rumi.dts index a97589ad..94784d0b 100755 --- a/qcom/cinder-du-rumi.dts +++ b/qcom/cinder-du-rumi.dts @@ -1,6 +1,7 @@ /dts-v1/; /memreserve/ 0x80C40000 0x00010000; +#include "cinder.dtsi" #include "cinder-du.dtsi" #include "cinder-rumi.dtsi" diff --git a/qcom/cinder-du-x100.dts b/qcom/cinder-du-x100.dts index 56757326..e4b0ca08 100755 --- a/qcom/cinder-du-x100.dts +++ b/qcom/cinder-du-x100.dts @@ -1,6 +1,8 @@ /dts-v1/; +#include "cinder.dtsi" #include "cinder-du.dtsi" +#include "cinder-du-hireg.dtsi" #include "cinder-x100.dtsi" / { diff --git a/qcom/cinder-du.dtsi b/qcom/cinder-du.dtsi index 64116713..c1487871 100755 --- a/qcom/cinder-du.dtsi +++ b/qcom/cinder-du.dtsi @@ -4,7 +4,6 @@ qcom,msm-id = <545 0x10000>, <587 0x10000>; }; -#include "cinder.dtsi" &reserved_memory { #address-cells = <2>; @@ -74,6 +73,11 @@ reg = <0x0 0x80c00000 0x0 0x40000>; }; + qup_firmware_mem: qup_firmware_region@80c40000 { + no-map; + reg = <0x0 0x80c40000 0x0 0x12c00>; + }; + /* uefi region can be reused by apps */ tz_stat_mem: tz_stat_region@81d00000 { @@ -135,17 +139,7 @@ tenx_mem: tenx_region@a0000000 { no-map; - reg = <0x0 0xa0000000 0x0 0x19600000>; - }; - - oem_tenx_mem: oem_tenx_region@b9600000 { - no-map; - reg = <0x0 0xb9600000 0x0 0x6a00000>; - }; - - tenx_q6_buffer_mem: tenx_q6_buffer_region@c0000000 { - no-map; - reg = <0x0 0xc0000000 0x0 0x3200000>; + reg = <0x0 0xa0000000 0x0 0x20000000>; }; ipa_buffer_mem: ipa_buffer_region@c3200000 { diff --git a/qcom/cinder-ru-hireg-2gb.dtsi b/qcom/cinder-ru-hireg-2gb.dtsi new file mode 100755 index 00000000..5e92bb69 --- /dev/null +++ b/qcom/cinder-ru-hireg-2gb.dtsi @@ -0,0 +1,15 @@ +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ecc_meta_data_reserved_mem: ecc_meta_data_reserved_region@b8000000 { + no-map; + reg = <0x0 0xb8000000 0x0 0x8000000>; + }; + + tenx_sp_mem: tenx_sp_region@800000000 { + no-map; + reg = <0x8 0x0 0x0 0x40000000>; + }; +}; diff --git a/qcom/cinder-ru-hireg.dtsi b/qcom/cinder-ru-hireg.dtsi new file mode 100755 index 00000000..2d8849bf --- /dev/null +++ b/qcom/cinder-ru-hireg.dtsi @@ -0,0 +1,15 @@ +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ecc_meta_data_reserved_mem: ecc_meta_data_reserved_region@f0000000 { + no-map; + reg = <0x0 0xf0000000 0x0 0x10000000>; + }; + + tenx_sp_mem: tenx_sp_region@800000000 { + no-map; + reg = <0x8 0x0 0x0 0x80000000>; + }; +}; diff --git a/qcom/cinder-ru-idp-2gb.dts b/qcom/cinder-ru-idp-2gb.dts index 997d83ad..9a8c26d0 100755 --- a/qcom/cinder-ru-idp-2gb.dts +++ b/qcom/cinder-ru-idp-2gb.dts @@ -1,6 +1,8 @@ /dts-v1/; +#include "cinder.dtsi" #include "cinder-ru.dtsi" +#include "cinder-ru-hireg-2gb.dtsi" #include "cinder-idp.dtsi" / { diff --git a/qcom/cinder-ru-idp.dts b/qcom/cinder-ru-idp.dts index a7cefc73..46899fef 100755 --- a/qcom/cinder-ru-idp.dts +++ b/qcom/cinder-ru-idp.dts @@ -1,6 +1,8 @@ /dts-v1/; +#include "cinder.dtsi" #include "cinder-ru.dtsi" +#include "cinder-ru-hireg.dtsi" #include "cinder-idp.dtsi" / { diff --git a/qcom/cinder-ru-rumi.dts b/qcom/cinder-ru-rumi.dts index f4f662c9..4853881e 100755 --- a/qcom/cinder-ru-rumi.dts +++ b/qcom/cinder-ru-rumi.dts @@ -1,6 +1,7 @@ /dts-v1/; /memreserve/ 0x80C40000 0x00010000; +#include "cinder.dtsi" #include "cinder-ru.dtsi" #include "cinder-rumi.dtsi" diff --git a/qcom/cinder-ru.dtsi b/qcom/cinder-ru.dtsi index 94eb3387..c9247120 100755 --- a/qcom/cinder-ru.dtsi +++ b/qcom/cinder-ru.dtsi @@ -4,8 +4,6 @@ qcom,msm-id = <539 0x10000>, <588 0x10000>, <589 0x10000>, <590 0x10000>; }; -#include "cinder.dtsi" - &reserved_memory { #address-cells = <2>; #size-cells = <2>; diff --git a/qcom/cinder-rumi.dtsi b/qcom/cinder-rumi.dtsi index afe44e12..70c3d2a5 100755 --- a/qcom/cinder-rumi.dtsi +++ b/qcom/cinder-rumi.dtsi @@ -13,18 +13,24 @@ &soc { pcie_ep: qcom,pcie@48020000 { compatible = "qcom,pcie-ep"; - reg = <0x48020000 0x10000>, - <0x48030000 0x40000>, - <0x48000000 0xf20>, - <0x48001000 0x800>, - <0x48000f40 0xa8>, - <0x48010000 0x10000>, - <0x01c00000 0x4000>, - <0x01c10000 0x10000>, - <0x01c04000 0x1000>, - <0x01c09054 0x4>; - reg-names = "msi", "msi_vf","dm_core", "dm_core_vf","elbi", "iatu", - "parf", "phy", "mmio", "rumi"; + reg = <0x48020000 0x100>, + <0x48000000 0xf20>, + <0x48001000 0x2200>, + <0x48000f40 0xa8>, + <0x48010000 0x10000>, + <0x48004000 0x4400>, + <0x48009000 0x1000>, + <0x01c00000 0x4000>, + <0x01c20000 0x10000>, + <0x01c04000 0x1000>, + <0x01fcb000 0x1000>, + <0xc2f1000 0x4>, + <0x48030000 0x100>, + <0x01c09054 0x4>; + reg-names = "msi", "dm_core", "dm_core_vf", "elbi", "iatu", + "msix_table", "msix_pba", "parf", + "phy", "mmio", "tcsr_pcie_perst_en", + "aoss_cc_reset", "msi_vf", "rumi"; qcom,pcie-link-speed = <1>; qcom,tcsr-not-supported; diff --git a/qcom/cinder-v2-du-hireg-4gb.dtsi b/qcom/cinder-v2-du-hireg-4gb.dtsi new file mode 100755 index 00000000..53dff54a --- /dev/null +++ b/qcom/cinder-v2-du-hireg-4gb.dtsi @@ -0,0 +1 @@ +#include "cinder-du-hireg-4gb.dtsi" diff --git a/qcom/cinder-v2-du-hireg.dtsi b/qcom/cinder-v2-du-hireg.dtsi new file mode 100755 index 00000000..d6acaef8 --- /dev/null +++ b/qcom/cinder-v2-du-hireg.dtsi @@ -0,0 +1 @@ +#include "cinder-du-hireg.dtsi" diff --git a/qcom/cinder-v2-du-idp.dts b/qcom/cinder-v2-du-idp.dts index cab7a40d..776cf5ec 100755 --- a/qcom/cinder-v2-du-idp.dts +++ b/qcom/cinder-v2-du-idp.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "cinder-v2-du.dtsi" +#include "cinder-v2-du-hireg.dtsi" #include "cinder-v2-idp.dtsi" / { diff --git a/qcom/cinder-v2-du-x100.dts b/qcom/cinder-v2-du-x100.dts index 1ac252a0..0c718abb 100755 --- a/qcom/cinder-v2-du-x100.dts +++ b/qcom/cinder-v2-du-x100.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "cinder-v2-du.dtsi" +#include "cinder-v2-du-hireg.dtsi" #include "cinder-v2-x100.dtsi" / { diff --git a/qcom/cinder-v2-ru-hireg-2gb.dtsi b/qcom/cinder-v2-ru-hireg-2gb.dtsi new file mode 100755 index 00000000..ac6aeed4 --- /dev/null +++ b/qcom/cinder-v2-ru-hireg-2gb.dtsi @@ -0,0 +1 @@ +#include "cinder-ru-hireg-2gb.dtsi" diff --git a/qcom/cinder-v2-ru-hireg.dtsi b/qcom/cinder-v2-ru-hireg.dtsi new file mode 100755 index 00000000..19606b7a --- /dev/null +++ b/qcom/cinder-v2-ru-hireg.dtsi @@ -0,0 +1 @@ +#include "cinder-ru-hireg.dtsi" diff --git a/qcom/cinder-v2-ru-idp-2gb.dts b/qcom/cinder-v2-ru-idp-2gb.dts index 7eadd142..d9fbfa56 100755 --- a/qcom/cinder-v2-ru-idp-2gb.dts +++ b/qcom/cinder-v2-ru-idp-2gb.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "cinder-v2-ru.dtsi" +#include "cinder-v2-ru-hireg-2gb.dtsi" #include "cinder-v2-idp.dtsi" / { diff --git a/qcom/cinder-v2-ru-idp.dts b/qcom/cinder-v2-ru-idp.dts index f74fb440..c40431ff 100755 --- a/qcom/cinder-v2-ru-idp.dts +++ b/qcom/cinder-v2-ru-idp.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "cinder-v2-ru.dtsi" +#include "cinder-v2-ru-hireg.dtsi" #include "cinder-v2-idp.dtsi" / { diff --git a/qcom/cinder-v2.dtsi b/qcom/cinder-v2.dtsi index dac2d670..dd0d4199 100755 --- a/qcom/cinder-v2.dtsi +++ b/qcom/cinder-v2.dtsi @@ -1,14 +1,37 @@ #include "cinder.dtsi" &pcie_ep { - /delete-property/ sriov-mask; + reg = <0x48020000 0x100>, + <0x48000000 0xf20>, + <0x48001000 0x2200>, + <0x48000f40 0xa8>, + <0x48010000 0x10000>, + <0x48004000 0x4400>, + <0x48009000 0x1000>, + <0x01c00000 0x4000>, + <0x01c20000 0x10000>, + <0x01c04000 0x1000>, + <0x01fcb000 0x1000>, + <0xc2f1000 0x4>, + <0x48030000 0x100>; + reg-names = "msi", "dm_core", "dm_core_vf", "elbi", "iatu", + "msix_table", "msix_pba", "parf", + "phy", "mmio", "tcsr_pcie_perst_en", + "aoss_cc_reset", "msi_vf"; + /delete-property/ qcom,sriov-mask; qcom,pcie-parf-msi-vf-indexed; qcom,db-fwd-off-varied; }; &mhi_device { qcom,mhi-ifc-id = <0x060117cb>; - interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>, + interrupts = <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, @@ -19,7 +42,9 @@ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mhi-virt-device-int-4", + interrupt-names = "mhi-device-inta", "mhi-virt-device-int-0", + "mhi-virt-device-int-1", "mhi-virt-device-int-2", + "mhi-virt-device-int-3", "mhi-virt-device-int-4", "mhi-virt-device-int-5", "mhi-virt-device-int-6", "mhi-virt-device-int-7", "mhi-virt-device-int-8", "mhi-virt-device-int-9", "mhi-virt-device-int-10", diff --git a/qcom/crow-reserved-memory.dtsi b/qcom/crow-reserved-memory.dtsi index 7c039d4b..709dc371 100755 --- a/qcom/crow-reserved-memory.dtsi +++ b/qcom/crow-reserved-memory.dtsi @@ -2,6 +2,7 @@ #address-cells = <2>; #size-cells = <2>; ranges; + removes_carveout_region; gunyah_hyp_mem: gunyah_hyp_region@80000000 { no-map; diff --git a/qcom/crow-rumi.dtsi b/qcom/crow-rumi.dtsi index 680d91a2..b3ba3fe9 100755 --- a/qcom/crow-rumi.dtsi +++ b/qcom/crow-rumi.dtsi @@ -42,3 +42,76 @@ &qupv3_se5_2uart { qcom,rumi_platform; }; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qrbtc-sdm845"; + + vdda-phy-supply = <&L2B>; + vdda-pll-supply = <&L4B>; + vdda-phy-max-microamp = <141730>; + vdda-pll-max-microamp = <18310>; + + status = "ok"; +}; + +&ufshc_mem { + limit-tx-hs-gear = <1>; + limit-rx-hs-gear = <1>; + limit-rate = <2>; /* HS Rate-B */ + + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&L12B>; + vcc-max-microamp = <800000>; + + vccq-supply = <&L2D>; + vccq-max-microamp = <750000>; + + vccq2-supply = <&L2D>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&L5B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,disable-lpm; + rpm-level = <0>; + spm-level = <0>; + + status = "ok"; +}; + +&SILVER_OFF { + status = "disabled"; +}; + +&SILVER_RAIL_OFF { + status = "disabled"; +}; + +&GOLD_OFF { + status = "disabled"; +}; + +&GOLD_RAIL_OFF { + status = "disabled"; +}; + +&GOLD_PLUS_OFF { + status = "disabled"; +}; + +&GOLD_PLUS_RAIL_OFF { + status = "disabled"; +}; + +&CLUSTER_PWR_DN { + status = "disabled"; +}; + +&CX_RET { + status = "disabled"; +}; + +&APSS_OFF { + status = "disabled"; +}; diff --git a/qcom/crow-usb.dtsi b/qcom/crow-usb.dtsi index 4852e6ce..a9cc9157 100755 --- a/qcom/crow-usb.dtsi +++ b/qcom/crow-usb.dtsi @@ -10,6 +10,7 @@ #size-cells = <1>; ranges; + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, @@ -31,6 +32,11 @@ compatible = "snps,dwc3"; reg = <0xa600000 0xd93c>; + iommus = <&apps_smmu 0x80 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + dma-coherent; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; diff --git a/qcom/crow.dtsi b/qcom/crow.dtsi index d2445a1d..ebce2922 100755 --- a/qcom/crow.dtsi +++ b/qcom/crow.dtsi @@ -5,10 +5,13 @@ #include <dt-bindings/clock/qcom,gpucc-crow.h> #include <dt-bindings/clock/qcom,tcsrcc-kalama.h> #include <dt-bindings/clock/qcom,videocc-crow.h> +#include <dt-bindings/interconnect/qcom,icc.h> +#include <dt-bindings/interconnect/qcom,crow.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/qcom,ipcc.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h> +#include <dt-bindings/gpio/gpio.h> / { model = "Qualcomm Technologies, Inc. Crow"; @@ -19,7 +22,9 @@ #address-cells = <2>; #size-cells = <2>; - chosen: chosen { }; + chosen: chosen { + bootargs = "console=ttyMSM0,115200n8 allow_mismatched_32bit_el0 log_buf_len=256K"; + }; memory { device_type = "memory"; reg = <0 0 0 0>; }; @@ -29,6 +34,7 @@ aliases { serial0 = &qupv3_se5_2uart; + ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ }; cpus { @@ -40,6 +46,9 @@ compatible = "qcom,kryo"; reg = <0x0 0x0>; enable-method = "psci"; + cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "arm,arch-cache"; @@ -57,6 +66,9 @@ compatible = "qcom,kryo"; reg = <0x0 0x100>; enable-method = "psci"; + cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; next-level-cache = <&L2_0>; }; @@ -65,6 +77,9 @@ compatible = "qcom,kryo"; reg = <0x0 0x200>; enable-method = "psci"; + cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; next-level-cache = <&L2_2>; L2_2: l2-cache { compatible = "arm,arch-cache"; @@ -78,6 +93,9 @@ compatible = "qcom,kryo"; reg = <0x0 0x300>; enable-method = "psci"; + cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; next-level-cache = <&L2_2>; }; @@ -86,6 +104,9 @@ compatible = "qcom,kryo"; reg = <0x0 0x400>; enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; next-level-cache = <&L2_4>; L2_4: l2-cache { compatible = "arm,arch-cache"; @@ -99,6 +120,9 @@ compatible = "qcom,kryo"; reg = <0x0 0x500>; enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; next-level-cache = <&L2_5>; L2_5: l2-cache { compatible = "arm,arch-cache"; @@ -112,6 +136,9 @@ compatible = "qcom,kryo"; reg = <0x0 0x600>; enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; next-level-cache = <&L2_6>; L2_6: l2-cache { compatible = "arm,arch-cache"; @@ -125,6 +152,9 @@ compatible = "qcom,kryo"; reg = <0x0 0x700>; enable-method = "psci"; + cpu-idle-states = <&GOLD_PLUS_OFF &GOLD_PLUS_RAIL_OFF>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; next-level-cache = <&L2_7>; L2_7: l2-cache { compatible = "arm,arch-cache"; @@ -174,11 +204,103 @@ }; }; + idle-states { + entry-method = "psci"; + + SILVER_OFF: silver-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <250>; + exit-latency-us = <900>; + min-residency-us = <3200>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + SILVER_RAIL_OFF: silver-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <550>; + exit-latency-us = <750>; + min-residency-us = <6700>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + GOLD_OFF: gold-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <400>; + exit-latency-us = <1100>; + min-residency-us = <4011>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + GOLD_RAIL_OFF: gold-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <600>; + exit-latency-us = <1300>; + min-residency-us = <8136>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + GOLD_PLUS_OFF: gold-plus-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <450>; + exit-latency-us = <1200>; + min-residency-us = <6230>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + GOLD_PLUS_RAIL_OFF: gold-plus-c4 { /* C4 */ + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <500>; + exit-latency-us = <1350>; + min-residency-us = <7480>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + + CLUSTER_PWR_DN: cluster-d4 { /* D4 */ + compatible = "domain-idle-state"; + idle-state-name = "l3-off"; + entry-latency-us = <750>; + exit-latency-us = <2350>; + min-residency-us = <9144>; + arm,psci-suspend-param = <0x41000044>; + }; + + CX_RET: cx-ret { /* Cx Ret */ + compatible = "domain-idle-state"; + idle-state-name = "cx-ret"; + entry-latency-us = <1561>; + exit-latency-us = <2801>; + min-residency-us = <8550>; + arm,psci-suspend-param = <0x41001344>; + }; + + APSS_OFF: cluster-e3 { /* E3 */ + compatible = "domain-idle-state"; + idle-state-name = "llcc-off"; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <10150>; + arm,psci-suspend-param = <0x4100b344>; + }; + }; + soc: soc { }; }; #include "crow-reserved-memory.dtsi" #include "crow-dma-heaps.dtsi" +#include "msm-arm-smmu-crow.dtsi" &reserved_memory { #address-cells = <2>; @@ -218,6 +340,14 @@ alignment = <0x0 0x400000>; size = <0x0 0x1000000>; }; + + adsp_mem_heap: adsp_heap_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xC00000>; + }; }; &soc { @@ -248,6 +378,7 @@ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&CLUSTER_PD>; apps_rsc_drv2: drv@2 { qcom,drv-id = <2>; @@ -259,9 +390,50 @@ <CONTROL_TCS 0>, <FAST_PATH_TCS 1>; }; + + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; + }; }; + cluster-device { + compatible = "qcom,lpm-cluster-dev"; + power-domains = <&CLUSTER_PD>; + }; + + soc-sleep-stats@c3f0000 { + compatible = "qcom,rpmh-sleep-stats"; + reg = <0xc3f0000 0x400>; + qcom,drv-max = <0x14>; + ss-name = "modem", "adsp", "adsp_island", + "cdsp", "apss", "wpss"; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + ddr-freq-update; + }; + + subsystem-sleep-stats@c3f0000 { + compatible = "qcom,subsystem-sleep-stats"; + reg = <0xc3f0000 0x400>; + ddr-freq-update; + }; + + cpuss-sleep-stats@17800054 { + compatible = "qcom,cpuss-sleep-stats"; + reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>, + <0x17830054 0x4>, <0x17840054 0x4>, <0x17850054 0x4>, + <0x17860054 0x4>, <0x17870054 0x4>, <0x178a0098 0x4>, + <0x178c0000 0x10000>; + reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1", + "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3", + "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5", + "seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7", + "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base"; + num-cpus = <8>; + }; + disp_rsc: rsc@af20000 { label = "disp_rsc"; compatible = "qcom,rpmh-rsc"; @@ -371,6 +543,182 @@ #mbox-cells = <2>; }; + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem_heap>; + restrict-access; + }; + + msm_fastrpc: qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-audio-pdr; + qcom,fastrpc-adsp-sensors-pdr; + qcom,rpc-latency-us = <235>; + qcom,fastrpc-gids = <2908>; + qcom,qos-cores = <0 1 2 3>; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C01 0x0000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C02 0x0000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C03 0x0000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C04 0x0000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C05 0x0000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C06 0x0000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb7 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C07 0x0000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb8 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C08 0x0000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x0C09 0x0000>; + qcom,iommu-dma-addr-pool = <0x40000000 0x98000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1003 0x0000>, + <&apps_smmu 0x1063 0x0000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb11 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1004 0x0000>, + <&apps_smmu 0x1064 0x0000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb12 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1005 0x0000>, + <&apps_smmu 0x1065 0x0000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + shared-cb = <5>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb13 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1006 0x0000>, + <&apps_smmu 0x1066 0x0000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb14 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C0C 0x0000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb15 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C0D 0x0000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb16 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C0E 0x0000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb17 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C0F 0x0000>; + qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent; + }; + }; + aoss_qmp: power-controller@c300000 { compatible = "qcom,kalama-aoss-qmp"; reg = <0xc300000 0x400>; @@ -550,6 +898,151 @@ psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD2: cpu-pd2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD3: cpu-pd3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD4: cpu-pd4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD5: cpu-pd5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD6: cpu-pd6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD7: cpu-pd7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: cluster-pd { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_PWR_DN &CX_RET &APSS_OFF>; + }; + }; + + clk_virt: interconnect@0 { + compatible = "qcom,crow-clk_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@1 { + compatible = "qcom,crow-mc_virt"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect@1600000 { + compatible = "qcom,crow-cnoc_cfg"; + reg = <0x01600000 0x9080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + cnoc_main: interconnect@1500000 { + compatible = "qcom,crow-cnoc_main"; + reg = <0x1500000 0x13080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,crow-system_noc"; + reg = <0x01680000 0x1D080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_noc: interconnect@16c0000 { + compatible = "qcom,crow-pcie_anoc"; + reg = <0x016C0000 0x12200>; + #interconnect-cells = <1>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,crow-aggre1_noc"; + reg = <0x016E0000 0x14400>; + #interconnect-cells = <1>; + clocks = + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,crow-aggre2_noc"; + reg = <0x01700000 0x1F400>; + #interconnect-cells = <1>; + clocks = <&rpmhcc RPMH_IPA_CLK>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1780000 { + compatible = "qcom,crow-mmss_noc"; + reg = <0x01780000 0x5b800>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@24100000 { + compatible = "qcom,crow-gem_noc"; + reg = <0x24100000 0xBD080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nsp_noc: interconnect@320c0000 { + compatible = "qcom,crow-nsp_noc"; + reg = <0x320C0000 0xE080>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_ag_noc: interconnect@3C40000 { + compatible = "qcom,crow-lpass_ag_noc"; + reg = <0x03C40000 0x17200>; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; }; clocks { @@ -714,6 +1207,217 @@ hyplog-address-offset = <0x410>; hyplog-size-offset = <0x414>; }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + vendor_hooks: qcom,cpu-vendor-hooks { + compatible = "qcom,cpu-vendor-hooks"; + }; + + qcom,chd { + compatible = "qcom,core-hang-detect"; + label = "core"; + qcom,threshold-arr = <0x17800058 0x17810058 0x17820058 0x17830058 + 0x17840058 0x17850058 0x17860058 0x17870058>; + qcom,config-arr = <0x17800060 0x17810060 0x17820060 0x17830060 + 0x17840060 0x17850060 0x17860060 0x17870060>; + }; + + ufsphy_mem: ufsphy_mem@1d80000 { + reg = <0x1d80000 0x2000>; + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + clock-names = "ref_clk_src", + "ref_aux_clk", + "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk", + "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>; + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>, + <0x1d88000 0x18000>, + <0x1d90000 0x9800>; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + qcom,prime-mask = <0x80>; + qcom,silver-mask = <0x0f>; + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <100000000 403000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <26>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <1844 0>, <1000 0>, /* PWM G1 L2 */ + <3688 0>, <1000 0>, /* PWM G2 L2 */ + <7376 0>, <1000 0>, /* PWM G3 L2 */ + <14752 0>, <1000 0>, /* PWM G4 L2 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <1492582 0>, <102400 0>, /* HS G3 RA */ + <2915200 0>, <204800 0>, /* HS G4 RA */ + <255591 0>, <1000 0>, /* HS G1 RA L2 */ + <511181 0>, <1000 0>, /* HS G2 RA L2 */ + <1492582 0>, <204800 0>, /* HS G3 RA L2 */ + <2915200 0>, <409600 0>, /* HS G4 RA L2 */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <1492582 0>, <102400 0>, /* HS G3 RB */ + <2915200 0>, <204800 0>, /* HS G4 RB */ + <298189 0>, <1000 0>, /* HS G1 RB L2 */ + <596378 0>, <1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */ + <2915200 0>, <409600 409600>, /* HS G4 RB L2 */ + <7643136 0>, <819200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "PWM_G5_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", "PWM_G5_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "MAX"; + + reset-gpios = <&tlmm 167 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + iommus = <&apps_smmu 0x20 0x0>; + qcom,iommu-dma = "bypass"; + dma-coherent; + + status = "disabled"; + }; + + qcom,msm-imem@146aa000 { + compatible = "qcom,msm-imem"; + reg = <0x146aa000 0x1000>; + ranges = <0x0 0x146aa000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + + pil@6dc { + compatible = "qcom,msm-imem-pil-disable-timeout"; + reg = <0x6dc 0x4>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + qcom,mpm2-sleep-counter@c221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; }; &firmware { @@ -735,6 +1439,7 @@ #include "crow-stub-regulators.dtsi" #include "kalama-gdsc.dtsi" #include "crow-qupv3.dtsi" +#include "ipcc-test-crow.dtsi" &qupv3_se5_2uart { status = "ok"; diff --git a/qcom/direwolf-vm-la-mt.dtsi b/qcom/direwolf-vm-la-mt.dtsi index bad51479..7dda3710 100755 --- a/qcom/direwolf-vm-la-mt.dtsi +++ b/qcom/direwolf-vm-la-mt.dtsi @@ -46,6 +46,10 @@ }; / { + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 cgroup.memory=nokmem,nosocket kpti=0 qcom_dma_heaps.enable_bitstream_contig_heap=y arm64.nopauth kasan=off msm_show_resume_irq.debug_mask=1 androidboot.usbcontroller=a600000.dwc3 androidboot.fstab_suffix=gen4.qcom"; + }; + rename_devices: rename_devices { compatible = "qcom,rename-devices"; rename_blk: rename_blk { diff --git a/qcom/direwolf-vm-la.dtsi b/qcom/direwolf-vm-la.dtsi index d3558686..28a906c7 100755 --- a/qcom/direwolf-vm-la.dtsi +++ b/qcom/direwolf-vm-la.dtsi @@ -68,7 +68,19 @@ status = "okay"; }; +&ufs2phy_mem { + status = "okay"; +}; + +&ufshc2_mem { + status = "okay"; +}; + / { + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 cgroup.memory=nokmem,nosocket kpti=0 qcom_dma_heaps.enable_bitstream_contig_heap=y arm64.nopauth kasan=off msm_show_resume_irq.debug_mask=1 androidboot.usbcontroller=a600000.dwc3 androidboot.fstab_suffix=gen4.qcom"; + }; + rename_devices: rename_devices { compatible = "qcom,rename-devices"; rename_blk: rename_blk { diff --git a/qcom/direwolf-vm-lv.dtsi b/qcom/direwolf-vm-lv.dtsi index b0061052..250a9290 100755 --- a/qcom/direwolf-vm-lv.dtsi +++ b/qcom/direwolf-vm-lv.dtsi @@ -21,18 +21,6 @@ size = <0x0 0x3c00000>; }; -&soc { - tlmm: pinctrl@f000000 { - compatible = "qcom,direwolf-pinctrl"; - reg = <0x0F000000 0x1000000>; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; - &hab { vmid = <3>; }; diff --git a/qcom/direwolf-vm-ufs.dtsi b/qcom/direwolf-vm-ufs.dtsi index 254b1b6c..01017fae 100755 --- a/qcom/direwolf-vm-ufs.dtsi +++ b/qcom/direwolf-vm-ufs.dtsi @@ -32,7 +32,7 @@ &soc { ufs2phy_mem: ufsphy_mem@1da7000 { - compatible = "qcom,ufs-phy-qmp-v4-direwolf"; + compatible = "qcom,ufs-phy-qmp-v4-lahaina"; reg = <0x1da7000 0xe10>; reg-names = "phy_mem"; @@ -178,5 +178,15 @@ dma-coherent; status = "disabled"; + + qos0 { + mask = <0xf0>; + vote = <44>; + }; + + qos1 { + mask = <0x0f>; + vote = <44>; + }; }; }; diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index 0a978442..936be3eb 100755 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -485,6 +485,10 @@ }; }; +&scc { + status = "disabled"; +}; + ®ulator { gcc_usb30_prim_gdsc: gcc_usb30_prim_gdsc { regulator-name = "gcc_usb30_prim_gdsc"; diff --git a/qcom/ipcc-test-crow.dtsi b/qcom/ipcc-test-crow.dtsi new file mode 100755 index 00000000..9809b5ab --- /dev/null +++ b/qcom/ipcc-test-crow.dtsi @@ -0,0 +1,5 @@ +#include "ipcc-test.dtsi" + +&soc { + /delete-node/ ipcc-self-ping-slpi; +}; diff --git a/qcom/kalama-coresight.dtsi b/qcom/kalama-coresight.dtsi index f7661b42..e9fa3b69 100755 --- a/qcom/kalama-coresight.dtsi +++ b/qcom/kalama-coresight.dtsi @@ -4,7 +4,7 @@ coresight-name = "coresight-audio-etm0"; qcom,inst-id = <5>; - atid = <40>; + atid = <40 41>; out-ports { port { diff --git a/qcom/kalama-debug.dtsi b/qcom/kalama-debug.dtsi index 33a70481..4afec956 100755 --- a/qcom/kalama-debug.dtsi +++ b/qcom/kalama-debug.dtsi @@ -25,6 +25,17 @@ reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0>; + per-ll-reg-cnt = <9>; + ll-reg-offsets = < + 0x034 0x03C 0x040 0x044 0x04C 0x050 0x068 0x06C 0x038 + 0x0B4 0x0BC 0x0C0 0x0C4 0x0CC 0x0D0 0x0E8 0x0EC 0x0B8 + 0x134 0x13C 0x140 0x144 0x14C 0x150 0x168 0x16C 0x138 + 0x1B4 0x1BC 0x1C0 0x1C4 0x1CC 0x1D0 0x1E8 0x1EC 0x1B8 + 0x234 0x23C 0x240 0x244 0x24C 0x250 0x268 0x26C 0x238 + 0x2B4 0x2BC 0x2C0 0x2C4 0x2CC 0x2D0 0x2E8 0x2EC 0x2B8 + 0x334 0x33C 0x340 0x344 0x34C 0x350 0x368 0x36C 0x338 + 0x3B4 0x3BC 0x3C0 0x3C4 0x3CC 0x3D0 0x3E8 0x3EC 0x3B8>; + link_list_0 { qcom,curr-link-list = <6>; qcom,data-sink = "sram"; diff --git a/qcom/kalama-eva.dtsi b/qcom/kalama-eva.dtsi new file mode 100755 index 00000000..15eb44ff --- /dev/null +++ b/qcom/kalama-eva.dtsi @@ -0,0 +1,110 @@ +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/qcom,ipcc.h> +#include <dt-bindings/interconnect/qcom,kalama.h> +#include <dt-bindings/clock/qcom,videocc-kalama.h> + +&soc { + msm_cvp: qcom,cvp@ab00000 { + compatible = "qcom,msm-cvp", "qcom,kalama-cvp"; + status = "ok"; + reg = <0xab00000 0x100000>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; + + /* LLCC Cache */ + cache-slice-names = "cvp"; + + /* Supply */ + cvp-supply = <&video_cc_mvs1c_gdsc>; + cvp-core-supply = <&video_cc_mvs1_gdsc>; + + /* Clocks */ + clock-names = "gcc_video_axi1", "cvp_clk", "core_clk", + "video_cc_mvs1_clk_src"; + clock-ids = <GCC_VIDEO_AXI1_CLK VIDEO_CC_MVS1C_CLK + VIDEO_CC_MVS1_CLK VIDEO_CC_MVS1_CLK_SRC>; + clocks = <&gcc GCC_VIDEO_AXI1_CLK>, + <&videocc VIDEO_CC_MVS1C_CLK>, + <&videocc VIDEO_CC_MVS1_CLK>, + <&videocc VIDEO_CC_MVS1_CLK_SRC>; + qcom,proxy-clock-names = "gcc_video_axi1", + "cvp_clk", "core_clk", "video_cc_mvs1_clk_src"; + + qcom,clock-configs = <0x0 0x0 0x0 0x1>; + qcom,allowed-clock-rates = <350000000 450000000 500000000 550000000>; + + resets = <&gcc GCC_VIDEO_AXI1_CLK_ARES>, + <&videocc VIDEO_CC_MVS1C_CLK_ARES>; + reset-names = "cvp_axi_reset", "cvp_core_reset"; + reset-power-status = <0x2 0x2>; + + qcom,reg-presets = <0xB0088 0x0>; + qcom,ipcc-reg = <0x400000 0x100000>; + qcom,gcc-reg = <0x110000 0x40000>; + + pas-id = <26>; + memory-region = <&cvp_mem>; + + /* CVP Firmware ELF image name */ + cvp,firmware-name = "evass"; + + /* Buses */ + cvp_cnoc { + compatible = "qcom,msm-cvp,bus"; + label = "cvp-cnoc"; + qcom,bus-master = <MASTER_APPSS_PROC>; + qcom,bus-slave = <SLAVE_VENUS_CFG>; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + }; + + cvp_bus_ddr { + compatible = "qcom,msm-cvp,bus"; + label = "cvp-ddr"; + qcom,bus-master = <MASTER_VIDEO_PROC>; + qcom,bus-slave = <SLAVE_EBI1>; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 6533000>; + }; + + /* MMUs */ + cvp_non_secure_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_hlos"; + iommus = + <&apps_smmu 0x1920 0x0000>; + buffer-types = <0xfff>; + dma-coherent; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; + }; + + + cvp_secure_nonpixel_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_sec_nonpixel"; + iommus = + <&apps_smmu 0x1924 0x0000>; + buffer-types = <0x741>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>; + qcom,iommu-vmid = <0xB>; + }; + + cvp_secure_pixel_cb { + compatible = "qcom,msm-cvp,context-bank"; + label = "cvp_sec_pixel"; + iommus = + <&apps_smmu 0x1923 0x0000>; + buffer-types = <0x106>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; + qcom,iommu-vmid = <0xA>; + }; + + /* Memory Heaps */ + qcom,msm-cvp,mem_cdsp { + compatible = "qcom,msm-cvp,mem-cdsp"; + memory-region = <&cdsp_eva_mem>; + }; + }; +}; diff --git a/qcom/kalama-pinctrl.dtsi b/qcom/kalama-pinctrl.dtsi index 61d990b0..8a497db6 100755 --- a/qcom/kalama-pinctrl.dtsi +++ b/qcom/kalama-pinctrl.dtsi @@ -40,6 +40,55 @@ }; }; + gamepad_gpio_key { + gpio_key_active: gpio_key_active { + mux { + pins = "gpio0", "gpio14", "gpio15", "gpio40", + "gpio48", "gpio56", "gpio59", "gpio60", + "gpio62", "gpio63", "gpio73", "gpio75", + "gpio85", "gpio87", "gpio89", "gpio119", + "gpio137"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio14", "gpio15", "gpio40", + "gpio48", "gpio56", "gpio59", "gpio60", + "gpio62", "gpio63", "gpio73", "gpio75", + "gpio85", "gpio87", "gpio89", "gpio119", + "gpio137"; + drive-strength = <2>; + input-enable; + input; + bias-pull-up; + }; + }; + + gpio_key_suspend: gpio_key_suspend { + mux { + pins = "gpio0", "gpio14", "gpio15", "gpio40", + "gpio48", "gpio56", "gpio59", "gpio60", + "gpio62", "gpio63", "gpio73", "gpio75", + "gpio85", "gpio87", "gpio89", "gpio119", + "gpio137"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio14", "gpio15", "gpio40", + "gpio48", "gpio56", "gpio59", "gpio60", + "gpio62", "gpio63", "gpio73", "gpio75", + "gpio85", "gpio87", "gpio89", "gpio119", + "gpio137"; + drive-strength = <2>; + input-enable; + input; + bias-pull-up; + }; + }; + }; + + trigout_a: trigout_a { mux { pins = "gpio10"; diff --git a/qcom/kalama-qcm.dtsi b/qcom/kalama-qcm.dtsi index ba45e497..dda89da7 100755 --- a/qcom/kalama-qcm.dtsi +++ b/qcom/kalama-qcm.dtsi @@ -29,3 +29,10 @@ &adspslpi_mem { reg = <0x0 0x9f300000 0x0 0x4080000>; }; + +&reserved_memory { + hyp_mem: hyp_mem_region@80c00000 { + no-map; + reg = <0x0 0x80c00000 0x0 0x600000>; + }; +}; diff --git a/qcom/kalama-sg-hhg.dtsi b/qcom/kalama-sg-hhg.dtsi index 376667df..f172f220 100755 --- a/qcom/kalama-sg-hhg.dtsi +++ b/qcom/kalama-sg-hhg.dtsi @@ -117,6 +117,292 @@ 0x6 0x53>; }; +&qupv3_se10_i2c { + status = "ok"; + + adcl: adc@48 { + compatible = "aks,ti-ads1015"; + reg = <0x48>; + ti,vdd-supply = <&L3N>; + regulator-name = "ti,vdd"; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@4 { + reg = <4>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + channel@5 { + reg = <5>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + channel@6 { + reg = <6>; + ti,gain = <1>; + ti,datarate = <4>; + }; + }; +}; + +&qupv3_se11_i2c { + status = "ok"; + + adcr: adc@48 { + compatible = "aks,ti-ads1015"; + reg = <0x48>; + ti,vdd-supply = <&L3N>; + regulator-name = "ti,vdd"; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@4 { + reg = <4>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + channel@5 { + reg = <5>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + channel@6 { + reg = <6>; + ti,gain = <1>; + ti,datarate = <4>; + }; + }; +}; + +&soc { + aks_joystick_mt: aks_joystick_mt { + status = "ok"; + compatible = "aks,joystick_mt"; + label = "aks-joystick-mt"; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&gpio_key_active>; + pinctrl-1 = <&gpio_key_suspend>; + io-channels = <&adcl 4>, <&adcl 5>, <&adcl 6>, <&adcr 4>, <&adcr 5>, <&adcr 6>; + #address-cells = <1>; + #size-cells = <0>; + + btn_screen_cap { + label = "btn_screen_cap"; + gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_SYSRQ>; + debounce-interval = <15>; + linux,can-disable; + }; + + btn_function { + label = "btn_function"; + gpios = <&tlmm 14 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_FN>; + debounce-interval = <15>; + linux,can-disable; + }; + + btn_mode { + label = "btn_mode"; + gpios = <&tlmm 15 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <BTN_MODE>; + debounce-interval = <15>; + linux,can-disable; + }; + + btn_l1 { + label = "btn_l1"; + gpios = <&tlmm 40 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <BTN_TL>; + debounce-interval = <15>; + linux,can-disable; + }; + + btn_r1 { + label = "btn_r1"; + gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <BTN_TR>; + debounce-interval = <15>; + linux,can-disable; + }; + + btn_l3 { + label = "btn_l3"; + gpios = <&tlmm 59 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <BTN_THUMBL>; + debounce-interval = <15>; + linux,can-disable; + }; + + btn_r3 { + label = "btn_r3"; + gpios = <&tlmm 60 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <BTN_THUMBR>; + debounce-interval = <15>; + linux,can-disable; + }; + + btn_a { + label = "btn_a"; + gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <BTN_A>; + debounce-interval = <15>; + linux,can-disable; + }; + + btn_b { + label = "btn_b"; + gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <BTN_B>; + debounce-interval = <15>; + linux,can-disable; + }; + + btn_x { + label = "btn_x"; + gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <BTN_X>; + debounce-interval = <15>; + linux,can-disable; + }; + + btn_y { + label = "btn_y"; + gpios = <&tlmm 137 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <BTN_Y>; + debounce-interval = <15>; + linux,can-disable; + }; + + btn_dpad_up { + label = "btn_dpad_up"; + gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <BTN_DPAD_UP>; + debounce-interval = <15>; + linux,can-disable; + }; + + btn_dpad_down { + label = "btn_dpad_down"; + gpios = <&tlmm 63 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <BTN_DPAD_DOWN>; + debounce-interval = <15>; + linux,can-disable; + }; + + btn_dpad_left { + label = "btn_dpad_left"; + gpios = <&tlmm 73 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <BTN_DPAD_LEFT>; + debounce-interval = <15>; + linux,can-disable; + }; + + btn_dpad_right { + label = "btn_dpad_right"; + gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <BTN_DPAD_RIGHT>; + debounce-interval = <15>; + linux,can-disable; + }; + + btn_home { + label = "btn_home"; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <KEY_HOME>; + debounce-interval = <15>; + linux,can-disable; + }; + + btn_start { + label = "btn_start"; + gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <BTN_START>; + debounce-interval = <15>; + linux,can-disable; + + }; + + axis@0 { + reg = <0>; + index = <0>; + linux,code = <ABS_X>; + abs-range = <580 2040>; + abs-fuzz = <5>; + abs-flat = <5>; + }; + + axis@1 { + reg = <1>; + index = <1>; + linux,code = <ABS_Y>; + abs-range = <630 2040>; + abs-fuzz = <5>; + abs-flat = <5>; + }; + + axis@2 { + reg = <2>; + index = <2>; + linux,code = <ABS_BRAKE>; + abs-range = <539 810>; + abs-fuzz = <5>; + abs-flat = <5>; + }; + + axis@3 { + reg = <0>; + index = <3>; + linux,code = <ABS_Z>; + abs-range = <580 2040>; + abs-fuzz = <5>; + abs-flat = <5>; + }; + + axis@4 { + reg = <1>; + index = <4>; + linux,code = <ABS_RZ>; + abs-range = <630 2040>; + abs-fuzz = <5>; + abs-flat = <5>; + }; + + axis@5 { + reg = <2>; + index = <5>; + linux,code = <ABS_GAS>; + abs-range = <539 810>; + abs-fuzz = <5>; + abs-flat = <5>; + }; + }; +}; + &pm8550_gpios { pwr_en_gpio { pwr_en_gpio_default: pwr_en_gpio_default { diff --git a/qcom/kalamap-vm-hdk.dts b/qcom/kalama-vm-hdk.dts index ebf4c1f3..ebf4c1f3 100755 --- a/qcom/kalamap-vm-hdk.dts +++ b/qcom/kalama-vm-hdk.dts diff --git a/qcom/kalamap-vm-hhg.dts b/qcom/kalama-vm-hhg.dts index 0f938027..0f938027 100755 --- a/qcom/kalamap-vm-hhg.dts +++ b/qcom/kalama-vm-hhg.dts diff --git a/qcom/kalama-vm.dtsi b/qcom/kalama-vm.dtsi index c3abaa1b..c5629e31 100755 --- a/qcom/kalama-vm.dtsi +++ b/qcom/kalama-vm.dtsi @@ -5,7 +5,7 @@ / { #address-cells = <0x2>; #size-cells = <0x2>; - qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>; + qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>, <604 0x20000>; interrupt-parent = <&vgic>; logbuf: qcom,logbuf-vendor-hooks { diff --git a/qcom/kalama.dtsi b/qcom/kalama.dtsi index b5b57b2f..058bcb11 100755 --- a/qcom/kalama.dtsi +++ b/qcom/kalama.dtsi @@ -804,7 +804,7 @@ }; }; - apps_rsc: rsc@17a00000 { + apps_rsc: apps_rsc@17a00000 { label = "apps_rsc"; compatible = "qcom,rpmh-rsc"; reg = <0x17a00000 0x10000>, @@ -854,7 +854,7 @@ clock-frequency = <19200000>; }; - cam_rsc: rsc@add9000 { + cam_rsc: cam_rsc@add9000 { label = "cam_rsc"; compatible = "qcom,rpmh-rsc"; reg = <0xadd9000 0x1000>, @@ -941,7 +941,7 @@ }; }; - disp_rsc: rsc@af20000 { + disp_rsc: disp_rsc@af20000 { label = "disp_rsc"; compatible = "qcom,rpmh-rsc"; reg = <0xaf20000 0x10000>; @@ -2281,12 +2281,14 @@ qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "QMC_DMA_LINE"; qcom,glinkpkt-dev-name = "qmc_dma"; + qcom,glinkpkt-enable-ch-close; }; qcom,glinkpkt-qmc-cma { qcom,glinkpkt-edge = "mpss"; qcom,glinkpkt-ch-name = "QMC_CMA_LINE"; qcom,glinkpkt-dev-name = "qmc_cma"; + qcom,glinkpkt-enable-ch-close; }; }; @@ -2425,7 +2427,7 @@ qcom,fastrpc-adsp-sensors-pdr; qcom,rpc-latency-us = <235>; qcom,fastrpc-gids = <2908>; - qcom,qos-cores = <0 1 2 3>; + qcom,qos-cores = <0 1 2>; qcom,msm_fastrpc_compute_cb1 { compatible = "qcom,msm-fastrpc-compute-cb"; @@ -3630,6 +3632,7 @@ #include "kalama-regulators.dtsi" #include "kalama-qupv3.dtsi" #include "kalama-usb.dtsi" +#include "kalama-eva.dtsi" #include "kalama-pcie.dtsi" #include "msm-rdbg.dtsi" #include "kalama-thermal.dtsi" diff --git a/qcom/kalamap-hdk.dtsi b/qcom/kalamap-hdk.dtsi index a2342d72..9bf1c178 100755 --- a/qcom/kalamap-hdk.dtsi +++ b/qcom/kalamap-hdk.dtsi @@ -36,4 +36,5 @@ &pcie1 { qcom,boot-option = <0x2>; qcom,apss-based-l1ss-sleep; + qcom,no-client-based-bw-voting; }; diff --git a/qcom/kalamap-qcs.dtsi b/qcom/kalamap-qcs.dtsi index 436d8bc5..f4f23594 100755 --- a/qcom/kalamap-qcs.dtsi +++ b/qcom/kalamap-qcs.dtsi @@ -29,3 +29,10 @@ &adspslpi_mem { reg = <0x0 0x9f300000 0x0 0x4080000>; }; + +&reserved_memory { + hyp_mem: hyp_mem_region@80c00000 { + no-map; + reg = <0x0 0x80c00000 0x0 0x600000>; + }; +}; diff --git a/qcom/kalamap-sg-hhg.dtsi b/qcom/kalamap-sg-hhg.dtsi index 1c231a2b..3abff18f 100755 --- a/qcom/kalamap-sg-hhg.dtsi +++ b/qcom/kalamap-sg-hhg.dtsi @@ -15,6 +15,7 @@ vreg-3p3-supply = <&nvme_vreg>; qcom,boot-option = <0x2>; qcom,apss-based-l1ss-sleep; + qcom,no-client-based-bw-voting; }; ®ulator_ocp_notifier { diff --git a/qcom/kalamap-vm.dtsi b/qcom/kalamap-vm.dtsi index 582a2752..d1faa0e7 100755 --- a/qcom/kalamap-vm.dtsi +++ b/qcom/kalamap-vm.dtsi @@ -3,5 +3,5 @@ / { model = "Qualcomm Technologies, Inc. KalamaP SVM"; compatible = "qcom,kalamap"; - qcom,msm-id = <536 0x10000>, <536 0x20000>; + qcom,msm-id = <536 0x10000>, <536 0x20000>, <603 0x20000>; }; diff --git a/qcom/khaje-dma-heaps.dtsi b/qcom/khaje-dma-heaps.dtsi index 73efb469..239ca99d 100755 --- a/qcom/khaje-dma-heaps.dtsi +++ b/qcom/khaje-dma-heaps.dtsi @@ -40,5 +40,11 @@ qcom,max-align = <9>; memory-region = <&non_secure_display_memory>; }; + + qcom,audio_ml { + qcom,dma-heap-name = "qcom,audio-ml"; + qcom,dma-heap-type = <HEAP_TYPE_CMA>; + memory-region = <&audio_cma_mem>; + }; }; }; diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index 6625ff8f..de8a5817 100755 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -567,6 +567,14 @@ mem-type = <2>; }; + audio_cma_mem: audio_cma_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1C00000>; + }; + /* global autoconfigured region for contiguous allocations */ system_cma: linux,cma { compatible = "shared-dma-pool"; @@ -2781,6 +2789,8 @@ status = "disabled"; iommus = <&apps_smmu 0x100 0x0>; qcom,iommu-dma = "fastmap"; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; qos0 { mask = <0xf0>; @@ -3105,6 +3115,7 @@ iommus = <&apps_smmu 0x0C09 0x0>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ }; qcom,msm_fastrpc_compute_cb10 { diff --git a/qcom/kona-hdk.dtsi b/qcom/kona-hdk.dtsi index fa9050d0..b66ab46c 100755 --- a/qcom/kona-hdk.dtsi +++ b/qcom/kona-hdk.dtsi @@ -10,3 +10,12 @@ }; }; }; + +&qupv3_se6_4uart { + status = "ok"; +}; + +&qupv3_se12_2uart { + status = "ok"; +}; + diff --git a/qcom/kona-iot-v2-rb5.dtsi b/qcom/kona-iot-v2-rb5.dtsi index 8137efce..640734cf 100755 --- a/qcom/kona-iot-v2-rb5.dtsi +++ b/qcom/kona-iot-v2-rb5.dtsi @@ -1,5 +1,13 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/iio/qti_power_supply_iio.h> +#include <dt-bindings/iio/qcom,spmi-vadc.h> + +&vendor { + kona_qrd_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + }; +}; &soc { gpio_keys { @@ -25,6 +33,10 @@ status = "ok"; }; +&qupv3_se6_4uart { + status = "ok"; +}; + &pcie2 { status = "ok"; qcom,boot-option = <0x2>; @@ -84,3 +96,420 @@ status = "ok"; }; + +&pm8150l_gpios { + lt9611_rst_pin_out { + lt9611_rst_pin_out_default: lt9611_rst_pin_out_default { + pins = "gpio5"; + function = "normal"; + output-enable; + input-disable; + bias-pull-down; + power-source = <0>; + }; + }; + + rb5_fan_controller_pin_init: rb5_fan_controller_pin_init { + pins = "gpio10"; + function = "normal"; + output-enable; + input-disable; + bias-pull-down; + power-source = <0>; + }; +}; + +&L11C { + regulator-always-on; +}; + +&vreg_hap_boost { + status = "ok"; +}; + +&pm8150b_pdphy { + #io-channel-cells = <1>; + io-channels = <&pm8150b_charger PSY_IIO_PD_ACTIVE>, + <&pm8150b_charger PSY_IIO_TYPEC_CC_ORIENTATION>, + <&pm8150b_charger PSY_IIO_CONNECTOR_TYPE>, + <&pm8150b_charger PSY_IIO_TYPEC_POWER_ROLE>, + <&pm8150b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>, + <&pm8150b_charger PSY_IIO_TYPEC_SRC_RP>, + <&pm8150b_charger PSY_IIO_PD_IN_HARD_RESET>, + <&pm8150b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm8150b_charger PSY_IIO_PR_SWAP>, + <&pm8150b_charger PSY_IIO_PD_VOLTAGE_MIN>, + <&pm8150b_charger PSY_IIO_PD_VOLTAGE_MAX>, + <&pm8150b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm8150b_charger PSY_IIO_TYPEC_MODE>, + <&pm8150b_charger PSY_IIO_PE_START>; + io-channel-names = "pd_active", + "typec_cc_orientation", + "connector_type", + "typec_power_role", + "pd_usb_suspend_supported", + "typec_src_rp", + "pd_in_hard_reset", + "pr_current_max", + "pr_swap", + "pd_voltage_min", + "pd_voltage_max", + "real_type", + "typec_mode", + "pe_start"; +}; + +&pm8150b_haptics { + qcom,vmax-mv = <1697>; + qcom,play-rate-us = <5882>; + vdd-supply = <&vreg_hap_boost>; + + wf_0 { + /* CLICK */ + qcom,wf-play-rate-us = <5882>; + qcom,wf-vmax-mv = <1697>; + }; + + wf_1 { + /* DOUBLE CLICK */ + qcom,wf-play-rate-us = <5882>; + qcom,wf-vmax-mv = <1697>; + }; + + wf_2 { + /* TICK */ + qcom,wf-play-rate-us = <5882>; + qcom,wf-vmax-mv = <1697>; + }; + + wf_3 { + /* THUD */ + qcom,wf-play-rate-us = <5882>; + qcom,wf-vmax-mv = <1697>; + }; + + wf_4 { + /* POP */ + qcom,wf-play-rate-us = <5882>; + qcom,wf-vmax-mv = <1697>; + }; + + wf_5 { + /* HEAVY CLICK */ + qcom,wf-play-rate-us = <5882>; + qcom,wf-vmax-mv = <1697>; + }; +}; + +&qupv3_se15_i2c { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + + #include "smb1390.dtsi" +}; + +&smb1390 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1390_charger { + io-channels = <&pm8150b_vadc ADC5_AMUX_THM2>; + io-channel-names = "cp_die_temp"; + qcom,parallel-output-mode = <2>; + qcom,min-ilim-ua = <750000>; + qcom,parallel-input-mode = <1>; + status = "ok"; +}; + +&smb1390_slave { + status = "ok"; +}; + +&smb1390_slave_charger { + status = "ok"; +}; + +&pm8150b_charger { + #io-channel-cells = <1>; + qcom,sec-charger-config = <1>; + qcom,auto-recharge-soc = <98>; + io-channels = <&pm8150b_vadc ADC5_USB_IN_V_16>, + <&pm8150b_vadc ADC5_USB_IN_I>, + <&pm8150b_vadc ADC5_SBUx>, + <&pm8150b_vadc ADC5_VPH_PWR>, + <&pm8150b_vadc ADC5_DIE_TEMP>, + <&pm8150b_vadc ADC5_MID_CHG_DIV6>, + <&pm8150b_vadc ADC5_CHG_TEMP>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "sbux_res", + "vph_voltage", + "die_temp", + "mid_voltage", + "chg_temp"; + qcom,batteryless-platform; + qcom,lpd-disable; + qcom,sw-jeita-enable; + qcom,wd-bark-time-secs = <16>; + qcom,suspend-input-on-debug-batt; + qcom,fcc-stepping-enable; + qcom,smb-internal-pull-kohm = <0>; + qcom,thermal-mitigation = <5325000 4500000 4000000 3500000 3000000 + 2500000 2000000 1500000 1000000 500000>; +}; + +&pm8150b_fg { + status = "ok"; + qcom,battery-data = <&kona_qrd_batterydata>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,five-pin-battery; + qcom,cl-wt-enable; + qcom,soc-scale-mode-en; + /* ESR fast calibration */ + qcom,fg-esr-timer-chg-fast = <0 7>; + qcom,fg-esr-timer-dischg-fast = <0 7>; + qcom,fg-esr-timer-chg-slow = <0 96>; + qcom,fg-esr-timer-dischg-slow = <0 96>; + qcom,fg-esr-cal-soc-thresh = <26 230>; + qcom,fg-esr-cal-temp-thresh = <10 40>; +}; + +&pm8150l_vadc { + #address-cells = <1>; + #size-cells = <0>; + + vph_pwr@83 { + reg = <ADC5_VPH_PWR>; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + camera_flash_therm@4d { + reg = <ADC5_AMUX_THM1_100K_PU>; + label = "camera_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_msm_therm@4e { + reg = <ADC5_AMUX_THM2_100K_PU>; + label = "skin_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm2@4f { + reg = <ADC5_AMUX_THM3_100K_PU>; + label = "pa_therm2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150b_vadc { + #address-cells = <1>; + #size-cells = <0>; + + conn_therm@4f { + reg = <ADC5_AMUX_THM3_100K_PU>; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + mid_chg_div6@1e { + reg = <ADC5_MID_CHG_DIV6>; + label = "chg_mid"; + qcom,pre-scaling = <1 6>; + }; +}; + +&pm8150_vadc { + #address-cells = <1>; + #size-cells = <0>; + + vph_pwr@83 { + reg = <ADC5_VPH_PWR>; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm@4c { + reg = <ADC5_XO_THERM_100K_PU>; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_therm@4d { + reg = <ADC5_AMUX_THM1_100K_PU>; + label = "skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1@4e { + reg = <ADC5_AMUX_THM2_100K_PU>; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150b_adc_tm { + conn_therm@4f { + reg = <0>; + io-channels = <&pm8150b_vadc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150_adc_tm { + xo_therm@4c { + reg = <0>; + io-channels = <&pm8150_vadc ADC5_XO_THERM_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin_therm@4d { + reg = <1>; + io-channels = <&pm8150_vadc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1@4e { + reg = <2>; + io-channels = <&pm8150_vadc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150l_adc_tm { + camera_flash_therm@4d { + reg = <0>; + io-channels = <&pm8150l_vadc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin_msm_therm@4e { + reg = <1>; + io-channels = <&pm8150l_vadc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm2@4f { + reg = <2>; + io-channels = <&pm8150l_vadc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + /delete-node/ modem-lte-sub6-pa1; + /delete-node/ modem-lte-sub6-pa2; + /delete-node/ modem-mmw0-usr; + /delete-node/ modem-mmw1-usr; + /delete-node/ modem-mmw2-usr; + /delete-node/ modem-mmw3-usr; + /delete-node/ modem-skin-usr; + /delete-node/ modem-wifi-usr; + /delete-node/ modem-ambient-usr; + /delete-node/ modem-0-usr; + /delete-node/ modem-1-usr; + /delete-node/ modem-streamer-usr; + /delete-node/ modem-mmw0-mod-usr; + /delete-node/ modem-mmw1-mod-usr; + /delete-node/ modem-mmw2-mod-usr; + /delete-node/ modem-mmw3-mod-usr; + + /delete-node/ skin-therm-usr; + /delete-node/ skin-therm-step; + /delete-node/ camera-therm-usr; + + /delete-node/ mmw-pa1-usr; + /delete-node/ mmw-pa1-step; + /delete-node/ mmw-pa2-usr; + /delete-node/ mmw-pa2-step; + /delete-node/ xo-therm-step; + /delete-node/ xo-therm-usr; + /delete-node/ skin-msm-therm-step; + + pm8250-wifi-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm 22>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <52000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + pm8150l-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm 2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <50000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + pm8250-xo-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm 0>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <50000>; + hysteresis = <4000>; + type = "passive"; + }; + + }; + }; + + pm8150l-skin-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150l_adc_tm 1>; + wake-capable-sensor; + trips { + skin_trip: skin-config0 { + temperature = <50000>; + hysteresis = <48000>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/kona-iot-v2.1-rb5.dtsi b/qcom/kona-iot-v2.1-rb5.dtsi index f9940cd2..b796327d 100755 --- a/qcom/kona-iot-v2.1-rb5.dtsi +++ b/qcom/kona-iot-v2.1-rb5.dtsi @@ -1,6 +1,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include "kona-pmic-overlay.dtsi" +#include <dt-bindings/iio/qti_power_supply_iio.h> +#include <dt-bindings/iio/qcom,spmi-vadc.h> &vendor { kona_qrd_batterydata: qcom,battery-data { @@ -32,6 +33,14 @@ status = "ok"; }; +&qupv3_se6_4uart { + status = "ok"; +}; + +&qupv3_se1_i2c { + status = "ok"; +}; + &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4-kona"; vdda-phy-supply = <&pm8150_l5>; @@ -188,6 +197,37 @@ }; }; +&qupv3_se15_i2c { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + + #include "smb1390.dtsi" +}; + +&smb1390 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1390_charger { + io-channels = <&pm8150b_vadc ADC5_AMUX_THM2>; + io-channel-names = "cp_die_temp"; + qcom,parallel-output-mode = <2>; + qcom,min-ilim-ua = <750000>; + qcom,parallel-input-mode = <1>; + status = "ok"; +}; + +&smb1390_slave { + status = "ok"; +}; + +&smb1390_slave_charger { + status = "ok"; +}; + &pm8150b_charger { #io-channel-cells = <1>; qcom,sec-charger-config = <1>; @@ -388,3 +428,161 @@ &usb2_phy0 { qcom,param-override-seq = <0x43 0x70>; }; + +&qupv3_se1_i2c { + status = "ok"; + qcom,clk-freq-out = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + /* TDK Chirp IO Expander */ + ch_io_expander@22 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1508q"; + reg = <0x22>; + gpio-controller; + }; +}; + +&qupv3_se15_i2c { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + qcom,clk-freq-out = <400000>; + + /* TDK Chirp 3, 4, and 5 are connected to QUP15 */ + ch101_1: ch101_1@45 { + compatible = "invensense,ch101"; + reg = <0x45>; + rst-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>; + rtc_rst-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + prg-gpios = <3 4 5>; + int-gpios = <&tlmm 122 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>, + <&tlmm 66 GPIO_ACTIVE_HIGH>; + }; +}; + +&qupv3_se4_i2c { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + qcom,clk-freq-out = <400000>; + + /* TDK Chirp 0, 1, and 2 are connected to QUP4 */ + ch101_0: ch101_0@45 { + compatible = "invensense,ch101"; + reg = <0x45>; + rst-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>; + rtc_rst-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + prg-gpios = <0 1 2>; + int-gpios = <&tlmm 129 GPIO_ACTIVE_HIGH>, + <&tlmm 141 GPIO_ACTIVE_HIGH>, + <&tlmm 113 GPIO_ACTIVE_HIGH>; + }; +}; + +&qupv3_se17_spi { + status = "okay"; + temp_sensor@0 { + compatible = "tdktherm"; + reg = <0>; // Chip select ID + spi-max-frequency = <10000000>; // Can support up to 24 MHz + spi-cpol; + spi-cpha; + status = "okay"; + }; +}; + +&thermal_zones { + /delete-node/ modem-lte-sub6-pa1; + /delete-node/ modem-lte-sub6-pa2; + /delete-node/ modem-mmw0-usr; + /delete-node/ modem-mmw1-usr; + /delete-node/ modem-mmw2-usr; + /delete-node/ modem-mmw3-usr; + /delete-node/ modem-skin-usr; + /delete-node/ modem-wifi-usr; + /delete-node/ modem-ambient-usr; + /delete-node/ modem-0-usr; + /delete-node/ modem-1-usr; + /delete-node/ modem-streamer-usr; + /delete-node/ modem-mmw0-mod-usr; + /delete-node/ modem-mmw1-mod-usr; + /delete-node/ modem-mmw2-mod-usr; + /delete-node/ modem-mmw3-mod-usr; + + /delete-node/ skin-therm-usr; + /delete-node/ skin-therm-step; + /delete-node/ camera-therm-usr; + + /delete-node/ mmw-pa1-usr; + /delete-node/ mmw-pa1-step; + /delete-node/ mmw-pa2-usr; + /delete-node/ mmw-pa2-step; + /delete-node/ xo-therm-step; + /delete-node/ xo-therm-usr; + /delete-node/ skin-msm-therm-step; + + pm8250-wifi-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm 22>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <52000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + pm8150l-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm 2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <50000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + pm8250-xo-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm 0>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <50000>; + hysteresis = <4000>; + type = "passive"; + }; + + }; + }; + + pm8150l-skin-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150l_adc_tm 1>; + wake-capable-sensor; + trips { + skin_trip: skin-config0 { + temperature = <50000>; + hysteresis = <48000>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/kona-iot-v2.1-vc.dtsi b/qcom/kona-iot-v2.1-vc.dtsi index 01713786..0daced82 100755 --- a/qcom/kona-iot-v2.1-vc.dtsi +++ b/qcom/kona-iot-v2.1-vc.dtsi @@ -3,3 +3,7 @@ &dwc1 { dr_mode = "host"; }; + +&pcie2 { + qcom,boot-option = <0x0>; +}; diff --git a/qcom/kona-iot-vc.dtsi b/qcom/kona-iot-vc.dtsi index 1f120cdb..21a34adc 100755 --- a/qcom/kona-iot-vc.dtsi +++ b/qcom/kona-iot-vc.dtsi @@ -1,5 +1,7 @@ #include <dt-bindings/gpio/gpio.h> -#include "kona-pmic-overlay.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/iio/qti_power_supply_iio.h> +#include <dt-bindings/iio/qcom,spmi-vadc.h> &vendor { kona_qrd_batterydata: qcom,battery-data { @@ -93,6 +95,10 @@ status = "ok"; }; +&qupv3_se6_4uart { + status = "ok"; +}; + &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4"; vdda-phy-supply = <&pm8150_l5>; diff --git a/qcom/kona-pinctrl.dtsi b/qcom/kona-pinctrl.dtsi index 2f5ea535..8877c24b 100755 --- a/qcom/kona-pinctrl.dtsi +++ b/qcom/kona-pinctrl.dtsi @@ -3052,6 +3052,58 @@ }; }; + ch101_rst: ch101_rst { + mux { + pins = "gpio140"; + function = "gpio"; + }; + + config { + pins = "gpio140"; + output-high; + drive-strength = <2>; + }; + }; + + ch101_tmr_rst: ch101_tmr_rst { + mux { + pins = "gpio0"; + function = "gpio"; + }; + + config { + pins = "gpio0"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + ch101_0_irq: ch101_0_irq { + mux { + pins = "gpio129", "gpio141", "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio129", "gpio141", "gpio113"; + bias-no-pull; + drive-strength = <2>; + }; + }; + + ch101_1_irq: ch101_1_irq { + mux { + pins = "gpio122", "gpio123", "gpio66"; + function = "gpio"; + }; + + config { + pins = "gpio122", "gpio123", "gpio66"; + bias-no-pull; + drive-strength = <2>; + }; + }; + /* QUPv3_0 North SE0 mappings */ qupv3_se0_i3c_pins: qupv3_se0_i3c_pins { qupv3_se0_i3c_active: qupv3_se0_i3c_active { diff --git a/qcom/kona-pmic-overlay.dtsi b/qcom/kona-pmic-overlay.dtsi index 1c290005..fbb48688 100755 --- a/qcom/kona-pmic-overlay.dtsi +++ b/qcom/kona-pmic-overlay.dtsi @@ -19,11 +19,13 @@ reg = <0x8 SPMI_USID>; #address-cells = <2>; #size-cells = <0>; + status = "disabled"; qcom,power-on@800 { compatible = "qcom,qpnp-power-on"; reg = <0x800 0x100>; qcom,modem-reset; + status = "disabled"; }; }; @@ -32,6 +34,7 @@ reg = <0x9 SPMI_USID>; #address-cells = <2>; #size-cells = <0>; + status = "disabled"; }; }; diff --git a/qcom/kona-rb5-HDMI.dtsi b/qcom/kona-rb5-HDMI.dtsi index ab445afb..cb68d8b4 100755 --- a/qcom/kona-rb5-HDMI.dtsi +++ b/qcom/kona-rb5-HDMI.dtsi @@ -25,6 +25,10 @@ status = "ok"; }; +&qupv3_se6_4uart { + status = "ok"; +}; + &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4-kona"; vdda-phy-supply = <&pm8150_l5>; diff --git a/qcom/kona.dtsi b/qcom/kona.dtsi index 8f8a0ed6..f8664f02 100755 --- a/qcom/kona.dtsi +++ b/qcom/kona.dtsi @@ -42,6 +42,7 @@ aliases { ufshc1 = &ufshc_mem; /* Embedded UFS slot */ serial0 = &qupv3_se12_2uart; + hsuart0 = &qupv3_se6_4uart; pci-domain0 = &pcie0; /* PCIe0 domain */ pci-domain1 = &pcie1; /* PCIe1 domain */ pci-domain2 = &pcie2; /* PCIe2 domain */ @@ -421,6 +422,10 @@ compatible = "qcom,tee-shared-memory-bridge"; }; + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + android { compatible = "android,firmware"; vbmeta { @@ -563,16 +568,6 @@ size = <0x0 0x400000>; }; - cont_splash_memory: cont_splash_region@9c000000 { - reg = <0x0 0x9c000000 0x0 0x02300000>; - label = "cont_splash_region"; - }; - - disp_rdump_memory: disp_rdump_region@9c000000 { - reg = <0x0 0x9c000000 0x0 0x00800000>; - label = "disp_rdump_region"; - }; - dfps_data_memory: dfps_data_region@9e300000 { reg = <0x0 0x9e300000 0x0 0x0100000>; label = "dfps_data_region"; @@ -804,6 +799,14 @@ qcom,qsee-reentrancy-support = <2>; }; + qcom_tzlog: tz-log@146bf720 { + compatible = "qcom,tz-log"; + reg = <0x146bf720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + cpu_pmu: cpu-pmu { compatible = "arm,armv8-pmuv3"; qcom,irq-is-percpu; @@ -1757,13 +1760,13 @@ qcom,target-dev = <&qcom_ddr_dcvs_hw>; }; - qcom,chd_silver { + qcom,chd { compatible = "qcom,core-hang-detect"; - label = "silver"; - qcom,threshold-arr = <0x18000058 0x18010058 - 0x18020058 0x18030058>; - qcom,config-arr = <0x18000060 0x18010060 - 0x18020060 0x18030060>; + label = "core"; + qcom,threshold-arr = <0x18000058 0x18010058 0x18020058 0x18030058 + 0x18040058 0x18050058 0x18060058 0x18070058>; + qcom,config-arr = <0x18000060 0x18010060 0x18020060 0x18030060 + 0x18040060 0x18050060 0x18060060 0x18070060>; }; dsu_pmu@0 { @@ -1773,15 +1776,6 @@ <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; }; - qcom,chd_gold { - compatible = "qcom,core-hang-detect"; - label = "gold"; - qcom,threshold-arr = <0x18040058 0x18050058 - 0x18060058 0x18070058>; - qcom,config-arr = <0x18040060 0x18050060 - 0x18060060 0x18070060>; - }; - ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>; /* PHY regs */ reg-names = "phy_mem"; @@ -2695,7 +2689,7 @@ slpi_pas: remoteproc-slpi@5c00000 { compatible = "qcom,kona-slpi-pas"; reg = <0x5c00000 0x4000>; - status = "disabled"; + status = "ok"; cx-supply = <&L11A_LEVEL>; cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>; diff --git a/qcom/lemans-adp-air.dtsi b/qcom/lemans-adp-air.dtsi index d14e1d28..fccf29b5 100755 --- a/qcom/lemans-adp-air.dtsi +++ b/qcom/lemans-adp-air.dtsi @@ -1,5 +1,3 @@ -#include "lemans-adp-common.dtsi" - &cdsp1_pas { status = "disabled"; }; diff --git a/qcom/lemans-adp-star.dtsi b/qcom/lemans-adp-star.dtsi index d14e1d28..fccf29b5 100755 --- a/qcom/lemans-adp-star.dtsi +++ b/qcom/lemans-adp-star.dtsi @@ -1,5 +1,3 @@ -#include "lemans-adp-common.dtsi" - &cdsp1_pas { status = "disabled"; }; diff --git a/qcom/lemans-dma-heaps.dtsi b/qcom/lemans-dma-heaps.dtsi index 75ffb7b7..44bcdf22 100755 --- a/qcom/lemans-dma-heaps.dtsi +++ b/qcom/lemans-dma-heaps.dtsi @@ -24,12 +24,6 @@ memory-region = <&non_secure_display_memory>; }; - qcom,secure_display { - qcom,dma-heap-name = "qcom,secure-display"; - qcom,dma-heap-type = <HEAP_TYPE_CMA>; - memory-region = <&secure_display_memory>; - }; - qcom,adsp { qcom,dma-heap-name = "qcom,adsp"; qcom,dma-heap-type = <HEAP_TYPE_CMA>; diff --git a/qcom/lemans-thermal.dtsi b/qcom/lemans-thermal.dtsi index 07a2aaa1..c991ec75 100755 --- a/qcom/lemans-thermal.dtsi +++ b/qcom/lemans-thermal.dtsi @@ -10,8 +10,8 @@ reg = <0x0C263000 0x1ff>, <0x0C222000 0x1ff>; #qcom,sensors = <12>; - interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow","critical"; #thermal-sensor-cells = <1>; }; @@ -21,8 +21,8 @@ reg = <0x0C265000 0x1ff>, <0x0C223000 0x1ff>; #qcom,sensors = <12>; - interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow","critical"; #thermal-sensor-cells = <1>; }; @@ -32,8 +32,8 @@ reg = <0x0C251000 0x1ff>, <0x0C224000 0x1ff>; #qcom,sensors = <13>; - interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow","critical"; #thermal-sensor-cells = <1>; }; @@ -43,8 +43,8 @@ reg = <0x0C252000 0x1ff>, <0x0C225000 0x1ff>; #qcom,sensors = <13>; - interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow","critical"; #thermal-sensor-cells = <1>; }; diff --git a/qcom/lemans-usb.dtsi b/qcom/lemans-usb.dtsi index 1a34f303..9aef9396 100755 --- a/qcom/lemans-usb.dtsi +++ b/qcom/lemans-usb.dtsi @@ -491,7 +491,8 @@ snps,usb2-gadget-lpm-disable; tx-fifo-resize; maximum-speed = "high-speed"; - dr_mode = "host"; + dr_mode = "otg"; + usb-role-switch; }; }; diff --git a/qcom/lemans-vm-la.dtsi b/qcom/lemans-vm-la.dtsi index eb7bd3a2..0ef5c816 100755 --- a/qcom/lemans-vm-la.dtsi +++ b/qcom/lemans-vm-la.dtsi @@ -2,6 +2,10 @@ }; / { + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 cgroup.memory=nokmem,nosocket kpti=0 qcom_dma_heaps.enable_bitstream_contig_heap=y arm64.nopauth kasan=off msm_show_resume_irq.debug_mask=1 androidboot.usbcontroller=a600000.dwc3 androidboot.fstab_suffix=gen4.qcom"; + }; + rename_devices: rename_devices { compatible = "qcom,rename-devices"; rename_blk: rename_blk { @@ -61,3 +65,11 @@ &qupv3_se17_4uart { status = "ok"; }; + +&pcie0 { + status = "ok"; +}; + +&pcie0_msi_snps { + status = "ok"; +}; diff --git a/qcom/lemans-vm-lv.dtsi b/qcom/lemans-vm-lv.dtsi index 4e85f50a..de77f923 100755 --- a/qcom/lemans-vm-lv.dtsi +++ b/qcom/lemans-vm-lv.dtsi @@ -40,3 +40,15 @@ &usb2_phy2 { status = "ok"; }; + +&qcom_rng_ee3 { + status = "okay"; +}; + +&pcie0 { + status = "ok"; +}; + +&pcie0_msi_snps { + status = "ok"; +}; diff --git a/qcom/lemans-vm-pcie.dtsi b/qcom/lemans-vm-pcie.dtsi new file mode 100755 index 00000000..f6b0b771 --- /dev/null +++ b/qcom/lemans-vm-pcie.dtsi @@ -0,0 +1,602 @@ +#include <dt-bindings/clock/qcom,gcc-lemans.h> +#include <dt-bindings/gpio/gpio.h> + +&soc { + pcie0: qcom,pcie@0x01c00000 { + compatible = "qcom,pci-msm"; + + reg = <0x01c00000 0x3000>, + <0x1c04000 0x2000>, + <0x40000000 0xf20>, + <0x40000f20 0xa8>, + <0x40001000 0x4000>, + <0x40100000 0x100000>, + <0x01c03000 0x1000>; + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "mhi"; + + cell-index = <0>; + linux,pci-domain = <0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>; + + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + + perst-gpio = <&tlmm 2 GPIO_ACTIVE_HIGH>; + wake-gpio = <&tlmm 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie0_perst_default + &pcie0_clkreq_default + &pcie0_wake_default>; + pinctrl-1 = <&pcie0_perst_default + &pcie0_clkreq_sleep + &pcie0_wake_default>; + + gdsc-core-vdd-supply = <&gcc_pcie_0_gdsc>; + vreg-1p2-supply = <&L1C>; + vreg-0p9-supply = <&L5A>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MXC_LEVEL>; + + qcom,vreg-1p2-voltage-level = <1200000 1200000 25800>; + qcom,vreg-0p9-voltage-level = <880000 880000 186000>; + qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX + RPMH_REGULATOR_LEVEL_NOM 0>; + qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX + RPMH_REGULATOR_LEVEL_NOM 0>; + + qcom,bw-scale = /* Gen1 */ + <RPMH_REGULATOR_LEVEL_SVS_L1 + RPMH_REGULATOR_LEVEL_SVS_L1 + 19200000 + /* Gen2 */ + RPMH_REGULATOR_LEVEL_SVS_L1 + RPMH_REGULATOR_LEVEL_SVS_L1 + 19200000 + /* Gen3 */ + RPMH_REGULATOR_LEVEL_SVS_L1 + RPMH_REGULATOR_LEVEL_SVS_L1 + 100000000 + /* Gen4 */ + RPMH_REGULATOR_LEVEL_NOM + RPMH_REGULATOR_LEVEL_NOM + 100000000>; + + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&rpmh_cxo_clk>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&gcc GCC_PCIE_0_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, + <&pcie_0_pipe_clk>; + + clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", + "pcie_0_slv_q2a_axi_clk", "pcie_phy_refgen_clk", + "pcie_pipe_clk_mux", "pcie_phy_aux_clk", + "pcie_0_pipediv2_clk", + "pcie_pipe_clk_ext_src"; + + clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <100000000>, <0>, + <0>, <0>, <0>; + + clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, + <0>, <0>, <0>, <0>, <0>, <0>; + + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + dma-coherent; + + msi-parent = <&pcie0_msi_snps>; + qcom,smmu-sid-base = <0x0000>; + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>, + <0x200 &pcie_smmu 0x0002 0x1>, + <0x300 &pcie_smmu 0x0003 0x1>, + <0x400 &pcie_smmu 0x0004 0x1>, + <0x500 &pcie_smmu 0x0005 0x1>, + <0x600 &pcie_smmu 0x0006 0x1>, + <0x700 &pcie_smmu 0x0007 0x1>, + <0x800 &pcie_smmu 0x0008 0x1>, + <0x900 &pcie_smmu 0x0009 0x1>, + <0xa00 &pcie_smmu 0x000a 0x1>, + <0xb00 &pcie_smmu 0x000b 0x1>, + <0xc00 &pcie_smmu 0x000c 0x1>, + <0xd00 &pcie_smmu 0x000d 0x1>, + <0xe00 &pcie_smmu 0x000e 0x1>, + <0xf00 &pcie_smmu 0x000f 0x1>; + + qcom,boot-option = <0x0>; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ + qcom,slv-addr-space-size = <0x1fd00000>; + qcom,ep-latency = <10>; + qcom,core-preset = <0x77777777>; + + qcom,pcie-phy-ver = <109>; + qcom,phy-status-offset = <0x1214>; + qcom,phy-status-bit = <7>; + qcom,phy-power-down-offset = <0x1240>; + qcom,phy-sequence = <0x1240 0x03 0x0 + 0x1010 0x00 0x0 + 0x101c 0x31 0x0 + 0x1020 0x01 0x0 + 0x1024 0xde 0x0 + 0x1028 0x07 0x0 + 0x1030 0x97 0x0 + 0x1034 0x0c 0x0 + 0x1044 0x14 0x0 + 0x1048 0x90 0x0 + 0x1058 0x0f 0x0 + 0x1074 0x06 0x0 + 0x1078 0x06 0x0 + 0x107c 0x16 0x0 + 0x1080 0x16 0x0 + 0x1084 0x36 0x0 + 0x1088 0x36 0x0 + 0x1094 0x08 0x0 + 0x10a4 0x46 0x0 + 0x10a8 0x04 0x0 + 0x10ac 0x0a 0x0 + 0x10b0 0x1a 0x0 + 0x10b4 0x14 0x0 + 0x10b8 0x34 0x0 + 0x10bc 0x82 0x0 + 0x10c4 0xd0 0x0 + 0x10cc 0x55 0x0 + 0x10d0 0x55 0x0 + 0x10d4 0x03 0x0 + 0x10d8 0x55 0x0 + 0x10dc 0x55 0x0 + 0x10e0 0x05 0x0 + 0x110c 0x02 0x0 + 0x1154 0x34 0x0 + 0x1158 0x12 0x0 + 0x115c 0x00 0x0 + 0x1168 0x0a 0x0 + 0x116c 0x04 0x0 + 0x119c 0x88 0x0 + 0x1174 0x60 0x0 + 0x117c 0x06 0x0 + 0x11a0 0x14 0x0 + 0x11a8 0x0f 0x0 + 0x0220 0x16 0x0 + 0x03c0 0x38 0x0 + 0x0a20 0x16 0x0 + 0x0bc0 0x38 0x0 + 0x0360 0x9a 0x0 + 0x0364 0xb0 0x0 + 0x0368 0x92 0x0 + 0x036c 0xf0 0x0 + 0x0370 0x42 0x0 + 0x0374 0x99 0x0 + 0x0378 0x29 0x0 + 0x037c 0x9a 0x0 + 0x0380 0xfb 0x0 + 0x0384 0x92 0x0 + 0x0388 0xec 0x0 + 0x038c 0x43 0x0 + 0x0390 0xdd 0x0 + 0x0394 0x0d 0x0 + 0x0398 0xf3 0x0 + 0x039c 0xf8 0x0 + 0x03a0 0xec 0x0 + 0x03a4 0xd6 0x0 + 0x03a8 0x83 0x0 + 0x03ac 0xf5 0x0 + 0x03b0 0x5e 0x0 + 0x0b60 0x9a 0x0 + 0x0b64 0xb0 0x0 + 0x0b68 0x92 0x0 + 0x0b6c 0xf0 0x0 + 0x0b70 0x42 0x0 + 0x0b74 0x99 0x0 + 0x0b78 0x29 0x0 + 0x0b7c 0x9a 0x0 + 0x0b80 0xfb 0x0 + 0x0b84 0x92 0x0 + 0x0b88 0xec 0x0 + 0x0b8c 0x43 0x0 + 0x0b90 0xdd 0x0 + 0x0b94 0x0d 0x0 + 0x0b98 0xf3 0x0 + 0x0b9c 0xf8 0x0 + 0x0ba0 0xec 0x0 + 0x0ba4 0xd6 0x0 + 0x0ba8 0x83 0x0 + 0x0bac 0xf5 0x0 + 0x0bb0 0x5e 0x0 + 0x03b4 0x20 0x0 + 0x022c 0x3f 0x0 + 0x0230 0x37 0x0 + 0x0bb4 0x20 0x0 + 0x0a2c 0x3f 0x0 + 0x0a30 0x37 0x0 + 0x0078 0x05 0x0 + 0x007c 0xf6 0x0 + 0x0080 0x0f 0x0 + 0x0878 0x05 0x0 + 0x087c 0xf6 0x0 + 0x0880 0x0f 0x0 + 0x0290 0x00 0x0 + 0x0a90 0x00 0x0 + 0x03f8 0x1f 0x0 + 0x0400 0x1f 0x0 + 0x0408 0x1f 0x0 + 0x0410 0x1f 0x0 + 0x0418 0x1f 0x0 + 0x0420 0x1f 0x0 + 0x03f4 0x1f 0x0 + 0x03fc 0x1f 0x0 + 0x0404 0x1f 0x0 + 0x0bf8 0x1f 0x0 + 0x0c00 0x1f 0x0 + 0x0c08 0x1f 0x0 + 0x0c10 0x1f 0x0 + 0x0c18 0x1f 0x0 + 0x0c20 0x1f 0x0 + 0x0bf4 0x1f 0x0 + 0x0bfc 0x1f 0x0 + 0x0c04 0x1f 0x0 + 0x0438 0x09 0x0 + 0x0c38 0x09 0x0 + 0x0208 0x0c 0x0 + 0x0a08 0x0c 0x0 + 0x020c 0x08 0x0 + 0x0a0c 0x08 0x0 + 0x021c 0x04 0x0 + 0x0a1c 0x04 0x0 + 0x02d4 0x04 0x0 + 0x0ad4 0x04 0x0 + 0x02dc 0x08 0x0 + 0x0adc 0x08 0x0 + 0x0308 0x0b 0x0 + 0x0b08 0x0b 0x0 + 0x0318 0x7c 0x0 + 0x0b18 0x7c 0x0 + 0x027c 0x10 0x0 + 0x0a7c 0x10 0x0 + 0x02b4 0x00 0x0 + 0x0ab4 0x00 0x0 + 0x02ec 0x05 0x0 + 0x0aec 0x05 0x0 + 0x02c4 0x00 0x0 + 0x02c8 0x1f 0x0 + 0x0ac4 0x00 0x0 + 0x0ac8 0x1f 0x0 + 0x0030 0x1f 0x0 + 0x0034 0x07 0x0 + 0x0830 0x1f 0x0 + 0x0834 0x07 0x0 + 0x141c 0xc1 0x0 + 0x1490 0x00 0x0 + 0x13e0 0x16 0x0 + 0x13e4 0x22 0x0 + 0x1508 0x02 0x0 + 0x14a0 0x16 0x0 + 0x1584 0x28 0x0 + 0x1370 0x2e 0x0 + 0x155c 0x2e 0x0 + 0x140c 0x1d 0x0 + 0x1388 0x66 0x0 + 0x1e24 0x00 0x0 + 0x1e28 0x00 0x0 + 0x1828 0x00 0x0 + 0x1c28 0x00 0x0 + 0x127c 0x00 0x0 + 0x1260 0x00 0x0 + 0x1200 0x00 0x0 + 0x1244 0x03 0x0>; + + status = "disabled"; + + pcie0_rp: pcie0_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie1: qcom,pcie@0x01c10000 { + compatible = "qcom,pci-msm"; + + reg = <0x01c10000 0x3000>, + <0x01c14000 0x4000>, + <0x60000000 0xf20>, + <0x60000f20 0xa8>, + <0x60001000 0x4000>, + <0x60100000 0x100000>, + <0x01c13000 0x1000>; + reg-names = "parf", "phy", "dm_core", + "elbi", "iatu", "conf", "mhi"; + + cell-index = <1>; + linux,pci-domain = <1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x60300000 0x0 0x1fd00000>; + + interrupt-parent = <&pcie1>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc 0 GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc 0 GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + + perst-gpio = <&tlmm 4 GPIO_ACTIVE_HIGH>; + wake-gpio = <&tlmm 5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie1_perst_default + &pcie1_clkreq_default + &pcie1_wake_default>; + pinctrl-1 = <&pcie1_perst_default + &pcie1_clkreq_sleep + &pcie1_wake_default>; + + gdsc-core-vdd-supply = <&gcc_pcie_1_gdsc>; + vreg-1p2-supply = <&L1C>; + vreg-0p9-supply = <&L5A>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MXC_LEVEL>; + + qcom,vreg-1p2-voltage-level = <1200000 1200000 33300>; + qcom,vreg-0p9-voltage-level = <880000 880000 439000>; + qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX + RPMH_REGULATOR_LEVEL_NOM 0>; + qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX + RPMH_REGULATOR_LEVEL_NOM 0>; + + qcom,bw-scale = /* Gen1 */ + <RPMH_REGULATOR_LEVEL_SVS_L1 + RPMH_REGULATOR_LEVEL_SVS_L1 + 19200000 + /* Gen2 */ + RPMH_REGULATOR_LEVEL_SVS_L1 + RPMH_REGULATOR_LEVEL_SVS_L1 + 19200000 + /* Gen3 */ + RPMH_REGULATOR_LEVEL_SVS_L1 + RPMH_REGULATOR_LEVEL_SVS_L1 + 100000000 + /* Gen4 */ + RPMH_REGULATOR_LEVEL_NOM + RPMH_REGULATOR_LEVEL_NOM + 100000000>; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&rpmh_cxo_clk>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, + <&gcc GCC_PCIE_1_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>, + <&pcie_1_pipe_clk>; + + clock-names = "pcie_pipe_clk", "pcie_ref_clk_src", + "pcie_1_aux_clk", "pcie_1_cfg_ahb_clk", + "pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk", + "pcie_1_ldo", + "pcie_1_slv_q2a_axi_clk", "pcie_phy_refgen_clk", + "pcie_pipe_clk_mux", "pcie_phy_aux_clk", + "pcie_1_pipediv2_clk", + "pcie_pipe_clk_ext_src"; + + clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <100000000>, <0>, + <0>, <0>, <0>; + + clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, + <0>, <0>, <0>, <0>, <0>, <0>; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "pcie_1_core_reset", + "pcie_1_phy_reset"; + + dma-coherent; + + msi-parent = <&pcie1_msi_snps>; + qcom,smmu-sid-base = <0x0080>; + iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, + <0x100 &pcie_smmu 0x0081 0x1>, + <0x200 &pcie_smmu 0x0082 0x1>, + <0x300 &pcie_smmu 0x0083 0x1>, + <0x400 &pcie_smmu 0x0084 0x1>, + <0x500 &pcie_smmu 0x0085 0x1>, + <0x600 &pcie_smmu 0x0086 0x1>, + <0x700 &pcie_smmu 0x0087 0x1>, + <0x800 &pcie_smmu 0x0088 0x1>, + <0x900 &pcie_smmu 0x0089 0x1>, + <0xa00 &pcie_smmu 0x008a 0x1>, + <0xb00 &pcie_smmu 0x008b 0x1>, + <0xc00 &pcie_smmu 0x008c 0x1>, + <0xd00 &pcie_smmu 0x008d 0x1>, + <0xe00 &pcie_smmu 0x008e 0x1>, + <0xf00 &pcie_smmu 0x008f 0x1>; + + qcom,boot-option = <0x0>; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ + qcom,slv-addr-space-size = <0x1fd00000>; + qcom,ep-latency = <10>; + qcom,core-preset = <0x77777777>; + + qcom,pcie-phy-ver = <1093>; + qcom,phy-status-offset = <0x2214>; + qcom,phy-status-bit = <7>; + qcom,phy-power-down-offset = <0x2240>; + + qcom,phy-sequence = <0x2240 0x03 0x0 + 0x2010 0x00 0x0 + 0x201c 0x31 0x0 + 0x2020 0x01 0x0 + 0x2024 0xde 0x0 + 0x2028 0x07 0x0 + 0x2030 0x97 0x0 + 0x2034 0x0c 0x0 + 0x2044 0x1c 0x0 + 0x2048 0x90 0x0 + 0x2058 0x0f 0x0 + 0x2074 0x06 0x0 + 0x2078 0x06 0x0 + 0x207c 0x16 0x0 + 0x2080 0x16 0x0 + 0x2084 0x36 0x0 + 0x2088 0x36 0x0 + 0x2094 0x08 0x0 + 0x20a4 0x46 0x0 + 0x20a8 0x04 0x0 + 0x20ac 0x0a 0x0 + 0x20b0 0x1a 0x0 + 0x20b4 0x14 0x0 + 0x20b8 0x34 0x0 + 0x20bc 0x82 0x0 + 0x20c4 0xd0 0x0 + 0x20cc 0x55 0x0 + 0x20d0 0x55 0x0 + 0x20d4 0x03 0x0 + 0x20d8 0x55 0x0 + 0x20dc 0x55 0x0 + 0x20e0 0x05 0x0 + 0x210c 0x02 0x0 + 0x2154 0x34 0x0 + 0x2158 0x12 0x0 + 0x215c 0x00 0x0 + 0x2168 0x0a 0x0 + 0x216c 0x04 0x0 + 0x219c 0x88 0x0 + 0x2174 0x60 0x0 + 0x217c 0x06 0x0 + 0x21a0 0x14 0x0 + 0x21a8 0x0f 0x0 + 0x3a2c 0x3f 0x0 + 0x3a30 0x37 0x0 + 0x3a90 0x00 0x0 + 0x3bc0 0x38 0x0 + 0x3ab4 0x00 0x0 + 0x3aec 0x05 0x0 + 0x3bb4 0x20 0x0 + 0x3b08 0x0b 0x0 + 0x3b18 0x7c 0x0 + 0x3a7c 0x10 0x0 + 0x3bf4 0x1f 0x0 + 0x3bf8 0x1f 0x0 + 0x3bfc 0x1f 0x0 + 0x3c00 0x1f 0x0 + 0x3c04 0x1f 0x0 + 0x3c08 0x1f 0x0 + 0x3c10 0x1f 0x0 + 0x3c18 0x1f 0x0 + 0x3c20 0x1f 0x0 + 0x3c38 0x09 0x0 + 0x3b60 0x9a 0x0 + 0x3b64 0xb0 0x0 + 0x3b68 0x92 0x0 + 0x3b6c 0xf0 0x0 + 0x3b70 0x42 0x0 + 0x3b74 0x99 0x0 + 0x3b78 0x29 0x0 + 0x3b7c 0x9a 0x0 + 0x3b80 0xb6 0x0 + 0x3b84 0x92 0x0 + 0x3b88 0xf0 0x0 + 0x3b8c 0x43 0x0 + 0x3b90 0xdd 0x0 + 0x3b94 0x0d 0x0 + 0x3b98 0xf3 0x0 + 0x3b9c 0xf6 0x0 + 0x3ba0 0xee 0x0 + 0x3ba4 0xd2 0x0 + 0x3ba8 0x83 0x0 + 0x3bac 0xf9 0x0 + 0x3bb0 0x3d 0x0 + 0x3ac4 0x00 0x0 + 0x3ac8 0x1f 0x0 + 0x3a08 0x0c 0x0 + 0x3a0c 0x08 0x0 + 0x3a1c 0x04 0x0 + 0x3a20 0x16 0x0 + 0x3ad4 0x04 0x0 + 0x3adc 0x08 0x0 + 0x3878 0x05 0x0 + 0x387c 0xf6 0x0 + 0x3880 0x0f 0x0 + 0x3834 0x07 0x0 + 0x3830 0x1f 0x0 + 0x241c 0xc1 0x0 + 0x2490 0x00 0x0 + 0x23e0 0x16 0x0 + 0x23e4 0x22 0x0 + 0x2508 0x02 0x0 + 0x24a0 0x16 0x0 + 0x2584 0x28 0x0 + 0x2370 0x2e 0x0 + 0x255c 0x2e 0x0 + 0x2388 0x66 0x0 + 0x240c 0x1d 0x0 + 0x2200 0x00 0x0 + 0x2244 0x03 0x0>; + + status = "disabled"; + + pcie1_rp: pcie1_rp { + reg = <0 0 0 0 0>; + }; + }; + + pcie0_msi_snps: qcom,pcie0_msi@a0000000 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0xa0000000 0x0>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; + qcom,snps; + status = "disabled"; + }; + + pcie1_msi_snps: qcom,pcie1_msi@a0000000 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0xa0000000 0x0>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>; + qcom,snps; + status = "disabled"; + }; +}; + diff --git a/qcom/lemans-vm-usb.dtsi b/qcom/lemans-vm-usb.dtsi index 471dbd2d..dd00bc3d 100755 --- a/qcom/lemans-vm-usb.dtsi +++ b/qcom/lemans-vm-usb.dtsi @@ -488,7 +488,8 @@ snps,usb2-gadget-lpm-disable; tx-fifo-resize; maximum-speed = "high-speed"; - dr_mode = "host"; + dr_mode = "otg"; + usb-role-switch; }; }; diff --git a/qcom/lemans-vm.dtsi b/qcom/lemans-vm.dtsi index 3a610881..5998c4ad 100755 --- a/qcom/lemans-vm.dtsi +++ b/qcom/lemans-vm.dtsi @@ -85,7 +85,8 @@ reg-names = "base", "tcu-base"; #iommu-cells = <2>; qcom,skip-init; - qcom,handoff-smrs = <0x100 0x0>,<0x420 0x0>,<0x20 0x0>,<0x80 0x0>,<0xa0 0x0>,<0x1800 0x402>,<0x1000 0x402>,<0x1001 0x400>,<0x4a0 0x40>,<0x4c0 0x0>,<0x120 0xf>,<0x1801 0x400>,<0x140 0xf>,<0x880 0x400>,<0x887 0x400>,<0x883 0x400>,<0x881 0x404>,<0x884 0x400>,<0x8a0 0x400>,<0x8a3 0x400>,<0x8a4 0x400>,<0x460 0x0>,<0x461 0x0>,<0x462 0x0>,<0x860 0x400>,<0x840 0x480>,<0x800 0x0>,<0xc00 0x0>,<0x3400 0x0>,<0x3420 0x0>,<0x3403 0x20>,<0x803 0x400>,<0x3001 0x0>,<0x3003 0x0>,<0x3005 0x0>,<0x21c1 0x0>,<0x25c1 0x0>,<0x2161 0x0>,<0x2561 0x0>,<0x2141 0x0>,<0x2541 0x0>,<0x21e1 0x0>,<0x25e1 0x0>,<0x2181 0x0>,<0x2581 0x0>,<0x21c2 0x0>,<0x2162 0x0>,<0x2562 0x0>,<0x25c2 0x0>,<0x2142 0x0>,<0x2542 0x0>,<0x21e2 0x0>,<0x25e2 0x0>,<0x2182 0x0>,<0x2582 0x0>,<0x21c3 0x0>,<0x2163 0x0>,<0x2563 0x0>,<0x25c3 0x0>,<0x2143 0x0>,<0x2543 0x0>,<0x21e3 0x0>,<0x25e3 0x0>,<0x2183 0x0>,<0x2583 0x0>,<0x21c4 0x0>,<0x25c4 0x0>,<0x2164 0x0>,<0x2564 0x0>,<0x2144 0x0>,<0x2544 0x0>,<0x21e4 0x0>,<0x25e4 0x0>,<0x2184 0x0>,<0x2584 0x0>,<0x2961 0x0>,<0x2d61 0x0>,<0x29c1 0x0>,<0x2dc1 0x0>,<0x2941 0x0>,<0x2d41 0x0>,<0x29e1 0x0>,<0x2de1 0x0>,<0x2981 0x0>,<0x2d81 0x0>,<0x2962 0x0>,<0x2d62 0x0>,<0x29c2 0x0>,<0x2dc2 0x0>,<0x2942 0x0>,<0x2d42 0x0>,<0x29e2 0x0>,<0x2de2 0x0>,<0x2982 0x0>,<0x2d82 0x0>,<0x2963 0x0>,<0x2d63 0x0>,<0x29c3 0x0>,<0x2dc3 0x0>,<0x2943 0x0>,<0x2d43 0x0>,<0x29e3 0x0>,<0x2de3 0x0>,<0x2983 0x0>,<0x2d83 0x0>,<0x2964 0x0>,<0x2d64 0x0>,<0x29c4 0x0>,<0x2dc4 0x0>,<0x2944 0x0>,<0x2d44 0x0>,<0x29e4 0x0>,<0x2de4 0x0>,<0x2984 0x0>,<0x2d84 0x0>,<0x416 0x0>,<0x456 0x0>,<0x5b6 0x0>,<0x56 0x0>,<0x403 0x0>,<0x443 0x0>,<0x5a3 0x0>,<0x43 0x0>,<0x38a1 0x0>,<0x38a2 0x0>,<0x38a3 0x0>,<0x38c1 0x0>,<0x38c2 0x0>,<0x38c3 0x0>,<0x481 0x0>,<0x5c1 0x0>,<0x480 0x0>,<0x5c0 0x0>,<0x580 0x0>,<0x882 0x400>,<0x29c0 0x400>,<0x21c0 0x400>,<0x45 0x0>,<0x5a5 0x0>,<0x445 0x0>,<0x405 0x0>,<0x3048 0x5>,<0x304a 0x1>,<0x3040 0x0>,<0x3062 0x0>,<0x3060 0x9>,<0x3000 0x0>,<0x3064 0x0>,<0x3063 0x0>,<0x3035 0x0>,<0x303b 0x0>,<0x303a 0x4>,<0x303c 0x1>,<0x3020 0x7>,<0x38c0 0x0>,<0x38a0 0x0>,<0x8a2 0x400>,<0x8a7 0x400>,<0x810 0x40f>,<0x3410 0x2f>,<0x8c1 0x400>,<0x8c2 0x400>,<0x841 0x420>; + qcom,handoff-smrs = <0xffff 0x0>; + qcom,multi-match-handoff-smr; qcom,use-3-lvl-tables; #global-interrupts = <2>; #size-cells = <1>; @@ -224,6 +225,91 @@ <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; }; + + pcie_smmu: pcie-smmu@0x15200000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15200000 0x80000>, + <0x152F2000 0x28>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,split-tables; + qcom,handoff-smrs = <0x0 0x7f>,<0x80 0x7f>,<0x440 0x0>; + #global-interrupts = <2>; + #size-cells = <1>; + #address-cells = <1>; + #tcu-testbus-version = <1>; + ranges; + + interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; + }; + dma_dev@0x0 { compatible = "qcom,iommu-dma"; memory-region = <&system_cma>; @@ -300,6 +386,46 @@ gpio = <&pm8775_2_gpios 6 0>; }; + VDD_CX_LEVEL: S1A_LEVEL: + pm8775_a_s1_level: regulator-pm8775_a-s1-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8775_a_s1_level"; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + }; + + VDD_MXC_LEVEL: S5E_LEVEL: + pm8775_e_s5_level: regulator-pm8775_e-s5-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8775_e_s5_level"; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + }; + + pcie_0_pipe_clk: pcie_0_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + }; + + pcie_1_pipe_clk: pcie_1_pipe_clk { + compatible = "fixed-clock"; + clock-frequency = <1000>; + clock-output-names = "pcie_1_pipe_clk"; + #clock-cells = <0>; + }; + + rpmh_cxo_clk: rpmh_cxo_clk { + compatible = "qcom,dummycc"; + clock-output-names = "bi_tcxo"; + #clock-cells = <0>; + }; + /* PWR_CTR2_VDD_1P8 supply */ vreg_conn_1p8: vreg_conn_1p8 { compatible = "regulator-fixed"; @@ -391,6 +517,7 @@ #include "pm8775-vm.dtsi" #include "lemans-vm-qupv3.dtsi" #include "lemans-vm-usb.dtsi" +#include "lemans-vm-pcie.dtsi" &pm8775_3_gpios { usb201_vbus_boost { @@ -435,3 +562,4 @@ pinctrl-names = "default"; pinctrl-0 = <&usb22_vbus_boost_default>; }; + diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index 3b0f14f1..2ef1e460 100755 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -444,9 +444,14 @@ reg = <0x0 0xd1300000 0x0 0x500000>; }; - trusted_apps_mem: trusted_apps_region@d1800000 { + deep_sleep_backup_mem: deep_sleep_backup_region@d1800000 { no-map; - reg = <0x0 0xd1800000 0x0 0x3900000>; + reg = <0x0 0xd1800000 0x0 0x100000>; + }; + + trusted_apps_mem: trusted_apps_region@d1900000 { + no-map; + reg = <0x0 0xd1900000 0x0 0x3800000>; }; dump_mem: mem_dump_region { @@ -504,14 +509,6 @@ alignment = <0x0 0x400000>; }; - secure_display_memory: secure_display_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0xA000000>; - }; - user_contig_mem: user_contig_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; @@ -690,12 +687,6 @@ apps_bcm_voter: bcm_voter { compatible = "qcom,bcm-voter"; }; - - dcvs_fp: qcom,dcvs-fp { - compatible = "qcom,dcvs-fp"; - qcom,ddr-bcm-name = "MC4"; - qcom,llcc-bcm-name = "SH5"; - }; }; }; @@ -800,10 +791,15 @@ }; pil@94c { - compatible = "qcom,msm-imem-pil"; + compatible = "qcom,pil-reloc-info"; reg = <0x94c 0xc8>; }; + pil@6dc { + compatible = "qcom,msm-imem-pil-disable-timeout"; + reg = <0x6dc 0x4>; + }; + diag_dload@c8 { compatible = "qcom,msm-imem-diag-dload"; reg = <0xc8 0xc8>; @@ -1335,12 +1331,6 @@ interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; }; - - ddr_dcvs_fp: fp { - compatible = "qcom,dcvs-path"; - qcom,dcvs-path-type = <1>; - qcom,fp-voter = <&dcvs_fp>; - }; }; qcom_llcc_dcvs_hw: llcc { @@ -1355,12 +1345,6 @@ interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>; }; - - llcc_dcvs_fp: fp { - compatible = "qcom,dcvs-path"; - qcom,dcvs-path-type = <1>; - qcom,fp-voter = <&dcvs_fp>; - }; }; qcom_ddrqos_dcvs_hw: ddrqos { @@ -1384,7 +1368,7 @@ ddr { compatible = "qcom,memlat-grp"; qcom,target-dev = <&qcom_ddr_dcvs_hw>; - qcom,sampling-path = <&ddr_dcvs_fp>; + qcom,sampling-path = <&ddr_dcvs_sp>; qcom,miss-ev = <0x1000>; gold-0 { @@ -1423,7 +1407,7 @@ llcc { compatible = "qcom,memlat-grp"; qcom,target-dev = <&qcom_llcc_dcvs_hw>; - qcom,sampling-path = <&llcc_dcvs_fp>; + qcom,sampling-path = <&llcc_dcvs_sp>; qcom,miss-ev = <0x37>; gold-0 { @@ -2166,11 +2150,12 @@ qtee_shmbridge { compatible = "qcom,tee-shared-memory-bridge"; + qcom,disable-shmbridge-support; }; - qcom_qseecom: qseecom@d1800000 { + qcom_qseecom: qseecom@d1900000 { compatible = "qcom,qseecom"; - reg = <0xd1800000 0x3900000>; + reg = <0xd1900000 0x3800000>; reg-names = "secapp-region"; memory-region = <&qseecom_mem>; #qcom,hlos-num-ce-hw-instances = <1>; diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index 360e59f9..3bd671a8 100755 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -183,7 +183,7 @@ soc: soc { }; chosen { - bootargs = "console=ttyMSM0,115200n8 loglevel=6 kpti=off log_buf_len=256K kernel.panic_on_rcu_stall=1 msm_rtb.filter=0x237 rcupdate.rcu_expedited=1 rcu_nocbs=0-3 ftrace_dump_on_oops fw_devlink.strict=1 allow_mismatched_32bit_el0 printk.console_no_auto_verbose=1 irqaffinity=0-2 cpufreq.default_governor=performance"; + bootargs = "console=ttyMSM0,115200n8 loglevel=6 kpti=off log_buf_len=256K kernel.panic_on_rcu_stall=1 msm_rtb.filter=0x237 rcupdate.rcu_expedited=1 rcu_nocbs=0-3 ftrace_dump_on_oops fw_devlink.strict=1 allow_mismatched_32bit_el0 printk.console_no_auto_verbose=1 irqaffinity=0-2 cpufreq.default_governor=performance android_kmalloc_64_create"; }; reserved-memory { @@ -1621,6 +1621,12 @@ qcom,glinkpkt-ch-name = "ss_bt_data"; qcom,glinkpkt-dev-name = "glink_pkt_ss_bt_data"; }; + + qcom,glinkpkt-ss-bt-le-data { + qcom,glinkpkt-edge = "slate"; + qcom,glinkpkt-ch-name = "ss_bt_le_data"; + qcom,glinkpkt-dev-name = "glink_pkt_ss_bt_le_data"; + }; }; jtag_mm0: jtagmm@9040000 { @@ -2074,7 +2080,7 @@ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; qcom,sampling-enabled; qcom,cpufreq-memfreq-tbl = - < 614400 547000 >, + < 614400 681000 >, < 864000 681000 >, < 1363200 1353000 >, < 1708800 1804000 >; @@ -2086,7 +2092,7 @@ qcom,sampling-enabled; qcom,compute-mon; qcom,cpufreq-memfreq-tbl = - < 614400 200000 >, + < 614400 547000 >, < 864000 547000 >, < 1363200 681000 >, < 1708800 1353000 >; diff --git a/qcom/monaco_auto-stub-regulators.dtsi b/qcom/monaco_auto-stub-regulators.dtsi new file mode 100755 index 00000000..add46746 --- /dev/null +++ b/qcom/monaco_auto-stub-regulators.dtsi @@ -0,0 +1,311 @@ +#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h> + +&soc { + + VDD_MMCX_LEVEL: + S5A_LEVEL: + pm7255_a_s5_level: regulator-pm7255_a-s5-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_a_s5_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + }; + + VDD_MMCX_LEVEL_AO: + S5A_LEVEL_AO: + pm7255_a_s5_level_ao: regulator-pm7255_a-s5-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_a_s5_level_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + }; + + VDD_CX_LEVEL: + S7A_LEVEL: + pm7255_a_s7_level: regulator-pm7255_a-s7-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_a_s7_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + }; + + VDD_CX_LEVEL_AO: + S7A_LEVEL_AO: + pm7255_a_s7_level_ao: regulator-pm7255_a-s7-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_a_s7_level_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + }; + + VDD_LPI_MX_LEVEL: + L1A_LEVEL: + pm7255_a_l1_level: regulator-pm7255_a-l1-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_a_l1_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + }; + + VDD_LPI_CX_LEVEL: + L2A_LEVEL: + pm7255_a_l2_level: regulator-pm7255_a-l2-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_a_l2_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + }; + + VDD_MXC_LEVEL: + S1C_LEVEL: + pm7255_c_s1_level: regulator-pm7255_c-s1-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_c_s1_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + }; + + VDD_MXC_LEVEL_AO: + S1C_LEVEL_AO: + pm7255_c_s1_level_ao: regulator-pm7255_c-s1-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_c_s1_level_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + }; + + VDD_MXA_LEVEL: + S3C_LEVEL: + pm7255_c_s3_level: regulator-pm7255_c-s3-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_c_s3_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + }; + + VDD_MXA_LEVEL_AO: + S3C_LEVEL_AO: + pm7255_c_s3_level_ao: regulator-pm7255_c-s3-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_c_s3_level_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + }; + + VDD_GFX_LEVEL: + S4C_LEVEL: + pm7255_c_s4_level: regulator-pm7255_c-s4-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_c_s4_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + }; + + VDD_EBI_LEVEL: + S6C_LEVEL: + pm7255_c_s6_level: regulator-pm7255_c-s6-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_c_s6_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + }; + + S2A: + pm7255_a_s2: regulator-pm7255_a-s2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_a_s2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <628000>; + regulator-max-microvolt = <904000>; + }; + + S9A: + pm7255_a_s9: regulator-pm7255_a-s9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_a_s9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <628000>; + regulator-max-microvolt = <904000>; + }; + + L3A: + pm7255_a_l3: regulator-pm7255_a-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_a_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + L4A: + pm7255_a_l4: regulator-pm7255_a-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_a_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <788000>; + regulator-max-microvolt = <1050000>; + }; + + L5A: + pm7255_a_l5: regulator-pm7255_a-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_a_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + }; + + L6A: + pm7255_a_l6: regulator-pm7255_a-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_a_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <950000>; + }; + + L7A: + pm7255_a_l7: regulator-pm7255_a-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_a_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + }; + + L8A: + pm7255_a_l8: regulator-pm7255_a-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_a_l8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + L9A: + pm7255_a_l9: regulator-pm7255_a-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_a_l9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3544000>; + }; + + S5C: + pm7255_c_s5: regulator-pm7255_c-s5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_c_s5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + S9C: + pm7255_c_s9: regulator-pm7255_c-s9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_c_s9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1370000>; + }; + + L1C: + pm7255_c_l1: regulator-pm7255_c-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_c_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <570000>; + }; + + L3C: + pm7255_c_l3: regulator-pm7255_c-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_c_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + }; + + L4C: + pm7255_c_l4: regulator-pm7255_c-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_c_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + L6C: + pm7255_c_l6: regulator-pm7255_c-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_c_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + L7C: + pm7255_c_l7: regulator-pm7255_c-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_c_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L8C: + pm7255_c_l8: regulator-pm7255_c-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_c_l8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1950000>; + }; + + L9C: + pm7255_c_l9: regulator-pm7255_c-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm7255_c_l9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + }; +}; + diff --git a/qcom/monaco_auto-thermal.dtsi b/qcom/monaco_auto-thermal.dtsi new file mode 100755 index 00000000..2465ded5 --- /dev/null +++ b/qcom/monaco_auto-thermal.dtsi @@ -0,0 +1,1264 @@ +#include <dt-bindings/thermal/thermal_qti.h> + +&soc { + tsens0:tsens@c263000 { + compatible = "qcom,tsens-v2"; + reg = <0x0C263000 0x1ff>, + <0x0C222000 0x1ff>; + #qcom,sensors = <10>; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow","critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1:tsens@c265000 { + compatible = "qcom,tsens-v2"; + reg = <0x0C265000 0x1ff>, + <0x0C223000 0x1ff>; + #qcom,sensors = <10>; + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow","critical"; + #thermal-sensor-cells = <1>; + }; + + tsens2:tsens@c251000 { + compatible = "qcom,tsens-v2"; + reg = <0x0C251000 0x1ff>, + <0x0C224000 0x1ff>; + #qcom,sensors = <10>; + interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow","critical"; + #thermal-sensor-cells = <1>; + }; + + tsens3:tsens@c252000 { + compatible = "qcom,tsens-v2"; + reg = <0x0C252000 0x1ff>, + <0x0C225000 0x1ff>; + #qcom,sensors = <10>; + interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow","critical"; + #thermal-sensor-cells = <1>; + }; + + qcom,cpu-pause { + compatible = "qcom,thermal-pause"; + + cpu0_pause: cpu0-pause { + qcom,cpus = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_pause: cpu1-pause { + qcom,cpus = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_pause: cpu2-pause { + qcom,cpus = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_pause: cpu3-pause { + qcom,cpus = <&CPU3>; + #cooling-cells = <2>; + }; + + cpu4_pause: cpu4-pause { + qcom,cpus = <&CPU4>; + #cooling-cells = <2>; + }; + + cpu5_pause: cpu5-pause { + qcom,cpus = <&CPU5>; + #cooling-cells = <2>; + }; + + cpu6_pause: cpu6-pause { + qcom,cpus = <&CPU6>; + #cooling-cells = <2>; + }; + + cpu7_pause: cpu7-pause { + qcom,cpus = <&CPU7>; + #cooling-cells = <2>; + }; + + /* Thermal-engine cooling devices */ + pause-cpu0 { + qcom,cpus = <&CPU0>; + qcom,cdev-alias = "pause-cpu0"; + }; + + pause-cpu1 { + qcom,cpus = <&CPU1>; + qcom,cdev-alias = "pause-cpu1"; + }; + + pause-cpu2 { + qcom,cpus = <&CPU2>; + qcom,cdev-alias = "pause-cpu2"; + }; + + pause-cpu3 { + qcom,cpus = <&CPU3>; + qcom,cdev-alias = "pause-cpu3"; + }; + + pause-cpu4 { + qcom,cpus = <&CPU4>; + qcom,cdev-alias = "pause-cpu4"; + }; + + pause-cpu5 { + qcom,cpus = <&CPU5>; + qcom,cdev-alias = "pause-cpu5"; + }; + + pause-cpu6 { + qcom,cpus = <&CPU6>; + qcom,cdev-alias = "pause-cpu6"; + }; + + pause-cpu7 { + qcom,cpus = <&CPU7>; + qcom,cdev-alias = "pause-cpu7"; + }; + }; + + qcom,cpu-hotplug { + compatible = "qcom,cpu-hotplug"; + cpu0_hotplug: cpu0-hotplug { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_hotplug: cpu1-hotplug { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_hotplug: cpu2-hotplug { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_hotplug: cpu3-hotplug { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + + cpu4_hotplug: cpu4-hotplug { + qcom,cpu = <&CPU4>; + #cooling-cells = <2>; + }; + + cpu5_hotplug: cpu5-hotplug { + qcom,cpu = <&CPU5>; + #cooling-cells = <2>; + }; + + cpu6_hotplug: cpu6-hotplug { + qcom,cpu = <&CPU6>; + #cooling-cells = <2>; + }; + + cpu7_hotplug: cpu7-hotplug { + qcom,cpu = <&CPU7>; + #cooling-cells = <2>; + }; + }; + + qcom,cpufreq-cdev { + compatible = "qcom,cpufreq-cdev"; + qcom,cpus = <&CPU0 &CPU2 &CPU4>; + }; + + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + cdsp { + qcom,instance-id = <QMI_CDSP_INST_ID>; + + cdsp_sw: cdsp { + qcom,qmi-dev-name = "cdsp_sw"; + #cooling-cells = <2>; + }; + + cdsp_hw: cdsp_hw { + qcom,qmi-dev-name = "cdsp_hw"; + #cooling-cells = <2>; + }; + }; + }; +}; + +&thermal_zones { + aoss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-0-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu000_config: cpu000-config { + temperature = <126000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu000_cdev { + trip = <&cpu000_config>; + cooling-device = <&cpu0_pause 1 1>; + }; + }; + }; + + cpu-0-1-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu010_config: cpu010-config { + temperature = <126000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu010_cdev { + trip = <&cpu010_config>; + cooling-device = <&cpu1_pause 1 1>; + }; + }; + }; + + cpu-0-2-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu020_config: cpu020-config { + temperature = <126000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu020_cdev { + trip = <&cpu020_config>; + cooling-device = <&cpu2_pause 1 1>; + }; + }; + }; + + cpu-0-3-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu030_config: cpu030-config { + temperature = <126000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu030_cdev { + trip = <&cpu030_config>; + cooling-device = <&cpu3_pause 1 1>; + }; + }; + }; + + gpuss-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + gpuss0_config: gpuss0-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + audio { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pcie-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-0-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu001_config: cpu001-config { + temperature = <126000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu001_cdev { + trip = <&cpu001_config>; + cooling-device = <&cpu0_pause 1 1>; + }; + }; + }; + + cpu-0-1-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu011_config: cpu011-config { + temperature = <126000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu011_cdev { + trip = <&cpu011_config>; + cooling-device = <&cpu1_pause 1 1>; + }; + }; + }; + + cpu-0-2-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu021_config: cpu021-config { + temperature = <126000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu021_cdev { + trip = <&cpu021_config>; + cooling-device = <&cpu2_pause 1 1>; + }; + }; + }; + + cpu-0-3-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu031_config: cpu031-config { + temperature = <126000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu031_cdev { + trip = <&cpu031_config>; + cooling-device = <&cpu3_pause 1 1>; + }; + }; + }; + + gpuss-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + gpuss1_config: gpuss1-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 6>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 7>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pcie-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 9>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss-2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 0>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 1>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu100_config: cpu100-config { + temperature = <126000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu100_cdev { + trip = <&cpu100_config>; + cooling-device = <&cpu4_pause 1 1>; + }; + }; + }; + + cpu-1-1-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 2>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu110_config: cpu110-config { + temperature = <126000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu110_cdev { + trip = <&cpu110_config>; + cooling-device = <&cpu5_pause 1 1>; + }; + }; + }; + + cpu-1-2-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 3>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu120_config: cpu120-config { + temperature = <126000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu120_cdev { + trip = <&cpu120_config>; + cooling-device = <&cpu6_pause 1 1>; + }; + }; + }; + + cpu-1-3-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 4>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu130_config: cpu130-config { + temperature = <126000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu130_cdev { + trip = <&cpu130_config>; + cooling-device = <&cpu7_pause 1 1>; + }; + }; + }; + + nsp-0-0-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 5>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + nsp000_config: nsp000-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + nsp000_cdev { + trip = <&nsp000_config>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + nsp-0-1-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 6>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + nsp010_config: nsp010-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + nsp010_cdev { + trip = <&nsp010_config>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + nsp-0-2-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 7>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + nsp020_config: nsp020-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + nsp020_cdev { + trip = <&nsp020_config>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + ddrss-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 8>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-1-0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 9>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss-3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 0>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens3 1>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu101_config: cpu101-config { + temperature = <126000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu101_cdev { + trip = <&cpu101_config>; + cooling-device = <&cpu4_pause 1 1>; + }; + }; + }; + + cpu-1-1-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens3 2>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu111_config: cpu111-config { + temperature = <126000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu111_cdev { + trip = <&cpu111_config>; + cooling-device = <&cpu5_pause 1 1>; + }; + }; + }; + + cpu-1-2-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens3 3>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu121_config: cpu121-config { + temperature = <126000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu121_cdev { + trip = <&cpu121_config>; + cooling-device = <&cpu6_pause 1 1>; + }; + }; + }; + + cpu-1-3-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens3 4>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu131_config: cpu131-config { + temperature = <126000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu131_cdev { + trip = <&cpu131_config>; + cooling-device = <&cpu7_pause 1 1>; + }; + }; + }; + + nsp-0-0-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens3 5>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + nsp001_config: nsp001-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + nsp001_cdev { + trip = <&nsp001_config>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + nsp-0-1-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens3 6>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + nsp011_config: nsp011-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + nsp011_cdev { + trip = <&nsp011_config>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + nsp-0-2-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens3 7>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + nsp021_config: nsp021-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + nsp021_cdev { + trip = <&nsp021_config>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + ddrss-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 8>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-1-1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens3 9>; + trips { + thermal-engine-config { + temperature = <135000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <130000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/monaco_auto.dtsi b/qcom/monaco_auto.dtsi index 821d6eef..ab72ea0a 100755 --- a/qcom/monaco_auto.dtsi +++ b/qcom/monaco_auto.dtsi @@ -1,4 +1,5 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/qcom,ipcc.h> / { model = "Qualcomm Technologies, Inc. Monaco AUTO"; @@ -30,9 +31,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x0>; - enable-method = "spin-table"; + enable-method = "psci"; cpu-release-addr = <0x0 0xc0000000>; next-level-cache = <&L2_0>; + #cooling-cells = <2>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -49,9 +51,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x100>; - enable-method = "spin-table"; + enable-method = "psci"; cpu-release-addr = <0x0 0xc0000000>; next-level-cache = <&L2_1>; + #cooling-cells = <2>; L2_1: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -63,9 +66,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x200>; - enable-method = "spin-table"; + enable-method = "psci"; cpu-release-addr = <0x0 0xc0000000>; next-level-cache = <&L2_2>; + #cooling-cells = <2>; L2_2: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -77,9 +81,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x300>; - enable-method = "spin-table"; + enable-method = "psci"; cpu-release-addr = <0x0 0xc0000000>; next-level-cache = <&L2_3>; + #cooling-cells = <2>; L2_3: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -91,9 +96,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x10000>; - enable-method = "spin-table"; + enable-method = "psci"; cpu-release-addr = <0x0 0xc0000000>; next-level-cache = <&L2_4>; + #cooling-cells = <2>; L2_4: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -110,9 +116,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x10100>; - enable-method = "spin-table"; + enable-method = "psci"; cpu-release-addr = <0x0 0xc0000000>; next-level-cache = <&L2_5>; + #cooling-cells = <2>; L2_5: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -124,9 +131,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x10200>; - enable-method = "spin-table"; + enable-method = "psci"; cpu-release-addr = <0x0 0xc0000000>; next-level-cache = <&L2_6>; + #cooling-cells = <2>; L2_6: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -138,9 +146,10 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x10300>; - enable-method = "spin-table"; + enable-method = "psci"; cpu-release-addr = <0x0 0xc0000000>; next-level-cache = <&L2_7>; + #cooling-cells = <2>; L2_7: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -194,6 +203,11 @@ }; &reserved_memory { + + smem_region: smem@90900000 { + no-map; + reg = <0x0 0x90900000 0x0 0x200000>; + }; }; &soc { @@ -212,6 +226,18 @@ #interrupt-cells = <2>; }; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + wdog: qcom,wdt@17c10000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -294,6 +320,134 @@ }; }; + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + ipcc_mproc: qcom,ipcc@408000 { + compatible = "qcom,ipcc"; + reg = <0x408000 0x1000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + aoss_qmp: power-controller@c300000 { + + compatible = "qcom,sm8150-aoss-qmp"; + reg = <0xc300000 0x400>; + mboxes = <&ipcc_mproc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "aop_qmp"; + interrupt-parent = <&ipcc_mproc>; + interrupts = <IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + #clock-cells = <0>; + #power-domain-cells = <1>; + }; + + qmp_aop: qcom,qmp-aop@c300000 { + compatible = "qcom,qmp-mbox"; + qcom,qmp = <&aoss_qmp>; + label = "aop"; + #mbox-cells = <1>; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupt-parent = <&ipcc_mproc>; + interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-cdsp@1799000c { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupt-parent = <&ipcc_mproc>; + interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-gpdsp0 { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupt-parent = <&ipcc_mproc>; + interrupts = <IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc_mproc IPCC_CLIENT_GPDSP0 + IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <17>; + + gpdsp0_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + gpdsp0_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + thermal_zones: thermal-zones { + }; }; #include "monaco_auto-pinctrl.dtsi" +#include "monaco_auto-stub-regulators.dtsi" +#include "msm-arm-smmu-monaco_auto.dtsi" +#include "monaco_auto-thermal.dtsi" diff --git a/qcom/msm-arm-smmu-crow.dtsi b/qcom/msm-arm-smmu-crow.dtsi new file mode 100755 index 00000000..1b6e1223 --- /dev/null +++ b/qcom/msm-arm-smmu-crow.dtsi @@ -0,0 +1,279 @@ +#include <dt-bindings/interrupt-controller/arm-gic.h> + +&soc { + kgsl_smmu: kgsl-smmu@3da0000 { + compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu"; + reg = <0x3da0000 0x40000>; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + qcom,actlr = + /* All CBs of GFX: +15 deep PF */ + <0x000 0x3ff 0x32B>; + + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; + + gpu_qtb: gpu_qtb@3de8000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x3de8000 0x1000>; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <49>; + qcom,num-qtb-ports = <2>; + }; + }; + + apps_smmu: apps-smmu@15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>; + #iommu-cells = <2>; + qcom,use-3-lvl-tables; + qcom,handoff-smrs = <0x1c00 0x2>; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; + + anoc_1_qtb: anoc_1_qtb@16f0000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16f0000 0x1000>; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <36>; + qcom,num-qtb-ports = <1>; + }; + + anoc_2_qtb: anoc_2_qtb@171b000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x171b000 0x1000>; + qcom,stream-id-range = <0x400 0x400>; + qcom,iova-width = <36>; + qcom,num-qtb-ports = <1>; + }; + + mnoc_hf_01_qtb: mnoc_hf_01_qtb@17d2000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17d2000 0x1000>; + qcom,stream-id-range = <0x800 0x400>; + qcom,iova-width = <32>; + qcom,num-qtb-ports = <2>; + }; + + nsp_qtb: nsp_qtb@523000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x523000 0x1000>; + qcom,stream-id-range = <0xc00 0x400>; + qcom,iova-width = <32>; + qcom,num-qtb-ports = <2>; + }; + + lpass_qtb: lpass_qtb@503000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x503000 0x1000>; + qcom,stream-id-range = <0x1000 0x400>; + qcom,iova-width = <32>; + qcom,num-qtb-ports = <1>; + }; + + anoc_pcie_qtb: anoc_pcie_qtb@16cd000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x16cd000 0x1000>; + qcom,stream-id-range = <0x1400 0x400>; + qcom,iova-width = <36>; + qcom,num-qtb-ports = <1>; + qcom,opt-out-tbu-halting; + }; + + mnoc_sf_qtb: mnoc_sf_qtb@17d1000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17d1000 0x1000>; + qcom,stream-id-range = <0x1800 0x400>; + qcom,iova-width = <32>; + qcom,num-qtb-ports = <2>; + }; + + mnoc_hf_23_qtb: mnoc_hf_23_qtb@17d0000 { + compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; + reg = <0x17d0000 0x1000>; + qcom,stream-id-range = <0x1c00 0x400>; + qcom,iova-width = <36>; + qcom,num-qtb-ports = <2>; + }; + }; + + dma_dev { + compatible = "qcom,iommu-dma"; + memory-region = <&system_cma>; + }; + + iommu_test_device { + compatible = "qcom,iommu-debug-test"; + + usecase0_apps { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + }; + + usecase1_apps_fastmap { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + qcom,iommu-dma = "fastmap"; + }; + + usecase2_apps_atomic { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + qcom,iommu-dma = "atomic"; + }; + + usecase3_apps_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + dma-coherent; + }; + + usecase4_apps_secure { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x400 0x0>; + qcom,iommu-vmid = <0xa>; /* VMID_CP_PIXEL */ + }; + + usecase5_kgsl { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x7 0x0>; + }; + + usecase6_kgsl_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&kgsl_smmu 0x7 0x0>; + dma-coherent; + }; + }; +}; diff --git a/qcom/msm-arm-smmu-kalama.dtsi b/qcom/msm-arm-smmu-kalama.dtsi index 4ee4ddbd..c096bc20 100755 --- a/qcom/msm-arm-smmu-kalama.dtsi +++ b/qcom/msm-arm-smmu-kalama.dtsi @@ -3,7 +3,9 @@ &soc { kgsl_smmu: kgsl-smmu@3da0000 { compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu"; - reg = <0x3da0000 0x40000>; + reg = <0x3da0000 0x40000>, + <0x3DE6000 0x40>; + reg-names = "base", "tcu-base"; #iommu-cells = <2>; qcom,use-3-lvl-tables; #global-interrupts = <1>; @@ -58,7 +60,9 @@ gpu_qtb: gpu_qtb@3de8000 { compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; - reg = <0x3de8000 0x1000>; + reg = <0x3de8000 0x1000>, + <0x3DEC000 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x0 0x400>; qcom,iova-width = <49>; interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; @@ -68,7 +72,9 @@ apps_smmu: apps-smmu@15000000 { compatible = "qcom,qsmmu-v500"; - reg = <0x15000000 0x100000>; + reg = <0x15000000 0x100000>, + <0x151fe000 0x40>; + reg-names = "base", "tcu-base"; #iommu-cells = <2>; qcom,use-3-lvl-tables; qcom,handoff-smrs = <0x1c00 0x2>; @@ -247,7 +253,9 @@ anoc_1_qtb: anoc_1_qtb@16f0000 { compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; - reg = <0x16f0000 0x1000>; + reg = <0x16f0000 0x1000>, + <0x16e1100 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x0 0x400>; qcom,iova-width = <36>; interconnects = <&system_noc MASTER_A1NOC_SNOC &mc_virt SLAVE_EBI1>; @@ -256,7 +264,9 @@ anoc_2_qtb: anoc_2_qtb@171a000 { compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; - reg = <0x171a000 0x1000>; + reg = <0x171a000 0x1000>, + <0x16e1100 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x400 0x400>; qcom,iova-width = <36>; interconnects = <&system_noc MASTER_A2NOC_SNOC &mc_virt SLAVE_EBI1>; @@ -265,7 +275,9 @@ cam_hf_qtb: cam_hf_qtb@17d2000 { compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; - reg = <0x17d2000 0x1000>; + reg = <0x17d2000 0x1000>, + <0x1783000 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x800 0x400>; qcom,iova-width = <36>; interconnects = <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI1>; @@ -274,7 +286,9 @@ nsp_qtb: nsp_qtb@523000 { compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; - reg = <0x523000 0x1000>; + reg = <0x523000 0x1000>, + <0x532000 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0xc00 0x400>; qcom,iova-width = <34>; interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; @@ -283,7 +297,9 @@ lpass_qtb: lpass_qtb@503000 { compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; - reg = <0x503000 0x1000>; + reg = <0x503000 0x1000>, + <0x511000 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x1000 0x400>; qcom,iova-width = <32>; interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC &mc_virt SLAVE_EBI1>; @@ -292,7 +308,9 @@ pcie_qtb: pcie_qtb@16cd000 { compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; - reg = <0x16cd000 0x1000>; + reg = <0x16cd000 0x1000>, + <0x16C3000 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x1400 0x400>; qcom,iova-width = <36>; interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; @@ -302,7 +320,9 @@ sf_qtb: sf_qtb@17d1000 { compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; - reg = <0x17d1000 0x1000>; + reg = <0x17d1000 0x1000>, + <0x1783000 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x1800 0x400>; qcom,iova-width = <36>; interconnects = <&mmss_noc MASTER_VIDEO &mc_virt SLAVE_EBI1>; @@ -311,7 +331,9 @@ mdp_hf_qtb: mdp_hf_qtb@17d0000 { compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500"; - reg = <0x17d0000 0x1000>; + reg = <0x17d0000 0x1000>, + <0x1783000 0x1000>; + reg-names = "base", "debugchain-base"; qcom,stream-id-range = <0x1c00 0x400>; qcom,iova-width = <32>; interconnects = <&mmss_noc MASTER_MDP &mc_virt SLAVE_EBI1>; diff --git a/qcom/msm-arm-smmu-kona.dtsi b/qcom/msm-arm-smmu-kona.dtsi index d120810c..06a075b8 100755 --- a/qcom/msm-arm-smmu-kona.dtsi +++ b/qcom/msm-arm-smmu-kona.dtsi @@ -8,6 +8,8 @@ reg-names = "base", "tcu-base"; #iommu-cells = <2>; qcom,use-3-lvl-tables; + qcom,num-context-banks-override = <0x05>; + qcom,num-smr-override = <0x06>; qcom,no-dynamic-asid; #global-interrupts = <2>; #size-cells = <1>; @@ -68,6 +70,8 @@ reg-names = "base", "tcu-base"; #iommu-cells = <2>; qcom,use-3-lvl-tables; + qcom,num-context-banks-override = <0x4a>; + qcom,num-smr-override = <0x57>; #global-interrupts = <2>; #size-cells = <1>; #address-cells = <1>; diff --git a/qcom/msm-arm-smmu-monaco_auto.dtsi b/qcom/msm-arm-smmu-monaco_auto.dtsi new file mode 100755 index 00000000..d2c4d42c --- /dev/null +++ b/qcom/msm-arm-smmu-monaco_auto.dtsi @@ -0,0 +1,280 @@ +#include <dt-bindings/interrupt-controller/arm-gic.h> + +&soc { + apps_smmu: apps-smmu@15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x151A2000 0x28>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + #global-interrupts = <2>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 913 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; + + anoc_1_tbu: anoc_1_tbu@15189000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151A9000 0x1000>, + <0x151A2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,iova-width = <36>; + }; + + anoc_2_tbu: anoc_2_tbu@15191000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151B1000 0x1000>, + <0x151A2208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,iova-width = <36>; + }; + + mnoc_sf_0_tbu: mnoc_sf_0_tbu@15199000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151B9000 0x1000>, + <0x151A2210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,iova-width = <36>; + }; + + mnoc_sf_1_tbu: mnoc_sf_1_tbu@0x151a1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151C1000 0x1000>, + <0x151A2218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xC00 0x400>; + qcom,iova-width = <36>; + }; + + mdp_00_tbu: mdp_00_tbu@0x151a9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151C9000 0x1000>, + <0x151A2220 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1000 0x400>; + qcom,iova-width = <32>; + }; + + mdp_01_tbu: mdp_01_tbu@0x151b1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151D1000 0x1000>, + <0x151A2228 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1400 0x400>; + qcom,iova-width = <32>; + }; + + nsp_00_tbu: nsp_00_tbu@151c9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151D9000 0x1000>, + <0x151A2230 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1900 0x400>; + qcom,iova-width = <32>; + }; + + nsp_01_tbu: nsp_01_tbu@151d1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151E1000 0x1000>, + <0x151A2238 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1D00 0x200>; + qcom,iova-width = <32>; + }; + + lpass_tbu: lpass_tbu@151e9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151E9000 0x1000>, + <0x151A2240 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x2000 0x400>; + qcom,iova-width = <32>; + }; + + cam_tbu: cam_tbu@151f1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151F1000 0x1000>, + <0x151A2248 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x2400 0x400>; + qcom,iova-width = <32>; + }; + + gpdsp_sail_ss_tbu: gpdsp_sail_ss_tbu@151f9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151F9000 0x1000>, + <0x151A2250 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x2800 0x400>; + qcom,iova-width = <32>; + }; + }; + + iommu_test_device { + + compatible = "qcom,iommu-debug-test"; + + usecase0_apps { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x580 0>; + }; + + usecase1_apps_fastmap { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x580 0>; + qcom,iommu-dma = "fastmap"; + }; + + usecase2_apps_atomic { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x580 0>; + qcom,iommu-dma = "atomic"; + }; + + usecase3_apps_dma { + compatible = "qcom,iommu-debug-usecase"; + iommus = <&apps_smmu 0x581 0>; + dma-coherent; + }; + }; +}; diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi index 15c1a55a..8b65a0d4 100755 --- a/qcom/pm5100.dtsi +++ b/qcom/pm5100.dtsi @@ -141,8 +141,9 @@ pm5100_adc: vadc@8000 { compatible = "qcom,spmi-adc5-gen3"; - reg = <0x8000>, <0x8300>; - reg-names = "adc5-gen3-base", "adc5-gen3-debug-base"; + reg = <0x8000>; + reg-names = "adc5-gen3-base"; + qcom,debug-base = <0x8300>; #address-cells = <1>; #size-cells = <0>; interrupts = <0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>; @@ -553,6 +554,17 @@ qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; qcom,wf-auto-res-disable; }; + + primitive_8 { + /* LOW_TICK */ + qcom,primitive-id = <8>; + qcom,wf-vmax-mv = <4800>; + qcom,wf-pattern-data = <0x0ff S_PERIOD_T_LRA 0>, + <0x07f S_PERIOD_T_LRA 0>; + qcom,wf-pattern-period-us = <4167>; + qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>; + qcom,wf-auto-res-disable; + }; }; }; }; diff --git a/qcom/pmx35.dtsi b/qcom/pmx35.dtsi index e633ab80..de9b61bd 100755 --- a/qcom/pmx35.dtsi +++ b/qcom/pmx35.dtsi @@ -67,11 +67,11 @@ qcom,num-lpg-channels = <4>; }; - pmx35_rtc: qcom,pmx35_rtc { - compatible = "qcom,pm8941-rtc"; + pmx35_rtc: rtc@6400 { + compatible = "qcom,pm5100-rtc"; reg = <0x6400>, <0x6500>; reg-names = "rtc", "alarm"; - interrupts = <0x0 0x65 0x1 IRQ_TYPE_NONE>; + interrupts = <0x0 0x65 0x1 IRQ_TYPE_EDGE_RISING>; }; pmx35_sdam_2: sdam@7100 { diff --git a/qcom/qcs405-dma-heaps.dtsi b/qcom/qcs405-dma-heaps.dtsi new file mode 100755 index 00000000..44c39d56 --- /dev/null +++ b/qcom/qcs405-dma-heaps.dtsi @@ -0,0 +1,19 @@ +#include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h> + +&soc { + qcom,dma-heaps { + compatible = "qcom,dma-heaps"; + + qcom,qseecom { + qcom,dma-heap-name = "qcom,qseecom"; + qcom,dma-heap-type = <HEAP_TYPE_CMA>; + memory-region = <&qseecom_mem>; + }; + + qcom,qseecom_ta { + qcom,dma-heap-name = "qcom,qseecom-ta"; + qcom,dma-heap-type = <HEAP_TYPE_CMA>; + memory-region = <&qseecom_ta_mem>; + }; + }; +}; diff --git a/qcom/qcs405-thermal.dtsi b/qcom/qcs405-thermal.dtsi new file mode 100755 index 00000000..0d2fa562 --- /dev/null +++ b/qcom/qcs405-thermal.dtsi @@ -0,0 +1,420 @@ +#include <dt-bindings/thermal/thermal_qti.h> + +&soc { + tsens0: tsens@4a8000 { + compatible = "qcom,qcs405-tsens"; + reg = <0x4a8000 0x1000>, + <0x4a9000 0x1000>, + <0xa4000 0x1000>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical", + "tsens_eeprom_physical"; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tsens-upper-lower"; + #thermal-sensor-cells = <1>; + }; + + qcom,cpu-pause { + compatible = "qcom,thermal-pause"; + + cpu0_pause: cpu0-pause { + qcom,cpus = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_pause: cpu1-pause { + qcom,cpus = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_pause: cpu2-pause { + qcom,cpus = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_pause: cpu3-pause { + qcom,cpus = <&CPU3>; + #cooling-cells = <2>; + }; + + /* Thermal-engine cooling devices */ + pause-cpu0 { + qcom,cpus = <&CPU0>; + qcom,cdev-alias = "pause-cpu0"; + }; + + pause-cpu1 { + qcom,cpus = <&CPU1>; + qcom,cdev-alias = "pause-cpu1"; + }; + + pause-cpu2 { + qcom,cpus = <&CPU2>; + qcom,cdev-alias = "pause-cpu2"; + }; + + pause-cpu3 { + qcom,cpus = <&CPU3>; + qcom,cdev-alias = "pause-cpu3"; + }; + }; + + qcom,cpu-hotplug { + compatible = "qcom,cpu-hotplug"; + + cpu0_hotplug: cpu0-hotplug { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_hotplug: cpu1-hotplug { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_hotplug: cpu2-hotplug { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_hotplug: cpu3-hotplug { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + }; + + qcom,cpufreq-cdev { + compatible = "qcom,cpufreq-cdev"; + qcom,cpus = <&CPU0>; + }; + + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem { + qcom,instance-id = <0x0>; + + modem_pa: modem_pa { + qcom,qmi-dev-name = "pa"; + #cooling-cells = <2>; + }; + + modem_proc: modem_proc { + qcom,qmi-dev-name = "modem"; + #cooling-cells = <2>; + }; + + modem_current: modem_current { + qcom,qmi-dev-name = "modem_current"; + #cooling-cells = <2>; + }; + + modem_vdd: modem_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + }; +}; + +&rpm_bus { + rpm_smd_cdev: rpm-smd-cdev { + compatible = "qcom,rpm-smd-cooling-device"; + #cooling-cells = <2>; + }; +}; + +&thermal_zones { + aoss { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <120000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + q6-hvx { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <120000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + lpass { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <120000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + wlan { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <120000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu_trip:cpu-trip { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <120000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_cdev { + trip = <&cpu_trip>; + cooling-device = <&CPU0 0 1>; + }; + + cpu1_cdev { + trip = <&cpu_trip>; + cooling-device = <&CPU1 0 1>; + }; + + cpu2_cdev { + trip = <&cpu_trip>; + cooling-device = <&CPU2 0 1>; + }; + + cpu3_cdev { + trip = <&cpu_trip>; + cooling-device = <&CPU3 0 1>; + }; + }; + }; + + cpuss-0 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpuss0_config: cpuss0-config { + temperature = <118000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <120000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu0_cdev { + trip = <&cpuss0_config>; + cooling-device = <&cpu0_pause 1 1>; + }; + }; + }; + + cpuss-1 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpuss1_config: cpuss1-config { + temperature = <118000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <120000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu1_cdev { + trip = <&cpuss1_config>; + cooling-device = <&cpu1_pause 1 1>; + }; + }; + }; + + cpuss-2 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpuss2_config: cpuss2-config { + temperature = <118000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <120000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu2_cdev { + trip = <&cpuss2_config>; + cooling-device = <&cpu2_pause 1 1>; + }; + }; + }; + + cpuss-3 { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpuss3_config: cpuss3-config { + temperature = <118000>; + hysteresis = <10000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <120000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu3_cdev { + trip = <&cpuss3_config>; + cooling-device = <&cpu3_pause 1 1>; + }; + }; + }; + + xo-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pms405_adc_tm_iio ADC5_XO_THERM_100K_PU>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pms405_adc_tm_iio ADC5_AMUX_THM1_100K_PU>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pms405_adc_tm_iio ADC5_AMUX_THM3_100K_PU>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/qcs405.dtsi b/qcom/qcs405.dtsi index 6567969a..40d445ec 100755 --- a/qcom/qcs405.dtsi +++ b/qcom/qcs405.dtsi @@ -1,4 +1,5 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/iio/qcom,spmi-vadc.h> #include <dt-bindings/gpio/gpio.h> #define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) @@ -41,10 +42,70 @@ reg = <0x0 0x86100000 0x0 0x300000>; }; + wlan_fw_mem: wlan_fw_mem@86400000 { + no-map; + reg = <0x0 0x86400000 0x0 0x1000000>; + }; + + adsp_fw_mem: adsp_fw_mem@87400000 { + no-map; + reg = <0x0 0x87400000 0x0 0x1400000>; + }; + + cdsp_fw_mem: cdsp_fw_mem@88800000 { + no-map; + reg = <0x0 0x88800000 0x0 0x800000>; + }; + + wlan_msa_mem: wlan_msa_region@89000000 { + no-map; + reg = <0x0 0x89000000 0x0 0x100000>; + }; + + mdf_mem: mdf_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + reusable; + alignment = <0 0x400000>; + size = <0 0x1000000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + reusable; + alignment = <0 0x400000>; + size = <0 0x400000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + dump_mem: mem_dump_region { - compatible = "shared-dma-pool"; - reusable; - size = <0 0x400000>; + compatible = "shared-dma-pool"; + reusable; + alignment = <0 0x400000>; + size = <0 0x400000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x1000000>; + linux,cma-default; }; }; @@ -474,6 +535,8 @@ #interrupt-cells = <2>; }; }; + + thermal_zones: thermal-zones {}; }; &firmware { @@ -488,4 +551,7 @@ #include "qcs405-pinctrl.dtsi" #include "pms405-rpm-regulator.dtsi" #include "qcs405-regulator.dtsi" +#include "qcs405-dma-heaps.dtsi" +#include "pms405.dtsi" +#include "qcs405-thermal.dtsi" diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index 27918977..6eac8c10 100755 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -14,7 +14,7 @@ }; chosen { - bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 cgroup.memory=nokmem,nosocket kpti=0 qcom_dma_heaps.enable_bitstream_contig_heap=y arm64.nopauth kasan=off"; + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 cgroup.memory=nokmem,nosocket kpti=0 qcom_dma_heaps.enable_bitstream_contig_heap=y arm64.nopauth kasan=off msm_show_resume_irq.debug_mask=1"; }; soc: soc { }; @@ -176,7 +176,7 @@ qcom_dma_heaps: qcom,dma-heaps { compatible = "qcom,dma-heaps"; - qcom,qseecom { + qseecom_dma_heap: qcom,qseecom { qcom,dma-heap-name = "qcom,qseecom"; qcom,dma-heap-type = <HEAP_TYPE_CMA>; memory-region = <&qseecom_mem>; diff --git a/qcom/sa8155-vm-la.dtsi b/qcom/sa8155-vm-la.dtsi index e55f0152..e3133b3a 100755 --- a/qcom/sa8155-vm-la.dtsi +++ b/qcom/sa8155-vm-la.dtsi @@ -139,6 +139,10 @@ }; / { + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 cgroup.memory=nokmem,nosocket kpti=0 qcom_dma_heaps.enable_bitstream_contig_heap=y arm64.nopauth kasan=off msm_show_resume_irq.debug_mask=1 androidboot.usbcontroller=a600000.dwc3 androidboot.fstab_suffix=gen3.qcom"; + }; + rename_devices: rename_devices { compatible = "qcom,rename-devices"; rename_blk: rename_blk { diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi index 60318490..66adae68 100755 --- a/qcom/sa8155-vm.dtsi +++ b/qcom/sa8155-vm.dtsi @@ -371,6 +371,10 @@ }; }; +&qseecom_dma_heap { + qcom,uncached-heap; +}; + #include "sm8150-pinctrl.dtsi" #include "sa8155-vm-pcie.dtsi" #include "sa8155-vm-qupv3.dtsi" @@ -559,3 +563,8 @@ &hgsl_tcsr_receiver1>; }; }; + +&qseecom_mem { + /delete-property/ reusable; + no-map; +}; diff --git a/qcom/sa8195-vm-la.dtsi b/qcom/sa8195-vm-la.dtsi index 03eebbbe..a5506707 100755 --- a/qcom/sa8195-vm-la.dtsi +++ b/qcom/sa8195-vm-la.dtsi @@ -121,6 +121,10 @@ }; / { + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 cgroup.memory=nokmem,nosocket kpti=0 qcom_dma_heaps.enable_bitstream_contig_heap=y arm64.nopauth kasan=off msm_show_resume_irq.debug_mask=1 androidboot.usbcontroller=a600000.dwc3 androidboot.fstab_suffix=gen3.qcom"; + }; + rename_devices: rename_devices { compatible = "qcom,rename-devices"; rename_blk: rename_blk { diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi index 941cbfd9..382ef971 100755 --- a/qcom/sa8195-vm.dtsi +++ b/qcom/sa8195-vm.dtsi @@ -440,6 +440,10 @@ }; }; +&qseecom_dma_heap { + qcom,uncached-heap; +}; + #include "sdmshrike-pinctrl.dtsi" #include "sa8195-vm-qupv3.dtsi" #include "sa8195-vm-usb.dtsi" @@ -620,3 +624,8 @@ &hgsl_tcsr_receiver1>; }; }; + +&qseecom_mem { + /delete-property/ reusable; + no-map; +}; diff --git a/qcom/scuba-thermal.dtsi b/qcom/scuba-thermal.dtsi index f45f5fb9..2df83413 100755 --- a/qcom/scuba-thermal.dtsi +++ b/qcom/scuba-thermal.dtsi @@ -7,8 +7,8 @@ <0x04411000 0x1ff>; reg-names = "tsens_srot_physical", "tsens_tm_physical"; - interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 190 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tsens-upper-lower", "tsens-critical"; #thermal-sensor-cells = <1>; }; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 0d7ccca1..ff89880e 100755 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -413,7 +413,7 @@ reg = <0x0 0x8be00000 0x0 0x1a00000>; }; - pil_modem_mem: modem_region@8d800000 { + rproc_modem_mem: rproc_modem_region@8d800000 { no-map; reg = <0x0 0x8d800000 0x0 0x9600000>; }; @@ -465,11 +465,6 @@ label = "cont_splash_region"; }; - disp_rdump_memory: disp_rdump_region@9c000000 { - reg = <0x0 0x9c000000 0x0 0x02400000>; - label = "disp_rdump_region"; - }; - adsp_mem: adsp_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; @@ -1173,6 +1168,26 @@ }; }; + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs 0 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + wdog: qcom,wdt@17c10000 { compatible = "qcom,msm-watchdog"; reg = <0x17c10000 0x1000>; @@ -1390,7 +1405,8 @@ < 672000 768000 >, < 864000 960000 >, < 1171200 1228800 >, - < 1267200 1344000 >; + < 1267200 1344000 >, + < 1766400 1651200 >; qcom,sampling-enabled; }; @@ -1403,7 +1419,8 @@ < 768000 768000 >, < 960000 960000 >, < 1248000 1228800 >, - < 1593600 1344000 >; + < 1593600 1344000 >, + < 2841600 1651200 >; qcom,sampling-enabled; }; }; @@ -1574,6 +1591,74 @@ }; }; + modem_pas: remoteproc-modem@4080000 { + compatible = "qcom,sdmshrike-mpss-pas"; + reg = <0x4080000 0x00100>; + status = "disabled"; + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>; + mx-supply = <&VDD_MX_LEVEL>; + mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>; + reg-names = "cx", "mx"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + qcom,qmp = <&aoss_qmp>; + + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnect-names = "crypto_ddr"; + + memory-region = <&rproc_modem_mem>; + + /* Inputs from mss */ + interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack", + "shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink_edge_modem: glink-edge { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apss_shared 12>; + mbox-names = "mpss_smem"; + interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + }; + }; + }; sdhc2_opp_table: sdhc2-opp-table { compatible = "operating-points-v2"; @@ -1636,23 +1721,6 @@ }; }; - ufs_ice: ufsice@1d90000 { - compatible = "qcom,ice"; - reg = <0x1d90000 0x8000>; - qcom,enable-ice-clk; - clock-names = "ufs_core_clk", - "iface_clk", "ice_core_clk"; - clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; - qcom,op-freq-hz = <0>, <0>, <300000000>; - vdd-hba-supply = <&ufs_phy_gdsc>; - qcom,bus-vector-names = "MIN", - "MAX"; - qcom,instance-type = "ufs"; - qcom,num-fde-slots = <31>; - }; - ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>; /* PHY regs */ reg-names = "phy_mem"; diff --git a/qcom/sdxbaagha-pcie.dtsi b/qcom/sdxbaagha-pcie.dtsi index 2a6ff4b0..c8c72e19 100755 --- a/qcom/sdxbaagha-pcie.dtsi +++ b/qcom/sdxbaagha-pcie.dtsi @@ -99,8 +99,8 @@ resets = <&gcc GCC_PCIE_BCR>, <&gcc GCC_PCIE_PHY_BCR>; - reset-names = "pcie_core_reset", - "pcie_phy_reset"; + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; qcom,smmu-sid-base = <0x0400>; iommu-map = <0x0 &apps_smmu 0x0400 0x1>, diff --git a/qcom/sdxbaagha.dtsi b/qcom/sdxbaagha.dtsi index 9d2c6768..1ce0b392 100755 --- a/qcom/sdxbaagha.dtsi +++ b/qcom/sdxbaagha.dtsi @@ -142,7 +142,7 @@ alloc-ranges = <0x00000000 0xffffffff>; reusable; alignment = <0x400000>; - size = <0x800000>; + size = <0x400000>; }; qseecom_ta_mem: qseecom_ta_region { diff --git a/qcom/sdxpinn-pcie.dtsi b/qcom/sdxpinn-pcie.dtsi index fe825953..a741a2e9 100755 --- a/qcom/sdxpinn-pcie.dtsi +++ b/qcom/sdxpinn-pcie.dtsi @@ -122,14 +122,13 @@ qcom,l1-2-th-value = <150>; qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; - qcom,target-link-speed = <3>; - qcom,pcie-phy-ver = <100>; + qcom,pcie-phy-ver = <105>; qcom,phy-status-offset = <0x1214>; qcom,phy-status-bit = <7>; qcom,phy-power-down-offset = <0x1240>; qcom,phy-sequence = <0x1240 0x03 0x0 - 0x0030 0x1d 0x0 + 0x0030 0x18 0x0 0x0034 0x03 0x0 0x0078 0x01 0x0 0x007c 0x00 0x0 @@ -144,7 +143,7 @@ 0x02a0 0x7c 0x0 0x02b4 0x05 0x0 0x02e8 0x0a 0x0 - 0x030c 0x0d 0x0 + 0x030c 0x11 0x0 0x0320 0x0b 0x0 0x0348 0x1c 0x0 0x0388 0x20 0x0 @@ -164,7 +163,7 @@ 0x0420 0x78 0x0 0x0424 0x76 0x0 0x0428 0xff 0x0 - 0x0830 0x1d 0x0 + 0x0830 0x18 0x0 0x0834 0x03 0x0 0x0878 0x01 0x0 0x087c 0x00 0x0 @@ -179,7 +178,7 @@ 0x0aa0 0x7c 0x0 0x0ab4 0x05 0x0 0x0ae8 0x0a 0x0 - 0x0b0c 0x0d 0x0 + 0x0b0c 0x11 0x0 0x0b20 0x0b 0x0 0x0b48 0x1c 0x0 0x0b88 0x20 0x0 @@ -203,11 +202,11 @@ 0x0eb4 0x00 0x0 0x0ec4 0x00 0x0 0x0ec8 0x1f 0x0 - 0x0ed4 0x12 0x0 + 0x0ed4 0xd4 0x0 0x0ed8 0x12 0x0 0x0edc 0xdb 0x0 0x0ee0 0x9a 0x0 - 0x0ee4 0x38 0x0 + 0x0ee4 0x32 0x0 0x0ee8 0xb6 0x0 0x0eec 0x64 0x0 0x0ef0 0x1f 0x0 @@ -276,6 +275,8 @@ 0x1450 0x03 0x0 0x1490 0x00 0x0 0x14a0 0x16 0x0 + 0x14f0 0x27 0x0 + 0x14f4 0x27 0x0 0x1508 0x02 0x0 0x155c 0x2e 0x0 0x157c 0x03 0x0 @@ -287,6 +288,7 @@ 0x158c 0x0f 0x0 0x15ac 0xf2 0x0 0x15c0 0xf2 0x0 + 0x1370 0x17 0x0 0x1828 0x00 0x0 0x1c28 0x00 0x0 0x1e24 0x00 0x0 @@ -433,7 +435,7 @@ qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; - qcom,pcie-phy-ver = <101>; + qcom,pcie-phy-ver = <104>; qcom,phy-status-offset = <0x214>; qcom,phy-status-bit = <6>; qcom,phy-power-down-offset = <0x240>; @@ -457,7 +459,7 @@ 0x0110 0x08 0x0 0x00bc 0x0e 0x0 0x0120 0x42 0x0 - 0x0080 0x0a 0x0 + 0x0080 0x08 0x0 0x0084 0x1a 0x0 0x0020 0x14 0x0 0x0024 0x34 0x0 @@ -501,6 +503,7 @@ 0x1118 0x1c 0x0 0x10f8 0x07 0x0 0x11f8 0x08 0x0 + 0x1600 0x00 0x0 0x0e84 0x15 0x0 0x0e90 0x3f 0x0 0x0ee4 0x02 0x0 @@ -540,12 +543,14 @@ 0x0388 0x77 0x0 0x0398 0x0b 0x0 0x06a4 0x1e 0x0 + 0x06f4 0x27 0x0 0x03e0 0x0f 0x0 0x060c 0x1d 0x0 0x0614 0x07 0x0 0x0620 0xc1 0x0 0x0694 0x00 0x0 0x03d0 0x8c 0x0 + 0x0368 0x17 0x0 0x1424 0x00 0x0 0x1428 0x00 0x0 0x0200 0x00 0x0 @@ -691,7 +696,7 @@ qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; - qcom,pcie-phy-ver = <001>; + qcom,pcie-phy-ver = <102>; qcom,phy-status-offset = <0x214>; qcom,phy-status-bit = <6>; qcom,phy-power-down-offset = <0x240>; @@ -709,6 +714,8 @@ 0x0034 0xaa 0x0 0x0038 0x02 0x0 0x003c 0x01 0x0 + 0x0048 0xb4 0x0 + 0x004c 0x03 0x0 0x0060 0xde 0x0 0x0064 0x07 0x0 0x0070 0x02 0x0 @@ -720,6 +727,7 @@ 0x0090 0x55 0x0 0x0094 0x55 0x0 0x0098 0x03 0x0 + 0x00a8 0x24 0x0 0x00bc 0x0e 0x0 0x00c0 0x00 0x0 0x00cc 0x31 0x0 @@ -737,12 +745,14 @@ 0x02dc 0x05 0x0 0x0388 0x77 0x0 0x0398 0x0b 0x0 + 0x03d0 0x0c 0x0 0x03e0 0x0f 0x0 0x060c 0x1d 0x0 0x061c 0x8c 0x0 0x0620 0xc1 0x0 0x0654 0x00 0x0 0x0694 0x00 0x0 + 0x06f4 0x27 0x0 0x0e3c 0x17 0x0 0x0e40 0x06 0x0 0x0e84 0x15 0x0 @@ -750,11 +760,15 @@ 0x0ee4 0x02 0x0 0x1008 0x09 0x0 0x1014 0x05 0x0 + 0x1044 0xf0 0x0 0x104c 0x08 0x0 0x1050 0x08 0x0 0x10cc 0xf0 0x0 0x10d8 0x0f 0x0 - 0x10dc 0x11 0x0 + 0x10dc 0x0d 0x0 + 0x10ec 0x0e 0x0 + 0x10f0 0x4a 0x0 + 0x10f4 0x06 0x0 0x10f8 0x07 0x0 0x1118 0x0c 0x0 0x115c 0x3f 0x0 diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi index 315942a6..854c3fab 100755 --- a/qcom/sdxpinn.dtsi +++ b/qcom/sdxpinn.dtsi @@ -828,7 +828,8 @@ <1057800 725760>; iommus = <&apps_smmu 0x100 0x3>; - qcom,iommu-dma = "bypass"; + qcom,iommu-dma = "atomic"; + dma-coherent; status = "disabled"; }; diff --git a/qcom/slate.dtsi b/qcom/slate.dtsi index 2c7e3a71..945c0069 100755 --- a/qcom/slate.dtsi +++ b/qcom/slate.dtsi @@ -181,6 +181,11 @@ qcom,intents = <0x1000 10>; }; + qcom,glink-ss-bt-le-data { + qcom,glink-channels = "ss_bt_le_data"; + qcom,intents = <0x1000 10>; + }; + }; qcom,slatecom-rpmsg { diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index fac2d671..cf8903c8 100755 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -465,16 +465,11 @@ reg = <0x0 0xa4c00000 0x0 0x3c00000>; }; - cont_splash_memory: cont_splash_region { + cont_splash_memory: splash_region { reg = <0x0 0x9c000000 0x0 0x2400000>; label = "cont_splash_region"; }; - disp_rdump_memory: disp_rdump_region { - reg = <0x0 0x9c000000 0x0 0x02400000>; - label = "disp_rdump_region"; - }; - adsp_mem: adsp_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; @@ -709,6 +704,7 @@ cpu_pmu: cpu-pmu { compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; }; @@ -1112,24 +1108,6 @@ }; }; - ufs_ice: ufsice@1d90000 { - compatible = "qcom,ice"; - reg = <0x1d90000 0x8000>; - qcom,enable-ice-clk; - clock-names = "ufs_core_clk", "bus_clk", - "iface_clk", "ice_core_clk"; - clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; - qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; - vdd-hba-supply = <&ufs_phy_gdsc>; - qcom,bus-vector-names = "MIN", - "MAX"; - qcom,instance-type = "ufs"; - qcom,num-fde-slots = <31>; - }; - ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xda8>; /* PHY regs */ reg-names = "phy_mem"; @@ -1687,7 +1665,7 @@ qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; - glink-edge { + glink_edge_modem: glink-edge { qcom,remote-pid = <1>; transport = "smem"; mboxes = <&apss_shared 12>; @@ -1721,17 +1699,6 @@ }; }; - qcom,pmu { - compatible = "qcom,pmu"; - qcom,long-counter; - qcom,pmu-events-tbl = - < 0x0008 0xFF 0xFF 0xFF >, - < 0x0011 0xFF 0xFF 0xFF >, - < 0x0017 0xFF 0xFF 0xFF >, - < 0x002A 0xFF 0xFF 0xFF >, - < 0x1000 0xFF 0xFF 0xFF >; - }; - ddr_freq_table: ddr-freq-table { qcom,freq-tbl = < 200000 >, @@ -1916,7 +1883,8 @@ < 1152000 768000 >, < 1344000 960000 >, < 1689600 1228800 >, - < 2016000 1344000 >; + < 2016000 1344000 >, + < 2131200 1612800 >; qcom,sampling-enabled; }; @@ -1929,7 +1897,8 @@ < 1152000 768000 >, < 1344000 960000 >, < 1689600 1228800 >, - < 2016000 1344000 >; + < 2016000 1344000 >, + < 2419200 1612800 >; qcom,sampling-enabled; }; }; diff --git a/qcom/smb1390.dtsi b/qcom/smb1390.dtsi new file mode 100755 index 00000000..a273f89c --- /dev/null +++ b/qcom/smb1390.dtsi @@ -0,0 +1,56 @@ +#include <dt-bindings/interrupt-controller/irq.h> + +smb1390: qcom,smb1390@10 { + compatible = "qcom,i2c-pmic"; + reg = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x2 0xC5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt_names = "smb1390"; + interrupt-controller; + #interrupt-cells = <3>; + qcom,periph-map = <0x10>; + status = "disabled"; + + smb1390_charger: qcom,charge_pump { + compatible = "qcom,smb1390-charger-psy"; + #io-channel-cells = <1>; + interrupt-parent = <&smb1390>; + status = "disabled"; + + qcom,core { + interrupts = <0x10 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x5 IRQ_TYPE_EDGE_RISING>, + <0x10 0x6 IRQ_TYPE_EDGE_RISING>, + <0x10 0x7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "switcher-off-window", + "switcher-off-fault", + "tsd-fault", + "irev-fault", + "vph-ov-hard", + "vph-ov-soft", + "ilim", + "temp-alarm"; + }; + }; +}; + +smb1390_slave: qcom,smb1390_slave@18 { + compatible = "qcom,i2c-pmic"; + reg = <0x18>; + #address-cells = <1>; + #size-cells = <0>; + qcom,periph-map = <0x10>; + status = "disabled"; + + smb1390_slave_charger: qcom,charge_pump_slave { + compatible = "qcom,smb1390-slave"; + #io-channel-cells = <1>; + status = "disabled"; + }; +}; diff --git a/qcom/trinket-dma-heaps.dtsi b/qcom/trinket-dma-heaps.dtsi new file mode 100755 index 00000000..724a3992 --- /dev/null +++ b/qcom/trinket-dma-heaps.dtsi @@ -0,0 +1,45 @@ +#include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h> + +&soc { + qcom,dma-heaps { + compatible = "qcom,dma-heaps"; + + qcom,qseecom { + qcom,dma-heap-name = "qcom,qseecom"; + qcom,dma-heap-type = <HEAP_TYPE_CARVEOUT>; + memory-region = <&qseecom_mem>; + }; + + qcom,qseecom_ta { + qcom,dma-heap-name = "qcom,qseecom-ta"; + qcom,dma-heap-type = <HEAP_TYPE_CMA>; + memory-region = <&qseecom_ta_mem>; + }; + + qcom,secure_display { + qcom,dma-heap-name = "qcom,secure-display"; + qcom,dma-heap-type = <HEAP_TYPE_CMA>; + memory-region = <&secure_display_memory>; + }; + + qcom,adsp { + qcom,dma-heap-name = "qcom,adsp"; + qcom,dma-heap-type = <HEAP_TYPE_CMA>; + memory-region = <&adsp_mem>; + }; + + qcom,secure_cdsp { + qcom,dma-heap-name = "qcom,secure-cdsp"; + qcom,dma-heap-type = <HEAP_TYPE_SECURE_CARVEOUT>; + memory-region = <&cdsp_sec_mem>; + qcom,token = <0x20000000>; + }; + + qcom,user_contig { + qcom,dma-heap-name = "qcom,user-contig"; + qcom,dma-heap-type = <HEAP_TYPE_CMA>; + memory-region = <&user_contig_mem>; + }; + + }; +}; diff --git a/qcom/trinket-iot-dp-idp-overlay.dts b/qcom/trinket-iot-dp-idp-overlay.dts new file mode 100755 index 00000000..41153588 --- /dev/null +++ b/qcom/trinket-iot-dp-idp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "trinket-iot-idp.dtsi" + +/ { + model = "Display Port Enable IDP"; + compatible = "qcom,trinket-iot-idp", "qcom,trinket-iot", "qcom,idp"; + qcom,msm-id = <467 0x10000>; + qcom,board-id = <34 4>; +}; diff --git a/qcom/trinket-iot-dp-idp.dts b/qcom/trinket-iot-dp-idp.dts new file mode 100755 index 00000000..137766cd --- /dev/null +++ b/qcom/trinket-iot-dp-idp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "trinket-iot.dtsi" +#include "trinket-iot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. TRINKET IOT Disp. Port Enable IDP"; + compatible = "qcom,trinket-iot-idp", "qcom,trinket-iot", "qcom,idp"; + qcom,board-id = <34 4>; +}; diff --git a/qcom/trinket-iot-external-codec-idp-overlay.dts b/qcom/trinket-iot-external-codec-idp-overlay.dts new file mode 100755 index 00000000..3c29b242 --- /dev/null +++ b/qcom/trinket-iot-external-codec-idp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "trinket-iot-idp.dtsi" + +/ { + model = "Ext Audio Codec IDP"; + compatible = "qcom,trinket-iot-idp", "qcom,trinket-iot", "qcom,idp"; + qcom,msm-id = <467 0x10000>; + qcom,board-id = <34 1>; +}; diff --git a/qcom/trinket-iot-external-codec-idp.dts b/qcom/trinket-iot-external-codec-idp.dts new file mode 100755 index 00000000..dded943f --- /dev/null +++ b/qcom/trinket-iot-external-codec-idp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "trinket-iot.dtsi" +#include "trinket-iot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. TRINKET IOT Ext Audio Codec IDP"; + compatible = "qcom,trinket-iot-idp", "qcom,trinket-iot", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/trinket-iot-idp-overlay.dts b/qcom/trinket-iot-idp-overlay.dts new file mode 100755 index 00000000..ede3d642 --- /dev/null +++ b/qcom/trinket-iot-idp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "trinket-iot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. TRINKET IOT IDP Overlay"; + compatible = "qcom,trinket-iot"; + qcom,msm-id = <467 0x10000>; + qcom,board-id = <34 0>; +}; diff --git a/qcom/trinket-iot-idp.dts b/qcom/trinket-iot-idp.dts new file mode 100755 index 00000000..0d05a3b2 --- /dev/null +++ b/qcom/trinket-iot-idp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "trinket-iot.dtsi" +#include "trinket-iot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. TRINKET IOT IDP SoC"; + compatible = "qcom,trinket-iot"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/trinket-iot-idp.dtsi b/qcom/trinket-iot-idp.dtsi new file mode 100755 index 00000000..e69de29b --- /dev/null +++ b/qcom/trinket-iot-idp.dtsi diff --git a/qcom/trinket-iot-usbc-external-codec-idp-overlay.dts b/qcom/trinket-iot-usbc-external-codec-idp-overlay.dts new file mode 100755 index 00000000..534c325d --- /dev/null +++ b/qcom/trinket-iot-usbc-external-codec-idp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "trinket-iot-idp.dtsi" + +/ { + model = "USB-C Ext Audio Codec IDP"; + compatible = "qcom,trinket-iot-idp", "qcom,trinket-iot", "qcom,idp"; + qcom,msm-id = <467 0x10000>; + qcom,board-id = <34 3>; +}; diff --git a/qcom/trinket-iot-usbc-external-codec-idp.dts b/qcom/trinket-iot-usbc-external-codec-idp.dts new file mode 100755 index 00000000..9601741c --- /dev/null +++ b/qcom/trinket-iot-usbc-external-codec-idp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "trinket-iot.dtsi" +#include "trinket-iot-idp.dtsi" + +/ { + model = "Qualcomm Technologies,Inc. TRINKET IOT USBC Ext Aud Codec IDP"; + compatible = "qcom,trinket-iot-idp", "qcom,trinket-iot", "qcom,idp"; + qcom,board-id = <34 3>; +}; diff --git a/qcom/trinket-iot-usbc-idp-overlay.dts b/qcom/trinket-iot-usbc-idp-overlay.dts new file mode 100755 index 00000000..26c0a300 --- /dev/null +++ b/qcom/trinket-iot-usbc-idp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "trinket-iot-idp.dtsi" + +/ { + model = "USBC Audio IDP"; + compatible = "qcom,trinket-iot-idp", "qcom,trinket-iot", "qcom,idp"; + qcom,msm-id = <467 0x10000>; + qcom,board-id = <34 2>; +}; diff --git a/qcom/trinket-iot-usbc-idp.dts b/qcom/trinket-iot-usbc-idp.dts new file mode 100755 index 00000000..d6320adc --- /dev/null +++ b/qcom/trinket-iot-usbc-idp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "trinket-iot.dtsi" +#include "trinket-iot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. TRINKET IOT USBC Audio IDP"; + compatible = "qcom,trinket-iot-idp", "qcom,trinket-iot", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/trinket-iot-usbc-idp.dtsi b/qcom/trinket-iot-usbc-idp.dtsi new file mode 100755 index 00000000..e69de29b --- /dev/null +++ b/qcom/trinket-iot-usbc-idp.dtsi diff --git a/qcom/trinket-iot.dts b/qcom/trinket-iot.dts new file mode 100755 index 00000000..4ae5e487 --- /dev/null +++ b/qcom/trinket-iot.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "trinket-iot.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. TRINKET IOT IDP SoC"; + compatible = "qcom,trinket-iot"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/trinket-iot.dtsi b/qcom/trinket-iot.dtsi new file mode 100755 index 00000000..9f1125f2 --- /dev/null +++ b/qcom/trinket-iot.dtsi @@ -0,0 +1,8 @@ +#include "trinket.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. TRINKET IOT"; + compatible = "qcom,trinket-iot"; + qcom,msm-id = <467 0x0>; + qcom,msm-name = "trinket"; +}; diff --git a/qcom/trinket-pinctrl.dtsi b/qcom/trinket-pinctrl.dtsi new file mode 100755 index 00000000..74c7087c --- /dev/null +++ b/qcom/trinket-pinctrl.dtsi @@ -0,0 +1,11 @@ +&soc { + tlmm: pinctrl@400000 { + compatible = "qcom,trinket-pinctrl"; + reg = <0x400000 0xc00000>; + interrupts = <GIC_SPI 227 IRQ_TYPE_NONE>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/qcom/trinket.dts b/qcom/trinket.dts new file mode 100755 index 00000000..5173a52e --- /dev/null +++ b/qcom/trinket.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +#include "trinket.dtsi" + +/ { + compatible = "qcom,trinket"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/trinket.dtsi b/qcom/trinket.dtsi new file mode 100755 index 00000000..6b8e12f1 --- /dev/null +++ b/qcom/trinket.dtsi @@ -0,0 +1,844 @@ +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Qualcomm Technologies, Inc. Trinket"; + compatible = "qcom,trinket"; + qcom,msm-id = <467 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x1 0x40000000 0x0 0x80000000>, + <0x1 0xc0000000 0x0 0xc0000000>, + <0x2 0xc0000000 0x1 0x40000000>; + granule = <512>; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + i-cache-size = <0x8000>; + d-cache-size = <0x8000>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x80000>; + cache-level = <2>; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + i-cache-size = <0x8000>; + d-cache-size = <0x8000>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + + L1_I_1: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_1: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + + L1_I_2: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_2: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + + L1_I_3: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_3: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + d-cache-size = <0x10000>; + i-cache-size = <0x10000>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x100000>; + cache-level = <2>; + }; + + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + d-cache-size = <0x10000>; + i-cache-size = <0x10000>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + + L1_I_101: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_101: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x102>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + d-cache-size = <0x10000>; + i-cache-size = <0x10000>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + + L1_I_102: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_102: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x103>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + dynamic-power-coefficient = <282>; + d-cache-size = <0x10000>; + i-cache-size = <0x10000>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + + L1_I_103: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_103: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + idle-states { }; + + soc: soc { }; + + firmware: firmware { + scm { + compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* HYP 6MB */ + hyp_region: hyp_region@45700000 { + no-map; + reg = <0x0 0x45700000 0x0 0x600000>; + }; + + /* XBL(BOOT) 1 MB + AOP (256KB) */ + xbl_aop_mem: xbl_aop_mem@45e00000 { + no-map; + reg = <0x0 0x45e00000 0x0 0x140000>; + }; + + /* Secdata / APSS (4 KB) */ + sec_apps_mem: sec_apps_region@45fff000 { + no-map; + reg = <0x0 0x45fff000 0x0 0x1000>; + }; + + /* SMEM (2 MB) */ + smem_region: smem@46000000 { + no-map; + reg = <0x0 0x46000000 0x0 0x200000>; + }; + + /* TZ_STAT (1 MB) + TAGS (8 MB) + TZ (2 MB) + TZ Apps (14 MB) + + * Stargate (TZ Apps) (20 MB) + */ + removed_region: removed_region@46200000 { + no-map; + reg = <0x0 0x46200000 0x0 0x2d00000>; + }; + + /* MPSS_WLAN (126 MB) */ + pil_modem_mem: modem_region@4b000000 { + no-map; + reg = <0x0 0x4b000000 0x0 0x7e00000>; + }; + + /* VIDEO (5 MB) */ + pil_video_mem: pil_video_region@52e00000 { + no-map; + reg = <0x0 0x52e00000 0x0 0x500000>; + }; + + /* WLAN (2 MB) */ + wlan_msa_mem: wlan_msa_region@53300000 { + no-map; + reg = <0x0 0x53300000 0x0 0x200000>; + }; + + /* cDSP (30 MB) */ + pil_cdsp_mem: cdsp_regions@53500000 { + no-map; + reg = <0x0 0x53500000 0x0 0x1e00000>; + }; + + /* ADSP (30 MB) */ + pil_adsp_mem: pil_adsp_region@55300000 { + no-map; + reg = <0x0 0x55300000 0x0 0x1e00000>; + }; + + /* IPA FW (64 KB) */ + pil_ipa_fw_mem: ips_fw_region@57100000 { + no-map; + reg = <0x0 0x57100000 0x0 0x10000>; + }; + + /* IPA GSI (20 KB) */ + pil_ipa_gsi_mem: ipa_gsi_region@57110000 { + no-map; + reg = <0x0 0x57110000 0x0 0x5000>; + }; + + /* GPU micro code (8 KB) */ + pil_gpu_mem: gpu_region@57115000 { + no-map; + reg = <0x0 0x57115000 0x0 0x2000>; + }; + + /* UEFI/secure_dsp_mem (8 MB) + Secure DSP Heap (22 MB) */ + cdsp_sec_mem: cdsp_sec_regions@5f800000 { + no-map; + reg = <0x0 0x5f800000 0x0 0x1e00000>; + }; + + /* QSEECOM (20 MB) */ + qseecom_mem: qseecom_region@5e400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0x0 0x5e400000 0x0 0x1400000>; + }; + + /* user_config (16 MB) */ + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + /* qseccom_ta_mem (16 MB) */ + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + /* secure_display_memory (140 MB) */ + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x8c00000>; + }; + + /* adsp_memory (8 MB) */ + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; + + /* sdsp_mem (4 MB) */ + sdsp_mem: sdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; + }; + + /* dump_mem (4 MB) */ + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0x0 0x400000>; + }; + + /* cont_splash_memory (15 MB) */ + cont_splash_memory: cont_splash_region@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + label = "cont_splash_region"; + }; + + /* dfps_data_memory (1 MB) */ + dfps_data_memory: dfps_data_region@5cf00000 { + reg = <0x0 0x5cf00000 0x0 0x0100000>; + label = "dfps_data_region"; + }; + + /* disp_rdump_memory (15 MB) */ + disp_rdump_memory: disp_rdump_region@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + label = "disp_rdump_region"; + }; + + /* global autoconfigured region for contiguous allocations (32 MB) */ + system_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + #gpio-cells = <2>; + compatible = "simple-bus"; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0xf200000 0x10000>, /* GICD */ + <0xf300000 0x100000>; /* GICR * 8 */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + wdog: qcom,wdt@f017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf017000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 3 0>, <0 4 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <19200000>; + }; + + memtimer: timer@f120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0f120000 0x1000>; + clock-frequency = <19200000>; + + frame@f121000 { + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0f121000 0x1000>, + <0x0f122000 0x1000>; + }; + + frame@f123000 { + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf123000 0x1000>; + status = "disabled"; + }; + + frame@f124000 { + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf124000 0x1000>; + status = "disabled"; + }; + + frame@f125000 { + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf125000 0x1000>; + status = "disabled"; + }; + + frame@f126000 { + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf126000 0x1000>; + status = "disabled"; + }; + + frame@f127000 { + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf127000 0x1000>; + status = "disabled"; + }; + + frame@f128000 { + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf128000 0x1000>; + status = "disabled"; + }; + }; + + vendor_hooks: qcom,cpu-vendor-hooks { + compatible = "qcom,cpu-vendor-hooks"; + }; + + tcsr_mutex_block: syscon@00340000 { + compatible = "syscon"; + reg = <0x340000 0x40000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@03c0000 { + compatible = "syscon"; + reg = <0x003C0000 0x40000>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + qcom-secure-buffer { + compatible = "qcom,secure-buffer"; + }; + + restart@440b000 { + compatible = "qcom,pshold"; + reg = <0x440b000 0x4>, <0x03d3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + qcom,mpm2-sleep-counter@4403000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x4403000 0x1000>; + clock-frequency = <32768>; + }; + + qcom,msm-imem@c125000 { + compatible = "qcom,msm-imem"; + reg = <0xc125000 0x1000>; + ranges = <0x0 0xc125000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + + pil@6dc { + compatible = "qcom,msm-imem-pil-disable-timeout"; + reg = <0x6dc 0x4>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c200_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c300_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c400_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c500_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c600_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c700_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + tmc_etf { + qcom,dump-size = <0x8000>; + qcom,dump-id = <0xf0>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + l1_icache0 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x60>; + }; + + l1_icache100 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x61>; + }; + + l1_icache200 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x62>; + }; + + l1_icache300 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x63>; + }; + + l1_icache400 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x64>; + }; + + l1_icache500 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x65>; + }; + + l1_icache600 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x66>; + }; + + l1_icache700 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x80>; + }; + + l1_dcache100 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x81>; + }; + + l1_dcache200 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x82>; + }; + + l1_dcache300 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x83>; + }; + + l1_dcache400 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x84>; + }; + + l1_dcache500 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x85>; + }; + + l1_dcache600 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x86>; + }; + + l1_dcache700 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x87>; + }; + + l1_tlb0 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x120>; + }; + + l1_tlb100 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x121>; + }; + + l1_tlb200 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x122>; + }; + + l1_tlb300 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x123>; + }; + + l1_tlb400 { + qcom,dump-size = <0x4800>; + qcom,dump-id = <0x124>; + }; + + l1_tlb500 { + qcom,dump-size = <0x4800>; + qcom,dump-id = <0x125>; + }; + + l1_tlb600 { + qcom,dump-size = <0x4800>; + qcom,dump-id = <0x126>; + }; + + l1_tlb700 { + qcom,dump-size = <0x4800>; + qcom,dump-id = <0x127>; + }; + }; + + mini_dump_mode { + compatible = "qcom,minidump"; + status = "ok"; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + +}; + +#include "trinket-pinctrl.dtsi" +#include "trinket-dma-heaps.dtsi" diff --git a/qcom/trinketp-iot-dp-idp-overlay.dts b/qcom/trinketp-iot-dp-idp-overlay.dts new file mode 100755 index 00000000..13b47902 --- /dev/null +++ b/qcom/trinketp-iot-dp-idp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "trinketp-iot-idp.dtsi" + +/ { + model = "Display Port Enable IDP"; + compatible = "qcom,trinketp-iot-idp", "qcom,trinketp-iot", "qcom,idp"; + qcom,msm-id = <468 0x10000>; + qcom,board-id = <34 4>; +}; diff --git a/qcom/trinketp-iot-dp-idp.dts b/qcom/trinketp-iot-dp-idp.dts new file mode 100755 index 00000000..ec79c8b6 --- /dev/null +++ b/qcom/trinketp-iot-dp-idp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "trinketp-iot.dtsi" +#include "trinketp-iot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. TRINKETIOT Disp. Port Enable IDP"; + compatible = "qcom,trinketp-iot-idp", "qcom,trinketp-iot", "qcom,idp"; + qcom,board-id = <34 4>; +}; diff --git a/qcom/trinketp-iot-external-codec-idp-overlay.dts b/qcom/trinketp-iot-external-codec-idp-overlay.dts new file mode 100755 index 00000000..af7ac2f7 --- /dev/null +++ b/qcom/trinketp-iot-external-codec-idp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "trinketp-iot-idp.dtsi" + +/ { + model = "Ext Audio Codec IDP"; + compatible = "qcom,trinketp-iot-idp", "qcom,trinketp-iot", "qcom,idp"; + qcom,msm-id = <468 0x10000>; + qcom,board-id = <34 1>; +}; diff --git a/qcom/trinketp-iot-external-codec-idp.dts b/qcom/trinketp-iot-external-codec-idp.dts new file mode 100755 index 00000000..f3b59b41 --- /dev/null +++ b/qcom/trinketp-iot-external-codec-idp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "trinketp-iot.dtsi" +#include "trinket-iot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. TRINKETP IOT Ext Audio Codec IDP"; + compatible = "qcom,trinketp-iot-idp", "qcom,trinketp-iot", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/qcom/trinketp-iot-idp-overlay.dts b/qcom/trinketp-iot-idp-overlay.dts new file mode 100755 index 00000000..3c8bbbea --- /dev/null +++ b/qcom/trinketp-iot-idp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "trinketp-iot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. TRINKETP IOT IDP Overlay"; + compatible = "qcom,trinketp-iot"; + qcom,msm-id = <468 0x10000>; + qcom,board-id = <34 0>; +}; diff --git a/qcom/trinketp-iot-idp.dts b/qcom/trinketp-iot-idp.dts new file mode 100755 index 00000000..2f635c32 --- /dev/null +++ b/qcom/trinketp-iot-idp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "trinketp-iot.dtsi" +#include "trinketp-iot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. TRINKETP IOT IDP SoC"; + compatible = "qcom,trinketp-iot"; + qcom,board-id = <34 0>; +}; diff --git a/qcom/trinketp-iot-idp.dtsi b/qcom/trinketp-iot-idp.dtsi new file mode 100755 index 00000000..e69de29b --- /dev/null +++ b/qcom/trinketp-iot-idp.dtsi diff --git a/qcom/trinketp-iot-qcs.dtsi b/qcom/trinketp-iot-qcs.dtsi new file mode 100755 index 00000000..e69de29b --- /dev/null +++ b/qcom/trinketp-iot-qcs.dtsi diff --git a/qcom/trinketp-iot-usbc-external-codec-idp-overlay.dts b/qcom/trinketp-iot-usbc-external-codec-idp-overlay.dts new file mode 100755 index 00000000..067de064 --- /dev/null +++ b/qcom/trinketp-iot-usbc-external-codec-idp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "trinketp-iot-idp.dtsi" + +/ { + model = "USB-C Ext Audio Codec IDP"; + compatible = "qcom,trinketp-iot-idp", "qcom,trinketp-iot", "qcom,idp"; + qcom,msm-id = <468 0x10000>; + qcom,board-id = <34 3>; +}; diff --git a/qcom/trinketp-iot-usbc-external-codec-idp.dts b/qcom/trinketp-iot-usbc-external-codec-idp.dts new file mode 100755 index 00000000..4f150404 --- /dev/null +++ b/qcom/trinketp-iot-usbc-external-codec-idp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "trinketp-iot.dtsi" +#include "trinketp-iot-idp.dtsi" + +/ { + model = "Qualcomm Technologies,Inc. TRINKETP USBC Ext AudioCodec IDP"; + compatible = "qcom,trinketp-iot-idp", "qcom,trinketp-iot", "qcom,idp"; + qcom,board-id = <34 3>; +}; diff --git a/qcom/trinketp-iot-usbc-idp-overlay.dts b/qcom/trinketp-iot-usbc-idp-overlay.dts new file mode 100755 index 00000000..95756f9e --- /dev/null +++ b/qcom/trinketp-iot-usbc-idp-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "trinketp-iot-idp.dtsi" + +/ { + model = "USBC Audio IDP"; + compatible = "qcom,trinketp-iot-idp", "qcom,trinketp-iot", "qcom,idp"; + qcom,msm-id = <468 0x10000>; + qcom,board-id = <34 2>; +}; diff --git a/qcom/trinketp-iot-usbc-idp.dts b/qcom/trinketp-iot-usbc-idp.dts new file mode 100755 index 00000000..9fe5a176 --- /dev/null +++ b/qcom/trinketp-iot-usbc-idp.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "trinketp-iot.dtsi" +#include "trinketp-iot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. TRINKETP IOT USBC Audio IDP"; + compatible = "qcom,trinketp-iot-idp", "qcom,trinket-iot", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/trinketp-iot-usbc-idp.dtsi b/qcom/trinketp-iot-usbc-idp.dtsi new file mode 100755 index 00000000..e69de29b --- /dev/null +++ b/qcom/trinketp-iot-usbc-idp.dtsi diff --git a/qcom/trinketp-iot.dts b/qcom/trinketp-iot.dts new file mode 100755 index 00000000..d6abac33 --- /dev/null +++ b/qcom/trinketp-iot.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "trinketp-iot.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. TRINKETP SoC"; + compatible = "qcom,trinketp-iot"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/trinketp-iot.dtsi b/qcom/trinketp-iot.dtsi new file mode 100755 index 00000000..e1a12e69 --- /dev/null +++ b/qcom/trinketp-iot.dtsi @@ -0,0 +1,9 @@ +#include "trinket.dtsi" +#include "trinketp-iot-qcs.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. TRINKETP"; + compatible = "qcom,trinketp-iot"; + qcom,msm-id = <468 0x0>; + qcom,msm-name = "trinket"; +}; |