diff options
author | Andrei Ciubotariu <aciubotariu@google.com> | 2022-12-18 01:40:22 +0000 |
---|---|---|
committer | Andrei Ciubotariu <aciubotariu@google.com> | 2022-12-18 01:40:22 +0000 |
commit | 36ec2798c4b055b069c6cc5b9af35ebff6c6d1a0 (patch) | |
tree | 3ec1fcd76a0999932a5207e4fbdd01204dea927c | |
parent | 6c016fdc10ba024b2b7310b7f5924f07e2165703 (diff) | |
parent | 18cf3949e42fff558cd370ac1e28fe5dcbbce1a0 (diff) | |
download | devicetree-36ec2798c4b055b069c6cc5b9af35ebff6c6d1a0.tar.gz |
sw5100: Integrate LW 2.0 r00019.1
Bug: 262997652
Change-Id: Ib3f56ef1ca1f933dc96a871d52953db2a5a0a3d2
Signed-off-by: Andrei Ciubotariu <aciubotariu@google.com>
74 files changed, 4129 insertions, 295 deletions
diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index c8f05b54..57c1943f 100755 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -187,6 +187,9 @@ Generic board variants: - CCARD device: compatible = "qcom,ccard" +- QAM device: + compatible = "qcom,qam" + Boards (SoC type + board variant): compatible = "qcom,apq8016" @@ -353,6 +356,8 @@ compatible = "qcom,lemans-rumi" compatible = "qcom,lemans-ivi" compatible = "qcom,lemans-ivi-adp-air" compatible = "qcom,lemans-ivi-adp-star" +compatible = "qcom,lemans-ivi-qam-star" compatible = "qcom,lemans-adas-high" compatible = "qcom,lemans-adas-high-adp-air" compatible = "qcom,lemans-adas-high-adp-star" +compatible = "qcom,lemans-adas-high-qam-star" diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt index 9b82f696..6c035229 100755 --- a/bindings/arm/msm/qcom,llcc.txt +++ b/bindings/arm/msm/qcom,llcc.txt @@ -15,7 +15,8 @@ Properties: "qcom,lahaina-llcc" or "qcom,shima-llcc" or "qcom,waipio-llcc" or "qcom,sdxlemur-llcc" or "qcom,diwali-llcc" or "qcom,kalama-llcc" or "qcom,cinder-llcc" - or "qcom,sdmshrike-llcc" or "qcom,lemans-llcc". + or "qcom,sdmshrike-llcc" or "qcom,lemans-llcc" + or "qcom,kona-llcc". "qcom,llcc-v2" must be appended for V2 hardware or "qcom,llcc-v21" for V2.1 or "qcom,llcc-v31" for V3.1 or "qcom,llcc-v41" for V4.1. diff --git a/bindings/arm/msm/qcom,silent-boot.txt b/bindings/arm/msm/qcom,silent-boot.txt new file mode 100755 index 00000000..993ea6c6 --- /dev/null +++ b/bindings/arm/msm/qcom,silent-boot.txt @@ -0,0 +1,42 @@ +Power management Silent mode is a boot up mode with display and +audio disabled. This mode allows the platform to boot up the kernel +without enabling the UI, thereby masking the overall system boot latency. +Predominant usage could be seen in automotive applications where +boot latency is critical. +Top 2 use cases could be: +- One possible occasion for booting silently is when the driver approaches the + vehicle and based on the trigger by proximity sensor the vehicle does a remote + start before driver comes in the car. + +- Another might be if the system needs to run in the middle of + the night to perform updates. + +Add " pm_silentmode_kernel_state" viewable/editable via sysfs. + +Kernel driver to monitor external GPIO input to indicate boot into +kernel silent mode or not. This driver sets up the GPIO and links it +up with an IRQ that is rising/falling edge triggered. +On the GPIO rising edge, the IRQ thread is used to clear the sysfs +in the PM framework that holds the state of the pm_silentmode_kernel_state. +On the GPIO falling edge, the IRQ thread is used to set the sysfs +in the PM framework that holds the state of the pm_silentmode_kernel_state. + +The Device tree entry for silent mode can be used to register a GPIO +to the driver framework and use it to communicate to the Vehicle +interface processor. + +Required properties: + +- compatible: "qcom,silent-mode" +- qcom,silent-boot-gpio: GPIO needed HW interface from VIP to SoC +- interrupts: Assign interrupt that is dual edge triggered +- interrupt-names: Name of the interrupt under /proc/interrupt + +Example: + + qcom,silent-mode { + compatible = "qcom,silent-mode"; + qcom,silent-boot-gpio = <&pm8150_1_gpios 6 GPIO_ACTIVE_LOW>; + interrupts = < 0xc5 0 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "silent_pm8150_1_gpio6"; + }; diff --git a/bindings/msm_mhi_dev.txt b/bindings/msm_mhi_dev.txt index c46a176a..52d20dde 100755 --- a/bindings/msm_mhi_dev.txt +++ b/bindings/msm_mhi_dev.txt @@ -20,7 +20,7 @@ Required properties: - qcom,mhi-version: MHI specification version supported by the device. Optional property: - - qcom,use-ipa-software-channel: If property is present use IPA hardware + - qcom,use-mhi-dma-software-channel: If property is present use IPA hardware accelerated path for MHI software channel data transfers between host and device. - qcom,mhi-config-iatu: If property is present map the control and data region diff --git a/bindings/pci/pci-msm.txt b/bindings/pci/pci-msm.txt index 464a61b8..cdf1976c 100755 --- a/bindings/pci/pci-msm.txt +++ b/bindings/pci/pci-msm.txt @@ -265,6 +265,11 @@ interconnects: Value type: <bool> Definition: L1 sub-state (L1ss) is not supported +- qcom,apss-based-l1ss-sleep: + Usage: optional + Value type: <bool> + Definition: Apss based L1ss sleep is supported + - qcom,no-aux-clk-sync: Usage: optional Value type: <bool> diff --git a/bindings/pinctrl/qcom,direwolf-pinctrl.yaml b/bindings/pinctrl/qcom,direwolf-pinctrl.yaml new file mode 100755 index 00000000..33cc8e59 --- /dev/null +++ b/bindings/pinctrl/qcom,direwolf-pinctrl.yaml @@ -0,0 +1,148 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,direwolf-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. DIREWOLF TLMM block + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + Direwolf platform. + +properties: + compatible: + Usage: required + Value type: <string> + Definition: must be "qcom,direwolf-pinctrl" + + reg: + Usage: required + Value type: <prop-encoded-array> + Definition: the base address and size of the TLMM register space. + + interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: should specify the TLMM summary IRQ. + + interrupt-controller: + Usage: required + Value type: <none> + Definition: identifies this node as an interrupt controller + + #interrupt-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/interrupt-controller/irq.h> + + gpio-controller: + Usage: required + Value type: <none> + Definition: identifies this node as a gpio controller + + #gpio-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/gpio/gpio.h> + + wakeup-parent: + Usage: optional + Value type: <phandle> + Definition: A phandle to the wakeup interrupt controller for the SoC. + + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for + a general description of GPIO and interrupt bindings. + + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + The pin configuration nodes act as a container for an arbitrary number of + subnodes. Each of these subnodes represents some desired configuration for a + pin, a group, or a list of pins or groups. This configuration can include the + mux function to select on those pin(s)/group(s), and various pin configuration + parameters, such as pull-up, drive strength, etc. + + + PIN CONFIGURATION NODES: + + The name of each subnode is not important; all subnodes should be enumerated + and processed purely based on their content. + + Each subnode only affects those parameters that are explicitly listed. In + other words, a subnode that lists a mux function but no pin configuration + parameters implies no information about any pin configuration parameters. + Similarly, a pin subnode that describes a pullup parameter implies no + information about e.g. the mux function. + + + The following generic properties as defined in pinctrl-bindings.txt are valid + to specify in a pin configuration subnode: + + pins: + Usage: required + Value type: <string-array> + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins: + gpio0-gpio227 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + + function: + Usage: required + Value type: <string> + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + + bias-disable: + Usage: optional + Value type: <none> + Definition: The specified pins should be configured as no pull. + + bias-pull-down: + Usage: optional + Value type: <none> + Definition: The specified pins should be configured as pull down. + + bias-pull-up: + Usage: optional + Value type: <none> + Definition: The specified pins should be configured as pull up. + + output-high: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven high. + Not valid for sdc pins. + + output-low: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven low. + Not valid for sdc pins. + + drive-strength: + Usage: optional + Value type: <u32> + Definition: Selects the drive strength for the specified pins, in mA. + Valid values: 2, 4, 6, 8, 10, 12, 14 and 16 + +examples: + - | + tlmm: pinctrl@03000000 { + compatible = "qcom,direwolf-pinctrl"; + reg = <0x03000000 0xdc2000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + }; diff --git a/bindings/power/supply/qcom/qpnp-qnovo5.txt b/bindings/power/supply/qcom/qpnp-qnovo5.txt new file mode 100755 index 00000000..fb277287 --- /dev/null +++ b/bindings/power/supply/qcom/qpnp-qnovo5.txt @@ -0,0 +1,55 @@ +QPNP Qnovo5 pulse engine + +QPNP Qnovo5 is a PBS based pulse charging engine which works in tandem with the +QPNP SMB5 Charger device. It configures the QPNP SMB5 charger to +charge/discharge as per pulse characteristics. + +The QPNP Qnovo5 pulse engine has a single peripheral assigned to it. + +Properties: +- compatible: + Usage: required + Value type: <string> + Definition: It must be "qcom,qpnp-qnovo5". + +- reg: + Usage: required + Value type: <u32> + Definition: Specifies the base address of the module. Qnovo5 is using a + SDAM peripheral so this is the address of the SDAM module + being used. + +- interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: Specifies the interrupt associated with Qnovo5. + +- interrupt-names: + Usage: required + Value type: <string> + Definition: Specifies the interrupt name for Qnovo5. There is only one + interrupt named as "ptrain-done". + +- pinctrl-N: + Usage: optional + Value type: <phandle> + Definition: Specifies the pinctrl configuration that needs to be applied + when the charger is removed for controlling external FET. + +- pinctrl-names: + Usage: optional + Value type: <string> + Definition: Specifies the names for pinctrl configurations defined above. + Allowed names are "q_state1" and "q_state2". + +Example: + +qcom,qpnp-qnovo@b000 { + compatible = "qcom,qpnp-qnovo5"; + reg = <0xb000 0x100>; + interrupts = <0x2 0xb0 0x1 IRQ_TYPE_NONE>; + interrupt-names = "ptrain-done"; + pinctrl-names = "q_state1", "q_state2"; + pinctrl-0 = <&qnovo_fet_ctrl_state1>; + pinctrl-1 = <&qnovo_fet_ctrl_state2>; +}; diff --git a/bindings/remoteproc/qcom,rproc-slate.txt b/bindings/remoteproc/qcom,rproc-slate.txt new file mode 100755 index 00000000..7275180c --- /dev/null +++ b/bindings/remoteproc/qcom,rproc-slate.txt @@ -0,0 +1,20 @@ +* Slate Remoteproc Driver + +qcom_rproc_slate driver is responsible for loading slate firmware image, +crashdump collection and recovery. + +Required properties: +- compatible: Must be "qcom,rproc-slate" +- qcom,firmware-name: Slate Firmware Image name +- qcom,slate2ap-status-gpio: GPIO input from blackghost +- qcom,ap2slate-status-gpio: GPIO output to blackghost + +Example: + qcom,rproc-slate { + compatible = "qcom,rproc-slate"; + qcom,firmware-name = "slate.mdt"; + /* GPIO inputs from blackghost */ + qcom,slate2ap-status-gpio = <&tlmm 98 0>; + /* GPIO output to blackghost */ + qcom,ap2slate-status-gpio = <&tlmm 97 0>; + } diff --git a/bindings/soc/qcom/rename_devices.txt b/bindings/soc/qcom/rename_devices.txt new file mode 100755 index 00000000..9332903e --- /dev/null +++ b/bindings/soc/qcom/rename_devices.txt @@ -0,0 +1,29 @@ +* rename devices + +Required properties for block devices rename: + +- compatible: "qcom,rename-devices" compatibility string +- device-type: Device type to be renamed and supported device-types are block +- actual-dev: Original name of the disk assigned by generic driver +- rename-dev: New name of the disk or to set for disks respectively + +Example: + +rename_devices: rename_devices { + compatible = "qcom,rename-devices"; + rename_blk: rename_blk { + device-type = "block"; + actual-dev = "vda", "vdb", "vdc", + "vdd", "vde", "vdf", + "vdg", "vdh", "vdi", + "vdj", "vdk", "vdl", + "vdm", "vdn", "vdo", + "vdp", "vdq"; + rename-dev = "super", "userdata", "metadata", + "persist", "modem_a", "modem_b", + "bluetooth_a", "bluetooth_b", + "misc", "vbmeta_a", "vbmeta_b", + "boot_a", "boot_b", "dtbo_a", + "dtbo_b", "dsp_a", "dsp_b"; + }; +}; diff --git a/bindings/thermal/qti-aop-pmic-sensor.txt b/bindings/thermal/qti-aop-pmic-sensor.txt new file mode 100755 index 00000000..5176d2a6 --- /dev/null +++ b/bindings/thermal/qti-aop-pmic-sensor.txt @@ -0,0 +1,62 @@ +=================================================================== +QTI AOP pmic sensor driver +=================================================================== + +QTI AOP pmic sensor driver will be used to give external data of pmic rails like temperature, voltage, etc. +This driver reads the required external data from MSGRAM which is updated by +communicating to RPMH via QMP. + +Properties: +- compatible: + Usage: required + Value type: <string> + Definition: must be "qcom,aop-pmic-sensor" + + QTI AOP pmic sensor driver properties: +-qcom,dbu-id: + Usage: required + Value type: <Integer> + Definition: Unique ID for a particular pmic. + +-qcom,type: + Usage: required + Value type: <Integer> + Definition: It will be 1 and 0. 1 is identifier for voltage and 0 is for temperature. + +Example: + aop_pmic_sensor: aop-pmic-sensor@c3f03d8 { + compatible = "qcom,aop-pmic-sensor"; + reg = <0x0c3f03d8 0x28>; + mboxes = <&qmp_aop 0>; + #thermal-sensor-cells = <1>; + + mss-temp { + qcom,dbu-id = <1>; + qcom,type = <0>; + }; + + mx-temp { + qcom,dbu-id = <2>; + qcom,type = <0>; + }; + + cx-temp { + qcom,dbu-id = <3>; + qcom,type = <0>; + }; + + mss-volt { + qcom,dbu-id = <1>; + qcom,type = <1>; + }; + + mx-volt { + qcom,dbu-id = <2>; + qcom,type = <1>; + }; + + cx-volt { + qcom,dbu-id = <3>; + qcom,type = <1>; + }; + };
\ No newline at end of file diff --git a/qcom/Makefile b/qcom/Makefile index 5e38c8a2..f143af50 100755 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -71,6 +71,7 @@ kalama-dtb-$(CONFIG_ARCH_KALAMA) += \ $(call add-overlays, $(KALAMA_BOARDS) $(NOAPQ_KALAMA_BOARDS),$(KALAMA_BASE_DTB))\ $(call add-overlays, $(KALAMA_BOARDS) $(APQ_KALAMA_BOARDS),$(KALAMA_APQ_BASE_DTB)) kalama-overlays-dtb-$(CONFIG_ARCH_KALAMA) += $(KALAMA_BOARDS) $(NOAPQ_KALAMA_BOARDS) $(KALAMA_BASE_DTB) $(KALAMA_APQ_BASE_DTB) +kalama_le-overlays-dtb-$(CONFIG_ARCH_KALAMA) += $(KALAMA_BOARDS) $(NOAPQ_KALAMA_BOARDS) $(KALAMA_BASE_DTB) $(KALAMA_APQ_BASE_DTB) dtb-y += $(kalama-dtb-y) KHAJE_BASE_DTB += khaje.dtb khajep.dtb khajeq.dtb khajeg.dtb @@ -215,9 +216,11 @@ LEMANS_ADAS_HIGH_BASE_DTB += lemans-adas-high.dtb LEMANS_BOARDS += lemans-rumi-overlay.dtbo LEMANS_IVI_BOARDS += lemans-ivi-adp-air-overlay.dtbo \ - lemans-ivi-adp-star-overlay.dtbo + lemans-ivi-adp-star-overlay.dtbo \ + lemans-ivi-qam-star-overlay.dtbo LEMANS_ADAS_HIGH_BOARDS += lemans-adas-high-adp-air-overlay.dtbo \ - lemans-adas-high-adp-star-overlay.dtbo + lemans-adas-high-adp-star-overlay.dtbo \ + lemans-adas-high-qam-star-overlay.dtbo gen4auto-dtb-$(CONFIG_ARCH_LEMANS) += \ $(call add-overlays, $(LEMANS_IVI_BOARDS),$(LEMANS_IVI_BASE_DTB))\ @@ -255,6 +258,10 @@ DIREWOLF_LV_GVM_BASE_DTB += direwolf-vm-lv.dtb DIREWOLF_LV_GVM_BOARDS += \ direwolf-vm-lv-overlay.dtbo +DIREWOLF_LA_GVM_BASE_DTB += direwolf-vm-la.dtb + +DIREWOLF_LA_GVM_BOARDS += \ + direwolf-vm-la-overlay.dtbo SA8195_LA_GVM_BASE_DTB += sa8195-vm-la.dtb @@ -264,10 +271,12 @@ SA8195_LA_GVM_BOARDS += \ autogvm-dtb-$(CONFIG_QTI_QUIN_GVM) += \ $(call add-overlays, $(SA8155_LA_GVM_BOARDS),$(SA8155_LA_GVM_BASE_DTB)) \ $(call add-overlays, $(DIREWOLF_LV_GVM_BOARDS),$(DIREWOLF_LV_GVM_BASE_DTB)) \ - $(call add-overlays, $(SA8195_LA_GVM_BOARDS),$(SA8195_LA_GVM_BASE_DTB)) + $(call add-overlays, $(SA8195_LA_GVM_BOARDS),$(SA8195_LA_GVM_BASE_DTB)) \ + $(call add-overlays, $(DIREWOLF_LA_GVM_BOARDS),$(DIREWOLF_LA_GVM_BASE_DTB)) + autogvm-overlays-dtb-$(CONFIG_QTI_QUIN_GVM) += \ $(SA8155_LA_GVM_BOARDS) $(DIREWOLF_LV_GVM_BOARDS) $(SA8155_LA_GVM_BASE_DTB) $(DIREWOLF_LV_GVM_BASE_DTB) \ - $(SA8195_LA_GVM_BOARDS) $(SA8195_LA_GVM_BASE_DTB) + $(SA8195_LA_GVM_BOARDS) $(SA8195_LA_GVM_BASE_DTB) $(DIREWOLF_LA_GVM_BOARDS) $(DIREWOLF_LA_GVM_BASE_DTB) dtb-y += $(autogvm-dtb-y) diff --git a/qcom/cinder-coresight.dtsi b/qcom/cinder-coresight.dtsi index 884bb3f2..fa5d2503 100755 --- a/qcom/cinder-coresight.dtsi +++ b/qcom/cinder-coresight.dtsi @@ -6,7 +6,7 @@ reg-names = "tpdm-base"; atid = <71>; - coresight-name = "coresight-tpdm-swao_prio0"; + coresight-name = "coresight-tpdm-swao-prio-0"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; diff --git a/qcom/cinder-thermal.dtsi b/qcom/cinder-thermal.dtsi index d35287d6..29dee327 100755 --- a/qcom/cinder-thermal.dtsi +++ b/qcom/cinder-thermal.dtsi @@ -26,6 +26,43 @@ qcom,logic = <1>; }; }; + + aop_pmic_sensor: aop-pmic-sensor@c3f03d8 { + compatible = "qcom,aop-pmic-sensor"; + reg = <0x0c3f03d8 0x28>; + mboxes = <&qmp_aop 0>; + #thermal-sensor-cells = <1>; + + mss-temp { + qcom,pmic-id = <1>; + qcom,type = <0>; + }; + + mx-temp { + qcom,pmic-id = <2>; + qcom,type = <0>; + }; + + cx-temp { + qcom,pmic-id = <3>; + qcom,type = <0>; + }; + + mss-volt { + qcom,pmic-id = <1>; + qcom,type = <1>; + }; + + mx-volt { + qcom,pmic-id = <2>; + qcom,type = <1>; + }; + + cx-volt { + qcom,pmic-id = <3>; + qcom,type = <1>; + }; + }; }; &thermal_zones { @@ -394,4 +431,61 @@ }; }; }; -}; + + cx_temp { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&aop_pmic_sensor 1>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mx_temp { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&aop_pmic_sensor 2>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mss_temp { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&aop_pmic_sensor 3>; + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; +};
\ No newline at end of file diff --git a/qcom/cinder-v2.dtsi b/qcom/cinder-v2.dtsi index 5651ec65..b06264c7 100755 --- a/qcom/cinder-v2.dtsi +++ b/qcom/cinder-v2.dtsi @@ -1 +1,29 @@ #include "cinder.dtsi" + +&pcie_ep { + /delete-property/ sriov-mask; + qcom,pcie-parf-msi-vf-indexed; + qcom,db-fwd-off-varied; +}; + +&mhi_device { + qcom,mhi-ifc-id = <0x060117cb>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mhi-virt-device-int-4", + "mhi-virt-device-int-5", "mhi-virt-device-int-6", + "mhi-virt-device-int-7", "mhi-virt-device-int-8", + "mhi-virt-device-int-9", "mhi-virt-device-int-10", + "mhi-virt-device-int-11", "mhi-virt-device-int-12", + "mhi-virt-device-int-13", "mhi-virt-device-int-14", + "mhi-virt-device-int-15"; +}; diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi index cdf53652..7a075ddd 100755 --- a/qcom/cinder.dtsi +++ b/qcom/cinder.dtsi @@ -1318,7 +1318,7 @@ qcom,pcie-mhi-a7-irq; qcom,tcsr-not-supported; qcom,phy-status-reg2 = <0x1214>; - qcom,mhi-soc-reset-offset = <0xb01b8>; + qcom,mhi-soc-reset-offset = <0xb001b8>; qcom,aux-clk = <0x11>; qcom,sriov-mask = <0x1E0>; diff --git a/qcom/direwolf-vm-la-overlay.dts b/qcom/direwolf-vm-la-overlay.dts new file mode 100755 index 00000000..d2cf8a1e --- /dev/null +++ b/qcom/direwolf-vm-la-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "direwolf-vm.dtsi" +#include "direwolf-vm-la.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Direwolf Single LA Virtual Machine"; + compatible = "qcom,direwolf", "qcom,quinvm"; + qcom,msm-id = <460 0x10000>; + qcom,board-id = <0 0x1000001>; +}; diff --git a/qcom/direwolf-vm-la.dts b/qcom/direwolf-vm-la.dts new file mode 100755 index 00000000..75989518 --- /dev/null +++ b/qcom/direwolf-vm-la.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "direwolf-vm.dtsi" +#include "direwolf-vm-la.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Direwolf Single LA Virtual Machine"; + compatible = "qcom,direwolf", "qcom,quinvm"; + qcom,board-id = <0 0x1000001>; +}; diff --git a/qcom/direwolf-vm-la.dtsi b/qcom/direwolf-vm-la.dtsi new file mode 100755 index 00000000..c9f71ee7 --- /dev/null +++ b/qcom/direwolf-vm-la.dtsi @@ -0,0 +1,25 @@ +&soc { +}; + +&reserved_memory { + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x0a000000>; + }; +}; + +&qcom_dma_heaps { + qcom,display { + qcom,dma-heap-name = "qcom,display"; + qcom,dma-heap-type = <HEAP_TYPE_CMA>; + qcom,max-align = <9>; + memory-region = <&secure_display_memory>; + }; +}; + +&qcom_rng_ee3 { + status = "okay"; +}; diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi index 82a270b1..25c6cf8e 100755 --- a/qcom/direwolf-vm.dtsi +++ b/qcom/direwolf-vm.dtsi @@ -6,6 +6,186 @@ qcom,msm-id = <460 0x10000>; }; +&soc { + apps_smmu: apps-smmu@15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x15182000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,handoff-smrs = <0xffff 0x0>; + qcom,multi-match-handoff-smr; + #global-interrupts = <2>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; + }; + + dma_dev@0x0 { + compatible = "qcom,iommu-dma"; + memory-region = <&system_cma>; + }; + + qcom_rng_ee3: qrng@10d3000 { + compatible = "qcom,msm-rng"; + reg = <0x10d3000 0x1000>; + qcom,no-qrng-config; + clocks = <&dummycc RPMH_HWKM_CLK>; + clock-names = "km_clk_src"; + status = "disabled"; + }; + + qcom_rng_ee4: qrng@10d4000 { + compatible = "qcom,msm-rng"; + reg = <0x10d4000 0x1000>; + qcom,no-qrng-config; + clocks = <&dummycc RPMH_HWKM_CLK>; + clock-names = "km_clk_src"; + status = "disabled"; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,pdc"; + reg = <0xb220000 0x30000>; + qcom,pdc-ranges = <12 492 6>, <126 611 8>, <136 621 1>, <138 623 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; +}; + ®ulator { virt_regulator { compatible = "virtio,device31"; @@ -117,3 +297,5 @@ }; }; }; + +#include "pm8540-vm.dtsi" diff --git a/qcom/kalama-qrd.dtsi b/qcom/kalama-qrd.dtsi index 400e9d0f..3b68e1d4 100755 --- a/qcom/kalama-qrd.dtsi +++ b/qcom/kalama-qrd.dtsi @@ -344,7 +344,7 @@ }; &pcie0 { - qcom,pcie-phy-ver = <101>; + qcom,pcie-phy-ver = <102>; qcom,phy-sequence = <0x0240 0x03 0x0 0x00c0 0x01 0x0 0x00cc 0x62 0x0 @@ -452,12 +452,12 @@ 0x060c 0x1d 0x0 0x0614 0x07 0x0 0x0620 0xc1 0x0 - 0x0368 0x0F 0x0 - 0x1180 0x8C 0x0 - 0x1980 0x8C 0x0 + 0x0368 0x0f 0x0 + 0x1180 0x8f 0x0 + 0x1980 0x8f 0x0 0x0120 0x40 0x0 - 0x0080 0x0A 0x0 - 0x0084 0x1A 0x0 + 0x0080 0x0a 0x0 + 0x0084 0x1a 0x0 0x0020 0x14 0x0 0x0024 0x34 0x0 0x0624 0x05 0x0 diff --git a/qcom/kalama-vm.dtsi b/qcom/kalama-vm.dtsi index 8c68c186..993c89e7 100755 --- a/qcom/kalama-vm.dtsi +++ b/qcom/kalama-vm.dtsi @@ -106,7 +106,7 @@ vendor = "QTI"; image-name = "qcom,trustedvm"; qcom,pasid = <0x0 0x1c>; - qcom,qtee-config-info = "p=39,77,78,7C,8F,97,159,199,47E,7F1;"; + qcom,qtee-config-info = "p=39,77,78,7C,8F,97,FE,159,199,47E,7F1;"; qcom,secdomain-ids = <45>; qcom,primary-vm-index = <0>; vm-uri = "vmuid/trusted-ui"; diff --git a/qcom/kalama.dtsi b/qcom/kalama.dtsi index cf8fece2..d592845b 100755 --- a/qcom/kalama.dtsi +++ b/qcom/kalama.dtsi @@ -506,7 +506,7 @@ hwfence_shbuf: hwfence-shmem { no-map; - reg = <0x0 0xe6440000 0x0 0x279000>; + reg = <0x0 0xe6440000 0x0 0x2dd000>; }; trust_ui_vm_mem: trust_ui_vm_region@f3800000 { @@ -2582,7 +2582,7 @@ qcom,glinkpkt-ch-name = "DATA11"; qcom,glinkpkt-dev-name = "smd11"; }; - qcom,glinkpkt-btoip_control { + qcom,glinkpkt-xpan_control { qcom,glinkpkt-edge = "adsp"; qcom,glinkpkt-ch-name = "bt_cp_ctrl"; qcom,glinkpkt-dev-name = "bt_cp_ctrl"; diff --git a/qcom/kalamap-hdk.dtsi b/qcom/kalamap-hdk.dtsi index 56db337e..a2342d72 100755 --- a/qcom/kalamap-hdk.dtsi +++ b/qcom/kalamap-hdk.dtsi @@ -35,4 +35,5 @@ &pcie1 { qcom,boot-option = <0x2>; + qcom,apss-based-l1ss-sleep; }; diff --git a/qcom/kalamap-sg-hhg.dtsi b/qcom/kalamap-sg-hhg.dtsi index 8db68a41..1c231a2b 100755 --- a/qcom/kalamap-sg-hhg.dtsi +++ b/qcom/kalamap-sg-hhg.dtsi @@ -14,6 +14,7 @@ &pcie1 { vreg-3p3-supply = <&nvme_vreg>; qcom,boot-option = <0x2>; + qcom,apss-based-l1ss-sleep; }; ®ulator_ocp_notifier { diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index e9e96265..b361d4e4 100755 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -587,7 +587,7 @@ }; chosen { - bootargs = "lpm_levels.sleep_disabled=1 console=ttyMSM0,115200n8 msm_rtb.filter=0x237 service_locator.enable=1 swiotlb=2048 loop.max_part=7 cpufreq.default_governor=performance rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off export_pmu_events movable_node"; + bootargs = "lpm_levels.sleep_disabled=1 console=ttyMSM0,115200n8 msm_rtb.filter=0x237 service_locator.enable=1 swiotlb=2048 loop.max_part=7 cpufreq.default_governor=performance rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off export_pmu_events movable_node ftrace_dump_on_oops ssbd=force-off"; }; soc: soc { }; @@ -641,6 +641,7 @@ clk_virt: interconnect { compatible = "qcom,bengal-clk_virt"; + qcom,keepalive; #interconnect-cells = <1>; clock-names = "bus", "bus_a"; clocks = <&rpmcc RPM_SMD_QUP_CLK>, @@ -1955,9 +1956,9 @@ qcom,msm-rng-iface-clk; qcom,no-qrng-config; interconnect-names = "data_path"; - interconnects = <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_HWKM_CORE>; + interconnects = <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_PRNG>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "km_clk_src"; - clocks = <&rpmcc RPM_SMD_HWKM_CLK>; }; qcom_tzlog: tz-log@c125720 { @@ -2126,24 +2127,13 @@ qcom,master-offset = <4096>; }; - qcom,chd_silver { + qcom,chd { compatible = "qcom,core-hang-detect"; - label = "silver"; - cluster-id = <0>; - qcom,threshold-arr = <0x0f1880b0 0x0f1980b0 - 0x0f1a80b0 0x0f1b80b0>; - qcom,config-arr = <0x0f1880b8 0x0f1980b8 - 0x0f1a80b8 0x0f1b80b8>; - }; - - qcom,chd_gold { - compatible = "qcom,core-hang-detect"; - label = "gold"; - cluster-id = <1>; - qcom,threshold-arr = <0x0f0880b0 0x0f0980b0 - 0x0f0a80b0 0x0f0b80b0>; - qcom,config-arr = <0x0f0880b8 0x0f0980b8 - 0x0f0a80b8 0x0f0b80b8>; + label = "core"; + qcom,threshold-arr = <0x0f1880b0 0x0f1980b0 0x0f1a80b0 0x0f1b80b0 + 0x0f0880b0 0x0f0980b0 0x0f0a80b0 0x0f0b80b0>; + qcom,config-arr = <0x0f1880b8 0x0f1980b8 0x0f1a80b8 0x0f1b80b8 + 0x0f0880b8 0x0f0980b8 0x0f0a80b8 0x0f0b80b8>; }; cluster-device0 { @@ -2221,6 +2211,7 @@ qcom,intents = <0x800 5 0x2000 3 0x4400 2>; + qcom,no-wake-svc = <0x190>; }; qcom,msm_fastrpc_rpmsg { @@ -2508,6 +2499,22 @@ }; }; + sdhc1_opp_table: sdhc1-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <250000 133320>; + opp-avg-kBps = <104000 0>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-peak-kBps = <800000 300000>; + opp-avg-kBps = <400000 0>; + }; + }; + sdhc_1: sdhci@4744000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x4744000 0x1000>, <0x4745000 0x1000>, @@ -2536,14 +2543,6 @@ mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; - /* PM QoS */ - qcom,pm-qos-irq-type = "affine_irq"; - qcom,pm-qos-irq-latency = <26 26>; - qcom,pm-qos-cpu-groups = <0x0f 0xf0>; - - qcom,pm-qos-cmdq-latency-us = <26 26>, <26 26>; - qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>; - clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_ICE_CORE_CLK>; @@ -2554,38 +2553,7 @@ interconnects = <&system_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>, <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_1>; interconnect-names = "sdhc-ddr","cpu-sdhc"; - qcom,msm-bus,name = "sdhc1"; - qcom,msm-bus,num-cases = <9>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - /* No vote */ - <0 0>, <0 0>, - /* 400 KB/s*/ - <1046 1600>, - <1600 1600>, - /* 20 MB/s */ - <20480 80000>, - <80000 80000>, - /* 25 MB/s */ - <25600 250000>, - <50000 133320>, - /* 50 MB/s */ - <51200 250000>, - <65000 133320>, - /* 100 MB/s */ - <102400 250000>, - <65000 133320>, - /* 200 MB/s */ - <204800 800000>, - <200000 300000>, - /* 400 MB/s */ - <204800 800000>, - <200000 300000>, - /* Max. bandwidth */ - <1338562 4096000>, - <1338562 4096000>; - qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 - 100750000 200000000 400000000 4294967295>; + operating-points-v2 = <&sdhc1_opp_table>; /* Add support for gcc hw reset */ resets = <&gcc GCC_SDCC1_BCR>; @@ -2597,6 +2565,31 @@ qcom,iommu-dma = "fastmap"; status = "disabled"; + qos0 { + mask = <0xf0>; + vote = <44>; + }; + + qos1 { + mask = <0x0f>; + vote = <44>; + }; + }; + + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <250000 133320>; + opp-avg-kBps = <50000 0>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + opp-peak-kBps = <800000 300000>; + opp-avg-kBps = <104000 0>; + }; }; sdhc_2: sdhci@4784000 { @@ -2614,13 +2607,6 @@ no-mmc; qcom,restore-after-cx-collapse; - /* PM QoS */ - qcom,pm-qos-irq-type = "affine_irq"; - qcom,pm-qos-irq-latency = <26 26>; - - qcom,pm-qos-cpu-groups = <0x0f 0xf0>; - qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>; - clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>; clock-names = "iface", "core"; @@ -2628,38 +2614,7 @@ interconnects = <&system_noc MASTER_SDCC_2 &bimc SLAVE_EBI_CH0>, <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_2>; interconnect-names = "sdhc-ddr","cpu-sdhc"; - - qcom,msm-bus,name = "sdhc2"; - qcom,msm-bus,num-cases = <8>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - /* No vote */ - <0 0>, <0 0>, - /* 400 KB/s*/ - <1046 3200>, - <1600 1600>, - /* 20 MB/s */ - <52286 250000>, - <80000 133320>, - /* 25 MB/s */ - <65360 250000>, - <100000 133320>, - /* 50 MB/s */ - <130718 250000>, - <133320 133320>, - /* 100 MB/s */ - <261438 250000>, - <150000 133320>, - /* 200 MB/s */ - <261438 800000>, - <300000 300000>, - /* Max. bandwidth */ - <1338562 4096000>, - <1338562 4096000>; - qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 - 100750000 200000000 4294967295>; - - qcom,devfreq,freq-table = <50000000 202000000>; + operating-points-v2 = <&sdhc2_opp_table>; /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */ qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; @@ -2669,6 +2624,16 @@ qcom,iommu-dma = "fastmap"; status = "disabled"; + + qos0 { + mask = <0xf0>; + vote = <44>; + }; + + qos1 { + mask = <0x0f>; + vote = <44>; + }; }; ufsphy_mem: ufsphy_mem@4807000 { @@ -2704,6 +2669,9 @@ phys = <&ufsphy_mem>; phy-names = "ufsphy"; + qcom,prime-mask = <0x80>; + qcom,silver-mask = <0x0f>; + limit-rx-hs-gear = <3>; limit-tx-hs-gear = <3>; lanes-per-direction = <2>; @@ -2744,6 +2712,9 @@ <0 0>, <0 0>, <0 0>; + interconnects = <&system_noc MASTER_UFS_MEM &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; qcom,ufs-bus-bw,name = "ufshc_mem"; qcom,ufs-bus-bw,num-cases = <22>; qcom,ufs-bus-bw,num-paths = <2>; @@ -4024,6 +3995,7 @@ tpdm_turing_llm: tpdm@8861000 { &qupv3_se1_i2c { status = "ok"; + qcom,leica-used-i2c; #include "pm8008.dtsi" }; diff --git a/qcom/lemans-4pmic-regulators.dtsi b/qcom/lemans-4pmic-regulators.dtsi index fd73f348..2da37d95 100755 --- a/qcom/lemans-4pmic-regulators.dtsi +++ b/qcom/lemans-4pmic-regulators.dtsi @@ -386,8 +386,9 @@ pm8775_a_l7: regulator-pm8775_a-l7 { regulator-name = "pm8775_a_l7"; qcom,set = <RPMH_REGULATOR_SET_ALL>; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <950000>; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + regulator-always-on; qcom,init-voltage = <880000>; qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>; diff --git a/qcom/lemans-adas-high-qam-star-overlay.dts b/qcom/lemans-adas-high-qam-star-overlay.dts new file mode 100755 index 00000000..d7d3a8c6 --- /dev/null +++ b/qcom/lemans-adas-high-qam-star-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "lemans-qam-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans ADAS HIGH QAM STAR"; + compatible = "qcom,lemans", "qcom,qam-star", "qcom,lemans-adas-high", "qcom,lemans-adas-high-qam-star"; + qcom,msm-id = <533 0x10000>; + qcom,board-id = <0x10025 0>; +}; + diff --git a/qcom/lemans-adas-high-qam-star.dts b/qcom/lemans-adas-high-qam-star.dts new file mode 100755 index 00000000..879abed8 --- /dev/null +++ b/qcom/lemans-adas-high-qam-star.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "lemans-adas-high.dtsi" +#include "lemans-qam-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans ADAS HIGH QAM STAR"; + compatible = "qcom,lemans", "qcom,qam-star", "qcom,lemans-adas-high", "qcom,lemans-adas-high-qam-star"; +}; + diff --git a/qcom/lemans-dma-heaps.dtsi b/qcom/lemans-dma-heaps.dtsi index 4bf89fdf..87f446c4 100755 --- a/qcom/lemans-dma-heaps.dtsi +++ b/qcom/lemans-dma-heaps.dtsi @@ -24,6 +24,12 @@ memory-region = <&non_secure_display_memory>; }; + qcom,secure_display { + qcom,dma-heap-name = "qcom,secure-display"; + qcom,dma-heap-type = <HEAP_TYPE_CMA>; + memory-region = <&secure_display_memory>; + }; + qcom,adsp { qcom,dma-heap-name = "qcom,adsp"; qcom,dma-heap-type = <HEAP_TYPE_CMA>; diff --git a/qcom/lemans-ivi-qam-star-overlay.dts b/qcom/lemans-ivi-qam-star-overlay.dts new file mode 100755 index 00000000..04dbe636 --- /dev/null +++ b/qcom/lemans-ivi-qam-star-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "lemans-qam-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans IVI QAM STAR"; + compatible = "qcom,lemans", "qcom,qam-star", "qcom,lemans-ivi", "qcom,lemans-ivi-qam-star"; + qcom,msm-id = <532 0x10000>; + qcom,board-id = <0x10025 0>; +}; + diff --git a/qcom/lemans-ivi-qam-star.dts b/qcom/lemans-ivi-qam-star.dts new file mode 100755 index 00000000..a77dd155 --- /dev/null +++ b/qcom/lemans-ivi-qam-star.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "lemans-ivi.dtsi" +#include "lemans-qam-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans IVI QAM STAR"; + compatible = "qcom,lemans", "qcom,qam-star", "qcom,lemans-ivi", "qcom,lemans-ivi-qam-star"; +}; + diff --git a/qcom/lemans-pinctrl.dtsi b/qcom/lemans-pinctrl.dtsi index c3153f08..a95e84b6 100755 --- a/qcom/lemans-pinctrl.dtsi +++ b/qcom/lemans-pinctrl.dtsi @@ -1578,4 +1578,628 @@ }; }; }; + + sec_tdm_sck { + sec_tdm_sck_sleep: sec_tdm_sck_sleep { + mux { + pins = "gpio106"; + function = "gpio"; + }; + + config { + pins = "gpio106"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_sck_active: sec_tdm_sck_active { + mux { + pins = "gpio106"; + function = "mi2s1_sck"; + }; + + config { + pins = "gpio106"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + sec_tdm_ws { + sec_tdm_ws_sleep: sec_tdm_ws_sleep { + mux { + pins = "gpio107"; + function = "gpio"; + }; + + config { + pins = "gpio107"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_ws_active: sec_tdm_ws_active { + mux { + pins = "gpio107"; + function = "mi2s1_ws"; + }; + + config { + pins = "gpio107"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + sec_tdm_din { + sec_tdm_din_sleep: sec_tdm_din_sleep { + mux { + pins = "gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio108"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_din_active: sec_tdm_din_active { + mux { + pins = "gpio108"; + function = "mi2s1_data0"; + }; + + config { + pins = "gpio108"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_tdm_dout { + sec_tdm_dout_sleep: sec_tdm_dout_sleep { + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_dout_active: sec_tdm_dout_active { + mux { + pins = "gpio109"; + function = "mi2s1_data1"; + }; + + config { + pins = "gpio109"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_tdm_sck { + tert_tdm_sck_sleep: tert_tdm_sck_sleep { + mux { + pins = "gpio110"; + function = "gpio"; + }; + + config { + pins = "gpio110"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_sck_active: tert_tdm_sck_active { + mux { + pins = "gpio110"; + function = "mi2s2_sck"; + }; + + config { + pins = "gpio110"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_tdm_ws { + tert_tdm_ws_sleep: tert_tdm_ws_sleep { + mux { + pins = "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_ws_active: tert_tdm_ws_active { + mux { + pins = "gpio111"; + function = "mi2s2_ws"; + }; + + config { + pins = "gpio111"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_tdm_din { + tert_tdm_din_sleep: tert_tdm_din_sleep { + mux { + pins = "gpio112"; + function = "gpio"; + }; + + config { + pins = "gpio112"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_din_active: tert_tdm_din_active { + mux { + pins = "gpio112"; + function = "mi2s2_data0"; + }; + + config { + pins = "gpio112"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_tdm_dout { + tert_tdm_dout_sleep: tert_tdm_dout_sleep { + mux { + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_dout_active: tert_tdm_dout_active { + mux { + pins = "gpio113"; + function = "mi2s2_data1"; + }; + + config { + pins = "gpio113"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs0_i2s_sck { + hs0_i2s_sck_sleep: hs0_i2s_sck_sleep { + mux { + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs0_i2s_sck_active: hs0_i2s_sck_active { + mux { + pins = "gpio114"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio114"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs0_i2s_ws { + hs0_i2s_ws_sleep: hs0_i2s_ws_sleep { + mux { + pins = "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio115"; + drive-strength = <2>; /* 8 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs0_i2s_ws_active: hs0_i2s_ws_active { + mux { + pins = "gpio115"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio115"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs0_i2s_data0 { + hs0_i2s_data0_sleep: hs0_i2s_data0_sleep { + mux { + pins = "gpio116"; + function = "gpio"; + }; + + config { + pins = "gpio116"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs0_i2s_data0_active: hs0_i2s_data0_active { + mux { + pins = "gpio116"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio116"; + drive-strength = <8>; /* 2 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + hs0_i2s_data1 { + hs0_i2s_data1_sleep: hs0_i2s_data1_sleep { + mux { + pins = "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio117"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs0_i2s_data1_active: hs0_i2s_data1_active { + mux { + pins = "gpio117"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio117"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs1_i2s_sck { + hs1_i2s_sck_sleep: hs1_i2s_sck_sleep { + mux { + pins = "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio118"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs1_i2s_sck_active: hs1_i2s_sck_active { + mux { + pins = "gpio118"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio118"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs1_i2s_ws { + hs1_i2s_ws_sleep: hs1_i2s_ws_sleep { + mux { + pins = "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio119"; + drive-strength = <2>; /* 8 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs1_i2s_ws_active: hs1_i2s_ws_active { + mux { + pins = "gpio119"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio119"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs1_i2s_data0 { + hs1_i2s_data0_sleep: hs1_i2s_data0_sleep { + mux { + pins = "gpio120"; + function = "gpio"; + }; + + config { + pins = "gpio120"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs1_i2s_data0_active: hs1_i2s_data0_active { + mux { + pins = "gpio120"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio120"; + drive-strength = <8>; /* 2 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + hs1_i2s_data1 { + hs1_i2s_data1_sleep: hs1_i2s_data1_sleep { + mux { + pins = "gpio121"; + function = "gpio"; + }; + + config { + pins = "gpio121"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs1_i2s_data1_active: hs1_i2s_data1_active { + mux { + pins = "gpio121"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio121"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs2_i2s_sck { + hs2_i2s_sck_sleep: hs2_i2s_sck_sleep { + mux { + pins = "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio122"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs2_i2s_sck_active: hs2_i2s_sck_active { + mux { + pins = "gpio122"; + function = "hs2_mi2s"; + }; + + config { + pins = "gpio122"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs2_i2s_ws { + hs2_i2s_ws_sleep: hs2_i2s_ws_sleep { + mux { + pins = "gpio123"; + function = "gpio"; + }; + + config { + pins = "gpio123"; + drive-strength = <2>; /* 8 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs2_i2s_ws_active: hs2_i2s_ws_active { + mux { + pins = "gpio123"; + function = "hs2_mi2s"; + }; + + config { + pins = "gpio123"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs2_i2s_data0 { + hs2_i2s_data0_sleep: hs2_i2s_data0_sleep { + mux { + pins = "gpio124"; + function = "gpio"; + }; + + config { + pins = "gpio124"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs2_i2s_data0_active: hs2_i2s_data0_active { + mux { + pins = "gpio124"; + function = "hs2_mi2s"; + }; + + config { + pins = "gpio124"; + drive-strength = <8>; /* 2 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + hs2_i2s_data1 { + hs2_i2s_data1_sleep: hs2_i2s_data1_sleep { + mux { + pins = "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio125"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs2_i2s_data1_active: hs2_i2s_data1_active { + mux { + pins = "gpio125"; + function = "hs2_mi2s"; + }; + + config { + pins = "gpio125"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + audio_internal_mclk1 { + audio_internal_mclk1_sleep: audio_internal_mclk1_sleep { + mux { + pins = "gpio105"; + function = "gpio"; + }; + + config { + pins = "gpio105"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + audio_internal_mclk1_active: audio_internal_mclk1_active { + mux { + pins = "gpio105"; + function = "mi2s_mclk0"; + }; + + config { + pins = "gpio105"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; }; diff --git a/qcom/lemans-pmic-overlay.dtsi b/qcom/lemans-pmic-overlay.dtsi index 18ffd3dd..f1cd9b03 100755 --- a/qcom/lemans-pmic-overlay.dtsi +++ b/qcom/lemans-pmic-overlay.dtsi @@ -98,6 +98,12 @@ nvmem = <&pm8775_1_sdam_5>; nvmem-names = "pon_log"; }; + + reboot_reason { + compatible = "qcom,reboot-reason"; + nvmem-cells = <&restart_reason>; + nvmem-cell-names = "restart_reason"; + }; }; &thermal_zones { diff --git a/qcom/lemans-qam-star.dtsi b/qcom/lemans-qam-star.dtsi new file mode 100755 index 00000000..689bf563 --- /dev/null +++ b/qcom/lemans-qam-star.dtsi @@ -0,0 +1 @@ +#include "lemans-adp-common.dtsi" diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index d69a1497..69e44b7f 100755 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -4,9 +4,11 @@ #include <dt-bindings/clock/qcom,gcc-lemans.h> #include <dt-bindings/clock/qcom,gpucc-lemans.h> #include <dt-bindings/clock/qcom,videocc-lemans.h> +#include <dt-bindings/clock/qcom,aop-qmp.h> #include <dt-bindings/interconnect/qcom,lemans.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/soc/qcom,ipcc.h> @@ -27,6 +29,8 @@ aliases { serial0 = &qupv3_se10_2uart; ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + i2c4 = &qupv3_se11_i2c; + spi16 = &qupv3_se16_spi; }; soc: soc { }; @@ -228,6 +232,7 @@ &firmware { scm { compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; }; }; @@ -302,7 +307,7 @@ reg = <0x0 0x95200000 0x0 0x500000>; }; - pil_adsp_mem: pil_adsp_region@95c00000 { + rproc_adsp_mem: rproc_adsp_region@95c00000 { no-map; reg = <0x0 0x95c00000 0x0 0x1e00000>; }; @@ -317,7 +322,7 @@ reg = <0x0 0x99900000 0x0 0x1e00000>; }; - pil_cdsp0_mem: pil_cdsp0_region@9b800000 { + rproc_cdsp_mem: rproc_cdsp_region@9b800000 { no-map; reg = <0x0 0x9b800000 0x0 0x1e00000>; }; @@ -422,6 +427,14 @@ alignment = <0x0 0x400000>; }; + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xA000000>; + }; + user_contig_mem: user_contig_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; @@ -652,6 +665,11 @@ #interrupt-cells = <2>; }; + qcom,secure-buffer { + compatible = "qcom,secure-buffer"; + qcom,vmid-cp-camera-preview-ro; + }; + wdog: qcom,wdt@17c10000 { compatible = "qcom,msm-watchdog"; reg = <0x17c10000 0x1000>; @@ -668,6 +686,20 @@ #mbox-cells = <2>; }; + cache-controller@9200000 { + compatible = "qcom,lemans-llcc", "qcom,llcc-v31"; + reg = <0x9200000 0x580000> , <0x9a00000 0x80000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; + cap-based-alloc-and-pwr-collapse; + + llcc-perfmon { + compatible = "qcom,llcc-perfmon"; + clocks = <&aoss_qmp QDSS_CLK>; + clock-names = "qdss_clk"; + }; + }; + clocks { xo_board: xo_board { compatible = "fixed-clock"; @@ -909,7 +941,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; mc_virt: interconnect@1 { @@ -917,7 +948,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; config_noc: interconnect@014C0000 { @@ -926,7 +956,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; system_noc: interconnect@01680000 { @@ -935,7 +964,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; aggre1_noc:interconnect@016C0000 { @@ -944,7 +972,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, @@ -958,7 +985,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, <&rpmhcc RPMH_IPA_CLK>; }; @@ -969,7 +995,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; gpdsp_anoc: interconnect@01780000 { @@ -978,7 +1003,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; mmss_noc: interconnect@017A0000 { @@ -987,7 +1011,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; lpass_ag_noc: interconnect@03C40000 { @@ -996,7 +1019,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; dc_noc: interconnect@090E0000 { @@ -1005,7 +1027,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; gem_noc: interconnect@09100000 { @@ -1015,7 +1036,6 @@ qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>; - qcom,skip-qos; }; nspa_noc: interconnect@260C0000 { @@ -1024,7 +1044,6 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; nspb_noc: interconnect@2A0C0000 { @@ -1033,13 +1052,154 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - qcom,skip-qos; }; vendor_hooks: qcom,cpu-vendor-hooks { compatible = "qcom,cpu-vendor-hooks"; }; + dload_mode { + compatible = "qcom,dload-mode"; + }; + + tcsr: syscon@1fc0000 { + compatible = "syscon"; + reg = <0x1fc0000 0x30000>; + }; + + adsp_pas: remoteproc-adsp@3000000 { + compatible = "qcom,lemans-adsp-pas"; + reg = <0x3000000 0x00100>; + status = "ok"; + + memory-region = <&rproc_adsp_mem>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + vdd_cx-supply = <&VDD_LPI_CX_LEVEL>; + qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>; + vdd_mx-supply = <&VDD_LPI_MX_LEVEL>; + qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>; + reg-names = "cx","mx"; + + /* Inputs from lpass */ + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack"; + + qcom,qmp = <&aoss_qmp>; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink_adsp: glink-edge { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "adsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = <IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + label = "adsp"; + qcom,glink-label = "lpass"; + cpu-affinity = <1 2>; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + }; + }; + + cdsp_pas: remoteproc-cdsp@26300000 { + compatible = "qcom,lemans-cdsp-pas"; + reg = <0x26300000 0x10000>; + status = "ok"; + + memory-region = <&rproc_cdsp_mem>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>; + mx-supply = <&VDD_MXC_LEVEL>; + mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>; + nsp0-supply = <&VDD_NSP_0_LEVEL>; + nsp0-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>; + reg-names = "cx","mx","nsp0"; + + interconnects = <&nspa_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; + interconnect-names = "crypto_ddr"; + + /* Inputs from turing */ + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>; + + interrupt-names = "wdog", + "fatal", + "handover", + "ready", + "stop-ack"; + + qcom,qmp = <&aoss_qmp>; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink_cdsp0: glink-edge { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "cdsp0_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = <IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + label = "cdsp0"; + qcom,glink-label = "cdsp0"; + + qcom,cdsp0_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + }; + }; + spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0x1100>, @@ -1246,6 +1406,35 @@ #mbox-cells = <1>; }; + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; + + qcom_qseecom: qseecom@d1800000 { + compatible = "qcom,qseecom"; + reg = <0xd1800000 0x3900000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + #qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + #qcom,disk-encrypt-pipe-pair = <2>; + #qcom,support-fde; + qcom,no-clock-support; + #qcom,fde-key-size; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_tzlog: tz-log@146d8720 { + compatible = "qcom,tz-log"; + reg = <0x146d8720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + qcom,glinkpkt { compatible = "qcom,glinkpkt"; diff --git a/qcom/monaco-gdsc.dtsi b/qcom/monaco-gdsc.dtsi index 628e2498..bda43c44 100755 --- a/qcom/monaco-gdsc.dtsi +++ b/qcom/monaco-gdsc.dtsi @@ -113,7 +113,7 @@ compatible = "qcom,gdsc"; reg = <0x5994064 0x4>; regulator-name = "gpu_cx_gdsc"; - hw-ctl-addr = <&gpu_cx_hw_ctrl>; + hw-ctrl-addr = <&gpu_cx_hw_ctrl>; qcom,gds-timeout = <500>; qcom,clk-dis-wait-val = <8>; qcom,no-status-check-on-disable; diff --git a/qcom/monaco-idp-v1.dtsi b/qcom/monaco-idp-v1.dtsi index 28aa6597..46a0a0f2 100755 --- a/qcom/monaco-idp-v1.dtsi +++ b/qcom/monaco-idp-v1.dtsi @@ -2,6 +2,7 @@ #include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm5100.h> #include <dt-bindings/iio/qti_power_supply_iio.h> #include <dt-bindings/clock/qcom,rpmcc.h> +#include "slate.dtsi" &soc { bluetooth: bt_wcn3990 { diff --git a/qcom/monaco-pinctrl.dtsi b/qcom/monaco-pinctrl.dtsi index dcc209d5..aaf4f203 100755 --- a/qcom/monaco-pinctrl.dtsi +++ b/qcom/monaco-pinctrl.dtsi @@ -1112,7 +1112,7 @@ config { pins = "gpio26"; drive-strength = <2>; - bias-disable; + bias-pull-down; }; }; diff --git a/qcom/monaco-qupv3.dtsi b/qcom/monaco-qupv3.dtsi index 3d51f4ba..d1d513a0 100755 --- a/qcom/monaco-qupv3.dtsi +++ b/qcom/monaco-qupv3.dtsi @@ -34,7 +34,6 @@ qcom,ev-factor = <2>; qcom,iommu-dma-addr-pool = <0x100000 0x100000>; qcom,gpi-ee-offset = <0x10000>; - dma-coherent; status = "ok"; }; @@ -51,7 +50,6 @@ qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; - dma-coherent; ranges; status = "ok"; diff --git a/qcom/monaco-standalone-idp-v1.dtsi b/qcom/monaco-standalone-idp-v1.dtsi index b897432c..fe84251f 100755 --- a/qcom/monaco-standalone-idp-v1.dtsi +++ b/qcom/monaco-standalone-idp-v1.dtsi @@ -1 +1,72 @@ #include "monaco-idp-v1-common.dtsi" +#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm5100.h> +#include <dt-bindings/iio/qti_power_supply_iio.h> + +&pm5100_qbg { + status = "ok"; + qcom,battery-data = <&monaco_batterydata>; + nvmem-cell-names = "qbg_debug_mask_low", "qbg_debug_mask_high", "skip_esr_state"; + nvmem-cells = <&qbg_debug_mask_low>, <&qbg_debug_mask_high>, <&skip_esr_state>; + #io-channel-cells = <1>; + io-channels = <&pm5100_adc PM5100_ADC5_GEN3_BATT_THM_100K_PU>, + <&pm5100_adc PM5100_ADC5_GEN3_BAT_ID_100K_PU>, + <&pm5100_charger PSY_IIO_CHARGE_DONE>, + <&pm5100_charger PSY_IIO_RECHARGE_SOC>, + <&pm5100_charger PSY_IIO_FORCE_RECHARGE>, + <&pm5100_charger PSY_IIO_SYS_SOC>; + io-channel-names = "batt-temp", + "batt-id", + "charge_done", + "recharge_soc", + "force_recharge", + "sys_soc"; + qcom,vbat-cutoff-mv = <3100>; + qcom,ibat-cutoff-ma = <10>; + qcom,vph-min-mv = <2500>; + qcom,iterm-ma = <20>; + qcom,vbatt-empty-threshold-mv = <3600>; +}; + +&pm5100_charger { + #io-channel-cells = <1>; + io-channels = <&pm5100_adc PM5100_ADC5_GEN3_USB_SNS_V_16>, + <&pm5100_adc PM5100_ADC5_GEN3_USB_IN_I>, + <&pm5100_adc PM5100_ADC5_GEN3_CHG_TEMP>, + <&pm5100_adc PM5100_ADC5_GEN3_DIE_TEMP>, + <&pm5100_adc PM5100_ADC5_GEN3_VPH_PWR>, + <&pm5100_qbg PSY_IIO_RESISTANCE_ID>, + <&pm5100_qbg PSY_IIO_VOLTAGE_NOW>, + <&pm5100_qbg PSY_IIO_TEMP>, + <&pm5100_qbg PSY_IIO_CAPACITY>, + <&pm5100_qbg PSY_IIO_VOLTAGE_OCV>, + <&pm5100_qbg PSY_IIO_VOLTAGE_AVG>, + <&pm5100_qbg PSY_IIO_DEBUG_BATTERY>, + <&pm5100_qbg PSY_IIO_CURRENT_NOW>, + <&pm5100_qbg PSY_IIO_VOLTAGE_MAX>, + <&pm5100_qbg PSY_IIO_CHARGE_FULL>, + <&pm5100_qbg PSY_IIO_CHARGE_COUNTER>, + <&pm5100_qbg PSY_IIO_CYCLE_COUNT>, + <&pm5100_qbg PSY_IIO_CHARGE_FULL_DESIGN>, + <&pm5100_qbg PSY_IIO_TIME_TO_FULL_NOW>; + + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "vph_voltage", + "resistance_id", + "voltage_now", + "temp", + "capacity", + "voltage_ocv", + "voltage_avg", + "debug_battery", + "current_now", + "voltage_max", + "charge_full", + "charge_counter", + "cycle_count", + "charge_full_design", + "time_to_full_now"; +}; + diff --git a/qcom/monaco-usb.dtsi b/qcom/monaco-usb.dtsi index aba8f0ac..c9667e4b 100755 --- a/qcom/monaco-usb.dtsi +++ b/qcom/monaco-usb.dtsi @@ -30,6 +30,7 @@ USB3_GDSC-supply = <&gcc_usb20_prim_gdsc>; dpdm-supply = <&usb2_phy0>; + extcon = <&eud>; qcom,core-clk-rate = <60000000>; qcom,default-bus-vote = <2>; /* use svs bus voting */ @@ -68,7 +69,7 @@ snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; maximum-speed = "high-speed"; - dr_mode = "peripheral"; + dr_mode = "otg"; }; qcom,usbbam@0x04f04000 { diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi index f64bb5df..5252a692 100755 --- a/qcom/monaco.dtsi +++ b/qcom/monaco.dtsi @@ -35,6 +35,9 @@ device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x0>; + cpu-idle-states = <&SILVER_OFF>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; enable-method = "psci"; d-cache-size = <0x8000>; i-cache-size = <0x8000>; @@ -63,6 +66,9 @@ device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x1>; + cpu-idle-states = <&SILVER_OFF>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; enable-method = "psci"; d-cache-size = <0x8000>; i-cache-size = <0x8000>; @@ -85,6 +91,9 @@ device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x2>; + cpu-idle-states = <&SILVER_OFF>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; enable-method = "psci"; d-cache-size = <0x8000>; i-cache-size = <0x8000>; @@ -107,6 +116,9 @@ device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x3>; + cpu-idle-states = <&SILVER_OFF>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; enable-method = "psci"; d-cache-size = <0x8000>; i-cache-size = <0x8000>; @@ -147,6 +159,27 @@ }; }; + idle-states { + SILVER_OFF: silver-c3 { /* C3 */ + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <297>; + exit-latency-us = <324>; + min-residency-us = <1110>; + arm,psci-suspend-param = <0x40000003>; + local-timer-stop; + }; + + SILVER_CLUSTER_D3: silver-cluster-d3 { /* D3 */ + compatible = "domain-idle-state"; + idle-state-name = "pwr-l2-pc"; + entry-latency-us = <800>; + exit-latency-us = <2118>; + min-residency-us = <7376>; + arm,psci-suspend-param = <0x41000043>; + }; + }; + soc: soc { }; chosen { @@ -370,6 +403,31 @@ psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: cpu-pd0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD1: cpu-pd1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD2: cpu-pd2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CPU_PD3: cpu-pd3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: cluster-pd0 { + #power-domain-cells = <0>; + domain-idle-states = <&SILVER_CLUSTER_D3>; + }; }; arch_timer: timer { @@ -950,7 +1008,7 @@ /* Outputs to lpass */ qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; - glink-edge { + glink_edge: glink-edge { qcom,remote-pid = <2>; transport = "smem"; mboxes = <&apcs_glb 8>; @@ -1658,6 +1716,26 @@ rpm-channel-name = "rpm_requests"; interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; rpm-channel-type = <15>; /* SMD_APPS_RPM */ + power-domains = <&CLUSTER_PD>; + }; + + cluster-device { + compatible = "qcom,lpm-cluster-dev"; + power-domains = <&CLUSTER_PD>; + }; + + rpm-sleep-stats@4690000 { + compatible = "qcom,rpm-sleep-stats"; + reg = <0x04690000 0x400>; + ss-name = "modem", "adsp", "cdsp", "apss"; + }; + + qcom,rpm-master-stats@45f0150 { + compatible = "qcom,rpm-master-stats"; + reg = <0x45f0150 0x5000>; + qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ"; + qcom,master-stats-version = <2>; + qcom,master-offset = <4096>; }; sdhc1_opp_table: sdhc1-opp-table { @@ -2044,6 +2122,7 @@ }; &usb0 { + extcon = <&pm5100_charger>, <&eud>; #io-channel-cells = <1>; io-channels= <&pm5100_charger PSY_IIO_USB_REAL_TYPE>; io-channel-names = "chg_type"; diff --git a/qcom/msm-arm-smmu-monaco.dtsi b/qcom/msm-arm-smmu-monaco.dtsi index 5ae347c6..cb34461f 100755 --- a/qcom/msm-arm-smmu-monaco.dtsi +++ b/qcom/msm-arm-smmu-monaco.dtsi @@ -57,6 +57,7 @@ #iommu-cells = <2>; qcom,skip-init; qcom,use-3-lvl-tables; + qcom,handoff-smrs = <0x420 0x2>; #global-interrupts = <1>; #size-cells = <1>; #address-cells = <1>; @@ -127,7 +128,11 @@ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_TCU>; + qcom,active-only; + qcom,actlr = /* For rt TBU +3 deep PF */ <0x400 0x3ff 0x103>, @@ -140,6 +145,10 @@ <0xc7f2200 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; + interconnects = <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_IMEM_CFG>, + <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_TCU>; qcom,active-only; qcom,iova-width = <36>; }; @@ -152,6 +161,10 @@ qcom,stream-id-range = <0x400 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc>; + interconnects = <&mmrt_virt MASTER_MDP_PORT0 + &mmrt_virt SLAVE_SNOC_BIMC_RT>, + <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_TCU>; qcom,active-only; qcom,iova-width = <36>; }; @@ -164,6 +177,10 @@ qcom,stream-id-range = <0x800 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc>; + interconnects = <&mmnrt_virt MASTER_CAMNOC_SF + &mmnrt_virt SLAVE_SNOC_BIMC_NRT>, + <&bimc MASTER_AMPSS_M0 + &config_noc SLAVE_TCU>; qcom,active-only; qcom,iova-width = <36>; }; diff --git a/qcom/msm-arm-smmu-sdmshrike.dtsi b/qcom/msm-arm-smmu-sdmshrike.dtsi index f63b387f..0cb085aa 100755 --- a/qcom/msm-arm-smmu-sdmshrike.dtsi +++ b/qcom/msm-arm-smmu-sdmshrike.dtsi @@ -2,7 +2,7 @@ &soc { kgsl_smmu: kgsl-smmu@2ca0000 { - compatible = "qcom,qsmmu-v500"; + compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu"; reg = <0x2ca0000 0x10000>, <0x2cc2000 0x20>; reg-names = "base", "tcu-base"; diff --git a/qcom/pm2250.dtsi b/qcom/pm2250.dtsi new file mode 100755 index 00000000..bcde3f10 --- /dev/null +++ b/qcom/pm2250.dtsi @@ -0,0 +1,378 @@ +#include <dt-bindings/input/input.h> +#include <dt-bindings/input/qcom,qpnp-power-on.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/iio/qcom,spmi-vadc.h> + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm2250@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "kpdpwr", "resin"; + qcom,pon-dbc-delay = <15625>; + qcom,kpdpwr-sw-debounce; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>; + qcom,pull-up = <1>; + linux,code = <KEY_POWER>; + }; + + qcom,pon_2 { + qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>; + qcom,pull-up = <1>; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; + + pm2250_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pm2250_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pm2250_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5-lite"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel nodes */ + ref_gnd { + reg = <ADC5_REF_GND>; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = <ADC5_1P25VREF>; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = <ADC5_DIE_TEMP>; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr { + reg = <ADC5_VPH_PWR>; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vbat_sns { + reg = <ADC5_VBAT_SNS>; + label = "vbat_sns"; + qcom,pre-scaling = <1 3>; + }; + + usb_in_v_div_16 { + reg = <ADC5_USB_IN_V_16>; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; + + chg_temp { + reg = <ADC5_CHG_TEMP>; + label = "chg_temp"; + qcom,pre-scaling = <1 1>; + }; + + bat_therm { + reg = <ADC5_BAT_THERM_100K_PU>; + label = "bat_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_30k { + reg = <ADC5_BAT_THERM_30K_PU>; + label = "bat_therm_30k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_400k { + reg = <ADC5_BAT_THERM_400K_PU>; + label = "bat_therm_400k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + i_parallel { + reg = <ADC5_PARALLEL_ISENSE>; + label = "i_parallel"; + qcom,pre-scaling = <1 1>; + }; + + bat_id { + reg = <ADC5_BAT_ID_100K_PU>; + label = "bat_id"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + die_temp_s3 { + reg = <ADC5_SBUx>; + label = "die_temp_s3"; + qcom,pre-scaling = <1 3>; + qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM2250_S3_DIE_TEMP>; + }; + }; + + pm2250_gpios: pinctrl@c000 { + compatible = "qcom,pm2250-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm2250_rtc: qcom,pm2250_rtc { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + + pm2250_qg: qpnp,qg { + compatible = "qcom,qpnp-qg-lite"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,vbatt-cutoff-mv = <3400>; + qcom,vbatt-low-mv = <3500>; + qcom,vbatt-low-cold-mv = <3800>; + qcom,vbatt-empty-mv = <3200>; + qcom,vbatt-empty-cold-mv = <3000>; + qcom,s3-entry-fifo-length = <2>; + + io-channels = <&pm2250_vadc ADC5_BAT_THERM_100K_PU>, + <&pm2250_vadc ADC5_BAT_ID_100K_PU>; + io-channel-names = "batt-therm", "batt-id"; + + qcom,qgauge@4800 { + status = "okay"; + reg = <0x4800>; + interrupts = + <0x0 0x48 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x48 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x48 0x5 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "qg-vbat-empty", + "qg-fifo-done", + "qg-good-ocv"; + }; + + qcom,qg-sdam@b600 { + status = "okay"; + reg = <0xb600>; + }; + }; + + pm2250_charger: qcom,qpnp-smblite { + compatible = "qcom,qpnp-smblite"; + #address-cells = <1>; + #size-cells = <0>; + #cooling-cells = <2>; + + qcom,chgr@1000 { + reg = <0x1000>; + interrupts = + <0x0 0x10 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "chgr-error", + "chg-state-change", + "buck-oc", + "vph-ov"; + }; + + qcom,batif@1200 { + reg = <0x1200>; + interrupts = + <0x0 0x12 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x4 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "bat-temp", + "bat-therm-or-id-missing", + "bat-low", + "bat-ov", + "bsm-active"; + }; + + qcom,usb@1300 { + reg = <0x1300>; + interrupts = + <0x0 0x13 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x13 0x6 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "usbin-plugin", + "usbin-collapse", + "usbin-uv", + "usbin-ov", + "usbin-gtvt", + "usbin-icl-change"; + }; + + qcom,typec@1500 { + reg = <0x1500>; + interrupts = + <0x0 0x15 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "typec-or-rid-detect-change", + "typec-vpd-detect", + "typec-cc-state-change", + "typec-vbus-change", + "typec-attach-detach", + "typec-legacy-cable-detect", + "typec-try-snk-src-detect"; + }; + + qcom,misc@1600 { + reg = <0x1600>; + interrupts = + <0x0 0x16 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x6 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "wdog-snarl", + "wdog-bark", + "aicl-fail", + "aicl-done", + "imp-trigger", + "all-chnl-cond-done", + "temp-change"; + }; + + qcom,schgm-flashlite@a600 { + reg = <0xa600>; + interrupts = + <0x0 0xa6 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0xa6 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0xa6 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0xa6 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "flash-state-change", + "ilim1-s1", + "ilim2-s2", + "vreg-ok"; + }; + }; + }; + + pm2250_1: qcom,pm2250@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm2250_vib: qcom,vibrator@5600 { + compatible = "qcom,qpnp-vibrator-ldo"; + reg = <0x5600>; + qcom,vib-ldo-volt-uv = <3000000>; + qcom,disable-overdrive; + }; + + pm2250_pwm1: qcom,pwms@bc00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbc00>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <1>; + #pwm-cells = <2>; + }; + + pm2250_pwm2: qcom,pwms@bd00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbd00>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <1>; + #pwm-cells = <2>; + }; + + pm2250_pwm3: qcom,pwms@be00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbe00>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <1>; + #pwm-cells = <2>; + }; + }; +}; + +&thermal_zones { + pm2250-tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm2250_tz>; + + trips { + pm2250_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm2250_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/qcom/pm5100.dtsi b/qcom/pm5100.dtsi index 0058595b..a4f3b005 100755 --- a/qcom/pm5100.dtsi +++ b/qcom/pm5100.dtsi @@ -249,6 +249,10 @@ interrupts = <0x0 0x65 0x1 IRQ_TYPE_EDGE_RISING>; }; + pm5100_cdc: qcom,pm5100-cdc { + compatible = "qcom,pm5100-spmi"; + }; + pm5100_bcl: bcl@4700 { compatible = "qcom,bcl-v5"; reg = <0x4700 0x100>; diff --git a/qcom/pm8150.dtsi b/qcom/pm8150.dtsi index d0d24b5a..41e60e6d 100755 --- a/qcom/pm8150.dtsi +++ b/qcom/pm8150.dtsi @@ -36,6 +36,10 @@ mode-dm-verity-device-corrupted = <0x4>; mode-dm-verity-enforcing = <0x5>; mode-keys-clear = <0x6>; + mode-silent = <0xa>; + mode-nonsilent = <0xb>; + mode-forcedsilent = <0xc>; + mode-forcednonsilent = <0xd>; pon_pwrkey: pwrkey { compatible = "qcom,pm8941-pwrkey"; diff --git a/qcom/pm8540-vm.dtsi b/qcom/pm8540-vm.dtsi new file mode 100755 index 00000000..483a3b82 --- /dev/null +++ b/qcom/pm8540-vm.dtsi @@ -0,0 +1,77 @@ +#include <dt-bindings/spmi/spmi.h> + +&spmi_bus { + + qcom,pm8540@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8540_1_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8540_1_rtc: qcom,pm8540_1_rtc { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + disable-alarm-wakeup; + }; + }; + + + qcom,pm8540@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8540_2_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,pm8540@8 { + compatible = "qcom,spmi-pmic"; + reg = <8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8540_3_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,pm8540@C { + compatible = "qcom,spmi-pmic"; + reg = <12 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8540_4_gpios: pinctrl@c000 { + compatible = "qcom,pm8150-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/qcom/pm8775.dtsi b/qcom/pm8775.dtsi index 8f6caf84..32b34cfe 100755 --- a/qcom/pm8775.dtsi +++ b/qcom/pm8775.dtsi @@ -83,6 +83,11 @@ reg = <0x7100>; #address-cells = <1>; #size-cells = <1>; + + restart_reason: restart@48 { + reg = <0x48 0x1>; + bits = <1 7>; + }; }; pm8775_1_sdam_5: sdam@7400 { diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi index 85b07256..18282678 100755 --- a/qcom/quin-vm-common.dtsi +++ b/qcom/quin-vm-common.dtsi @@ -54,6 +54,30 @@ size = <0x0 0x1000000>; }; }; + + firmware: firmware { + android { + compatible = "android,firmware"; + boot_devices = "vdevs/1c140000.virtio_blk,vdevs/1c0b0000.virtio_blk,vdevs/1c0f0000.virtio_blk,vdevs/1c160000.virtio_blk,vdevs/1c130000.virtio_blk,vdevs/1c0e0000.virtio_blk,vdevs/1c100000.virtio_blk,vdevs/1c170000.virtio_blk,vdevs/1c180000.virtio_blk,vdevs/1c110000.virtio_blk,vdevs/1c120000.virtio_blk,vdevs/1c210000.virtio_blk,vdevs/1c220000.virtio_blk,vdevs/1c230000.virtio_blk,vdevs/1c240000.virtio_blk,vdevs/1c250000.virtio_blk,vdevs/1c260000.virtio_blk"; + + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,system,vendor"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev="/dev/block/platform/vdevs/1c0f0000.virtio_blk/vdc"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait"; + status = "disabled"; + }; + }; + }; + }; }; &soc { @@ -219,6 +243,21 @@ compatible = "qcom,msm-imem-boot_stats"; reg = <0x6b0 0x20>; }; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; }; qcom,mpm2-sleep-counter@c221000 { @@ -227,7 +266,7 @@ clock-frequency = <32768>; }; - spmi_bus: virtio-spmi@1c800000 { + virtio-spmi@1c800000 { compatible = "virtio,mmio"; #address-cells = <1>; #size-cells = <1>; @@ -238,6 +277,10 @@ #interrupt-cells = <4>; cell-index = <0>; status = "okay"; + + spmi_bus: virt_spmi { + compatible = "virtio,device33"; + }; }; }; diff --git a/qcom/sa410m-pinctrl.dtsi b/qcom/sa410m-pinctrl.dtsi index 609b06df..d5ec8b66 100755 --- a/qcom/sa410m-pinctrl.dtsi +++ b/qcom/sa410m-pinctrl.dtsi @@ -739,6 +739,9 @@ rclk { pins = "sdc1_rclk"; bias-pull-down; + }; + }; + pcie0 { pcie0_clkreq_default: pcie0_clkreq_default { mux { diff --git a/qcom/sa410m-rumi.dtsi b/qcom/sa410m-rumi.dtsi index e9d21f68..75bba422 100755 --- a/qcom/sa410m-rumi.dtsi +++ b/qcom/sa410m-rumi.dtsi @@ -24,6 +24,25 @@ clock-output-names = "bi_tcxo_ao"; #clock-cells = <0>; }; + + usb_emu_phy: usb_emu_phy@4f20000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x04f20000 0x9500>, + <0x04ef8800 0x100>; + reg-names = "base", "qscratch_base"; + + qcom,emu-init-seq = <0xfff0 0x4 + 0xfff3 0x4 + 0xfff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x101f0 0x20 + 0x100000 0x3c + 0x0 0x3c + 0x4 0x3c + 0x0 0x4 + 0x9 0x14>; + }; }; &rpmcc { @@ -63,3 +82,11 @@ pinctrl-0 = <&sdc1_on>; pinctrl-1 = <&sdc1_off>; }; + +&usb0 { + dwc3@4e00000 { + usb-phy = <&usb_emu_phy>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; +}; diff --git a/qcom/sa410m-usb.dtsi b/qcom/sa410m-usb.dtsi new file mode 100755 index 00000000..22281cae --- /dev/null +++ b/qcom/sa410m-usb.dtsi @@ -0,0 +1,258 @@ +#include <dt-bindings/clock/qcom,gcc-sa410m.h> +#include <dt-bindings/phy/qcom,usb3-11nm-qmp-combo.h> + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@4e00000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x4e00000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event_irq", "ss_phy_irq", + "hs_phy_irq"; + + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_EN>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "xo", "sleep_clk", "utmi_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <133333333>; + qcom,core-clk-rate-hs = <66666667>; + + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&sys_noc MASTER_USB3 &bimc_noc SLAVE_EBI_CH0>, + <&sys_noc MASTER_USB3 &config_noc SLAVE_IPA_CFG>, + <&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>; + + dwc3@4e00000 { + compatible = "snps,dwc3"; + reg = <0x4e00000 0xe000>; + + iommus = <&apps_smmu 0x120 0x0>; + qcom,iommu-dma = "bypass"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + + usb-phy = <&qusb_phy0>, <&usb_qmp_phy>; + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; + tx-fifo-resize; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* Primary USB port related High Speed PHY */ + qusb_phy0: qusb@1613000 { + compatible = "qcom,qusb2phy"; + reg = <0x01613000 0x180>, + <0x003cb250 0x4>, + <0x01b40258 0x4>, + <0x01612000 0x4>; + reg-names = "qusb_phy_base", + "tcsr_clamp_dig_n_1p8", + "tune2_efuse_addr", + "eud_enable_reg"; + + vdd-supply = <&pm2250_l12>; + vdda18-supply = <&pm2250_l13>; + vdda33-supply = <&pm2250_l21>; + qcom,vdd-voltage-level = <0 925000 970000>; + qcom,tune2-efuse-bit-pos = <25>; + qcom,tune2-efuse-num-bits = <4>; + qcom,qusb-phy-init-seq = <0xc8 0x80 + 0xb3 0x84 + 0x83 0x88 + 0xc0 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x80 0x04 + 0x9f 0x1c + 0x00 0x18>; + phy_type = "utmi"; + qcom,phy-clk-scheme = "cmos"; + qcom,major-rev = <1>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_AHB2PHY_USB_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + usb_qmp_phy: ssphy@1615000 { + compatible = "qcom,usb-ssphy-qmp-usb3-or-dp"; + reg = <0x01615000 0x1000>, + <0x03cb244 0x4>; + reg-names = "qmp_phy_base", + "vls_clamp_reg"; + + vdd-supply = <&pm2250_l12>; + core-supply = <&pm2250_l13>; + qcom,vdd-voltage-level = <0 925000 970000>; + qcom,core-voltage-level = <0 1800000 1800000>; + qcom,qmp-phy-init-seq = + /* <reg_offset, value, delay> */ + <USB3PHY_QSERDES_COM_SYSCLK_EN_SEL 0x14 + USB3PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x08 + USB3PHY_QSERDES_COM_CLK_SELECT 0x30 + USB3PHY_QSERDES_COM_SYS_CLK_CTRL 0x06 + USB3PHY_QSERDES_COM_RESETSM_CNTRL 0x00 + USB3PHY_QSERDES_COM_RESETSM_CNTRL2 0x08 + USB3PHY_QSERDES_COM_BG_TRIM 0x0f + USB3PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x01 + USB3PHY_QSERDES_COM_HSCLK_SEL 0x00 + USB3PHY_QSERDES_COM_DEC_START_MODE0 0x82 + USB3PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0x55 + USB3PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0x55 + USB3PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x03 + USB3PHY_QSERDES_COM_CP_CTRL_MODE0 0x0b + USB3PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x16 + USB3PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x28 + USB3PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x80 + USB3PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x00 + USB3PHY_QSERDES_COM_CORECLK_DIV 0x0a + USB3PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x15 + USB3PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x34 + USB3PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x00 + USB3PHY_QSERDES_COM_LOCK_CMP_EN 0x00 + USB3PHY_QSERDES_COM_CORE_CLK_EN 0x00 + USB3PHY_QSERDES_COM_LOCK_CMP_CFG 0x00 + USB3PHY_QSERDES_COM_VCO_TUNE_MAP 0x00 + USB3PHY_QSERDES_COM_BG_TIMER 0x0a + USB3PHY_QSERDES_COM_SSC_EN_CENTER 0x01 + USB3PHY_QSERDES_COM_SSC_PER1 0x31 + USB3PHY_QSERDES_COM_SSC_PER2 0x01 + USB3PHY_QSERDES_COM_SSC_ADJ_PER1 0x00 + USB3PHY_QSERDES_COM_SSC_ADJ_PER2 0x00 + USB3PHY_QSERDES_COM_SSC_STEP_SIZE1 0xde + USB3PHY_QSERDES_COM_SSC_STEP_SIZE2 0x07 + USB3PHY_QSERDES_COM_PLL_IVCO 0x0f + USB3PHY_QSERDES_COM_CMN_CONFIG 0x06 + USB3PHY_QSERDES_COM_INTEGLOOP_INITVAL 0x80 + USB3PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x01 + USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x0b + USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x0b + USB3PHY_QSERDES_RXA_UCDR_PI_CONTROLS 0x00 + USB3PHY_QSERDES_RXB_UCDR_PI_CONTROLS 0x00 + USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0x00 + USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0x00 + USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x00 + USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x00 + USB3PHY_QSERDES_RXA_UCDR_FO_GAIN 0x0a + USB3PHY_QSERDES_RXB_UCDR_FO_GAIN 0x0a + USB3PHY_QSERDES_RXA_UCDR_SO_GAIN 0x06 + USB3PHY_QSERDES_RXB_UCDR_SO_GAIN 0x06 + USB3PHY_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x75 + USB3PHY_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x75 + USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x02 + USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x02 + USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4e + USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4e + USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x18 + USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x18 + USB3PHY_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 + USB3PHY_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 + USB3PHY_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x80 + USB3PHY_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x80 + USB3PHY_QSERDES_RXA_VGA_CAL_CNTRL2 0x0a + USB3PHY_QSERDES_RXB_VGA_CAL_CNTRL2 0x0a + USB3PHY_QSERDES_RXA_SIGDET_CNTRL 0x03 + USB3PHY_QSERDES_RXB_SIGDET_CNTRL 0x03 + USB3PHY_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x16 + USB3PHY_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x16 + USB3PHY_QSERDES_RXA_SIGDET_ENABLES 0x00 + USB3PHY_QSERDES_RXB_SIGDET_ENABLES 0x00 + USB3PHY_QSERDES_RXA_RX_MODE_00 0x00 + USB3PHY_QSERDES_RXB_RX_MODE_00 0x00 + USB3PHY_QSERDES_TXA_HIGHZ_DRVR_EN 0x10 + USB3PHY_QSERDES_TXB_HIGHZ_DRVR_EN 0x10 + USB3PHY_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 + USB3PHY_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 + USB3PHY_QSERDES_TXA_LANE_MODE_1 0xc6 + USB3PHY_QSERDES_TXB_LANE_MODE_1 0xc6 + USB3PHY_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x00 + USB3PHY_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x00 + USB3PHY_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x00 + USB3PHY_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x00 + USB3PHY_PCS_TXMGN_V0 0x9f + USB3PHY_PCS_TXDEEMPH_M6DB_V0 0x17 + USB3PHY_PCS_TXDEEMPH_M3P5DB_V0 0x0f + USB3PHY_PCS_FLL_CNTRL2 0x83 + USB3PHY_PCS_FLL_CNTRL1 0x02 + USB3PHY_PCS_FLL_CNT_VAL_L 0x09 + USB3PHY_PCS_FLL_CNT_VAL_H_TOL 0xa2 + USB3PHY_PCS_FLL_MAN_CODE 0x85 + USB3PHY_PCS_LOCK_DETECT_CONFIG1 0xd1 + USB3PHY_PCS_LOCK_DETECT_CONFIG2 0x1f + USB3PHY_PCS_LOCK_DETECT_CONFIG3 0x47 + USB3PHY_PCS_RXEQTRAINING_WAIT_TIME 0x75 + USB3PHY_PCS_RXEQTRAINING_RUN_TIME 0x13 + USB3PHY_PCS_LFPS_TX_ECSTART_EQTLOCK 0x86 + USB3PHY_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x04 + USB3PHY_PCS_TSYNC_RSYNC_TIME 0x44 + USB3PHY_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 + USB3PHY_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 + USB3PHY_PCS_RCVR_DTCT_DLY_U3_L 0x40 + USB3PHY_PCS_RCVR_DTCT_DLY_U3_H 0x00 + USB3PHY_PCS_RX_SIGDET_LVL 0x88>; + + qcom,qmp-phy-reg-offset = + <0xd74 /* USB3_PHY_PCS_STATUS */ + 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */ + 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */ + 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */ + 0xc00 /* USB3_PHY_SW_RESET */ + 0xc08 /* USB3_PHY_START */ + 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */ + + clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_AHB2PHY_USB_CLK>; + + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "cfg_ahb_clk"; + + resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + }; + +}; diff --git a/qcom/sa410m.dtsi b/qcom/sa410m.dtsi index 96aa915d..c8d0e1c4 100755 --- a/qcom/sa410m.dtsi +++ b/qcom/sa410m.dtsi @@ -836,7 +836,6 @@ }; #include "sa410m-stub-regulators.dtsi" - #include "scuba-thermal.dtsi" &thermal_zones { @@ -938,6 +937,7 @@ #include "sa410m-qupv3.dtsi" #include "sa410m-dma-heap.dtsi" #include "sa410m-pcie.dtsi" +#include "sa410m-usb.dtsi" &gcc_emac0_gdsc { status = "ok"; @@ -970,3 +970,7 @@ &qupv3_se4_2uart { status = "ok"; }; + +&usb0 { + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; +}; diff --git a/qcom/sa8155-vm-la-overlay.dts b/qcom/sa8155-vm-la-overlay.dts index 1abe5787..b8a83882 100755 --- a/qcom/sa8155-vm-la-overlay.dts +++ b/qcom/sa8155-vm-la-overlay.dts @@ -5,5 +5,6 @@ / { model = "Qualcomm Technologies, Inc. SA8155 Single LA Guest Virtual Machine"; compatible = "qcom,sa8155", "qcom,quinvm"; + qcom,msm-id = <362 0x20000>; qcom,board-id = <0x0 0x1000001>; }; diff --git a/qcom/sa8155-vm-la.dtsi b/qcom/sa8155-vm-la.dtsi index 828cf0ab..feb10fe9 100755 --- a/qcom/sa8155-vm-la.dtsi +++ b/qcom/sa8155-vm-la.dtsi @@ -39,3 +39,24 @@ &usb_qmp_phy { status = "ok"; }; + +/ { + rename_devices: rename_devices { + compatible = "qcom,rename-devices"; + rename_blk: rename_blk { + device-type = "block"; + actual-dev = "vda", "vdb", "vdc", + "vdd", "vde", "vdf", + "vdg", "vdh", "vdi", + "vdj", "vdk", "vdl", + "vdm", "vdn", "vdo", + "vdp", "vdq"; + rename-dev = "super", "userdata", "metadata", + "persist", "modem_a", "modem_b", + "bluetooth_a", "bluetooth_b", + "misc", "vbmeta_a", "vbmeta_b", + "boot_a", "boot_b", "dtbo_a", + "dtbo_b", "dsp_a", "dsp_b"; + }; + }; +}; diff --git a/qcom/sa8155-vm-usb.dtsi b/qcom/sa8155-vm-usb.dtsi index 63e5cef5..056154e0 100755 --- a/qcom/sa8155-vm-usb.dtsi +++ b/qcom/sa8155-vm-usb.dtsi @@ -184,106 +184,105 @@ qcom,vdd-max-load-uA = <47000>; core-supply = <&L8C>; qcom,qmp-phy-init-seq = - /* <reg_offset, value, delay> */ - <USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1a 0 - USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0 - USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0 - USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0 - USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab 0 - USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea 0 - USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0 - USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca 0 - USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e 0 - USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x02 0 - USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0 - USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0 - USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0 - USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0 - USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0 - USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0 - USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0 - USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0 - USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0 - USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0 - USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0 - USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab 0 - USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea 0 - USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0 - USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0 - USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0 - USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0 - USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0 - USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0 - USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0 - USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0 - USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0 - USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0 - USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0 - USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde 0 - USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0 - USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde 0 - USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0 - USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0 - USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0 - USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xa4 0 - USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x7f 0 - USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x37 0 - USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x2f 0 - USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xaf 0 - USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb6 0 - USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0b 0 - USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c 0 - USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc 0 - USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc 0 - USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0X99 0 - USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04 0 - USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0 - USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05 0 - USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05 0 - USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2f 0 - USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff 0 - USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0 - USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0 - USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0a 0 - USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0 - USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x00 0 - USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0 - USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f 0 - USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a 0 - USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a 0 - USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x04 0 - USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0 - USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0 - USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0 - USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e 0 - USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00 0 - USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 0 - USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x20 0 - USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06 0 - USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0 - USB3_UNI_QSERDES_TX_LANE_MODE_1 0x95 0 - USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40 0 - USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0xe4 0 - USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0xd0 0 - USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10 0 - USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0 - USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0 0 - USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0 - USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0 - USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0 - USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0 - USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0 - USB3_UNI_PCS_RX_SIGDET_LVL 0xaa 0 - USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0 - USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0 - USB3_UNI_PCS_CDR_RESET_TIME 0x0a 0 - USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0 - USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0 - USB3_UNI_PCS_EQ_CONFIG1 0x4b 0 - USB3_UNI_PCS_EQ_CONFIG5 0x10 0 - USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0 - USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c 0 - 0xffffffff 0xffffffff 0x00>; + /* <reg_offset, valuey> */ + <USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1a + USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 + USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 + USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 + USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab + USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea + USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e + USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x02 + USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 + USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 + USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 + USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 + USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 + USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 + USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a + USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 + USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 + USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 + USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 + USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab + USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea + USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 + USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 + USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 + USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 + USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 + USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca + USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e + USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 + USB3_UNI_QSERDES_COM_SSC_PER1 0x31 + USB3_UNI_QSERDES_COM_SSC_PER2 0x01 + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde + USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 + USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 + USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xa4 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x7f + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x37 + USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x2f + USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xaf + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb6 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0b + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc + USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc + USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 + USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04 + USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 + USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05 + USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05 + USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2f + USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff + USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f + USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f + USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0a + USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 + USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x00 + USB3_UNI_QSERDES_RX_GM_CAL 0x1f + USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f + USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a + USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a + USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x04 + USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 + USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 + USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 + USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e + USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00 + USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 + USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x20 + USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06 + USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 + USB3_UNI_QSERDES_TX_LANE_MODE_1 0x95 + USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40 + USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0xe4 + USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0xd0 + USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10 + USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c + USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0 + USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 + USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 + USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 + USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 + USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 + USB3_UNI_PCS_RX_SIGDET_LVL 0xaa + USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 + USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 + USB3_UNI_PCS_CDR_RESET_TIME 0x0a + USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 + USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 + USB3_UNI_PCS_EQ_CONFIG1 0x4b + USB3_UNI_PCS_EQ_CONFIG5 0x10 + USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 + USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c>; qcom,qmp-phy-reg-offset = <USB3_UNI_PCS_PCS_STATUS1 diff --git a/qcom/sa8195-vm-la-overlay.dts b/qcom/sa8195-vm-la-overlay.dts index 4c5bf46b..ab8fc5f4 100755 --- a/qcom/sa8195-vm-la-overlay.dts +++ b/qcom/sa8195-vm-la-overlay.dts @@ -8,5 +8,6 @@ model = "Qualcomm Technologies, Inc. SA8195 Single LA Virtual Machine"; compatible = "qcom,sa8195p", "qcom,quinvm"; qcom,pmic-name = "PM8195"; + qcom,msm-id = <405 0x20000>; qcom,board-id = <0 0x1000001>; }; diff --git a/qcom/sa8195p-adp-common.dtsi b/qcom/sa8195p-adp-common.dtsi index db0223b0..a6b1702d 100755 --- a/qcom/sa8195p-adp-common.dtsi +++ b/qcom/sa8195p-adp-common.dtsi @@ -1,5 +1,171 @@ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/qcom,gcc-sc8180x.h> + +&qupv3_3 { + status = "ok"; +}; + + +&qupv3_se0_spi { +status = "ok"; + +#address-cells = <1>; +#size-cells = <0>; + + can-controller@0 { + compatible = "qcom,nxp,mpc5746c"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <38 0>; + spi-max-frequency = <5000000>; + qcom,clk-freq-mhz = <40000000>; + qcom,max-can-channels = <1>; + qcom,bits-per-word = <8>; + qcom,support-can-fd; + }; +}; + &qupv3_se12_2uart { status = "ok"; }; + +&soc { + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xC>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-sp; + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3E800>; + snps,low_credit = <0xFFC18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3E800>; + snps,low_credit = <0xFFC18000>; + }; + }; + + ethqos_hw: qcom,ethernet@00020000 { + compatible = "qcom,stmmac-ethqos", "snps,dwmac-4.20a"; + qcom,arm-smmu; + emac-core-version = <0x20010001>; + reg = <0x20000 0x10000>, + <0x36000 0x100>, + <0x3D00000 0x300000>; + reg-names = "stmmaceth", "rgmii","tlmm-central-base"; + clocks = <&gcc GCC_EMAC_AXI_CLK>, + <&gcc GCC_EMAC_SLV_AHB_CLK>, + <&gcc GCC_EMAC_PTP_CLK>, + <&gcc GCC_EMAC_RGMII_CLK>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; + snps,ptp-ref-clk-rate = <250000000>; + snps,ptp-req-clk-rate = <96000000>; + interrupts-extended = <&intc 0 689 4>, <&intc 0 700 4>, + <&tlmm 124 2>; + interrupt-names = "macirq", "eth_lpi", + "phy-intr"; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <20480>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,reset-gpios = <&tlmm 79 GPIO_ACTIVE_HIGH>; + qcom,phy-intr-redirect = <&tlmm 124 GPIO_ACTIVE_LOW>; + gdsc_emac-supply = <&emac_gdsc>; + + pinctrl-names = "dev-emac-mdc", + "dev-emac-mdio", + "dev-emac-rgmii_txd0_state", + "dev-emac-rgmii_txd1_state", + "dev-emac-rgmii_txd2_state", + "dev-emac-rgmii_txd3_state", + "dev-emac-rgmii_txc_state", + "dev-emac-rgmii_tx_ctl_state", + "dev-emac-rgmii_rxd0_state", + "dev-emac-rgmii_rxd1_state", + "dev-emac-rgmii_rxd2_state", + "dev-emac-rgmii_rxd3_state", + "dev-emac-rgmii_rxc_state", + "dev-emac-rgmii_rx_ctl_state", + "dev-emac-phy_intr", + "dev-emac-phy_reset_state", + "dev-emac_pin_pps_0"; + + pinctrl-0 = <&emac_mdc>; + pinctrl-1 = <&emac_mdio>; + + pinctrl-2 = <&emac_rgmii_txd0>; + pinctrl-3 = <&emac_rgmii_txd1>; + pinctrl-4 = <&emac_rgmii_txd2>; + pinctrl-5 = <&emac_rgmii_txd3>; + pinctrl-6 = <&emac_rgmii_txc>; + pinctrl-7 = <&emac_rgmii_tx_ctl>; + + pinctrl-8 = <&emac_rgmii_rxd0>; + pinctrl-9 = <&emac_rgmii_rxd1>; + pinctrl-10 = <&emac_rgmii_rxd2>; + pinctrl-11 = <&emac_rgmii_rxd3>; + pinctrl-12 = <&emac_rgmii_rxc>; + pinctrl-13 = <&emac_rgmii_rx_ctl>; + + pinctrl-14 = <&emac_phy_intr>; + pinctrl-15 = <&emac_phy_reset_state>; + pinctrl-16 = <&emac_pin_pps_0>; + + snps,reset-delays-us = <0 11000 70000>; + phy-mode = "rgmii"; + eth-c22-mdio-probe; + ethqos_emb_smmu: ethqos_emb_smmu { + compatible = "qcom,emac-smmu-embedded"; + iommus = <&apps_smmu 0x7C0 0x0>; + qcom,iommu-dma = "fastmap"; + qcom,iommu-dma-addr-pool = <0x80000000 0x40000000>; + }; + }; +}; diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index e381c9a9..fb46d767 100755 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -19,10 +19,110 @@ #size-cells = <1>; read-only; ranges; - gpu_speed_bin: gpu_speed_bin@4002 { reg = <0x4002 0x2>; bits = <4 8>; + }; + }; + + hsi2s: qcom,hsi2s { + compatible = "qcom,sa8195-hsi2s", "qcom,hsi2s"; + number-of-interfaces = <3>; + reg = <0x172C0000 0x28000>, + <0x17080000 0xE000>; + reg-names = "lpa_if", "lpass_tcsr"; + interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + number-of-rate-detectors = <2>; + rate-detector-interfaces = <0 1>; + iommus = <&apps_smmu 0x1B5C 0x1>, + <&apps_smmu 0x1B5E 0x0>; + qcom,iommu-dma-addr-pool = <0x0 0xFFFFFFFF>; + + sdr0: qcom,hs0_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs1_i2s_mclk_active &hs1_i2s_sck_active + &hs1_i2s_ws_active &hs1_i2s_data0_active + &hs1_i2s_data1_active>; + pinctrl-1 = <&hs1_i2s_mclk_sleep &hs1_i2s_sck_sleep + &hs1_i2s_ws_sleep &hs1_i2s_data0_sleep + &hs1_i2s_data1_sleep>; + bit-clock-hz = <12288000>; + data-buffer-ms = <10>; + bit-depth = <32>; + spkr-channel-count = <2>; + mic-channel-count = <2>; + pcm-rate = <2>; + pcm-sync-src = <0>; + aux-mode = <0>; + rpcm-width = <1>; + tpcm-width = <1>; + enable-tdm = <1>; + tdm-rate = <32>; + tdm-rpcm-width = <16>; + tdm-tpcm-width = <16>; + tdm-sync-delay = <2>; + tdm-inv-sync = <0>; + pcm-lane-config = <1>; + }; + + sdr1: qcom,hs1_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs2_i2s_mclk_active &hs2_i2s_sck_active + &hs2_i2s_ws_active &hs2_i2s_data0_active + &hs2_i2s_data1_active>; + pinctrl-1 = <&hs2_i2s_mclk_sleep &hs2_i2s_sck_sleep + &hs2_i2s_ws_sleep &hs2_i2s_data0_sleep + &hs2_i2s_data1_sleep>; + bit-clock-hz = <12288000>; + data-buffer-ms = <10>; + bit-depth = <32>; + spkr-channel-count = <2>; + mic-channel-count = <2>; + pcm-rate = <2>; + pcm-sync-src = <0>; + aux-mode = <0>; + rpcm-width = <1>; + tpcm-width = <1>; + enable-tdm = <1>; + tdm-rate = <32>; + tdm-rpcm-width = <16>; + tdm-tpcm-width = <16>; + tdm-sync-delay = <2>; + tdm-inv-sync = <0>; + pcm-lane-config = <1>; + }; + + sdr2: qcom,hs2_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <2>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs3_i2s_mclk_active &hs3_i2s_sck_active + &hs3_i2s_ws_active &hs3_i2s_data0_active + &hs3_i2s_data1_active>; + pinctrl-1 = <&hs3_i2s_mclk_sleep &hs3_i2s_sck_sleep + &hs3_i2s_ws_sleep &hs3_i2s_data0_sleep + &hs3_i2s_data1_sleep>; + bit-clock-hz = <12288000>; + data-buffer-ms = <10>; + bit-depth = <32>; + spkr-channel-count = <2>; + mic-channel-count = <2>; + pcm-rate = <2>; + pcm-sync-src = <0>; + aux-mode = <0>; + rpcm-width = <1>; + tpcm-width = <1>; + enable-tdm = <1>; + tdm-rate = <32>; + tdm-rpcm-width = <16>; + tdm-tpcm-width = <16>; + tdm-sync-delay = <2>; + tdm-inv-sync = <0>; + pcm-lane-config = <1>; }; }; }; @@ -32,6 +132,24 @@ status = "ok"; }; +&sdhc_2 { + vdd-supply = <&pm8195_1_l10>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8195_1_l2>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&pm8195_1_gpios 4 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + &ufsphy_mem { compatible = "qcom,ufs-phy-qmp-v4"; vdda-phy-supply = <&pm8195_3_l5>; diff --git a/qcom/scuba_auto-pmic.dtsi b/qcom/scuba_auto-pmic.dtsi new file mode 100755 index 00000000..492c4e0b --- /dev/null +++ b/qcom/scuba_auto-pmic.dtsi @@ -0,0 +1,152 @@ +#include "pm2250.dtsi" + +&pm2250_gpios { + skin_therm { + skin_therm_default: skin_therm_default { + pins = "gpio5"; + bias-high-impedance; + }; + }; + + conn_therm { + conn_therm_default: conn_therm_default { + pins = "gpio6"; + bias-high-impedance; + }; + }; +}; + +&pm2250_vadc { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&conn_therm_default &skin_therm_default>; + + xo_therm { + reg = <ADC5_XO_THERM_100K_PU>; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm { + reg = <ADC5_AMUX_THM1_100K_PU>; + label = "pa_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = <ADC5_AMUX_THM2_100K_PU>; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + msm_therm { + reg = <ADC5_AMUX_THM3_100K_PU>; + label = "msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_therm { + reg = <ADC5_GPIO3_100K_PU>; + label = "skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + conn_therm { + reg = <ADC5_GPIO4_100K_PU>; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + /delete-node/ vbat_sns; + /delete-node/ usb_in_v_div_16; + /delete-node/ chg_temp; + /delete-node/ bat_therm; + /delete-node/ bat_therm_30k; + /delete-node/ bat_therm_400k; + /delete-node/ i_parallel; + /delete-node/ bat_id; + /delete-node/ die_temp_s3; +}; + +&spmi_bus { + qcom,pm2250@0 { + pm2250_adc_tm_iio: adc_tm@3400 { + compatible = "qcom,spmi-adc-tm5-iio"; + reg = <0x3400>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + xo_therm { + reg = <0>; + io-channels = <&pm2250_vadc ADC5_XO_THERM_100K_PU>; + }; + + pa_therm { + reg = <1>; + io-channels = <&pm2250_vadc ADC5_AMUX_THM1_100K_PU>; + }; + + quiet_therm { + reg = <2>; + io-channels = <&pm2250_vadc ADC5_AMUX_THM2_100K_PU>; + }; + + msm_therm { + reg = <3>; + io-channels = <&pm2250_vadc ADC5_AMUX_THM3_100K_PU>; + }; + + skin_therm { + reg = <4>; + io-channels = <&pm2250_vadc ADC5_GPIO3_100K_PU>; + }; + + conn_therm { + reg = <5>; + io-channels = <&pm2250_vadc ADC5_GPIO4_100K_PU>; + }; + }; + + /delete-node/ pm2250_qg; + /delete-node/ pm2250_charger; + }; + + qcom,pm2250@1 { + /delete-node/ pm2250_vib; + /delete-node/ pm2250_pwm1; + /delete-node/ pm2250_pwm2; + /delete-node/ pm2250_pwm3; + }; +}; + +&thermal_zones { + pm2250-tz { + trips { + trip0 { + temperature = <105000>; + }; + + trip1 { + temperature = <125000>; + }; + + trip2 { + temperature = <155000>; + }; + }; + }; +}; diff --git a/qcom/scuba_auto.dtsi b/qcom/scuba_auto.dtsi index 299b99b8..0f125493 100755 --- a/qcom/scuba_auto.dtsi +++ b/qcom/scuba_auto.dtsi @@ -973,6 +973,27 @@ #freq-domain-cells = <1>; }; + spmi_bus: qcom,spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x1c40000 0x1100>, + <0x1e00000 0x2000000>, + <0x3e00000 0x100000>, + <0x3f00000 0xa0000>, + <0x1c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + thermal_zones: thermal-zones { }; + clk_virt: interconnect@0 { compatible = "qcom,scuba-clk_virt"; qcom,keepalive; @@ -1091,6 +1112,7 @@ }; }; +#include "scuba_auto-pmic.dtsi" #include "pm2250-rpm-regulator.dtsi" #include "scuba-regulator.dtsi" #include "monaco-gdsc.dtsi" diff --git a/qcom/sdmshrike-dma-heaps.dtsi b/qcom/sdmshrike-dma-heaps.dtsi index 000e8954..a8e48717 100755 --- a/qcom/sdmshrike-dma-heaps.dtsi +++ b/qcom/sdmshrike-dma-heaps.dtsi @@ -24,7 +24,7 @@ qcom,qseecom { qcom,dma-heap-name = "qcom,qseecom"; - qcom,dma-heap-type = <HEAP_TYPE_CMA>; + qcom,dma-heap-type = <HEAP_TYPE_CARVEOUT>; memory-region = <&qseecom_mem>; }; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 7f3151c0..59710463 100755 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -28,6 +28,7 @@ aliases { ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + mmc1 = &sdhc_2; /* SDC2 SD Card slot */ serial0 = &qupv3_se12_2uart; spi22 = &qupv3_se22_spi; i2c7 = &qupv3_se20_i2c; @@ -335,7 +336,7 @@ }; chosen { - bootargs = "kpti=0 ssbd=force-off"; + bootargs = "kpti=0 ssbd=force-off qcom_dma_heaps.enable_bitstream_contig_heap=y"; }; firmware: firmware { @@ -459,10 +460,8 @@ qseecom_mem: qseecom_region { compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; + no-map; + reg = <0x0 0x9e400000 0x0 0x1400000>; }; @@ -1574,6 +1573,68 @@ }; }; + + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <1600000 280000>; + opp-avg-kBps = <50000 0>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + opp-peak-kBps = <5600000 1500000>; + opp-avg-kBps = <104000 0>; + }; + }; + + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + bus-width = <4>; + qcom,restore-after-cx-collapse; + + + iommus = <&apps_smmu 0x06A0 0x0>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + + interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + operating-points-v2 = <&sdhc2_opp_table>; + + + /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; + + qcom,devfreq,freq-table = <50000000 200000000>; + + status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <70>; + }; + + qos1 { + mask = <0xf0>; + vote = <70>; + }; + }; + ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>; /* PHY regs */ reg-names = "phy_mem"; diff --git a/qcom/sdxbaagha-pinctrl.dtsi b/qcom/sdxbaagha-pinctrl.dtsi index 0516b956..2b9c9bb2 100755 --- a/qcom/sdxbaagha-pinctrl.dtsi +++ b/qcom/sdxbaagha-pinctrl.dtsi @@ -50,6 +50,48 @@ }; }; }; + + pcie_ep { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio56"; + function = "pcie_clkreq_n"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; + }; }; pcie0 { pcie0_perst_default: pcie0_perst_default { diff --git a/qcom/sdxbaagha-regulators.dtsi b/qcom/sdxbaagha-regulators.dtsi new file mode 100755 index 00000000..3671dbe3 --- /dev/null +++ b/qcom/sdxbaagha-regulators.dtsi @@ -0,0 +1,365 @@ +#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h> + +&apps_rsc_drv1 { + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "cx.lvl"; + proxy-supply = <&VDD_CX_LEVEL>; + + VDD_MODEM_LEVEL: + VDD_CX_LEVEL: S1A_LEVEL: + pmx35_s1_level: regulator-pmx35-s1-level { + regulator-name = "pmx35_s1_level"; + qcom,set = <RPMH_REGULATOR_SET_ALL>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + qcom,init-voltage-level = + <RPMH_REGULATOR_LEVEL_TURBO>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + <RPMH_REGULATOR_LEVEL_TURBO + RPMH_REGULATOR_LEVEL_MAX>; + + }; + + VDD_CX_LEVEL_AO: S1A_LEVEL_AO: + pmx35_s1_level_ao: regulator-pmx35-s1-level-ao { + regulator-name = "pmx35_s1_level_ao"; + qcom,set = <RPMH_REGULATOR_SET_ACTIVE>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + qcom,init-voltage-level = + <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mx.lvl"; + proxy-supply = <&VDD_MXA_LEVEL>; + + VDD_EBI_LEVEL: VDD_MXA_LEVEL: L1A_LEVEL: + pmx35_l1_level: regulator-pmx35-l1-level { + regulator-name = "pmx35_l1_level"; + qcom,set = <RPMH_REGULATOR_SET_ALL>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + qcom,init-voltage-level = + <RPMH_REGULATOR_LEVEL_TURBO>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + <RPMH_REGULATOR_LEVEL_TURBO + RPMH_REGULATOR_LEVEL_MAX>; + }; + + VDD_MXA_LEVEL_AO: L1A_LEVEL_AO: + pmx35_l1_level_ao: regulator-pmx35-l1-level-ao { + regulator-name = "pmx35_l1_level_ao"; + qcom,set = <RPMH_REGULATOR_SET_ACTIVE>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + qcom,init-voltage-level = + <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + }; + + rpmh-regulator-mxclvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mxc.lvl"; + proxy-supply = <&VDD_MXC_LEVEL>; + + VDD_MXC_LEVEL: L2A_LEVEL: + pmx35_l2_level: regulator-pmx35-l2-level { + regulator-name = "pmx35_l2_level"; + qcom,set = <RPMH_REGULATOR_SET_ALL>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + qcom,init-voltage-level = + <RPMH_REGULATOR_LEVEL_TURBO>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + <RPMH_REGULATOR_LEVEL_TURBO + RPMH_REGULATOR_LEVEL_MAX>; + }; + + VDD_MXC_LEVEL_AO: L2A_LEVEL_AO: + pmx35_l2_level_ao: regulator-pmx35-l2-level-ao { + regulator-name = "pmx35_l2_level_ao"; + qcom,set = <RPMH_REGULATOR_SET_ACTIVE>; + regulator-min-microvolt = + <RPMH_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPMH_REGULATOR_LEVEL_MAX>; + qcom,init-voltage-level = + <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + }; + + rpmh-regulator-ldo3a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo3a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>; + + L3A: pmx35_l3: regulator-pmx35-l3 { + regulator-name = "pmx35_l3"; + qcom,set = <RPMH_REGULATOR_SET_ALL>; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + qcom,init-voltage = <910000>; + qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + rpmh-regulator-ldo4a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo4a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>; + + L4A: pmx35_l4: regulator-pmx35-l4 { + regulator-name = "pmx35_l4"; + qcom,set = <RPMH_REGULATOR_SET_ALL>; + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + qcom,init-voltage = <620000>; + qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + rpmh-regulator-ldo5a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo5a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>; + + L5A: pmx35_l5: regulator-pmx35-l5 { + regulator-name = "pmx35_l5"; + qcom,set = <RPMH_REGULATOR_SET_ALL>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + rpmh-regulator-ldo6a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo6a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>; + + L6A: pmx35_l6: regulator-pmx35-l6 { + regulator-name = "pmx35_l6"; + qcom,set = <RPMH_REGULATOR_SET_ALL>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + rpmh-regulator-ldo7a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo7a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>; + + L7A: pmx35_l7: regulator-pmx35-l7 { + regulator-name = "pmx35_l7"; + qcom,set = <RPMH_REGULATOR_SET_ALL>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + rpmh-regulator-ldo8a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo8a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>; + + L8A: pmx35_l8: regulator-pmx35-l8 { + regulator-name = "pmx35_l8"; + qcom,set = <RPMH_REGULATOR_SET_ALL>; + regulator-min-microvolt = <552000>; + regulator-max-microvolt = <904000>; + qcom,init-voltage = <552000>; + qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + rpmh-regulator-ldo9a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo9a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>; + + L9A: pmx35_l9: regulator-pmx35-l9 { + regulator-name = "pmx35_l9"; + qcom,set = <RPMH_REGULATOR_SET_ALL>; + regulator-min-microvolt = <960000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1128000>; + }; + }; + + rpmh-regulator-ldo10a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo10a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>; + + L10a: pmx35_l10: regulator-pmx35-l10 { + regulator-name = "pmx35_l10"; + qcom,set = <RPMH_REGULATOR_SET_ALL>; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <3088000>; + qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + rpmh-regulator-ldo11a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo11a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>; + + L11A: pmx35_l11: regulator-pmx35-l11 { + regulator-name = "pmx35_l11"; + qcom,set = <RPMH_REGULATOR_SET_ALL>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + rpmh-regulator-ldo12a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo12a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>; + + L12A: pmx35_l12: regulator-pmx35-l12 { + regulator-name = "pmx35_l12"; + qcom,set = <RPMH_REGULATOR_SET_ALL>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + rpmh-regulator-ldo13a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo13a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>; + + L13A: pmx35_l13: regulator-pmx35-l13 { + regulator-name = "pmx35_l13"; + qcom,set = <RPMH_REGULATOR_SET_ALL>; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <800000>; + qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + rpmh-regulator-ldo14a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo14a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + qcom,mode-threshold-currents = <0 30000>; + qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>; + + L14A: pmx35_l14: regulator-pmx35-l14 { + regulator-name = "pmx35_l14"; + qcom,set = <RPMH_REGULATOR_SET_ALL>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + rpmh-regulator-ldo15a { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldo15a"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + qcom,mode-threshold-currents = <0 10000>; + qcom,disable-mode = <RPMH_REGULATOR_MODE_LPM>; + + L15A: pmx35_l15: regulator-pmx35-l15 { + regulator-name = "pmx35_l15"; + qcom,set = <RPMH_REGULATOR_SET_ALL>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; diff --git a/qcom/sdxbaagha-rumi.dtsi b/qcom/sdxbaagha-rumi.dtsi index 48ff6d67..e3f70810 100755 --- a/qcom/sdxbaagha-rumi.dtsi +++ b/qcom/sdxbaagha-rumi.dtsi @@ -39,6 +39,22 @@ 0x0 0x4 0x9 0x14>; }; + + bi_tcxo: bi_tcxo { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <2>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; + + bi_tcxo_ao: bi_tcxo_ao { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <2>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; }; &qupv3_se3_2uart { @@ -63,3 +79,8 @@ &cpufreq_hw { clocks = <&bi_tcxo>, <&gcc GPLL0>; }; + +&rpmhcc { + compatible = "qcom,dummycc"; + clock-output-names = "rpmhcc_clocks"; +}; diff --git a/qcom/sdxbaagha.dtsi b/qcom/sdxbaagha.dtsi index 071966bd..8128cc80 100755 --- a/qcom/sdxbaagha.dtsi +++ b/qcom/sdxbaagha.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,sdxbaagha.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/gpio/gpio.h> / { #address-cells = <1>; @@ -262,6 +263,11 @@ <CONTROL_TCS 0>, <FAST_PATH_TCS 0>; }; + + rpmhcc: clock-controller { + compatible = "qcom,sdxbaagha-rpmh-clk"; + #clock-cells = <1>; + }; }; }; @@ -380,7 +386,7 @@ clocks { xo_board: xo_board { compatible = "fixed-clock"; - clock-frequency = <19200000>; + clock-frequency = <38400000>; clock-output-names = "xo_board"; #clock-cells = <0>; }; @@ -400,31 +406,6 @@ }; }; - bi_tcxo: bi_tcxo { - compatible = "fixed-factor-clock"; - clocks = <&xo_board>; - clock-mult = <1>; - clock-div = <1>; - #clock-cells = <0>; - clock-output-names = "bi_tcxo"; - }; - - bi_tcxo_ao: bi_tcxo_ao { - compatible = "fixed-factor-clock"; - clocks = <&xo_board>; - clock-mult = <1>; - clock-div = <1>; - #clock-cells = <0>; - clock-output-names = "bi_tcxo_ao"; - }; - - rpmhcc: clock-controller { - compatible = "fixed-clock"; - clock-output-names = "rpmh_clocks"; - clock-frequency = <19200000>; - #clock-cells = <1>; - }; - gcc: clock-controller@80000 { compatible = "qcom,sdxbaagha-gcc", "syscon"; reg = <0x80000 0x1f4200>; @@ -567,6 +548,177 @@ compatible = "qcom,msm-sps-4k"; qcom,pipe-attr-ee; }; + + pcie_ep: qcom,pcie@48000000 { + compatible = "qcom,pcie-ep"; + + reg = <0x48002000 0x1000>, + <0x48000000 0xf1d>, + <0x48000f20 0xa8>, + <0x48001000 0x1000>, + <0x01bf0000 0x4000>, + <0x01bf6000 0x2000>, + <0x01bf4000 0x1000>, + <0x01fcb000 0x1000>, + <0xc2f1000 0x4>; + reg-names = "msi", "dm_core", "elbi", "iatu", "parf", "phy", + "mmio", "tcsr_pcie_perst_en", "aoss_cc_reset"; + + #address-cells = <0>; + interrupt-parent = <&pcie_ep>; + interrupts = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int_global"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default + &pcie_ep_wake_default>; + + clkreq-gpio = <&tlmm 56 GPIO_ACTIVE_HIGH>; + perst-gpio = <&tlmm 57 GPIO_ACTIVE_HIGH>; + wake-gpio = <&tlmm 53 GPIO_ACTIVE_HIGH>; + + gdsc-vdd-supply = <&gcc_pcie_gdsc>; + vreg-1p2-supply = <&L14A>; + vreg-0p9-supply = <&L3A>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; + + qcom,vreg-1p2-voltage-level = <1200000 1200000 15000>; + qcom,vreg-0p9-voltage-level = <912000 880000 48100>; + qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX + RPMH_REGULATOR_LEVEL_NOM 0>; + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_PIPE_CLK_SRC>, + <&pcie_pipe_clk>, + <&rpmhcc RPMH_CXO_CLK>; + + clock-names = "pcie_pipe_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_aux_clk", "pcie_ldo", + "pcie_sleep_clk", "pcie_slv_q2a_axi_clk", + "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src", + "pcie_0_ref_clk_src"; + + resets = <&gcc GCC_PCIE_BCR>, <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "pcie_core_reset", "pcie_phy_reset"; + + interconnect-names = "icc_path"; + interconnects = <&aggre_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + + qcom,pcie-vendor-id = /bits/ 16 <0x17cb>; + qcom,pcie-device-id = /bits/ 16 <0x011a>; + qcom,pcie-link-speed = <1>; + qcom,pcie-phy-ver = <8>; + qcom,pcie-active-config; + qcom,pcie-aggregated-irq; + qcom,pcie-mhi-a7-irq; + qcom,phy-status-reg2 = <0x214>; + qcom,mhi-soc-reset-offset = <0xb001b8>; + qcom,aoss-rst-clr; + qcom,aux-clk = <0x13>; + qcom,phy-init = <0x0240 0x01 0x0 + 0x0094 0x00 0x0 + 0x0154 0x31 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x19 0x0 + 0x00b0 0x04 0x0 + 0x00ac 0xff 0x0 + 0x00c4 0x14 0x0 + 0x00b8 0x09 0x0 + 0x00b4 0xff 0x0 + 0x0158 0x01 0x0 + 0x0074 0x20 0x0 + 0x007c 0x13 0x0 + 0x0084 0x00 0x0 + 0x0078 0x12 0x0 + 0x0080 0x12 0x0 + 0x0088 0x00 0x0 + 0x01b0 0x1d 0x0 + 0x01ac 0x56 0x0 + 0x01b8 0x17 0x0 + 0x01b4 0x78 0x0 + 0x004c 0x07 0x0 + 0x0050 0x07 0x0 + 0x00f0 0x01 0x0 + 0x00ec 0xfb 0x0 + 0x00f8 0x01 0x0 + 0x00f4 0xfb 0x0 + 0x000c 0x02 0x0 + 0x01a0 0x14 0x0 + 0x0ee4 0x20 0x0 + 0x0e84 0x75 0x0 + 0x0e90 0x3f 0x0 + 0x115c 0x7f 0x0 + 0x1160 0xff 0x0 + 0x1164 0xbf 0x0 + 0x1168 0x3f 0x0 + 0x116c 0xd8 0x0 + 0x1170 0xdc 0x0 + 0x1174 0xdc 0x0 + 0x1178 0x5c 0x0 + 0x117c 0x34 0x0 + 0x1180 0xa6 0x0 + 0x1190 0x34 0x0 + 0x1194 0x38 0x0 + 0x10d8 0x0f 0x0 + 0x0e3c 0x12 0x0 + 0x0e40 0x01 0x0 + 0x10dc 0x00 0x0 + 0x104c 0x08 0x0 + 0x1050 0x08 0x0 + 0x1044 0xf0 0x0 + 0x11a4 0x38 0x0 + 0x10cc 0xf0 0x0 + 0x10f4 0x07 0x0 + 0x1008 0x09 0x0 + 0x1014 0x05 0x0 + 0x0654 0x00 0x0 + 0x06a8 0x0f 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x02dc 0x0d 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + + status = "disabled"; + }; + + mhi_device: mhi_dev@1bf4000 { + compatible = "qcom,msm-mhi-dev"; + reg = <0x1bf4000 0x1000>; + reg-names = "mhi_mmio_base"; + qcom,mhi-ep-msi = <0>; + qcom,mhi-version = <0x1000000>; + qcom,use-mhi-dma-software-channel; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mhi-device-inta"; + qcom,mhi-ifc-id = <0x011a17cb>; + qcom,mhi-interrupt; + qcom,no-m0-timeout; + status = "disabled"; + }; + + mhi_net_device: qcom,mhi_net_dev { + compatible = "qcom,msm-mhi-dev-net"; + status = "disabled"; + }; }; #include "sdxbaagha-pinctrl.dtsi" diff --git a/qcom/sdxpinn-pcie.dtsi b/qcom/sdxpinn-pcie.dtsi index e1d95457..fe825953 100755 --- a/qcom/sdxpinn-pcie.dtsi +++ b/qcom/sdxpinn-pcie.dtsi @@ -105,18 +105,21 @@ <0>, <0>, <0>, <0>; resets = <&gcc GCC_PCIE_BCR>, <&gcc GCC_PCIE_PHY_BCR>; - reset-names = "pcie_core_reset", - "pcie_phy_reset"; + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; qcom,smmu-sid-base = <0x0800>; iommu-map = <0x0 &apps_smmu 0x0800 0x1>, <0x100 &apps_smmu 0x0801 0x1>; + qcom,boot-option = <0x1>; qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,tpwr-on-scale = <1>; qcom,tpwr-on-value = <9>; qcom,eq-fmdc-t-min-phase23 = <1>; qcom,slv-addr-space-size = <0x4000000>; + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <150>; qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; qcom,target-link-speed = <3>; @@ -287,7 +290,7 @@ 0x1828 0x00 0x0 0x1c28 0x00 0x0 0x1e24 0x00 0x0 - 0x1e28 0x00 0x0 + 0x1e28 0x01 0x0 0x1200 0x00 0x0 0x1244 0x03 0x0>; @@ -419,11 +422,14 @@ iommu-map = <0x0 &apps_smmu 0x0880 0x1>, <0x100 &apps_smmu 0x0881 0x1>; + qcom,boot-option = <0x1>; qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,tpwr-on-scale = <1>; qcom,tpwr-on-value = <9>; qcom,eq-fmdc-t-min-phase23 = <1>; qcom,slv-addr-space-size = <0x4000000>; + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <150>; qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; @@ -648,7 +654,7 @@ <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, <&gcc GCC_PCIE_2_SLV_AXI_CLK>, <&gcc GCC_PCIE_2_CLKREF_EN>, - <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, <&gcc GCC_PCIE_2_PIPE_DIV2_CLK>, <&gcc GCC_PCIE_2_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_2_PIPE_CLK_SRC>, @@ -674,11 +680,14 @@ iommu-map = <0x0 &apps_smmu 0x0900 0x1>, <0x100 &apps_smmu 0x0901 0x1>; + qcom,boot-option = <0x1>; qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,tpwr-on-scale = <1>; qcom,tpwr-on-value = <9>; qcom,eq-fmdc-t-min-phase23 = <1>; qcom,slv-addr-space-size = <0x4000000>; + qcom,l1-2-th-scale = <2>; + qcom,l1-2-th-value = <150>; qcom,ep-latency = <10>; qcom,num-parf-testbus-sel = <0xb9>; @@ -718,7 +727,7 @@ 0x00e0 0x90 0x0 0x00e4 0x82 0x0 0x00f4 0x07 0x0 - 0x0110 0x04 0x0 + 0x0110 0x08 0x0 0x0120 0x42 0x0 0x0140 0x14 0x0 0x0164 0x34 0x0 diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi index fc2cef49..d534ebd9 100755 --- a/qcom/sdxpinn.dtsi +++ b/qcom/sdxpinn.dtsi @@ -790,7 +790,7 @@ /* Voting for max b/w on PNOC bus for now */ <1057800 725760>; - iommus = <&apps_smmu 0x100 0x7>; + iommus = <&apps_smmu 0x100 0x3>; qcom,iommu-dma = "bypass"; status = "disabled"; @@ -1407,6 +1407,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_SYS_NOC_MVMSS_CLK>; }; }; diff --git a/qcom/slate.dtsi b/qcom/slate.dtsi index b6cfc1e9..a5869c0d 100755 --- a/qcom/slate.dtsi +++ b/qcom/slate.dtsi @@ -1,13 +1,147 @@ -&soc { - qupv3_se4_spi: spi@4a90000 { /* BLSP4 QUP3*/ +&qupv3_se4_spi { /* BLSP4 QUP3*/ status = "ok"; qcom,shared_ee; qcom,slate-spi { compatible = "qcom,slate-spi"; reg = <0>; - spi-max-frequency = <737000>; + spi-max-frequency = <40000000>; interrupt-parent = <&tlmm>; qcom,irq-gpio = <&tlmm 95 1>; }; +}; + +&soc { + aon_pas:qcom,rproc-slate { + compatible = "qcom,rproc-slate"; + qcom,firmware-name = "slatefw.mdt"; + /* GPIO inputs from blackghost */ + qcom,slate2ap-status-gpio = <&tlmm 98 0>; + /* GPIO output to blackghost */ + qcom,ap2slate-status-gpio = <&tlmm 97 0>; + }; + + qcom,slate-daemon { + compatible = "qcom,slate-daemon"; + qcom,firmware-name = "slatefw.mdt"; + qcom,rproc-handle = <&aon_pas>; + }; + + qcom,glink-slatecom-xprt-slate { + compatible = "qcom,glink-slatecom-xprt"; + label = "slate"; + + qcom,glinkpkt-slate-ssc-hal { + qcom,glink-channels = "ssc_hal"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-sso-hal { + qcom,glink-channels = "sso_hal"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-cam-hal { + qcom,glink-channels = "cam_hal"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-usta { + qcom,glink-channels = "ssc_usta"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-0 { + qcom,glink-channels = "ssc_test_0"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-1 { + qcom,glink-channels = "ssc_test_1"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-2 { + qcom,glink-channels = "ssc_test_2"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-3 { + qcom,glink-channels = "ssc_test_3"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-4 { + qcom,glink-channels = "ssc_test_4"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-5 { + qcom,glink-channels = "ssc_test_5"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-6 { + qcom,glink-channels = "ssc_test_6"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-7 { + qcom,glink-channels = "ssc_test_7"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-8 { + qcom,glink-channels = "ssc_test_8"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-9 { + qcom,glink-channels = "ssc_test_9"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-10 { + qcom,glink-channels = "ssc_test_10"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-11 { + qcom,glink-channels = "ssc_test_11"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-12 { + qcom,glink-channels = "ssc_test_12"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-13 { + qcom,glink-channels = "ssc_test_13"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; + + qcom,glinkpkt-slate-ssc-test-14 { + qcom,glink-channels = "ssc_test_14"; + qcom,intents = <0x2710 2 + 0x3E8 2>; + }; }; }; diff --git a/qcom/sm8150-dma-heaps.dtsi b/qcom/sm8150-dma-heaps.dtsi index 3b46c5b0..c2a1bed8 100755 --- a/qcom/sm8150-dma-heaps.dtsi +++ b/qcom/sm8150-dma-heaps.dtsi @@ -31,7 +31,7 @@ qcom,qseecom { qcom,dma-heap-name = "qcom,qseecom"; - qcom,dma-heap-type = <HEAP_TYPE_CMA>; + qcom,dma-heap-type = <HEAP_TYPE_CARVEOUT>; memory-region = <&qseecom_mem>; }; diff --git a/qcom/sm8150-usb.dtsi b/qcom/sm8150-usb.dtsi index 65ec1043..76042da1 100755 --- a/qcom/sm8150-usb.dtsi +++ b/qcom/sm8150-usb.dtsi @@ -34,7 +34,7 @@ qcom,core-clk-rate = <200000000>; qcom,core-clk-rate-hs = <66666667>; - qcom,ignore-wakeup-src-in-hostmode; + qcom,host-poweroff-in-pm-suspend; interconnect-names = "usb-ddr", "ddr-usb"; interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, @@ -58,6 +58,35 @@ dr_mode = "otg"; usb-role-switch; }; + + qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + + qcom,usb-bam-fifo-baseaddr = <0x146bb000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; }; /* Primary USB port related High Speed PHY */ @@ -105,7 +134,7 @@ "ss_phy_irq","dm_hs_phy_irq"; qcom,use-pdc-interrupts; qcom,default-mode-host; - qcom,ignore-wakeup-src-in-hostmode; + qcom,host-poweroff-in-pm-suspend; USB3_GDSC-supply = <&usb30_sec_gdsc>; clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>, diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 77f81a81..843eabbb 100755 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -416,7 +416,7 @@ pil_modem_mem: modem_region { no-map; - reg = <0x0 0x8d800000 0x0 0x9600000>; + reg = <0x0 0x8d800000 0x0 0x4c1c000>; }; pil_video_mem: pil_video_region { @@ -456,10 +456,8 @@ qseecom_mem: qseecom_region { compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; + no-map; + reg = <0x0 0x9e400000 0x0 0x1400000>; }; cdsp_sec_mem: cdsp_sec_regions { @@ -1482,7 +1480,7 @@ memory-region = <&rproc_adsp_mem>; /* Inputs from ssc */ - interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <&adsp_smp2p_in 0 0>, <&adsp_smp2p_in 2 0>, <&adsp_smp2p_in 1 0>, |