sw5100: Integrate LW 2.0 r00040.3

Bug: 268128919
Change-Id: I0002b6c62f3167d4e8e039c5fc71d7e209161b49
Signed-off-by: Andrei Ciubotariu <aciubotariu@google.com>

169 files changed, 30842 insertions, 468 deletions

diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt
index 57c1943f..bdf8ed7d 100755
--- a/bindings/arm/msm/msm.txt
+++ b/bindings/arm/msm/msm.txt
@@ -251,6 +251,7 @@ compatible = "qcom,kona-mtp"
 compatible = "qcom,kona-cdp"
 compatible = "qcom,kona-qrd"
 compatible = "qcom,kona-iot"
+compatible = "qcom,kona-iot-qrd"
 compatible = "qcom,lahaina-rumi"
 compatible = "qcom,lahaina-atp"
 compatible = "qcom,lahaina-mtp"
@@ -352,8 +353,10 @@ compatible = "qcom,sdxbaagha-cdp"
 compatible = "qcom,sa410m-idp"
 compatible = "qcom,sa410m-qrd"
 compatible = "qcom,sa410m-ccard"
+compatible = "qcom,qam-star"
 compatible = "qcom,lemans-rumi"
 compatible = "qcom,lemans-ivi"
+compatible = "qcom,lemans-ivi-adas"
 compatible = "qcom,lemans-ivi-adp-air"
 compatible = "qcom,lemans-ivi-adp-star"
 compatible = "qcom,lemans-ivi-qam-star"
@@ -361,3 +364,5 @@ compatible = "qcom,lemans-adas-high"
 compatible = "qcom,lemans-adas-high-adp-air"
 compatible = "qcom,lemans-adas-high-adp-star"
 compatible = "qcom,lemans-adas-high-qam-star"
+compatible = "qcom,lemans-ivi-adas-adp-star"
+compatible = "qcom,lemans-ivi-adas-qam-star"
diff --git a/bindings/arm/msm/sys-pm-violators.txt b/bindings/arm/msm/sys-pm-violators.txt
index 7ed1512c..5ac94862 100755
--- a/bindings/arm/msm/sys-pm-violators.txt
+++ b/bindings/arm/msm/sys-pm-violators.txt
@@ -15,6 +15,7 @@ PROPERTIES
 		    - "qcom,sys-pm-lahaina"
 		    - "qcom,sys-pm-waipio"
 		    - "qcom,sys-pm-kalama"
+		    - "qcom,sys-pm-lemans"
 
 - reg:
 	Usage: required
diff --git a/bindings/clock/qcom,camcc.txt b/bindings/clock/qcom,camcc.txt
index ceac38a6..9cddfbce 100755
--- a/bindings/clock/qcom,camcc.txt
+++ b/bindings/clock/qcom,camcc.txt
@@ -17,6 +17,7 @@ Required properties :
 		"qcom,sa8155-camcc"
 		"qcom,sa8155-camcc-v2"
 		"qcom,sc8180x-camcc"
+		"qcom,sm8250-camcc"
 		"qcom,lemans-camcc"
 
 - reg : shall contain base register location and length.
diff --git a/bindings/clock/qcom,debugcc.txt b/bindings/clock/qcom,debugcc.txt
index 99c4c24a..cced5fab 100755
--- a/bindings/clock/qcom,debugcc.txt
+++ b/bindings/clock/qcom,debugcc.txt
@@ -21,6 +21,7 @@ Required properties :
 			"qcom,sdxbaagha-debugcc"
 			"qcom,lemans-debugcc"
 			"qcom,sa410m-debugcc"
+			"qcom,sm8250-debugcc"
 
 - qcom,gcc: phandle to the GCC device node.
 - qcom,videocc: phandle to the Video CC device node.
diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt
index 8c976d26..71a6cc58 100755
--- a/bindings/clock/qcom,dispcc.txt
+++ b/bindings/clock/qcom,dispcc.txt
@@ -28,6 +28,7 @@ Required properties :
 			"qcom,scuba-dispcc"
 			"qcom,lemans-dispcc0"
 			"qcom,lemans-dispcc1"
+                        "qcom,sm8250-dispcc"
 
 - reg : shall contain base register location and length.
 - #clock-cells : from common clock binding, shall contain 1.
diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt
index 521d86b7..1b13ef77 100755
--- a/bindings/clock/qcom,gcc.txt
+++ b/bindings/clock/qcom,gcc.txt
@@ -25,6 +25,7 @@ Required properties :
 			"qcom,gcc-sdm845"
 			"qcom,lahaina-gcc"
 			"qcom,sm8150-gcc"
+			"qcom,gcc-sm8250"
 			"qcom,sm8150-gcc-v2"
 			"qcom,sa8155-gcc"
 			"qcom,sa8155-gcc-v2"
@@ -44,6 +45,7 @@ Required properties :
 			"qcom,sdxbaagha-gcc"
 			"qcom,lemans-gcc"
 			"qcom,sa410m-gcc"
+			"qcom,direwolf-gcc"
 
 - reg : shall contain base register location and length
 - vdd_cx-supply: The vdd_cx logic rail supply.
diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt
index dbebb3c1..57af8042 100755
--- a/bindings/clock/qcom,gpucc.txt
+++ b/bindings/clock/qcom,gpucc.txt
@@ -11,6 +11,7 @@ Required properties :
 		"qcom,diwali-gpucc",
 		"qcom,kalama-gpucc"
 		"qcom,sm8150-gpucc",
+		"qcom,sm8250-gpucc",
 		"qcom,sa8155-gpucc",
 		"qcom,khaje-gpucc",
 		"qcom,sc8180x-gpucc".
diff --git a/bindings/clock/qcom,npucc.txt b/bindings/clock/qcom,npucc.txt
index b05c0012..2b21c7ba 100755
--- a/bindings/clock/qcom,npucc.txt
+++ b/bindings/clock/qcom,npucc.txt
@@ -4,6 +4,7 @@ Qualcomm Technologies, Inc. NPU Clock & Reset Controller Binding
 Required properties :
 - compatible : shall contain only one of the following:
 			"qcom,sm8150-npucc"
+			"qcom,sm8250-npucc"
 			"qcom,sm8150-npucc-v2"
 			"qcom,sa8155-npucc"
 			"qcom,sa8155-npucc-v2"
diff --git a/bindings/clock/qcom,videocc.txt b/bindings/clock/qcom,videocc.txt
index 020338ca..74772ab8 100755
--- a/bindings/clock/qcom,videocc.txt
+++ b/bindings/clock/qcom,videocc.txt
@@ -12,6 +12,7 @@ Required properties :
 			"qcom,kalama-videocc"
 			"qcom,kalama-videocc-v2"
 			"qcom,sm8150-videocc"
+			"qcom,sm8250-videocc"
 			"qcom,sm8150-videocc-v2"
 			"qcom,sa8155-videocc"
 			"qcom,sa8155-videocc-v2"
diff --git a/bindings/firmware/qcom/hwkm.txt b/bindings/firmware/qcom/hwkm.txt
new file mode 100755
index 00000000..25ddc158
--- /dev/null
+++ b/bindings/firmware/qcom/hwkm.txt
@@ -0,0 +1,28 @@
+HWKM (Hardware Key Manager)
+
+The HWKM driver is a platform device driver that helps
+communicating with both the master and slave blocks of the
+hardware key manager to issue commands to perform key operations
+mainly required for storage encryption.
+
+Required properties:
+- compatible : Should be "qcom,hwkm".
+- reg: Register set for both master and slaves.
+- reg-names : Identifiers for parsing master and slave regs.
+- clocks : clocks needed for operating master and the slave.
+- clock-names : name identifiers corresponding to the clocks.
+- qcom,enable-hwkm-clk: to ensure clocks can be handled by HLOS.
+- qcom,op-freq-hz: Max frequency of the listed clocks.
+
+Example:
+
+	qcom_hwkm: hwkm@10c0000 {
+		compatible = "qcom,hwkm";
+		reg = <0x10c0000 0x9000>, <0x1d90000 0x9000>;
+		reg-names = "km_master", "ice_slave";
+		qcom,enable-hwkm-clk;
+
+		clock-names = "km_clk_src";
+		clocks = <&clock_rpmh RPMH_HWKM_CLK>;
+		qcom,op-freq-hz = <75000000>;
+	};
diff --git a/bindings/i2c/qcom,i2c-msm-geni.txt b/bindings/i2c/qcom,i2c-msm-geni.txt
index a71d7235..2d4dcebb 100755
--- a/bindings/i2c/qcom,i2c-msm-geni.txt
+++ b/bindings/i2c/qcom,i2c-msm-geni.txt
@@ -21,8 +21,6 @@ Optional property:
    Needs to be added by client driver node in case of multi-ee usecase.
  - qcom,le-vm : Boolean flag to support I2C functionality in trusted VM.
  - qcom,i2c-hub : Boolean flag to support I2C hub functionality.
- - qcom,rtl_se : Boolean flag to bypass Cancel for RTL based SE. Applicable
-   for QUP version < 3.9.0 .
 
 Child nodes should conform to i2c bus binding.
 
diff --git a/bindings/input/qti-haptics.txt b/bindings/input/qti-haptics.txt
new file mode 100755
index 00000000..b86bae9a
--- /dev/null
+++ b/bindings/input/qti-haptics.txt
@@ -0,0 +1,209 @@
+Qualcomm Technologies, Inc. Haptics driver
+
+Haptics peripheral in QTI PMICs can support different type of actuators or
+vibrators:
+  1) Eccentric Rotation Mass (ERM);
+  2) Linear Resonant Actuator (LRA).
+This binding document describes the properties for this module.
+
+Properties:
+
+- compatible
+  Usage:      required
+  Value type: <string>
+  Definition: It can be one of the following:
+		"qcom,haptics",
+		"qcom,pm660-haptics",
+		"qcom,pm8150b-haptics".
+
+- reg
+  Usage:      required
+  Value type: <u32>
+  Definition: Base address of haptics peripheral.
+
+- interrupts
+  Usage:      required
+  Value type: <prop-encoded-array>
+  Definition: Peripheral interrupt specifier.
+
+- interrupt-names
+  Usage:      required
+  Value type: <stringlist>
+  Definition: Interrupt names.  This list must match up 1-to-1 with the
+		interrupts specified in the 'interrupts' property. Following
+		interrupts are required: "hap_play_irq", "hap_sc_irq".
+
+- qcom,actuator-type
+  Usage:      optional
+  Value type: <string>
+  Definition: Specifies the type of the actuator connected on the output of
+		haptics module. Allowed values: "erm", "lra". If this is
+		not specified, then LRA type will be used by default.
+
+- qcom,vmax-mv
+  Usage:      optional
+  Value type: <u32>
+  Definition: Specifies the maximum allowed output voltage in millivolts
+		for the actuator. Value specified here will be rounded
+		off to the closest multiple of 116 mV. Allowed values:
+		0 to 3596. If this is not specified, then 1800 mV will be
+		used by default.
+
+- qcom,play-rate-us
+  Usage:      optional
+  Value type: <u32>
+  Definition: Specifies the period at which each sample of the 8-byte waveform
+		registers is played. For ERM, this period is flexible and it
+		can be chosen based on the desired shape of the pattern.
+		For LRA, it should be set equal to the resonance period
+		specified in the LRA actuator datasheet. Allowed values are:
+		0 to 20475. If this is not specified, 5715us play rate is used.
+
+- vdd-supply
+  Usage:      optional
+  Value type: <phandle>
+  Definition: Specifies the phandle of the regulator device which supplies
+		haptics module through VDD_HAP pin. This is only needed if VDD_HAP
+		is supplied from an external boost regulator instead of VPH_PWR.
+
+Following properties are specific only when LRA actuator is used:
+
+- qcom,lra-resonance-sig-shape
+  Usage:      optional
+  Value type: <string>
+  Definition: Specifies the shape of the LRA resonance drive signal. Allowed
+		values: "sine", "square". If this is not specified, sinusoid
+		resonance driver signal is used.
+
+- qcom,lra-allow-variable-play-rate
+  Usage:      optional
+  Value type: <empty>
+  Definition: If specified, "qcom,wf-play-rate-us" for LRA defined in each
+		effect could be different with the resonance period of the
+		LRA actuator.
+
+- qcom,lra-auto-resonance-mode
+  Usage:      optional
+  Value type: <string>
+  Definition: Specifies the auto resonance technique for LRA. Allowed values are:
+		"zxd": zero crossing based discontinuous method;
+		"qwd": quarter wave drive method;
+
+Following properties could be specified in child nodes for defining vibrating
+waveforms/effects:
+
+- qcom,effect-id
+  Usage:      required
+  Value type: <u32>
+  Definition: Specifies the effect ID that the client can request to play the
+		corresponding waveform defined in this child node. The ID is
+		normaly defined and sent from userspace for certain user
+		notification event.
+
+- qcom,wf-pattern
+  Usage:      optional
+  Value type: <prop-encoded-array>
+  Definition: Specifies the waveform pattern in a byte array that will be
+		played for the effect-id. The bit fields of each byte are:
+		 [7]: drive direction, 0 - forward; 1 - reverse
+		 [6]: overdrive, 0 -- 1x drive; 1 -- 2x drive
+		 [5:1]: waveform amplitude
+		 [0]: reserved.
+
+- qcom,wf-vmax-mv
+  Usage:      optional
+  Value type: <u32>
+  Definition: Specifies the maximum allowed output voltage in millivolts
+		for this effect. Value specified here will be rounded
+		off to the closest multiple of 116 mV. Allowed values:
+		0 to 3596. If this is not specified, the value defined in
+		"qcom,vmax-mv" will be applied.
+
+- qcom,wf-play-rate-us
+  Usage:      optional
+  Value type: <u32>
+  Definition: Specifies the play period in microseconds for each byte pattern.
+		Allowed values are: 0 to 20475. For LRA actuator, if
+		"qcom,lra-allow-variable-play-rate" is defined, it could be
+		set to other values not equal to the resonance period of the
+		LRA actuator.
+
+- qcom,wf-repeat-count
+  Usage:      optional
+  Value type: <u32>
+  Definition: Specifies the repeat times for the waveform pattern. Allowed
+		values are: 1, 2, 4, 8, 16, 32, 64, 128.
+
+- qcom,wf-s-repeat-count
+  Usage:      optional
+  Value type: <u32>
+  Definition: Specifies the repeat times for each sample defined in
+		qcom,wf-pattern. Allowed values are: 1, 2, 4, 8.
+
+- qcom,wf-brake-pattern
+  Usage:      optional
+  Value type: <prop-encoded-array>
+  Definition: Specifies the brake pattern with 4 elements used to enable the
+		internal reverse braking. Allowed values for each element are:
+			0: no brake
+			1: brake with (Vmax / 2) strength
+			2: brake with Vmax strength
+			3: brake with (2 * Vmax) strength
+		If this property is specified with an array of non-zero values,
+		then the brake pattern is applied at the end of the playing
+		waveform.
+
+- qcom,lra-auto-resonance-disable
+  Usage:      optional
+  Value type: <empty>
+  Definition: If specified, the hardware feature of LRA auto resonance detection
+		is disabled.
+
+- qcom,wf-line-in-audio
+  Usage:      optional
+  Value type: <empty>
+  Definition: Boolean flag to indicate if the effect is playing the audio signal
+		comes into LINE-IN pin. If this is specified, the pattern
+		specified in "qcom,wf-pattern" will be ignored.
+
+- qcom,wf-line-in-pwm
+  Usage:      optional
+  Value type: <empty>
+  Definition: Boolean flag to indicate if the effect is playing the PWM signal
+		comes into LINE-IN pin. If this is specified, the pattern
+		specified in "qcom,wf-pattern" will be ignored.
+Example:
+  qcom,haptics@c000 {
+	compatible = "qcom,haptics";
+	reg = <0xc000 0x100>;
+	interrupts = <0x3 0xc0 0x0 IRQ_TYPE_EDGE_BOTH>,
+		     <0x3 0xc0 0x1 IRQ_TYPE_EDGE_BOTH>;
+	interrupt-names = "hap-sc-irq", "hap-play-irq";
+	qcom,actuator-type = "lra";
+	qcom,vmax-mv = <1800>;
+	qcom,play-rate-us = <8000>;
+	qcom,lra-resonance-sig-shape = "sine";
+	qcom,lra-auto-resonance-mode = "qwd";
+	qcom,lra-allow-variable-play-rate;
+
+	wf_0 {
+		/* CLICK effect */
+		qcom,effect-id = <0>;
+		qcom,wf-play-rate-us = <6250>;
+		qcom,wf-pattern = [3e 3e 3e];
+		qcom,lra-auto-resonance-disable;
+	};
+
+	wf_5 {
+		/* HEAVY_CLICK effect */
+		qcom,effect-id = <5>;
+		qcom,wf-play-rate-us = <6250>;
+		qcom,wf-pattern = [7e 7e 7e];
+	};
+
+	wf_6 {
+		/* RINGTONE_x effect */
+		qcom,effect-id = <6>;
+		qcom,wf-line-in-audio;
+	};
+  };
diff --git a/bindings/input/touchscreen/raydium_ts.txt b/bindings/input/touchscreen/raydium_ts.txt
new file mode 100755
index 00000000..80123bc5
--- /dev/null
+++ b/bindings/input/touchscreen/raydium_ts.txt
@@ -0,0 +1,58 @@
+Raydium WT030 touch controller
+
+Please add this description here: The Raydium Touch controller is connected to
+the
+host processor via I2C. The controller generates interrupts when the user
+touches
+the panel. The host controller is expected to read the touch coordinates over
+I2C and
+pass the coordinates to the rest of the system.
+
+Required properties:
+
+ - compatible                     : should be "raydium,raydium-ts".
+ - reg                            : i2c slave address of the device.
+ - interrupt-parent               : parent of interrupt.
+ - raydium,irq-gpio               : irq gpio.
+ - raydium,reset-gpio             : reset gpio.
+ - vdd_ana-supply                 : analog voltage power supply needed to
+   power device.
+ - vcc_i2c-supply                 : i2c voltage power supply needed to power
+   device.
+
+Optional property:
+ - raydium,max-num-touches   : addr of ub-i2c.
+ - raydium,display-coords    : array of display coordinates.
+ - raydium,x_max             : maximal x value of the panel.
+ - raydium,y_max             : maximal y value of the panel.
+ - raydium,fw_id             : firmware id.
+ - raydium,soft-reset-delay-ms  : reset delay for controller (ms), default
+   100.
+ - raydium,hard-reset-delay-ms  : reset delay for controller (ms), default
+   100.
+
+Example:
+       i2c@78b7000 {
+               status = "ok";
+               raydium_ts@39 {
+                       compatible = "raydium,raydium-ts";
+                       reg = <0x39>;
+                       interrupt-parent = <&msm_gpio>;
+                       interrupts = <13 0x2008>;
+                       vdd_ana-supply = <&pm8916_l17>;
+                       vcc_i2c-supply = <&pm8916_l6>;
+                       pinctrl-names ="pmx_ts_active","pmx_ts_suspend","pmx_ts_release";
+                       pinctrl-0 = <&ts_int_active &ts_reset_active>;
+                       pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+                       pinctrl-2 = <&ts_release>;
+                       raydium,reset-gpio = <&msm_gpio 12 0x00>;
+                       raydium,irq-gpio = <&msm_gpio 13 0x00>;
+                       raydium,num-max-touches = <2>;
+                       raydium,soft-reset-delay-ms = <50>;
+                       raydium,hard-reset-delay-ms = <100>;
+                       raydium,x_max = <390>;
+                       raydium,y_max = <390>;
+                       raydium,display-coords= <0  0 390 390>;
+                       raydium,fw_id = <0x2202>
+               };
+       };
diff --git a/bindings/interconnect/qcom,kona.txt b/bindings/interconnect/qcom,kona.txt
new file mode 100755
index 00000000..edec07e4
--- /dev/null
+++ b/bindings/interconnect/qcom,kona.txt
@@ -0,0 +1,32 @@
+Qualcomm Technologies, Inc. Kona Network-On-Chip interconnect driver binding
+------------------------------------------------------------------------------
+
+Kona interconnect providers support system bandwidth requirements through
+RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
+able to communicate with the BCM through the Resource State Coordinator (RSC)
+associated with each execution environment. Provider nodes must point to at
+least one RPMh device child node pertaining to their RSC and each provider
+can map to multiple RPMh resources.
+
+Required properties :
+- compatible : shall contain only one of the following:
+			"qcom,kona-aggre1_noc",
+			"qcom,kona-aggre2_noc",
+			"qcom,kona-camnoc_virt",
+			"qcom,kona-compute_noc",
+			"qcom,kona-config_noc",
+			"qcom,kona-dc_noc",
+			"qcom,kona-gem_noc",
+			"qcom,kona-ipa_virt",
+			"qcom,kona-mc_virt",
+			"qcom,kona-mmss_noc",
+			"qcom,kona-system_noc",
+			"qcom,kona-npu_noc",
+- #interconnect-cells : should contain 1
+
+Examples:
+
+aggre1_noc: interconnect@16e0000 {
+	compatible = "qcom,kona-aggre1_noc";
+	interconnect-cells = <1>;
+};
diff --git a/bindings/interconnect/qcom,monaco_auto.txt b/bindings/interconnect/qcom,monaco_auto.txt
new file mode 100755
index 00000000..79d72dc3
--- /dev/null
+++ b/bindings/interconnect/qcom,monaco_auto.txt
@@ -0,0 +1,29 @@
+Qualcomm Technologies, Inc. Monaco_auto Network-On-Chip interconnect driver binding
+------------------------------------------------------------------------------
+Monaco_auto interconnect providers support system bandwidth requirements through
+RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
+able to communicate with the BCM through the Resource State Coordinator (RSC)
+associated with each execution environment. Provider nodes must point to at
+least one RPMh device child node pertaining to their RSC and each provider
+can map to multiple RPMh resources.
+
+Required properties :
+- compatible : shall contain only one of the following:
+		"qcom,monaco_auto-aggre1_noc";
+		"qcom,monaco_auto-aggre2_noc";
+		"qcom,monaco_auto-clk_virt";
+		"qcom,monaco_auto-config_noc";
+		"qcom,monaco_auto-gem_noc";
+		"qcom,monaco_auto-mc_virt";
+		"qcom,monaco_auto-mmss_noc";
+		"qcom,monaco_auto-pcie_anoc";
+		"qcom,monaco_auto-system_noc";
+
+- #interconnect-cells : should contain 1
+
+Examples:
+
+aggre1_noc: interconnect@16c0000 {
+	"qcom,monaco_auto-aggre1_noc";
+	interconnect-cells = <1>;
+};
diff --git a/bindings/interconnect/qcom,sdxbaagha.txt b/bindings/interconnect/qcom,sdxbaagha.txt
index 2143431c..71f0e7ba 100755
--- a/bindings/interconnect/qcom,sdxbaagha.txt
+++ b/bindings/interconnect/qcom,sdxbaagha.txt
@@ -12,15 +12,17 @@ Required properties :
 - compatible : shall contain only one of the following:
 			"qcom,sdxbaagha-aggre_noc",
 			"qcom,sdxbaagha-cnoc_main",
-			"qcom,sdxbaagha-dc_noc_dch",
+			"qcom,sdxbaagha-dc_noc",
 			"qcom,sdxbaagha-mc_virt",
+			"qcom,sdxbaagha-clk_virt",
+			"qcom,sdxbaagha-pcie_anoc",
 			"qcom,sdxbaagha-mem_noc",
-			"qcom,sdxbaagha-snoc",
+			"qcom,sdxbaagha-system_noc",
 - #interconnect-cells : should contain 1
 
 Examples:
 
-snoc: interconnect@15C0000 {
+system_noc: interconnect@15C0000 {
 	compatible = "qcom,sdxbaagha-snoc";
 	#interconnect-cells = <1>;
 };
diff --git a/bindings/leds/leds-qpnp-flash-v2.txt b/bindings/leds/leds-qpnp-flash-v2.txt
new file mode 100755
index 00000000..08c92c5d
--- /dev/null
+++ b/bindings/leds/leds-qpnp-flash-v2.txt
@@ -0,0 +1,334 @@
+Qualcomm Technologies Inc. PNP v2 Flash LED
+
+QPNP (Qualcomm Technologies Inc. Plug N Play) Flash LED (Light
+Emitting Diode) driver v2 is used to provide illumination to
+camera sensor when background light is dim to capture good
+picture. It can also be used for flashlight/torch application.
+It is part of PMIC on Qualcomm Technologies Inc. reference platforms.
+
+Main node:
+
+Required properties:
+- compatible		: Should be "qcom,qpnp-flash-led-v2"
+- reg			: Base address and size for flash LED modules
+- qcom,pmic-revid	: phandle of PMIC revid module. This is used to
+			  identify the PMIC subtype.
+
+Optional properties:
+- interrupts		: Specifies the interrupts associated with flash-led.
+- interrupt-names	: Specify the interrupt names associated with interrupts.
+- qcom,hdrm-auto-mode	: Boolean type to select headroom auto mode enabled or not
+- qcom,isc-delay-us	: Integer type to specify short circuit delay. Valid values are 32, 64,
+			  128, 192. Unit is uS.
+- qcom,warmup-delay-us	: Integer type to specify warm up delay. Valid values are 32, 64,
+			  128, 192. Unit is uS.
+- qcom,ramp-up-step	: Integer property to specify flash current ramp up time
+			  step. Unit is in nS. Allowed values are: 200, 400, 800, 1600,
+			  3200, 6400, 12800, 25600.
+- qcom,ramp-down-step	: Integer property to specify flash current ramp down
+			  time step. Unit is in nS. Allowed values are: 200, 400, 800, 1600,
+			  3200, 6400, 12800, 25600.
+- qcom,torch-realtime-brightness-control : Boolean property which enables torch realtime brightness control
+				  which gives option to change brightness from torch node when it is
+				  already enabled from switch node.
+- qcom,short-circuit-det	: Boolean property which enables short circuit fault detection.
+- qcom,open-circuit-det		: Boolean property which enables open circuit fault detection.
+- qcom,vph-droop-det		: Boolean property which enables VPH droop detection.
+- qcom,vph-droop-hysteresis-mv	: Integer property to specify VPH droop hysteresis. It is only used if
+				  qcom,vph-droop-det is specified. Valid values are 0, 25, 50 and 75.
+				  Unit is mV.
+- qcom,vph-droop-threshold-mv	: Integer property to specify VPH droop threshold. It is only used if
+				  qcom,vph-droop-det is specified. Valid values are
+				  2500 to 3200 with step size of 100. Unit is mV.
+- qcom,vph-droop-debounce-us	: Integer property to specify VPH droop debounce time. It is only used
+				  if qcom,vph-droop-det is specified. Valid values are 0, 8, 16 and 26.
+				  Unit is uS.
+- qcom,led1n2-iclamp-low-ma	: Integer property to specify current clamp low
+				  level for mitigation. Unit is mA. Allowed
+				  values are same as under qcom,max-current.
+- qcom,led1n2-iclamp-mid-ma	: Integer property to specify current clamp mid
+				  level for mitigation. Unit is mA. Allowed
+				  values are same as under qcom,max-current.
+- qcom,led3-iclamp-low-ma	: Integer property to specify current clamp low
+				  level for mitigation. Unit is mA. Allowed
+				  values are same as under qcom,max-current.
+- qcom,led3-iclamp-mid-ma	: Integer property to specify current clamp mid
+				  level for mitigation. Unit is mA. Allowed
+				  values are same as under qcom,max-current.
+- qcom,vled-max-uv		: Integer property for flash current predictive mitigation.
+				  Default value is 3500000 uV.
+- qcom,ibatt-ocp-threshold-ua	: Integer property for flash current predictive mitigation.
+				  Default value is 4500000 uA.
+- qcom,rparasitic-uohm		: Integer property for flash current predictive mitigation indicating
+				  parasitic component of battery resistance. Default value is 0 uOhm.
+- qcom,lmh-ocv-threshold-uv	: Required property for flash current preemptive LMH mitigation.
+				  Default value is 3700000 uV.
+- qcom,lmh-rbatt-threshold-uohm	: Required property for flash current preemptive LMH mitigation.
+				  Default value is 400000 uOhm.
+- qcom,lmh-mitigation-sel	: Optional property to configure flash current preemptive LMH mitigation.
+				  Accepted values are:
+				  0: MITIGATION_DISABLED
+				  1: MITIGATION_BY_ILED_THRESHOLD
+				  2: MITIGATION_BY_SW
+				  Default value is 2.
+- qcom,chgr-mitigation-sel	: Optional property to configure flash current preemptive charger mitigation.
+				  Accepted values are:
+				  0: MITIGATION_DISABLED
+				  1: MITIGATION_BY_ILED_THRESHOLD
+				  2: MITIGATION_BY_SW
+				  Default value is 2.
+- qcom,lmh-level		: Optional property to configure flash current preemptive LMH mitigation.
+				  Accepted values are 0, 1, and 3. Default value is 0.
+- qcom,iled-thrsh-ma		: Optional property to configure the led current threshold at which HW
+				  preemptive mitigation is triggered. Unit is mA. Default value is 1000.
+				  Accepted values are in the range 0 - 3100, with steps of 100.
+				  0 disables autonomous HW mitigation.
+- qcom,thermal-derate-en	: Boolean property to enable flash current thermal mitigation.
+- qcom,thermal-derate-current	: Array of currrent limits for thermal mitigation. Required if
+				  qcom,thermal-derate-en is specified. Unit is mA. Format is
+				  qcom,thermal-derate-current = <OTST1_LIMIT, OTST2_LIMIT, OTST3_LIMIT>.
+- qcom,otst-ramp-back-up-dis	: Boolean property to disable current ramp
+				  backup after thermal derate trigger is
+				  deasserted.
+- qcom,thermal-derate-slow	: Integer property to specify slow ramping
+				  down thermal rate. Unit is in uS. Allowed
+				  values are: 128, 256, 512, 1024, 2048, 4096,
+				  8192 and 314592.
+- qcom,thermal-derate-fast	: Integer property to specify fast ramping
+				  down thermal rate. Unit is in uS. Allowed
+				  values are: 32, 64, 96, 128, 256, 384 and
+				  512.
+- qcom,thermal-debounce		: Integer property to specify thermal debounce
+				  time. It is only used if qcom,thermal-derate-en
+				  is specified. Unit is in uS. Allowed values
+				  are: 0, 16, 32, 64.
+- qcom,thermal-hysteresis	: Integer property to specify thermal derating
+				  hysteresis. Unit is in deciDegC. It is only
+				  used if qcom,thermal-derate-en is specified.
+				  Allowed values are:
+				  0, 15, 30, 45 for pmi8998.
+				  0, 20, 40, 60 for pm660l.
+- qcom,thermal-thrsh1		: Integer property to specify OTST1 threshold
+				  for thermal mitigation. Unit is in Celsius.
+				  Accepted values are:
+				  85, 79, 73, 67, 109, 103, 97, 91.
+- qcom,thermal-thrsh2		: Integer property to specify OTST2 threshold
+				  for thermal mitigation. Unit is in Celsius.
+				  Accepted values are:
+				  110, 104, 98, 92, 134, 128, 122, 116.
+- qcom,thermal-thrsh3		: Integer property to specify OTST3 threshold
+				  for thermal mitigation. Unit is in Celsius.
+				  Accepted values are:
+				  125, 119, 113, 107, 149, 143, 137, 131.
+- qcom,hw-strobe-option	: Integer type to specify hardware strobe option. Based on the specified
+			  value, additional GPIO configuration may be required to provide strobing
+			  support. Supported values are:
+			  0: Flash strobe is used for LED1, LED2, LED3
+			  1: Flash strobe is used for LED1, LED2 and GPIO10 is used for LED3
+			  2: Flash strobe is used for LED1; GPIO9 is used for LED2; GPIO10 is used for LED3
+			  For PM8150L/A and its derivatives, supported values are:
+			  0: Flash strobe is used for LED1, LED2, LED3
+			  1: Flash strobe is used for LED1, LED2 and GPIO12 is used for LED3
+- switchX-supply		: phandle of the regulator that needs to be used
+				  as a supply for flash switch_X device.
+- qcom,bst-pwm-ovrhd-uv		: Charger flash VPH overhead. Applicable for PMI632 only.
+				  Supported values (in mV) are: 300, 400, 500, 600. Default is 300.
+
+Child node: Contains settings for each individual LED. Each LED channel needs a flash node and
+torch node for itself, and an individual switch node to serve as an overall switch.
+
+Required Properties:
+- label			: Type of led that will be used, either "flash", "torch", or "switch.
+- qcom,led-name		: Name of the LED.
+- qcom,default-led-trigger	: Trigger for the camera flash and torch. Accepted values are
+			  "flash0_trigger", "flash1_trigger", "flash2_trigger, "torch0_trigger",
+			  "torch1_trigger", "torch2_trigger", and "switch_trigger".
+- qcom,id		: ID for each physical LED equipped. In order to handle situation when
+			  only 1 or 2 LEDs are installed, flash and torch nodes on LED channel 0
+			  should be specified with ID 0; nodes on channel 1 be ID 1, etc. This is
+			  not required for switch node.
+- qcom,max-current	: Maximum current allowed on this LED. Valid values should be
+			  integer from 0 to 1500 inclusive. Flash 2 should have maximum current of
+			  750 per hardware requirement. Unit is mA. For torch, the maximum current
+			  is clamped at 500 mA. This is not required for the switch node.
+- qcom,duration-ms	: Required property for flash nodes but not needed for torch. Integer
+			  type specifying flash duration. Values are from 10ms to 1280ms with
+			  10ms resolution. This is not required for switch node.
+- qcom,led-mask		: Required property for switch nodes. Bitmask to indicate which leds are
+			  controlled by this switch node. Accepted values are in the range 1 to 7,
+			  inclusive. Example:
+			  qcom,led-mask = <4>; /* This switch node controls the flash2/torch2 led. */
+
+Optional properties:
+- qcom,current-ma	: operational current intensity for LED in mA. Accepted values are a
+			  positive integer in the range of 0 to qcom,max-current inclusive.
+- qcom,ires-ua		: Integer type to specify current resolution. Accepted values should be
+			  12500, 10000, 7500, and 5000. Unit is uA.
+- qcom,hdrm-voltage-mv	: Integer type specifying headroom voltage. Values are from 125mV to 500mV
+			  with 25mV resolution. Default setting is 325mV
+- qcom,hdrm-vol-hi-lo-win-mv	: Integer type to specify headroom voltage swing range. Values are
+				  from 0mV to 375mV with 25mV resolution. Default setting is 100mV.
+- pinctrl-names		: Name of the pinctrl configuration that will be used when external GPIOs
+			  are used for enabling/disabling, HW strobing of flash LEDs. For more
+			  information on using pinctrl, please refer
+			  Documentation/devicetree/bindings/pinctrl/msm-pinctrl.txt
+                          Following are the pinctrl configs that can be specified:
+                          "led_enable" : pinctrl config to enable led. This should specify the active
+                          configuration defined for each pin or pin group.
+                          "led_disable" : pinctrl config to disable led. This should specify the sleep
+                          configuration defined for each pin or pin group.
+                          "strobe_enable" : pinctrl config to enable hw-strobe. This should specify the
+                          active configuration defined for each pin or pin group.
+                          "strobe_disable" : pinctrl config to disable hw-strobe. This should specify the
+                          sleep configuration defined for each pin or pin group.
+- qcom,hw-strobe-gpio	: phandle to specify GPIO for hardware strobing. This is used when there is no
+			  pinctrl support or PMIC GPIOs are used.
+- qcom,strobe-sel	: Property to select strobe type. If not defined,
+			  software strobe will be used. Allowed options are:
+			  0 - SW strobe
+			  1 - HW strobe
+			  2 - LPG strobe
+			  LPG strobe is supported only for LED3.
+			  If LPG strobe is specified, then strobe control is
+			  configured for active high and level triggered. Also
+			  qcom,hw-strobe-option should be set to 1 or 2.
+- qcom,hw-strobe-edge-trigger	: Boolean property to select trigger type. If defined, hw-strobe is set to
+				  be edge triggered. Otherwise, it is level triggered.
+- qcom,hw-strobe-active-low	: Boolean property to select strobe signal polarity. If defined, hw-strobe
+				  signal polarity is set to active-low, else it is active-high.
+- qcom,symmetry-en	: Boolean property to specify if the flash LEDs under a
+			  switch node are controlled symmetrically. This needs
+			  to be specified if a group of flash LED channels are
+			  connected to a single LED.
+Example:
+	qcom,leds@d300 {
+		compatible = "qcom,qpnp-flash-led-v2";
+		status = "okay";
+		reg = <0xd300 0x100>;
+		label = "flash";
+		interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_BOTH>,
+			     <0x3 0xd3 0x1 IRQ_TYPE_EDGE_BOTH>,
+			     <0x3 0xd3 0x2 IRQ_TYPE_EDGE_BOTH>,
+			     <0x3 0xd3 0x3 IRQ_TYPE_EDGE_BOTH>,
+			     <0x3 0xd3 0x4 IRQ_TYPE_EDGE_BOTH>,
+			     <0x3 0xd3 0x5 IRQ_TYPE_EDGE_BOTH>,
+			     <0x3 0xd3 0x6 IRQ_TYPE_EDGE_BOTH>,
+			     <0x3 0xd3 0x7 IRQ_TYPE_EDGE_BOTH>;
+		interrupt-names = "led-fault-irq",
+				"mitigation-irq",
+				"flash-timer-exp-irq",
+				"all-ramp-down-done-irq",
+				"all-ramp-up-done-irq",
+				"led3-ramp-up-done-irq",
+				"led2-ramp-up-done-irq",
+				"led1-ramp-up-done-irq";
+
+		qcom,hdrm-auto-mode;
+		qcom,isc-delay = <192>;
+		switch0-supply = <&pmi8998_bob>;
+
+		pmi8998_flash0: qcom,flash_0 {
+			label = "flash";
+			qcom,led-name = "led:flash_0";
+			qcom,max-current = <1500>;
+			qcom,default-led-trigger =
+						"flash0_trigger";
+			qcom,id = <0>;
+			qcom,current-ma = <1000>;
+			qcom,duration-ms = <1280>;
+			qcom,ires-ua = <12500>;
+			qcom,hdrm-voltage-mv = <325>;
+			qcom,hdrm-vol-hi-lo-win-mv = <100>;
+		};
+
+		pmi8998_flash1: qcom,flash_1 {
+			label = "flash";
+			qcom,led-name = "led:flash_1";
+			qcom,max-current = <1500>;
+			qcom,default-led-trigger =
+						"flash1_trigger";
+			qcom,id = <1>;
+			qcom,current-ma = <1000>;
+			qcom,duration-ms = <1280>;
+			qcom,ires-ua = <12500>;
+			qcom,hdrm-voltage-mv = <325>;
+			qcom,hdrm-vol-hi-lo-win-mv = <100>;
+		};
+
+		pmi8998_flash2: qcom,flash_2 {
+			label = "flash";
+			qcom,led-name = "led:flash_2";
+			qcom,max-current = <750>;
+			qcom,default-led-trigger =
+						"flash2_trigger";
+			qcom,id = <2>;
+			qcom,current-ma = <500>;
+			qcom,duration-ms = <1280>;
+			qcom,ires-ua = <12500>;
+			qcom,hdrm-voltage-mv = <325>;
+			qcom,hdrm-vol-hi-lo-win-mv = <100>;
+			pinctrl-names = "led_enable","led_disable";
+			pinctrl-0 = <&led_enable>;
+			pinctrl-1 = <&led_disable>;
+		};
+
+		pmi8998_torch0: qcom,torch_0 {
+			label = "torch";
+			qcom,led-name = "led:torch_0";
+			qcom,max-current = <500>;
+			qcom,default-led-trigger =
+						"torch0_trigger";
+			qcom,id = <0>;
+			qcom,current-ma = <300>;
+			qcom,ires-ua = <12500>;
+			qcom,hdrm-voltage-mv = <325>;
+			qcom,hdrm-vol-hi-lo-win-mv = <100>;
+		};
+
+		pmi8998_torch1: qcom,torch_1 {
+			label = "torch";
+			qcom,led-name = "led:torch_1";
+			qcom,max-current = <500>;
+			qcom,default-led-trigger =
+						"torch1_trigger";
+			qcom,id = <1>;
+			qcom,current-ma = <300>;
+			qcom,ires-ua = <12500>;
+			qcom,hdrm-voltage-mv = <325>;
+			qcom,hdrm-vol-hi-lo-win-mv = <100>;
+		};
+
+		pmi8998_torch2: qcom,torch_2 {
+			label = "torch";
+			qcom,led-name = "led:torch_2";
+			qcom,max-current = <500>;
+			qcom,default-led-trigger =
+						"torch2_trigger";
+			qcom,id = <2>;
+			qcom,current-ma = <300>;
+			qcom,ires-ua = <12500>;
+			qcom,hdrm-voltage-mv = <325>;
+			qcom,hdrm-vol-hi-lo-win-mv = <100>;
+			pinctrl-names = "led_enable","led_disable";
+			pinctrl-0 = <&led_enable>;
+			pinctrl-1 = <&led_disable>;
+		};
+
+		pmi8998_switch0: qcom,led_switch_0 {
+			label = "switch";
+			qcom,led-name = "led:switch_0";
+			qcom,led-mask = <3>;
+			qcom,default-led-trigger =
+						"switch0_trigger";
+			qcom,symmetry-en;
+		};
+
+		pmi8998_switch1: qcom,led_switch_1 {
+			label = "switch";
+			qcom,led-name = "led:switch_1";
+			qcom,led-mask = <4>;
+			qcom,default-led-trigger =
+						"switch1_trigger";
+		};
+	};
+
diff --git a/bindings/pinctrl/qcom,pmic-gpio.txt b/bindings/pinctrl/qcom,pmic-gpio.txt
index a77827d4..1c6a7002 100755
--- a/bindings/pinctrl/qcom,pmic-gpio.txt
+++ b/bindings/pinctrl/qcom,pmic-gpio.txt
@@ -27,6 +27,7 @@ PMIC's from Qualcomm.
 		    "qcom,pm660l-gpio"
 		    "qcom,pm8150-gpio"
 		    "qcom,pm8150b-gpio"
+		    "qcom,pm8150l-gpio"
 		    "qcom,pm8350-gpio"
 		    "qcom,pm8350b-gpio"
 		    "qcom,pm8350c-gpio"
diff --git a/bindings/power/supply/qcom/qpnp-fg-gen4.txt b/bindings/power/supply/qcom/qpnp-fg-gen4.txt
new file mode 100755
index 00000000..8bdbf936
--- /dev/null
+++ b/bindings/power/supply/qcom/qpnp-fg-gen4.txt
@@ -0,0 +1,687 @@
+Qualcomm Technologies, Inc. PMIC Fuel Gauge Gen4 Device
+
+QTI PMIC FG Gen4 device provides interface to the clients to read properties
+related to the battery. Its main function is to retrieve the State of Charge
+(SOC), in percentage scale representing the amount of charge left in the
+battery.
+
+=======================
+Required Node Structure
+=======================
+
+FG Gen4 device must be described in two levels of device nodes.  The first
+level describes the FG Gen4 device.  The second level describes one or more
+peripherals managed by FG Gen4 driver. All the peripheral specific parameters
+such as base address, interrupts etc., should be under second level node.
+
+====================================
+First Level Node - FG Gen4 device
+====================================
+
+- compatible
+	Usage:      required
+	Value type: <string>
+	Definition: Should be "qcom,fg-gen4".
+
+- qcom,pmic-revid
+	Usage:      required
+	Value type: <phandle>
+	Definition: Should specify the phandle of PMIC revid module. This is
+		    used to identify the PMIC subtype.
+
+- qcom,pmic-pbs
+	Usage:      optional
+	Value type: <phandle>
+	Definition: Should specify the phandle of PMIC PBS module. This is
+		    used to trigger PBS for certain configurations.
+
+- #thermal-sensor-cells: Should be 0. See thermal.txt for the description.
+
+- nvmem-names:
+	Usage: optional
+	Value type: <string>
+	Definition: Nvmem device name for SDAM to store parameters like cycle
+		    counters and learned capacity. It must be defined as
+		    "fg_sdam".
+
+- nvmem:
+	Usage: optional
+	Value type: <phandle>
+	Definition: Phandle of the nvmem device name to access SDAM to store
+		    parameters.
+
+- io-channels
+- io-channel-names
+	Usage:      optional
+	Value type: <phandle>
+	Definition: Specified if battery id is obtained through ADC channel
+		    If specified, it should have a name "batt_id".
+		    For details about IIO bindings see:
+		    Documentation/devicetree/bindings/iio/iio-bindings.txt
+
+- qcom,batt-id-pullup-kohms
+	Usage:      optional
+	Value type: <u32>
+	Definition: Battery id pull up resistor value in KOhms. This needs to
+		    be specified if battery id is obtained through ADC channel.
+		    If not specified, a default value of 100 KOhms is used.
+
+- qcom,fg-cutoff-voltage
+	Usage:      optional
+	Value type: <u32>
+	Definition: The voltage (in mV) where the fuel gauge will steer the SOC
+		    to be zero. For example, if the cutoff voltage is set to
+		    3400mv, the fuel gauge will try to count SoC so that the
+		    battery SOC will be 0 when it is 3400 mV. If this property
+		    is not specified, then the default value used will be
+		    3000 mV.
+
+- qcom,fg-empty-voltage
+	Usage:      optional
+	Value type: <u32>
+	Definition: The voltage threshold (in mV) based on which the empty soc
+		    interrupt will be triggered. When the empty soc interrupt
+		    fires, battery soc will be set to 0 and the userspace will
+		    be notified via the power supply framework. The userspace
+		    will read 0% soc and immediately shutdown. If this property
+		    is not specified, then the default value used will be
+		    2812 mV.
+
+- qcom,fg-sys-min-voltage
+	Usage:      optional
+	Value type: <u32>
+	Definition: The voltage threshold (in mV) which describes the system
+		    minimum voltage as per the hardware recommendation. This
+		    is not used for any configuration but only for calculating
+		    the available power. If this property is not specified,
+		    then the default value used is 2800 mV.
+
+- qcom,fg-sys-term-current
+	Usage:      optional
+	Value type: <u32>
+	Definition: Battery current (in mA) at which the fuel gauge will try to
+		    scale towards 100%. When the charge current goes above this
+		    the SOC should be at 100%. If this property is not
+		    specified, then the default value used will be -125 mA.
+		    This value has to be specified in negative values for
+		    the charging current.
+
+- qcom,fg-cutoff-current
+	Usage:      optional
+	Value type: <u32>
+	Definition: Minimum Battery current (in mA) used for cutoff SOC
+		    estimate. If this property is not specified, then a default
+		    value of 200 mA will be applied.
+
+- qcom,fg-delta-soc-thr
+	Usage:      optional
+	Value type: <u32>
+	Definition: Percentage of SOC increase upon which the delta monotonic &
+		    battery SOC interrupts will be triggered. If this property
+		    is not specified, then the default value will be 5 (0.5 %).
+		    Unit is in deci-percentage. Possible values are in the range
+		    of 1 to 124.
+
+- qcom,fg-esr-timer-chg-fast
+	Usage:      optional
+	Value type: <prop-encoded-array>
+	Definition: Number of cycles between ESR pulses while the battery is
+		    charging for fast calibration. Array of 2 elements if
+		    specified.
+		    Element 0 - Retry value for timer
+		    Element 1 - Maximum value for timer
+
+- qcom,fg-esr-timer-dischg-fast
+	Usage:      optional
+	Value type: <prop-encoded-array>
+	Definition: Number of cycles between ESR pulses while the battery is
+		    discharging for fast calibration. Array of 2 elements if
+		    specified.
+		    Element 0 - Retry value for timer
+		    Element 1 - Maximum value for timer
+
+- qcom,fg-esr-timer-chg-slow
+	Usage:      optional
+	Value type: <prop-encoded-array>
+	Definition: Number of cycles between ESR pulses while the battery is
+		    charging for default calibration. Array of 2 elements if
+		    specified.
+		    Element 0 - Retry value for timer
+		    Element 1 - Maximum value for timer
+
+- qcom,fg-esr-timer-dischg-slow
+	Usage:      optional
+	Value type: <prop-encoded-array>
+	Definition: Number of cycles between ESR pulses while the battery is
+		    discharging for default calibration. Array of 2 elements if
+		    specified.
+		    Element 0 - Retry value for timer
+		    Element 1 - Maximum value for timer
+
+- qcom,fg-esr-cal-soc-thresh
+	Usage:      optional
+	Value type: <prop-encoded-array>
+	Definition: SOC thresholds applied when ESR fast calibration is done.
+		    Array of 2 elements if specified. This should be specified
+		    if ESR fast calibration algorithm is needed.
+		    Element 0 - Minimum SOC threshold in percentage
+		    Element 1 - Maximum SOC threshold in percentage
+
+- qcom,fg-esr-cal-temp-thresh
+	Usage:      optional
+	Value type: <prop-encoded-array>
+	Definition: Battery temperature thresholds applied when ESR fast
+		    calibration is done. Array of 2 elements if specified.
+		    This should be specified if ESR fast calibration algorithm
+		    is needed.
+		    Element 0 - Minimum temperature threshold in Celsius
+		    Element 1 - Maximum temperature threshold in Celsius
+
+- qcom,fg-delta-esr-disable-count
+	Usage:      optional
+	Value type: <u32>
+	Definition: Value after which delta ESR interrupt will be disabled.
+		    This is applicable only when ESR fast calibration is
+		    enabled. Default value is 10.
+
+- qcom,fg-delta-esr-thr
+	Usage:      optional
+	Value type: <u32>
+	Definition: Threshold for delta ESR interrupt in uOhms. Default value
+		    is 1832. If ESR fast calibration algorithm is enabled, this
+		    will be overridden with a maximum value.
+
+- qcom,fg-esr-filter-factor
+	Usage:      optional
+	Value type: <u32>
+	Definition: ESR filter factor used in ESR fast calibration algorithm.
+		    This factor will be used when ESR correction delta is
+		    applied after the calculation. Default value is 2.
+
+- qcom,fg-esr-calib-dischg:
+	Usage:      optional
+	Value type: <empty>
+	Definition: Enables ESR calibration only during discharging. This
+		    should be specified only when ESR fast calibration is not
+		    required. Also, ESR discharging timers should be specified
+		    for the proper functionality.
+
+- qcom,fg-esr-pulse-thresh-ma
+	Usage:      optional
+	Value type: <u32>
+	Definition: ESR pulse qualification threshold in mA. If this is not
+		    specified, a default value of 110 mA will be configured.
+		    Allowed values are from 1 to 1000.
+
+- qcom,fg-esr-meas-curr-ma
+	Usage:      optional
+	Value type: <u32>
+	Definition: ESR measurement current in mA. If this is not specified,
+		    a default value of 120 mA will be configured. Allowed
+		    values are 60, 120, 180 and 240.
+
+- qcom,fg-batt-temp-delta
+	Usage:      optional
+	Value type: <u32>
+	Definition: Battery temperature delta interrupt threshold. Possible
+		    values are: 0, 1, 2 and 3. Unit is in Kelvin or Celsius.
+
+- qcom,fg-batt-temp-cold-thresh
+	Usage:      optional
+	Value type: <u32>
+	Definition: Battery temperature cold interrupt threshold. Allowed
+		    values are from -128 to 127. Unit is in Kelvin or Celsius.
+
+- qcom,fg-batt-temp-hot-thresh
+	Usage:      optional
+	Value type: <u32>
+	Definition: Battery temperature hot interrupt threshold. Allowed
+		    values are from -128 to 127. Unit is in Kelvin or Celsius.
+
+- qcom,fg-batt-temp-hyst
+	Usage:      optional
+	Value type: <u32>
+	Definition: Battery temperature hysteresis threshold. Possible values
+		    are: 0, 1, 2 and 3. Unit is in Kelvin or Celsius.
+
+- qcom,fg-batt-therm-freq
+	Usage:      optional
+	Value type: <u32>
+	Definition: Battery thermistor interval in seconds. Possible values
+		    are from 1-255. If not specified, then the default value
+		    configured is 8.
+
+- qcom,fg-force-load-profile
+	Usage:      optional
+	Value type: <empty>
+	Definition: If set, battery profile will be force loaded if the profile
+		    loaded earlier by bootloader doesn't match with the profile
+		    available in the device tree.
+
+- qcom,cl-start-capacity
+	Usage:      optional
+	Value type: <u32>
+	Definition: Battery SOC threshold to start the capacity learning.
+		    If this is not specified, then the default value used
+		    will be 15. Unit is in percentage.
+
+- qcom,cl-min-temp
+	Usage:      optional
+	Value type: <u32>
+	Definition: Lower limit of battery temperature to start the capacity
+		    learning. If this is not specified, then the default value
+		    used will be 150 (15 C). Unit is in decidegC.
+
+- qcom,cl-max-temp
+	Usage:      optional
+	Value type: <u32>
+	Definition: Upper limit of battery temperature to start the capacity
+		    learning. If this is not specified, then the default value
+		    used will be 500 (50 C). Unit is in decidegC.
+
+- qcom,cl-max-increment
+	Usage:      optional
+	Value type: <u32>
+	Definition: Maximum capacity increment allowed per capacity learning
+		    cycle. If this is not specified, then the default value
+		    used will be 5 (0.5%). Unit is in decipercentage.
+
+- qcom,cl-max-decrement
+	Usage:      optional
+	Value type: <u32>
+	Definition: Maximum capacity decrement allowed per capacity learning
+		    cycle. If this is not specified, then the default value
+		    used will be 100 (10%). Unit is in decipercentage.
+
+- qcom,cl-min-limit
+	Usage:      optional
+	Value type: <u32>
+	Definition: Minimum limit that the capacity cannot go below in a
+		    capacity learning cycle. If this is not specified, then
+		    the default value is 0. Unit is in decipercentage.
+
+- qcom,cl-max-limit
+	Usage:      optional
+	Value type: <u32>
+	Definition: Maximum limit that the capacity cannot go above in a
+		    capacity learning cycle. If this is not specified, then
+		    the default value is 0. Unit is in decipercentage.
+
+- qcom,cl-min-delta-batt-soc
+	Usage:      optional
+	Value type: <u32>
+	Definition: Minimum change in battery SOC to qualify for capacity
+		    learning. If this is not specified, then the default
+		    value is 10. Unit is in percentage.
+
+- qcom,cl-wt-enable
+	Usage:      optional
+	Value type: <empty>
+	Definition: A boolean property to enable weighted capacity learning
+		    based on change in battery SOC during a charging cycle.
+		    If this is specified "qcom,cl-start-capacity" is not used.
+
+- qcom,cl-skew
+	Usage:      optional
+	Value type: <u32>
+	Definition: Skew in decipercentage which when specified will be applied
+		    to the final learned capacity.
+
+- qcom,cl-ibat-flt-thresh-ma
+	Usage:      optional
+	Value type: <u32>
+	Definition: Filtered battery current to qualify the capacity learning
+		    algorithm to begin. If this is not specified, then the
+		    default value is 100 mA.
+
+- qcom,hold-soc-while-full
+	Usage:      optional
+	Value type: <empty>
+	Definition: A boolean property that when defined holds SOC at 100% when
+		    the battery is full.
+
+- qcom,linearize-soc
+	Usage:      optional
+	Value type: <empty>
+	Definition: A boolean property that when defined linearizes SOC when
+		    the SOC drops after charge termination monotonically to
+		    improve the user experience. This is applicable only if
+		    "qcom,hold-soc-while-full" is specified.
+
+- qcom,ki-coeff-soc-dischg
+	Usage:      optional
+	Value type: <prop-encoded-array>
+	Definition: Array of monotonic SOC threshold values to change the ki
+		    coefficient for medium discharge current during discharge.
+		    This should be defined in the ascending order and in the
+		    range of 0-100. Array limit is set to 3.
+
+- qcom,ki-coeff-low-dischg
+	Usage:      optional
+	Value type: <prop-encoded-array>
+	Definition: Array of ki coefficient values for low discharge current
+		    during discharge. These values will be applied when the
+		    monotonic SOC goes below the SOC threshold specified under
+		    qcom,ki-coeff-soc-dischg. Array limit is set to 3. This
+		    property should be specified if qcom,ki-coeff-soc-dischg
+		    is specified to make it fully functional. Value has no
+		    unit. Allowed range is 0 to 15564 in micro units. If this
+		    is not specified, the default value used will be 367.
+
+- qcom,ki-coeff-med-dischg
+	Usage:      optional
+	Value type: <prop-encoded-array>
+	Definition: Array of ki coefficient values for medium discharge current
+		    during discharge. These values will be applied when the
+		    monotonic SOC goes below the SOC threshold specified under
+		    qcom,ki-coeff-soc-dischg. Array limit is set to 3. This
+		    property should be specified if qcom,ki-coeff-soc-dischg
+		    is specified to make it fully functional. Value has no
+		    unit. Allowed range is 0 to 15564 in micro units. If this
+		    is not specified, the default value used will be 62.
+
+- qcom,ki-coeff-hi-dischg
+	Usage:      optional
+	Value type: <prop-encoded-array>
+	Definition: Array of ki coefficient values for high discharge current
+		    during discharge. These values will be applied when the
+		    monotonic SOC goes below the SOC threshold specified under
+		    qcom,ki-coeff-soc-dischg. Array limit is set to 3. This
+		    property should be specified if qcom,ki-coeff-soc-dischg
+		    is specified to make it fully functional. Value has no
+		    unit. Allowed range is 0 to 15564 in micro units. If this
+		    is not specified, the default value used will be 0.
+
+- qcom,ki-coeff-dischg-low-med-thresh-ma
+	Usage:      optional
+	Value type: <u32>
+	Definition: Threshold value of discharging current that decides which ki
+		    coefficient will be applied: qcom,ki-coeff-low-dischg if the
+		    threshold is not breached, and qcom,ki-coeff-med-dischg
+		    otherwise. Allowed range is 0 to 3984 milliamperes. If this
+		    is not specified, the default value used will be 50 (50 mA).
+
+- qcom,ki-coeff-dischg-med-hi-thresh-ma
+	Usage:      optional
+	Value type: <u32>
+	Definition: Threshold value of discharging current that decides which ki
+		    coefficient will be applied: qcom,ki-coeff-med-dischg if the
+		    threshold is not breached, and qcom,ki-coeff-hi-dischg
+		    otherwise. Allowed range is 0 to 3984 milliamperes. If this
+		    is not specified, the default value used will be 100
+		    (100 mA).
+
+- qcom,ki-coeff-low-chg
+	Usage:      optional
+	Value type: <u32>
+	Definition: ki coefficient value for low charge current during
+		    charging. Value has no unit. Allowed range is 0 to 15564
+		    in micro units. If this is not specified, the default value
+		    used will be 184.
+
+- qcom,ki-coeff-med-chg
+	Usage:      optional
+	Value type: <u32>
+	Definition: ki coefficient value for medium charge current during
+		    charging. Value has no unit. Allowed range is 0 to 15564
+		    in micro units. If this is not specified, the default value
+		    used will be 62.
+
+- qcom,ki-coeff-hi-chg
+	Usage:      optional
+	Value type: <u32>
+	Definition: ki coefficient value for high charge current during
+		    charging. Value has no unit. Allowed range is 0 to 15564
+		    in micro units. If this is not specified, the default value
+		    used will be 0.
+
+- qcom,ki-coeff-chg-low-med-thresh-ma
+	Usage:      optional
+	Value type: <u32>
+	Definition: Threshold value of charging current that decides which ki
+		    coefficient will be applied: qcom,ki-coeff-low-chg if the
+		    threshold is not breached, and qcom,ki-coeff-med-chg
+		    otherwise. Allowed range is 0 to 3984 milliamperes. If this
+		    is not specified, the default value used will be 500
+		    (500 mA).
+
+- qcom,ki-coeff-chg-med-hi-thresh-ma
+	Usage:      optional
+	Value type: <u32>
+	Definition: Threshold value of charging current that decides which ki
+		    coefficient will be applied: qcom,ki-coeff-med-chg if the
+		    threshold is not breached, and qcom,ki-coeff-hi-chg
+		    otherwise. Allowed range is 0 to 3984 milliamperes. If this
+		    is not specified, the default value used will be 1000
+		    (1000 mA).
+
+- qcom,ki-coeff-cutoff
+	Usage:      optional
+	Value type: <u32>
+	Definition: ki coefficient value for cutoff integration gain. Value has
+		    no unit. Allowed range is 62 to 15564 in micro units.
+
+- qcom,ki-coeff-full-dischg
+	Usage:      optional
+	Value type: <prop-encoded-array>
+	Definition: Array of Ki coefficient full SOC values that needs to be
+		    applied during discharging. If not specified, a value of
+		    0 will be set.
+		    Allowed range is from 62 to 15564.
+		    Element 0 - Ki coefficient for full SOC in room temperature
+		    Element 1 - Ki coefficient for full SOC in low temperature
+
+- qcom,fg-rconn-uohms
+	Usage:      optional
+	Value type: <u32>
+	Definition: Battery connector resistance (Rconn) in microohms. If it's
+		    already configured in bootloader, then it will not be
+		    configured again by GEN4 FG driver.
+
+- qcom,slope-limit-temp-threshold
+	Usage:      optional
+	Value type: <u32>
+	Definition: Battery temperature threshold to decide when slope limit
+		    coefficients should be applied along with charging status.
+		    Unit is in decidegC.
+
+- qcom,slope-limit-coeffs
+	Usage:      optional
+	Value type: <prop-encoded-array>
+	Definition: A list of integers which holds the slope limit coefficients
+		    in the following order. Allowed size is 4. Possible values
+		    are from 123 to 31128. Unit is in micro-percentage.
+		    Element 0 - Low temperature discharging
+		    Element 1 - Low temperature charging
+		    Element 2 - High temperature discharging
+		    Element 3 - High temperature charging
+		    These coefficients have to be specified along with the
+		    property "qcom,slope-limit-temp-threshold" to make dynamic
+		    slope limit adjustment functional.
+
+- qcom,rapid-soc-dec-en
+	Usage:      optional
+	Value type: <empty>
+	Definition: A boolean property that when defined enables rapid SOC
+		    decrease when the battery SOC is low but not converging to
+		    zero with battery voltage dropping rapidly below Vcutoff.
+
+- qcom,five-pin-battery
+	Usage:      optional
+	Value type: <empty>
+	Definition: A boolean property that when specified indicates that a
+		    five pin battery is used. Based on this, time to full
+		    calculations would use the Rbatt calculated properly.
+
+- qcom,multi-profile-load
+	Usage:      optional
+	Value type: <empty>
+	Definition: A boolean property that when specified indicates that
+		    multiple profile loading needs to be enabled. This requires
+		    multiple battery profiles to be specified for a battery for
+		    proper functionality.
+
+- qcom,soc-hi-res
+	Usage:      optional
+	Value type: <empty>
+	Definition: A boolean property that when specified shows high
+		    resolution of monotonic SOC under CAPACITY_RAW property
+		    during charging in the scale of 0-10000.
+
+- qcom,soc-scale-mode-en
+	Usage:      optional
+	Value type: <boolean>
+	Definition: A boolean property that when specified will enable scaling
+		    of the SOC linearly, based on the filtered battery voltage
+		    after crossing below a Vbatt threshold.
+
+- qcom,soc-scale-vbatt-mv
+	Usage:      optional
+	Value type: <u32>
+	Definition: Threshold voltage to decide when SOC should
+		    be scaled based on filtered voltage when
+		    qcom,soc-scale-mode-en is specified. If this
+		    is not specified, then the default value is 3400.
+		    Unit is in mV.
+
+- qcom,soc-scale-time-ms
+	Usage:      optional
+	Value type: <u32>
+	Definition: Timer value for doing SOC calculation based on
+		    filtered voltage when qcom,soc-scale-mode-en is
+		    specified. If this is not specified, then the
+		    default value is 10000. Unit is in ms.
+
+- qcom,force-calib-level
+	Usage:      optional
+	Value type: <u32>
+	Definition: Calibration level in decimal. When specified,
+		    the calibration level is forced to this value.
+		    Possible values are in the range of 1 to 130.
+
+==========================================================
+Second Level Nodes - Peripherals managed by FG Gen4 driver
+==========================================================
+- reg
+	Usage:      required
+	Value type: <prop-encoded-array>
+	Definition: Addresses and sizes for the specified peripheral
+
+- interrupts
+	Usage:      optional
+	Value type: <prop-encoded-array>
+	Definition: Interrupt mapping as per the interrupt encoding
+
+- interrupt-names
+	Usage:      optional
+	Value type: <stringlist>
+	Definition: Interrupt names.  This list must match up 1-to-1 with the
+		    interrupts specified in the 'interrupts' property.
+
+========
+Example
+========
+
+pm8150b_fg: qpnp,fg {
+	compatible = "qcom,fg-gen4";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	qcom,pmic-revid = <&pm8150b_revid>;
+	nvmem-names = "fg_sdam";
+	nvmem = <&pm8150_sdam_2>;
+	io-channels = <&pm8150b_vadc ADC_BAT_ID_PU2>;
+	io-channel-names = "batt_id";
+	#thermal-sensor-cells = <0>;
+	status = "okay";
+
+	qcom,fg-batt-soc@4000 {
+		status = "okay";
+		reg = <0x4000 0x100>;
+		interrupts = <0x2 0x40 0x0 IRQ_TYPE_EDGE_BOTH>,
+			     <0x2 0x40 0x1 IRQ_TYPE_EDGE_BOTH>,
+			     <0x2 0x40 0x2 IRQ_TYPE_EDGE_RISING>,
+			     <0x2 0x40 0x3 IRQ_TYPE_EDGE_RISING>,
+			     <0x2 0x40 0x4 IRQ_TYPE_EDGE_BOTH>,
+			     <0x2 0x40 0x5 IRQ_TYPE_EDGE_RISING>,
+			     <0x2 0x40 0x6 IRQ_TYPE_EDGE_BOTH>,
+			     <0x2 0x40 0x7 IRQ_TYPE_EDGE_BOTH>;
+		interrupt-names = "soc-update",
+				  "soc-ready",
+				  "bsoc-delta",
+				  "msoc-delta",
+				  "msoc-low",
+				  "msoc-empty",
+				  "msoc-high",
+				  "msoc-full";
+
+	};
+
+	qcom,fg-batt-info@4100 {
+		status = "okay";
+		reg = <0x4100 0x100>;
+		interrupts = <0x2 0x41 0x0 IRQ_TYPE_EDGE_BOTH>,
+			     <0x2 0x41 0x1 IRQ_TYPE_EDGE_BOTH>,
+			     <0x2 0x41 0x3 IRQ_TYPE_EDGE_BOTH>;
+		interrupt-names = "vbatt-low",
+				  "vbatt-pred-delta",
+				  "esr-delta";
+	};
+
+	qcom,adc-rr@4200 {
+		status = "okay";
+		reg = <0x4200 0x100>;
+		interrupts = <0x2 0x42 0x0 IRQ_TYPE_EDGE_BOTH>,
+			     <0x2 0x42 0x1 IRQ_TYPE_EDGE_BOTH>,
+			     <0x2 0x42 0x2 IRQ_TYPE_EDGE_BOTH>,
+			     <0x2 0x42 0x3 IRQ_TYPE_EDGE_BOTH>,
+			     <0x2 0x42 0x4 IRQ_TYPE_EDGE_BOTH>;
+		interrupt-names = "batt-missing",
+				  "batt-id",
+				  "batt-temp-delta",
+				  "batt-temp-hot",
+				  "batt-temp-cold";
+	};
+
+	qcom,fg-memif@4300 {
+		status = "okay";
+		reg = <0x4300 0x100>;
+		interrupts = <0x2 0x43 0x0 IRQ_TYPE_EDGE_BOTH>,
+			     <0x2 0x43 0x1 IRQ_TYPE_EDGE_BOTH>,
+			     <0x2 0x43 0x2 IRQ_TYPE_EDGE_BOTH>,
+			     <0x2 0x43 0x3 IRQ_TYPE_EDGE_BOTH>,
+		interrupt-names = "ima-rdy",
+				  "ima-xcp",
+				  "dma-xcp",
+				  "dma-grant",
+	};
+
+};
+
+======================================
+Example for thermal zone configuration
+======================================
+
+thermal_zones {
+	pm8150b_fg {
+		polling-delay-passive = <200>;
+		polling-delay = <200>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm8150b_fg>;
+
+		pm8150b_fg_trip1: pm8150b-fg-trip1 {
+			temperature = <40000>;
+			hysteresis = <0>;
+			type = "passive";
+		};
+		pm8150b_fg_trip2: pm8150b-fg-trip2 {
+			temperature = <45000>;
+			hysteresis = <0>;
+			type = "passive";
+		};
+		pm8150b_fg_trip3: pm8150b-fg-trip3 {
+			temperature = <55000>;
+			hysteresis = <0>;
+			type = "passive";
+		};
+	};
+};
diff --git a/bindings/regulator/qpnp-lcdb-regulator.txt b/bindings/regulator/qpnp-lcdb-regulator.txt
new file mode 100755
index 00000000..7fc3df91
--- /dev/null
+++ b/bindings/regulator/qpnp-lcdb-regulator.txt
@@ -0,0 +1,329 @@
+QPNP LCDB (LCD Bias) Regulator
+
+QPNP LCDB module provides voltage bias to the LCD display panel. The biases
+are positive (VDISP - supported by LDO) and negative (VDISN - supported by
+NCP) voltage signals. The module also supports TTW (touch-to-wake) capability.
+
+This document describes the bindings for QPNP LCDB module.
+
+=======================
+Required Node Structure
+=======================
+
+LCDB module must be described in two level of device nodes.
+
+==============================
+First Level Node - LCDB module
+==============================
+
+- compatible
+	Usage:      required
+	Value type: <string>
+	Definition: must be one of:
+			"qcom,qpnp-lcdb-regulator"
+			"qcom,lcdb-pm660"
+			"qcom,lcdb-pmi632"
+			"qcom,lcdb-pm6150l"
+			"qcom,lcdb-pm7325b"
+
+- reg
+	Usage:      required
+	Value type: <prop-encoded-array>
+	Definition:  Base address of the LCDB SPMI peripheral.
+
+- qcom,voltage-step-ramp
+	Usage:      optional
+	Value type: <bool>
+	Definition:  Required only if the voltage needs to be set in the
+		     steps of 500 mV starting from the 4500 mV. This needs
+		     to be enabled only on platforms where voltage needs to
+		     be ramped up with multiple steps.
+
+- qcom,ncp-symmetry
+	Usage:      optional
+	Value type: <bool>
+	Definition:  Enabling this will make NCP voltage follow LDO voltage
+		     directly.
+
+- qcom,pwrdn-delay-ms
+	Usage:      optional
+	Value type: <u32>
+	Definition:  Required to control the LDO power down delay.
+		     Possible values are 0, 1, 4, 8.
+
+- qcom,pwrup-delay-ms
+	Usage:      optional
+	Value type: <u32>
+	Definition:  Required to control the LDO power up delay.
+		     Possible values are 0, 1, 4, 8.
+
+- qcom,pwrup-config
+	Usage:      optional
+	Value type: <u32>
+	Definition:  Controls the order of powering up BOOST, LDO AND NCP
+		     blocks. Applicable for PM7325B. Possible values are: 0, 1, 2, 3, 4.
+		     0 - Boost, LDO, NCP
+		     1 - Boost, LDO
+		     2 - Boost, NCP
+		     3 - Boost only
+		     4 - Boost, NCP, LDO
+
+- qcom,high-p2-blank-time-ns
+	Usage:      optional
+	Value type: <u32>
+	Definition:  Controls the higher clamp threshold for p2 minimum on time.
+		     Applicable for PM7325B. Possible values are 40, 69, 99, 129, 159,
+		     189, 220, 250.
+
+- qcom,low-p2-blank-time-ns
+	Usage:      optional
+	Value type: <u32>
+	Definition:  Controls the lower clamp threshold for p2 minimum on time.
+		     Applicable for PM7325B. Possible values are 40, 69, 99, 129, 159,
+		     189, 220, 250.
+
+- qcom,mpc-current-thr-ma
+	Usage:      optional
+	Value type: <u32>
+	Definition:  Controls the mpc threshold for inductor current after start up
+		     is done. Applicable for PM7325B. Possible values are 160, 200, 240,
+		     280, 320, 360, 400, 440.
+
+Touch-to-wake (TTW) properties:
+
+TTW supports 2 modes of operation - HW and SW. In the HW mode the enable/disable
+logic is controlled by an external signal (pin) where as in the SW mode it is
+is controlled by a pre-configured timer (ton/toff) programmed in the TTW
+register.
+
+Properties below are specific to TTW mode only. They are sepecified in the
+main node.
+
+- qcom,ttw-enable
+	Usage:      optional
+	Value type:  <bool>
+	Definition: Touch to wake-up support enabled.
+
+- qcom,ttw-mode-sw
+	Usage:      optional
+	Value type:  <bool>
+	Definition: Touch to wake supported in SW mode.
+		    If not defined, ttw is enabled by HW pin.
+
+- qcom,attw-toff-ms
+	Usage:      required if 'qcom,ttw-mode-sw' is true.
+	Value type:  <bool>
+	Definition: Off time (in mS) for the VDISP/VDISN signals.
+		    Possible values are 4, 8, 16, 32.
+
+- qcom,attw-ton-ms
+	Usage:      required if 'qcom,ttw-mode-sw' is true.
+	Value type:  <bool>
+	Definition: ON time (in mS) for the VDISP/VDISN signals.
+		    Possible values are 4, 8, 16, 32.
+
+========================================
+Second Level Nodes - LDO/NCP/BOOST block
+========================================
+
+LDO / NCP subnode common properties:
+
+Properties below are common to the LDO and NCP bias.
+
+- label
+	Usage:      required
+	Value type: <string>
+	Definition: A string used to describe the bias type.
+		    Possible values are ldo, ncp, bst.
+
+- regulator-name
+	Usage:      required
+	Value type: <string>
+	Definition: A string used to describe the regulator.
+
+- regulator-min-microvolt
+	Usage:      required
+	Value type: <u32>
+	Definition: Minimum voltage (in uV) supported by the bias.
+
+- regulator-max-microvolt
+	Usage:      required
+	Value type: <u32>
+	Definition: Maximum voltage (in uV) supported by the bias.
+
+
+LDO subnode properties:
+
+Properties below are specific to LDO bias only.
+
+- qcom,ldo-voltage-mv
+	Usage:      optional
+	Value type:  <u32>
+	Definition: Voltage (in mV) progammed for the LDO (VDISP).
+		    Possile values are 4000mV to 6000mV. The range
+		    4000mV to 4900mV is in 100mV steps and 4900mV to
+		    6000mV is in 50mV steps.
+
+- qcom,ldo-pd
+	Usage:      optional
+	Value type:  <u32>
+	Definition: Pull-down configuration of LDO. Possible values are:
+		    1 - Enable pull-down
+		    0 - Disable pull-down
+
+- qcom,ldo-pd-strength
+	Usage:      optional
+	Value type:  <u32>
+	Definition: Pull-down strength. Possible values are:
+		    0 - Weak pull-down
+		    1 - Strong pull-down
+
+- qcom,ldo-ilim-ma
+	Usage:      optional
+	Value type:  <u32>
+	Definition:  Current limit (in mA) of the LDO bias. For PM7325B, possible
+		     values are 35, 175, 280, 420, 455, 595, 700, 840. For other PMICs,
+		     possible values are 110, 160, 210, 260, 310, 360, 410, 460.
+
+- qcom,ldo-soft-start-us
+	Usage:      optional
+	Value type:  <u32>
+	Definition:  Soft-start time (in uS) of the LDO bias.
+		     Possible values are 0, 500, 1000, 2000.
+
+NCP subnode properties:
+
+Properties below are specific to NCP bias only.
+
+- qcom,ncp-voltage-mv
+	Usage:      optional
+	Value type:  <u32>
+	Definition: Voltage (in mV) progammed for the NCP (VDISN).
+		    Possile values are 4000mV to 6000mV. The range
+		    4000mV to 4900mV is in 100mV steps and 4900mV to
+		    6000mV is in 50mV steps.
+
+- qcom,ncp-pd
+	Usage:      optional
+	Value type:  <u32>
+	Definition: Pull-down configuration of NCP. Possible values are:
+		    1 - Enable pull-down
+		    0 - Disable pull-down
+
+- qcom,ncp-pd-strength
+	Usage:      optional
+	Value type:  <u32>
+	Definition: Pull-down strength. Possible values are:
+		    0 - Weak pull-down
+		    1 - Strong pull-down
+
+- qcom,ncp-ilim-ma
+	Usage:      optional
+	Value type:  <u32>
+	Definition:  Current limit (in mA) of the NCP bias. For PM7325B, possible
+		     values are 700, 80, 900, 1000. For other PMICs, possible values
+		     are 260, 460, 640, 810.
+
+- qcom,ncp-soft-start-us
+	Usage:      optional
+	Value type:  <u32>
+	Definition:  Soft-start time (in uS) of the NCP bias.
+		     Possible values are 0, 500, 1000, 2000.
+
+
+BOOST subnode properties:
+
+Properties below are specific to BOOST subnode only.
+
+- qcom,bst-pd
+	Usage:      optional
+	Value type:  <bool>
+	Definition: Pull-down configuration of BOOST. Possible values are:
+		    1 - Enable pull-down
+		    0 - Disable pull-down
+
+- qcom,bst-pd-strength
+	Usage:      optional
+	Value type:  <u32>
+	Definition: Pull-down strength. Possible values are:
+		    0 - Weak pull-down
+		    1 - Strong pull-down
+
+- qcom,bst-ps
+	Usage:      optional
+	Value type:  <u32>
+	Definition: Pulse-skip configuration for boost. Possible values are:
+		    1 - Enable Pulse-skip
+		    0 - Disable Pulse-skip
+
+- qcom,bst-ps-threshold-ma
+	Usage:      optional
+	Value type:  <u32>
+	Definition: Current threshold (in mA) at which pulse-skip is entered.
+		    Possible values are 50, 60, 70, 80.
+
+- qcom,bst-ps-threshold-mv
+	Usage:      optional
+	Value type:  <u32>
+	Definition: Current threshold (in mv) at which pulse-skip is entered.
+		    Applicable for PM7325B. Possible values are 360, 384, 408, 432,
+		    456, 480, 504, 528.
+
+- qcom,bst-ilim-ma
+	Usage:      optional
+	Value type:  <u32>
+	Definition:  Current limit (in mA) of the BOOST rail. For PM7325B, possible
+		     possible values are 1130 to 2250mA in 160mA steps. For other PMICs,
+		     possible values are 200 to 1600mA in 200mA steps.
+
+- qcom,bst-headroom-mv
+	Usage:      optional
+	Value type:  <u16>
+	Definition:  Headroom of the boost (in mV). If not specified, then the
+		     default value is 200 mV (PM660L) or 150 mV (for PM8150L or
+		     PMI632).
+
+=======
+Example
+=======
+
+pm660l_lcdb: qpnp-lcdb@ec00 {
+	compatible = "qcom,qpnp-lcdb-regulator";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	reg = <0xec00 0x100>;
+
+	qcom,ttw-enable;
+
+	lcdb_ldo_vreg: ldo {
+		label = "ldo";
+		regulator-name = "lcdb_ldo";
+		regulator-min-microvolt = <4000000>;
+		regulator-max-microvolt = <6000000>;
+
+		qcom,ldo-voltage-mv = <5400>;
+		qcom,ldo-pd = <1>;
+		qcom,ldo-pd-strength = <1>;
+	};
+
+	lcdb_ncp_vreg: ncp {
+		label = "ncp";
+		regulator-name = "lcdb_ncp";
+		regulator-min-microvolt = <4000000>;
+		regulator-max-microvolt = <6000000>;
+
+		qcom,ncp-voltage-mv = <5400>;
+		qcom,ncp-pd = <1>;
+		qcom,ncp-pd-strength = <1>;
+	};
+
+	lcdb_bst: bst {
+		label = "bst";
+
+		qcom,bst-pd = <1>;
+		qcom,bst-pd-strength = <1>;
+		qcom,bst-ps = <1>;
+		qcom,bst-ps-threshold-ma = <50>;
+		qcom,bst-headroom-mv = <200>;
+	};
+};
diff --git a/bindings/sound/qcom,wcd_codec.txt b/bindings/sound/qcom,wcd_codec.txt
new file mode 100755
index 00000000..87202683
--- /dev/null
+++ b/bindings/sound/qcom,wcd_codec.txt
@@ -0,0 +1,65 @@
+Qualcomm Technologies, Inc. WCD audio CODEC
+
+PM5100 SPMI node
+
+pm5100_spmi: Child node of SPMI bus required for besbev codec
+	     in order to access SPMI register to reset the peripheral.
+
+Required properties:
+ -compatible: "qcom,pm5100-spmi";
+
+&spmi_bus {
+	pm5100_cdc: qcom,pm5100-cdc {
+	compatible = "qcom,pm5100-spmi";
+	};
+};
+
+Besbev Codec
+
+Required properties:
+ - compatible: "qcom,besbev-codec";
+ - qcom,split-codec: Property to check on split codec support.
+ - qcom,swr_ch_map: mapping of swr tx/rx slave port configuration to port_type and also
+		corresponding master port type it need to attach.
+		format: <port_id, slave_port_type, ch_mask, ch_rate, master_port_type>
+		same port_id configurations have to be grouped, and in ascending order.
+ - qcom,pmic-spmi-node: Phandle reference to the PMIC SPMI DT node.
+ - qcom,wcd-reset-reg: Reset register address in PMIC for rouleur codec.
+ - qcom,besbev-slave: phandle reference of Soundwire Tx/Rx slave device.
+ - qcom,speaker-present: Property to check besbev is connected RX SWR or TX SWR of bolero codec.
+
+Optional properties:
+
+ - cdc-mic-bias-supply: phandle of mic bias supply's regulator device tree node.
+ - qcom,cdc-mic-bias-voltage: mic bias supply's voltage level min and max in mV.
+ - qcom,cdc-mic-bias-current: mic bias supply's max current in mA.
+
+ - qcom,cdc-mic-bias-lpm-supported: mic bias supply's LPM mode.
+
+ - qcom,cdc-static-supplies: List of supplies to be enabled prior to codec
+			     hardware probe.  Supplies in this list will be
+			     stay enabled.
+
+Example:
+
+besbev_codec: besbev-codec {
+	compatible = "qcom,besbev-codec";
+	qcom,split-codec = <1>;
+	qcom,pmic-spmi-node = <&pm2250_cdc>;
+	qcom,wcd-reset-reg = <0x0000FCDB>;
+	qcom,foundry-id-reg = <0x0000704D>;
+	qcom,swr_ch_map = <0 SPKR_L 0x1 0 LO>,
+			<3 SPKR_L_VI 0x3 0 PCM_IN>;
+
+	qcom,besbev-slave = <&besbev_rx_slave>;
+	qcom,speaker-present = <1>;
+
+	cdc-mic-bias-supply = <&L28A>;
+	qcom,cdc-mic-bias-voltage = <2904000 2904000>;
+	qcom,cdc-mic-bias-current = <1180>
+
+	qcom,cdc-micbias1-mv = <1800>;
+	qcom,cdc-micbias2-mv = <1800>;
+
+	qcom,cdc-static-supplies = "cdc-mic-bias";
+};
diff --git a/bindings/spi/qcom,spi-msm-geni.txt b/bindings/spi/qcom,spi-msm-geni.txt
index 26145749..185f4816 100755
--- a/bindings/spi/qcom,spi-msm-geni.txt
+++ b/bindings/spi/qcom,spi-msm-geni.txt
@@ -36,7 +36,10 @@ Optional properties:
 - qcom,shared_se: 	Specifies that this serial engine is shared simultaneously
 			between execution environments. A true multi-EE usecase.
 - qcom,le_vm:		Specifies that this serial engine is operating in a trusted VM.
-
+- qcom,xfer-timeout-offset: Adds extra timeout offset on top driver calculated timeout.
+			    Depending on the use case and system latencies, the client can
+			    configure this.
+			    Unit - ms.
 
 SPI slave nodes must be children of the SPI master node and can contain
 the following properties.
diff --git a/bindings/thermal/qti-isense-cdsp.txt b/bindings/thermal/qti-isense-cdsp.txt
new file mode 100755
index 00000000..587c0392
--- /dev/null
+++ b/bindings/thermal/qti-isense-cdsp.txt
@@ -0,0 +1,14 @@
+===============================================================================
+QTI Limits cdsp isense driver:
+===============================================================================
+Limits cdsp isense driver reads cdsp isense calibration data from shared memory
+and enables sysfs file support to access the data read from shared memory.
+
+Required Parameters:
+- compatible: must be 'qcom,msm-limits-cdsp' for limits cdsp isense driver.
+
+Optional Parameters:
+
+		lmh_isense_cdsp {
+			compatible = "qcom,msm-limits-cdsp";
+		};
diff --git a/bindings/thermal/qti-qmi-cdev.txt b/bindings/thermal/qti-qmi-cdev.txt
index 94468708..a3e5b1d8 100755
--- a/bindings/thermal/qti-qmi-cdev.txt
+++ b/bindings/thermal/qti-qmi-cdev.txt
@@ -111,7 +111,9 @@ Subsystem properties:
 			"mmw1_sub1_dsc" -> DSC based MMW sub1 cooling device1,
 			"mmw2_sub1_dsc" -> DSC based MMW sub1 cooling device2,
 			"mmw3_sub1_dsc" -> DSC based MMW sub1 cooling device3,
-			"mmw_ific_sub1_dsc" -> DSC based MMW IFIC sub1 cooling device.
+			"mmw_ific_sub1_dsc" -> DSC based MMW IFIC sub1 cooling device,
+			"tmd_rf_cal" -> for acknowledging modem that bcl disable
+						is done.
 
 	-#cooling-cells:
 		Usage: required
diff --git a/bindings/thermal/qti-qmi-sensor.txt b/bindings/thermal/qti-qmi-sensor.txt
index b065feb0..ea955931 100755
--- a/bindings/thermal/qti-qmi-sensor.txt
+++ b/bindings/thermal/qti-qmi-sensor.txt
@@ -105,6 +105,19 @@ Subsystem properties:
 		72. epm7
 		73. sdr0_pa
 		74. sdr1_pa
+		75. sdr2_pa
+		76. sdr3_pa
+		77. sdr4_pa
+		78. sdr5_pa
+		79. sdr6_pa
+		80. sdr7_pa
+		81. sdr2
+		82. sdr3
+		83. sdr4
+		84. sdr5
+		85. sdr6
+		86. sdr7
+		87. rf_cal
 
 Example:
 
diff --git a/bindings/virtio/mmio.yaml b/bindings/virtio/mmio.yaml
index d4659702..df082a5c 100755
--- a/bindings/virtio/mmio.yaml
+++ b/bindings/virtio/mmio.yaml
@@ -31,6 +31,10 @@ properties:
     description: Required for devices making accesses thru an IOMMU.
     maxItems: 1
 
+  wakeup-source:
+    type: boolean
+    description: Required for setting irq of a virtio_mmio device as wakeup source.
+
 required:
   - compatible
   - reg
diff --git a/bindings/virtio/qcom,virtio-mem.yaml b/bindings/virtio/qcom,virtio-mem.yaml
index 87aec660..babcf068 100755
--- a/bindings/virtio/qcom,virtio-mem.yaml
+++ b/bindings/virtio/qcom,virtio-mem.yaml
@@ -17,7 +17,9 @@ properties:
   reg:
     description:
       Physical address and size of hotpluggable region. Must be aligned
-      to memory_block_size_bytes() - 128 Mb on arm64.
+      to memory_block_size_bytes() - This is same as section size on
+      arm64 which is 256MB when CONFIG_ARM64_MEMMAP_ON_MEMORY defined
+      else defaults to 128MB.
 
   qcom,block_size:
     description:
diff --git a/qcom/Makefile b/qcom/Makefile
index f143af50..2568dc72 100755
--- a/qcom/Makefile
+++ b/qcom/Makefile
@@ -44,8 +44,8 @@ waipio-overlays-dtb-$(CONFIG_ARCH_WAIPIO) += $(WAIPIO_BOARDS) $(NOAPQ_WAIPIO_BOA
 dtb-y += $(waipio-dtb-y)
 
 
-KALAMA_BASE_DTB += kalama.dtb kalama-v2.dtb kalama-sg.dtb
-KALAMA_APQ_BASE_DTB += kalamap.dtb kalamap-v2.dtb kalamap-sg.dtb
+KALAMA_BASE_DTB += kalama.dtb kalama-v2.dtb kalama-sg.dtb kalama-qcm.dtb
+KALAMA_APQ_BASE_DTB += kalamap.dtb kalamap-v2.dtb kalamap-sg.dtb kalamap-qcs.dtb
 
 KALAMA_BOARDS += \
 		 kalama-mtp-overlay.dtbo \
@@ -123,9 +123,10 @@ bengal-dtb-$(CONFIG_ARCH_KHAJE) += \
 bengal-overlays-dtb-$(CONFIG_ARCH_KHAJE) += $(KHAJE_BOARDS) $(KHAJE_BASE_DTB)
 dtb-y += $(bengal-dtb-y)
 
-KONA_BASE_DTB += kona-iot.dtb kona-iot-v2.dtb kona-iot-v2.1.dtb
+KONA_BASE_DTB += kona-iot.dtb kona-iot-v2.dtb kona-iot-v2.1.dtb kona-7230-iot-v2.1.dtb qrb5165-iot.dtb qrb5165n-iot.dtb
 
 KONA_BOARDS += \
+                 kona-iot-v2.1-rb5-overlay.dtbo \
                  kona-iot-v2.1-vc-overlay.dtbo
 
 kona-dtb-$(CONFIG_ARCH_KONA) += \
@@ -213,6 +214,7 @@ dtb-y += $(sdmsteppeauto-dtb-y)
 LEMANS_BASE_DTB		+= lemans.dtb
 LEMANS_IVI_BASE_DTB	+= lemans-ivi.dtb
 LEMANS_ADAS_HIGH_BASE_DTB += lemans-adas-high.dtb
+LEMANS_IVI_ADAS_BASE_DTB  += lemans-ivi-adas.dtb
 
 LEMANS_BOARDS		+= lemans-rumi-overlay.dtbo
 LEMANS_IVI_BOARDS	+= lemans-ivi-adp-air-overlay.dtbo \
@@ -222,12 +224,17 @@ LEMANS_ADAS_HIGH_BOARDS += lemans-adas-high-adp-air-overlay.dtbo \
 			   lemans-adas-high-adp-star-overlay.dtbo \
 			   lemans-adas-high-qam-star-overlay.dtbo
 
+LEMANS_IVI_ADAS_BOARDS  += lemans-ivi-adas-qam-star-overlay.dtbo \
+			   lemans-ivi-adas-adp-star-overlay.dtbo
+
 gen4auto-dtb-$(CONFIG_ARCH_LEMANS) += \
 	$(call add-overlays, $(LEMANS_IVI_BOARDS),$(LEMANS_IVI_BASE_DTB))\
-	$(call add-overlays, $(LEMANS_ADAS_HIGH_BOARDS),$(LEMANS_ADAS_HIGH_BASE_DTB))
+	$(call add-overlays, $(LEMANS_ADAS_HIGH_BOARDS),$(LEMANS_ADAS_HIGH_BASE_DTB))\
+	$(call add-overlays, $(LEMANS_IVI_ADAS_BOARDS),$(LEMANS_IVI_ADAS_BASE_DTB))
 
 gen4auto-overlays-dtb-$(CONFIG_ARCH_LEMANS) +=  \
-	$(LEMANS_IVI_BOARDS) $(LEMANS_ADAS_HIGH_BOARDS) $(LEMANS_IVI_BASE_DTB) $(LEMANS_ADAS_HIGH_BASE_DTB)
+	$(LEMANS_IVI_BOARDS) $(LEMANS_ADAS_HIGH_BOARDS) $(LEMANS_IVI_BASE_DTB) $(LEMANS_ADAS_HIGH_BASE_DTB) \
+	$(LEMANS_IVI_ADAS_BOARDS) $(LEMANS_IVI_ADAS_BASE_DTB)
 
 dtb-y += $(gen4auto-dtb-y)
 
@@ -253,6 +260,16 @@ SA8155_LA_GVM_BASE_DTB += sa8155-vm-la.dtb
 SA8155_LA_GVM_BOARDS += \
 		   sa8155-vm-la-overlay.dtbo
 
+LEMANS_LV_GVM_BASE_DTB += lemans-vm-lv.dtb
+
+LEMANS_LV_GVM_BOARDS += \
+		lemans-vm-lv-overlay.dtbo
+
+LEMANS_LA_GVM_BASE_DTB += lemans-vm-la.dtb
+
+LEMANS_LA_GVM_BOARDS += \
+		lemans-vm-la-overlay.dtbo
+
 DIREWOLF_LV_GVM_BASE_DTB += direwolf-vm-lv.dtb
 
 DIREWOLF_LV_GVM_BOARDS += \
@@ -272,11 +289,14 @@ autogvm-dtb-$(CONFIG_QTI_QUIN_GVM) += \
 	$(call add-overlays, $(SA8155_LA_GVM_BOARDS),$(SA8155_LA_GVM_BASE_DTB)) \
 	$(call add-overlays, $(DIREWOLF_LV_GVM_BOARDS),$(DIREWOLF_LV_GVM_BASE_DTB)) \
 	$(call add-overlays, $(SA8195_LA_GVM_BOARDS),$(SA8195_LA_GVM_BASE_DTB)) \
-	$(call add-overlays, $(DIREWOLF_LA_GVM_BOARDS),$(DIREWOLF_LA_GVM_BASE_DTB))
+	$(call add-overlays, $(DIREWOLF_LA_GVM_BOARDS),$(DIREWOLF_LA_GVM_BASE_DTB)) \
+	$(call add-overlays, $(LEMANS_LV_GVM_BOARDS),$(LEMANS_LV_GVM_BASE_DTB)) \
+	$(call add-overlays, $(LEMANS_LA_GVM_BOARDS),$(LEMANS_LA_GVM_BASE_DTB))
 
 autogvm-overlays-dtb-$(CONFIG_QTI_QUIN_GVM) += \
 	$(SA8155_LA_GVM_BOARDS) $(DIREWOLF_LV_GVM_BOARDS) $(SA8155_LA_GVM_BASE_DTB) $(DIREWOLF_LV_GVM_BASE_DTB) \
-	$(SA8195_LA_GVM_BOARDS) $(SA8195_LA_GVM_BASE_DTB) $(DIREWOLF_LA_GVM_BOARDS) $(DIREWOLF_LA_GVM_BASE_DTB)
+	$(SA8195_LA_GVM_BOARDS) $(SA8195_LA_GVM_BASE_DTB) $(DIREWOLF_LA_GVM_BOARDS) $(DIREWOLF_LA_GVM_BASE_DTB) \
+	$(LEMANS_LA_GVM_BOARDS) $(LEMANS_LA_GVM_BASE_DTB) $(LEMANS_LV_GVM_BOARDS) $(LEMANS_LV_GVM_BASE_DTB)
 
 dtb-y += $(autogvm-dtb-y)
 
diff --git a/qcom/bengal-coresight.dtsi b/qcom/bengal-coresight.dtsi
index 2d0a921b..43abf89c 100755
--- a/qcom/bengal-coresight.dtsi
+++ b/qcom/bengal-coresight.dtsi
@@ -1454,7 +1454,7 @@
 
 		coresight-name = "coresight-tmc-etr";
 
-
+		qcom,iommu-dma = "bypass";
 		iommus = <&apps_smmu 0x0180 0>,
 			<&apps_smmu 0x0160 0>;
 
@@ -1464,8 +1464,7 @@
 		ranges;
 
 		qcom,mem_support;
-		usb_bam_support;
-		dma-coherent;
+		qcom,sw-usb;
 		arm,buffer-size = <0x400000>;
 		arm,scatter-gather;
 
diff --git a/qcom/cinder-debug.dtsi b/qcom/cinder-debug.dtsi
index 2f30ec4b..130474ef 100755
--- a/qcom/cinder-debug.dtsi
+++ b/qcom/cinder-debug.dtsi
@@ -1,3 +1,5 @@
+#include <dt-bindings/soc/qcom,dcc_v2.h>
+
 &reserved_memory {
 	#address-cells = <2>;
 	#size-cells = <2>;
@@ -5,7 +7,7 @@
 
 	dump_mem: mem_dump_region {
 		compatible = "shared-dma-pool";
-		alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>;
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
 		reusable;
 		alignment = <0x0 0x400000>;
 		size = <0 0x800000>;
@@ -21,6 +23,748 @@
 		qcom,transaction_timeout = <0>;
 		reg-names = "dcc-base", "dcc-ram-base";
 		dcc-ram-offset = <0>;
+		link_list_0 {
+			qcom,curr-link-list = <3>;
+			qcom,data-sink = "sram";
+			qcom,link-list = <DCC_READ 0x17800058 1 0>,
+					<DCC_READ 0x17810058 1 0>,
+					<DCC_READ 0x17820058 1 0>,
+					<DCC_READ 0x17830058 1 0>,
+					<DCC_READ 0x1780005c 1 0>,
+					<DCC_READ 0x1781005c 1 0>,
+					<DCC_READ 0x1782005c 1 0>,
+					<DCC_READ 0x1783005c 1 0>,
+					<DCC_READ 0x1740003c 1 0>,
+					<DCC_READ 0x17800060 1 0>,
+					<DCC_READ 0x17810060 1 0>,
+					<DCC_READ 0x17820060 1 0>,
+					<DCC_READ 0x17830060 1 0>,
+					<DCC_READ 0x17800064 1 0>,
+					<DCC_READ 0x17810064 1 0>,
+					<DCC_READ 0x17820064 1 0>,
+					<DCC_READ 0x17830064 1 0>,
+					<DCC_READ 0x17600238 1 0>,
+					<DCC_READ 0x17600404 1 0>,
+					<DCC_READ 0x1760041c 2 0>,
+					<DCC_READ 0x17600434 1 0>,
+					<DCC_READ 0x1760043c 2 0>,
+					<DCC_WRITE 0x17a80000 0x8007 0>,
+					<DCC_READ 0x17a80000 1 0>,
+					<DCC_WRITE 0x17a80024 0x0 0>,
+					<DCC_READ 0x17a80024 1 0>,
+					<DCC_WRITE 0x17a80020 0x0 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_READ 0x17a80038 1 0>,
+					<DCC_WRITE 0x17a80020 0x40 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_READ 0x17a80038 1 0>,
+					<DCC_WRITE 0x17a80020 0x80 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_READ 0x17a80038 1 0>,
+					<DCC_WRITE 0x17a80020 0xc0 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_READ 0x17a80038 1 0>,
+					<DCC_WRITE 0x17a80020 0x100 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_READ 0x17a80038 1 0>,
+					<DCC_WRITE 0x17a80020 0x140 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_READ 0x17a80038 1 0>,
+					<DCC_WRITE 0x17a80020 0x180 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_READ 0x17a80038 1 0>,
+					<DCC_WRITE 0x17a80020 0x1c0 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_READ 0x17a80038 1 0>,
+					<DCC_WRITE 0x17a80020 0x200 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_READ 0x17a80038 1 0>,
+					<DCC_WRITE 0x17a80020 0x240 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_READ 0x17a80038 1 0>,
+					<DCC_WRITE 0x17a80020 0x280 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_READ 0x17a80038 1 0>,
+					<DCC_WRITE 0x17a80020 0x2c0 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_READ 0x17a80038 1 0>,
+					<DCC_WRITE 0x17a80020 0x300 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_READ 0x17a80038 1 0>,
+					<DCC_WRITE 0x17a80020 0x340 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_READ 0x17a80038 1 0>,
+					<DCC_WRITE 0x17a80020 0x380 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_READ 0x17a80038 1 0>,
+					<DCC_WRITE 0x17a80020 0x3c0 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_READ 0x17a80038 1 0>,
+					<DCC_WRITE 0x17a80020 0x4000 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_WRITE 0x17a80020 0x0 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_WRITE 0x17a80020 0x0 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_WRITE 0x17a80020 0x0 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_READ 0x17a80038 1 0>,
+					<DCC_WRITE 0x17a80020 0x40 0>,
+					<DCC_READ 0x17a80020 1 0>,
+					<DCC_READ 0x17a80038 1 0>,
+					<DCC_WRITE 0x17a84000 0x8007 0>,
+					<DCC_READ 0x17a84000 1 0>,
+					<DCC_WRITE 0x17a84024 0x0 0>,
+					<DCC_READ 0x17a84024 1 0>,
+					<DCC_WRITE 0x17a84020 0x0 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_READ 0x17a8400c 1 0>,
+					<DCC_WRITE 0x17a84020 0x40 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_READ 0x17a8400c 1 0>,
+					<DCC_WRITE 0x17a84020 0x80 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_READ 0x17a8400c 1 0>,
+					<DCC_WRITE 0x17a84020 0xc0 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_READ 0x17a8400c 1 0>,
+					<DCC_WRITE 0x17a84020 0x100 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_READ 0x17a8400c 1 0>,
+					<DCC_WRITE 0x17a84020 0x140 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_READ 0x17a8400c 1 0>,
+					<DCC_WRITE 0x17a84020 0x180 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_READ 0x17a8400c 1 0>,
+					<DCC_WRITE 0x17a84020 0x1c0 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_READ 0x17a8400c 1 0>,
+					<DCC_WRITE 0x17a84020 0x200 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_READ 0x17a8400c 1 0>,
+					<DCC_WRITE 0x17a84020 0x240 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_READ 0x17a8400c 1 0>,
+					<DCC_WRITE 0x17a84020 0x280 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_READ 0x17a8400c 1 0>,
+					<DCC_WRITE 0x17a84020 0x2c0 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_READ 0x17a8400c 1 0>,
+					<DCC_WRITE 0x17a84020 0x300 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_READ 0x17a8400c 1 0>,
+					<DCC_WRITE 0x17a84020 0x340 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_READ 0x17a8400c 1 0>,
+					<DCC_WRITE 0x17a84020 0x380 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_READ 0x17a8400c 1 0>,
+					<DCC_WRITE 0x17a84020 0x3c0 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_READ 0x17a8400c 1 0>,
+					<DCC_WRITE 0x17a84024 0x4000 0>,
+					<DCC_READ 0x17a84024 1 0>,
+					<DCC_WRITE 0x17a84020 0x0 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_WRITE 0x17a84020 0x0 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_WRITE 0x17a84020 0x0 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_READ 0x17a8400c 1 0>,
+					<DCC_WRITE 0x17a84020 0x40 0>,
+					<DCC_READ 0x17a84020 1 0>,
+					<DCC_READ 0x17a8400c 1 0>,
+					<DCC_READ 0xc201244 1 0>,
+					<DCC_READ 0xc202244 1 0>,
+					<DCC_READ 0x17b00000 70 0>,
+					<DCC_READ 0x17B00000 1 0>,
+					<DCC_READ 0x17800010 1 0>,
+					<DCC_READ 0x17800024 1 0>,
+					<DCC_READ 0x17800038 6 0>,
+					<DCC_READ 0x1780006c 1 0>,
+					<DCC_READ 0x178000f0 2 0>,
+					<DCC_READ 0x17810010 1 0>,
+					<DCC_READ 0x17810024 1 0>,
+					<DCC_READ 0x17810038 6 0>,
+					<DCC_READ 0x1781006c 1 0>,
+					<DCC_READ 0x178100f0 2 0>,
+					<DCC_READ 0x17820010 1 0>,
+					<DCC_READ 0x17820024 1 0>,
+					<DCC_READ 0x17820038 6 0>,
+					<DCC_READ 0x1782006c 1 0>,
+					<DCC_READ 0x178200f0 2 0>,
+					<DCC_READ 0x17830010 1 0>,
+					<DCC_READ 0x17830024 1 0>,
+					<DCC_READ 0x17830038 6 0>,
+					<DCC_READ 0x1783006c 1 0>,
+					<DCC_READ 0x178300f0 2 0>,
+					<DCC_READ 0x17880010 1 0>,
+					<DCC_READ 0x17880024 1 0>,
+					<DCC_READ 0x17880038 1 0>,
+					<DCC_READ 0x17880040 1 0>,
+					<DCC_READ 0x17880044 3 0>,
+					<DCC_READ 0x1788006c 5 0>,
+					<DCC_READ 0x17880084 1 0>,
+					<DCC_READ 0x178800f4 5 0>,
+					<DCC_READ 0x17880134 2 0>,
+					<DCC_READ 0x178801b4 1 0>,
+					<DCC_READ 0x178801bc 2 0>,
+					<DCC_READ 0x178801c8 1 0>,
+					<DCC_READ 0xb241024 1 0>,
+					<DCC_READ 0xbde1034 1 0>,
+					<DCC_READ 0xb201020 2 0>,
+					<DCC_READ 0xb211020 2 0>,
+					<DCC_READ 0xb221020 2 0>,
+					<DCC_READ 0xb204520 1 0>,
+					<DCC_READ 0xb200010 4 0>,
+					<DCC_READ 0xb200900 4 0>,
+					<DCC_READ 0xb201030 1 0>,
+					<DCC_READ 0xb201204 2 0>,
+					<DCC_READ 0xb201218 2 0>,
+					<DCC_READ 0xb20122c 2 0>,
+					<DCC_READ 0xb201240 2 0>,
+					<DCC_READ 0xb201254 2 0>,
+					<DCC_READ 0xb204510 2 0>,
+					<DCC_READ 0xb220010 4 0>,
+					<DCC_READ 0xb220900 4 0>,
+					<DCC_READ 0x17a00010 1 0>,
+					<DCC_READ 0x17a10010 1 0>,
+					<DCC_READ 0x17a20010 1 0>,
+					<DCC_READ 0x17a00030 1 0>,
+					<DCC_READ 0x17a10030 1 0>,
+					<DCC_READ 0x17a20030 1 0>,
+					<DCC_READ 0x17a00038 1 0>,
+					<DCC_READ 0x17a10038 1 0>,
+					<DCC_READ 0x17a20038 1 0>,
+					<DCC_READ 0x17a00040 1 0>,
+					<DCC_READ 0x17a10040 1 0>,
+					<DCC_READ 0x17a20040 1 0>,
+					<DCC_READ 0x17a00048 1 0>,
+					<DCC_READ 0x17a00400 3 0>,
+					<DCC_READ 0x17a10400 3 0>,
+					<DCC_READ 0x17a20400 3 0>,
+					<DCC_READ 0x17d80100 144 0>,
+					<DCC_READ 0x17d9001c 1 0>,
+					<DCC_READ 0x17d900dc 1 0>,
+					<DCC_READ 0x17d900e8 1 0>,
+					<DCC_READ 0x17d90320 1 0>,
+					<DCC_READ 0x17d90020 1 0>,
+					<DCC_READ 0x17d9034c 1 0>,
+					<DCC_READ 0x17d90300 1 0>,
+					<DCC_READ 0x17d9101c 1 0>,
+					<DCC_READ 0x17d910dc 1 0>,
+					<DCC_READ 0x17d910e8 1 0>,
+					<DCC_READ 0x17d91320 1 0>,
+					<DCC_READ 0x17d91020 1 0>,
+					<DCC_READ 0x17d9134c 1 0>,
+					<DCC_READ 0x17d91300 1 0>,
+					<DCC_READ 0x12822000 2 0>,
+					<DCC_READ 0x12824c00 1 0>,
+					<DCC_READ 0x12824d04 2 0>,
+					<DCC_READ 0x17d98014 4 0>,
+					<DCC_READ 0x17d900e0 1 0>,
+					<DCC_READ 0x17d90410 1 0>,
+					<DCC_READ 0x17d90074 1 0>,
+					<DCC_READ 0x17d90064 1 0>,
+					<DCC_READ 0x17d91074 1 0>,
+					<DCC_READ 0x17d910e0 1 0>,
+					<DCC_READ 0x17d91410 1 0>,
+					<DCC_READ 0x17400038 1 0>,
+					<DCC_READ 0x17d98010 1 0>,
+					<DCC_READ 0x1fc8000 1 0>,
+					<DCC_READ 0x17200104 29 0>,
+					<DCC_READ 0x17200204 29 0>,
+					<DCC_READ 0x17200384 29 0>,
+					<DCC_READ 0x80000 2 0>,
+					<DCC_READ 0x81000 2 0>,
+					<DCC_READ 0x82000 2 0>,
+					<DCC_READ 0x83000 2 0>,
+					<DCC_READ 0x84000 2 0>,
+					<DCC_READ 0x85000 2 0>,
+					<DCC_READ 0x86000 2 0>,
+					<DCC_READ 0x87000 2 0>,
+					<DCC_READ 0x88000 2 0>,
+					<DCC_READ 0xc2a0000 2 0>,
+					<DCC_READ 0xc2a1000 2 0>,
+					<DCC_READ 0xc2a900c 1 0>,
+					<DCC_READ 0xa7168 1 0>,
+					<DCC_READ 0xa729c 1 0>,
+					<DCC_READ 0xa73d0 1 0>,
+					<DCC_READ 0xa7504 1 0>,
+					<DCC_READ 0xa7638 1 0>,
+					<DCC_READ 0xa776c 1 0>,
+					<DCC_READ 0xa8168 1 0>,
+					<DCC_READ 0xa829c 1 0>,
+					<DCC_READ 0xa83d0 1 0>,
+					<DCC_READ 0xa8504 1 0>,
+					<DCC_READ 0xa8638 1 0>,
+					<DCC_READ 0xa876c 1 0>,
+					<DCC_READ 0xd1028 1 0>,
+					<DCC_READ 0x10406c 1 0>,
+					<DCC_READ 0xa7034 1 0>,
+					<DCC_READ 0xd4174 1 0>,
+					<DCC_READ 0x113024 1 0>,
+					<DCC_READ 0x10603c 1 0>,
+					<DCC_READ 0x11d004 2 0>,
+					<DCC_READ 0xfc004 2 0>,
+					<DCC_READ 0xc9008 1 0>,
+					<DCC_READ 0xc9004 1 0>,
+					<DCC_READ 0xe2000 1 0>,
+					<DCC_READ 0xe2008 1 0>,
+					<DCC_READ 0xe2010 1 0>,
+					<DCC_READ 0xe300c 1 0>,
+					<DCC_READ 0xe3014 1 0>,
+					<DCC_READ 0xe301c 1 0>,
+					<DCC_READ 0xe6000 1 0>,
+					<DCC_READ 0xe6008 1 0>,
+					<DCC_READ 0xe6010 1 0>,
+					<DCC_READ 0xe1000 1 0>,
+					<DCC_READ 0xe1008 1 0>,
+					<DCC_READ 0xe1010 1 0>,
+					<DCC_READ 0xea000 1 0>,
+					<DCC_READ 0xea008 1 0>,
+					<DCC_READ 0xea010 1 0>,
+					<DCC_READ 0xe7000 1 0>,
+					<DCC_READ 0xe7008 1 0>,
+					<DCC_READ 0xe7010 1 0>,
+					<DCC_READ 0xf900c 1 0>,
+					<DCC_READ 0xf9014 1 0>,
+					<DCC_READ 0xf901c 1 0>,
+					<DCC_READ 0xa0004 1 0>,
+					<DCC_READ 0x120004 1 0>,
+					<DCC_READ 0x113004 2 0>,
+					<DCC_READ 0xd4004 1 0>,
+					<DCC_READ 0x104008 2 0>,
+					<DCC_READ 0x11d02c 1 0>,
+					<DCC_READ 0x11d024 1 0>,
+					<DCC_READ 0x11d048 1 0>,
+					<DCC_READ 0x11d040 1 0>,
+					<DCC_READ 0x11d01c 1 0>,
+					<DCC_READ 0x11d018 1 0>,
+					<DCC_READ 0xa1004 4 0>,
+					<DCC_READ 0x150e8008 1 0>,
+					<DCC_READ 0x150025dc 1 0>,
+					<DCC_READ 0x150055dc 1 0>,
+					<DCC_READ 0x150075dc 1 0>,
+					<DCC_READ 0x150075dc 1 0>,
+					<DCC_READ 0x15002204 1 0>,
+					<DCC_READ 0x15002670 1 0>,
+					<DCC_READ 0x15002648 1 0>,
+					<DCC_READ 0x150022fc 3 0>,
+					<DCC_READ 0x150022fc 1 0>,
+					<DCC_READ 0x15002304 1 0>,
+					<DCC_READ 0x19100010 1 0>,
+					<DCC_READ 0x19100018 1 0>,
+					<DCC_READ 0x19100020 1 0>,
+					<DCC_READ 0x19100024 1 0>,
+					<DCC_READ 0x19100028 1 0>,
+					<DCC_READ 0x1910002C 1 0>,
+					<DCC_READ 0x19100030 1 0>,
+					<DCC_READ 0x19100034 1 0>,
+					<DCC_READ 0x19100410 1 0>,
+					<DCC_READ 0x19100418 1 0>,
+					<DCC_READ 0x19100420 1 0>,
+					<DCC_READ 0x19100424 1 0>,
+					<DCC_READ 0x19100428 1 0>,
+					<DCC_READ 0x1910042C 1 0>,
+					<DCC_READ 0x19100430 1 0>,
+					<DCC_READ 0x19100434 1 0>,
+					<DCC_READ 0x19100810 1 0>,
+					<DCC_READ 0x19100818 1 0>,
+					<DCC_READ 0x19100820 1 0>,
+					<DCC_READ 0x19100824 1 0>,
+					<DCC_READ 0x19100828 1 0>,
+					<DCC_READ 0x1910082C 1 0>,
+					<DCC_READ 0x19100830 1 0>,
+					<DCC_READ 0x19100834 1 0>,
+					<DCC_READ 0x19100C10 1 0>,
+					<DCC_READ 0x19100C18 1 0>,
+					<DCC_READ 0x19100C20 1 0>,
+					<DCC_READ 0x19100C24 1 0>,
+					<DCC_READ 0x19100C28 1 0>,
+					<DCC_READ 0x19100C2C 1 0>,
+					<DCC_READ 0x19100C30 1 0>,
+					<DCC_READ 0x19100C34 1 0>,
+					<DCC_READ 0x19140010 1 0>,
+					<DCC_READ 0x19140018 1 0>,
+					<DCC_READ 0x19140020 1 0>,
+					<DCC_READ 0x19140024 1 0>,
+					<DCC_READ 0x19140028 1 0>,
+					<DCC_READ 0x1914002C 1 0>,
+					<DCC_READ 0x19140030 1 0>,
+					<DCC_READ 0x19140034 1 0>,
+					<DCC_READ 0x19140410 1 0>,
+					<DCC_READ 0x19140418 1 0>,
+					<DCC_READ 0x19140420 1 0>,
+					<DCC_READ 0x19140424 1 0>,
+					<DCC_READ 0x19140428 1 0>,
+					<DCC_READ 0x1914042C 1 0>,
+					<DCC_READ 0x19140430 1 0>,
+					<DCC_READ 0x19140434 1 0>,
+					<DCC_READ 0x19140810 1 0>,
+					<DCC_READ 0x19140818 1 0>,
+					<DCC_READ 0x19140820 1 0>,
+					<DCC_READ 0x19140824 1 0>,
+					<DCC_READ 0x19140828 1 0>,
+					<DCC_READ 0x1914082C 1 0>,
+					<DCC_READ 0x19140830 1 0>,
+					<DCC_READ 0x19140834 1 0>,
+					<DCC_READ 0x19140C10 1 0>,
+					<DCC_READ 0x19140C18 1 0>,
+					<DCC_READ 0x19140C20 1 0>,
+					<DCC_READ 0x19140C24 1 0>,
+					<DCC_READ 0x19140C28 1 0>,
+					<DCC_READ 0x19140C2C 1 0>,
+					<DCC_READ 0x19140C30 1 0>,
+					<DCC_READ 0x19140C34 1 0>,
+					<DCC_READ 0x19180010 1 0>,
+					<DCC_READ 0x19180018 1 0>,
+					<DCC_READ 0x19180020 1 0>,
+					<DCC_READ 0x19180024 1 0>,
+					<DCC_READ 0x19180028 1 0>,
+					<DCC_READ 0x1918002C 1 0>,
+					<DCC_READ 0x19180030 1 0>,
+					<DCC_READ 0x19180034 1 0>,
+					<DCC_READ 0x19180410 1 0>,
+					<DCC_READ 0x19180418 1 0>,
+					<DCC_READ 0x19180420 1 0>,
+					<DCC_READ 0x19180424 1 0>,
+					<DCC_READ 0x19180428 1 0>,
+					<DCC_READ 0x1918042C 1 0>,
+					<DCC_READ 0x19180430 1 0>,
+					<DCC_READ 0x19180434 1 0>,
+					<DCC_READ 0x19180810 1 0>,
+					<DCC_READ 0x19180818 1 0>,
+					<DCC_READ 0x19180820 1 0>,
+					<DCC_READ 0x19180824 1 0>,
+					<DCC_READ 0x19180828 1 0>,
+					<DCC_READ 0x1918082C 1 0>,
+					<DCC_READ 0x19180830 1 0>,
+					<DCC_READ 0x19180834 1 0>,
+					<DCC_READ 0x19104008 1 0>,
+					<DCC_READ 0x1910400C 1 0>,
+					<DCC_READ 0x19104408 1 0>,
+					<DCC_READ 0x1910440C 1 0>,
+					<DCC_READ 0x19104808 1 0>,
+					<DCC_READ 0x1910480C 1 0>,
+					<DCC_READ 0x19104C08 1 0>,
+					<DCC_READ 0x19104C0C 1 0>,
+					<DCC_READ 0x19144008 1 0>,
+					<DCC_READ 0x1914400C 1 0>,
+					<DCC_READ 0x19144408 1 0>,
+					<DCC_READ 0x1914440C 1 0>,
+					<DCC_READ 0x19144808 1 0>,
+					<DCC_READ 0x1914480C 1 0>,
+					<DCC_READ 0x19144C08 1 0>,
+					<DCC_READ 0x19144C0C 1 0>,
+					<DCC_READ 0x19184008 1 0>,
+					<DCC_READ 0x1918400C 1 0>,
+					<DCC_READ 0x19184408 1 0>,
+					<DCC_READ 0x1918440C 1 0>,
+					<DCC_READ 0x19184808 1 0>,
+					<DCC_READ 0x1918480C 1 0>,
+					<DCC_READ 0x19180C48 1 0>,
+					<DCC_READ 0x19180C4C 1 0>,
+					<DCC_READ 0x191AF010 1 0>,
+					<DCC_READ 0x191B0010 1 0>,
+					<DCC_READ 0x191B1010 1 0>,
+					<DCC_READ 0x191B2010 1 0>,
+					<DCC_READ 0x191B3010 1 0>,
+					<DCC_READ 0x191B4010 1 0>,
+					<DCC_READ 0x191B5010 1 0>,
+					<DCC_READ 0x191B6010 1 0>,
+					<DCC_READ 0x191B7010 1 0>,
+					<DCC_READ 0x191B8010 1 0>,
+					<DCC_READ 0x19102000 1 0>,
+					<DCC_READ 0x19102004 1 0>,
+					<DCC_LOOP 0x5 0 0>,
+					<DCC_READ 0x19102008 1 0>,
+					<DCC_READ 0x19102010 1 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x19102014 1 0>,
+					<DCC_READ 0x19102018 1 0>,
+					<DCC_READ 0x19102080 1 0>,
+					<DCC_READ 0x19102084 1 0>,
+					<DCC_READ 0x19102088 1 0>,
+					<DCC_LOOP 0x5 0 0>,
+					<DCC_READ 0x19102090 1 0>,
+					<DCC_READ 0x19102094 1 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x19102098 1 0>,
+					<DCC_READ 0x19142000 1 0>,
+					<DCC_READ 0x19142004 1 0>,
+					<DCC_READ 0x19142008 1 0>,
+					<DCC_LOOP 0x5 0 0>,
+					<DCC_READ 0x19142010 1 0>,
+					<DCC_READ 0x19142014 1 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x19142018 1 0>,
+					<DCC_READ 0x19142080 1 0>,
+					<DCC_READ 0x19142084 1 0>,
+					<DCC_READ 0x19142088 1 0>,
+					<DCC_LOOP 0x5 0 0>,
+					<DCC_READ 0x19142090 1 0>,
+					<DCC_READ 0x19142094 1 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x19142098 1 0>,
+					<DCC_READ 0x19182000 1 0>,
+					<DCC_READ 0x19182004 1 0>,
+					<DCC_READ 0x19182008 1 0>,
+					<DCC_LOOP 0x4 0 0>,
+					<DCC_READ 0x19182010 1 0>,
+					<DCC_READ 0x19182014 1 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x19182018 1 0>,
+					<DCC_READ 0x19182080 1 0>,
+					<DCC_READ 0x19182084 1 0>,
+					<DCC_READ 0x19182088 1 0>,
+					<DCC_LOOP 0xb 0 0>,
+					<DCC_READ 0x19182090 1 0>,
+					<DCC_READ 0x19182094 1 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x19182098 1 0>,
+					<DCC_READ 0x19104010 1 0>,
+					<DCC_LOOP 0x40 0 0>,
+					<DCC_READ 0x19104038 1 0>,
+					<DCC_READ 0x19104030 2 0>,
+					<DCC_READ 0x19104030 2 0>,
+					<DCC_READ 0x19104030 2 0>,
+					<DCC_READ 0x19104030 2 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x19104410 1 0>,
+					<DCC_LOOP 0x40 0 0>,
+					<DCC_READ 0x19104438 1 0>,
+					<DCC_READ 0x19104430 2 0>,
+					<DCC_READ 0x19104430 2 0>,
+					<DCC_READ 0x19104430 2 0>,
+					<DCC_READ 0x19104430 2 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x19104810 1 0>,
+					<DCC_LOOP 0x40 0 0>,
+					<DCC_READ 0x19104838 1 0>,
+					<DCC_READ 0x19104830 2 0>,
+					<DCC_READ 0x19104830 2 0>,
+					<DCC_READ 0x19104830 2 0>,
+					<DCC_READ 0x19104830 2 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x19104C10 1 0>,
+					<DCC_LOOP 0x40 0 0>,
+					<DCC_READ 0x19104C38 1 0>,
+					<DCC_READ 0x19104C30 2 0>,
+					<DCC_READ 0x19104C30 2 0>,
+					<DCC_READ 0x19104C30 2 0>,
+					<DCC_READ 0x19104C30 2 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x19144010 1 0>,
+					<DCC_LOOP 0x40 0 0>,
+					<DCC_READ 0x19144038 1 0>,
+					<DCC_READ 0x19144030 2 0>,
+					<DCC_READ 0x19144030 2 0>,
+					<DCC_READ 0x19144030 2 0>,
+					<DCC_READ 0x19144030 2 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x19144410 1 0>,
+					<DCC_LOOP 0x40 0 0>,
+					<DCC_READ 0x19144438 1 0>,
+					<DCC_READ 0x19144430 2 0>,
+					<DCC_READ 0x19144430 2 0>,
+					<DCC_READ 0x19144430 2 0>,
+					<DCC_READ 0x19144430 2 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x19144810 1 0>,
+					<DCC_LOOP 0x40 0 0>,
+					<DCC_READ 0x19144838 1 0>,
+					<DCC_READ 0x19144830 2 0>,
+					<DCC_READ 0x19144830 2 0>,
+					<DCC_READ 0x19144830 2 0>,
+					<DCC_READ 0x19144830 2 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x19144C10 1 0>,
+					<DCC_LOOP 0x40 0 0>,
+					<DCC_READ 0x19144C38 1 0>,
+					<DCC_READ 0x19144C30 2 0>,
+					<DCC_READ 0x19144C30 2 0>,
+					<DCC_READ 0x19144C30 2 0>,
+					<DCC_READ 0x19144C30 2 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x19184010 1 0>,
+					<DCC_LOOP 0x40 0 0>,
+					<DCC_READ 0x19184038 1 0>,
+					<DCC_READ 0x19184030 2 0>,
+					<DCC_READ 0x19184030 2 0>,
+					<DCC_READ 0x19184030 2 0>,
+					<DCC_READ 0x19184030 2 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x19184410 1 0>,
+					<DCC_LOOP 0x40 0 0>,
+					<DCC_READ 0x19184438 1 0>,
+					<DCC_READ 0x19184430 2 0>,
+					<DCC_READ 0x19184430 2 0>,
+					<DCC_READ 0x19184430 2 0>,
+					<DCC_READ 0x19184430 2 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x19184810 1 0>,
+					<DCC_LOOP 0x40 0 0>,
+					<DCC_READ 0x19184838 1 0>,
+					<DCC_READ 0x19184830 2 0>,
+					<DCC_READ 0x19184830 2 0>,
+					<DCC_READ 0x19184830 2 0>,
+					<DCC_READ 0x19184830 2 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x1640008 1 0>,
+					<DCC_READ 0x1640010 1 0>,
+					<DCC_READ 0x1640018 1 0>,
+					<DCC_READ 0x1640020 1 0>,
+					<DCC_READ 0x1640024 1 0>,
+					<DCC_READ 0x1640028 1 0>,
+					<DCC_READ 0x164002C 1 0>,
+					<DCC_READ 0x1640030 1 0>,
+					<DCC_READ 0x1640034 1 0>,
+					<DCC_READ 0x1640038 1 0>,
+					<DCC_READ 0x164003C 1 0>,
+					<DCC_READ 0x1640240 1 0>,
+					<DCC_READ 0x1640248 1 0>,
+					<DCC_READ 0x1643040 1 0>,
+					<DCC_READ 0x1643044 1 0>,
+					<DCC_READ 0x1643048 1 0>,
+					<DCC_READ 0x164304C 1 0>,
+					<DCC_READ 0x1643050 1 0>,
+					<DCC_READ 0x1643054 1 0>,
+					<DCC_READ 0x1643058 1 0>,
+					<DCC_READ 0x164305C 1 0>,
+					<DCC_READ 0x1670010 1 0>,
+					<DCC_READ 0x1674010 1 0>,
+					<DCC_READ 0x1677010 1 0>,
+					<DCC_READ 0x167A010 1 0>,
+					<DCC_READ 0x167B010 1 0>,
+					<DCC_READ 0x167C010 1 0>,
+					<DCC_READ 0x167D010 1 0>,
+					<DCC_READ 0x1680010 1 0>,
+					<DCC_READ 0x1681010 1 0>,
+					<DCC_READ 0x1682010 1 0>,
+					<DCC_READ 0x1685010 1 0>,
+					<DCC_READ 0x1641008 1 0>,
+					<DCC_LOOP 0x6 0 0>,
+					<DCC_READ 0x1641010 1 0>,
+					<DCC_READ 0x1641014 1 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x1641018 1 0>,
+					<DCC_READ 0x1641088 1 0>,
+					<DCC_LOOP 0x6 0 0>,
+					<DCC_READ 0x1641090 1 0>,
+					<DCC_READ 0x1641094 1 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x1641098 1 0>,
+					<DCC_READ 0x1641108 1 0>,
+					<DCC_LOOP 0x16 0 0>,
+					<DCC_READ 0x1641110 1 0>,
+					<DCC_READ 0x1641114 1 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x1641118 1 0>,
+					<DCC_LOOP 0x4 0 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x190E0008 1 0>,
+					<DCC_READ 0x190E0010 1 0>,
+					<DCC_READ 0x190E0018 1 0>,
+					<DCC_READ 0x190E0020 1 0>,
+					<DCC_READ 0x190E0024 1 0>,
+					<DCC_READ 0x190E0028 1 0>,
+					<DCC_READ 0x190E002C 1 0>,
+					<DCC_READ 0x190E0030 1 0>,
+					<DCC_READ 0x190E0034 1 0>,
+					<DCC_READ 0x190E0038 1 0>,
+					<DCC_READ 0x190E003C 1 0>,
+					<DCC_READ 0x190E0240 1 0>,
+					<DCC_READ 0x190E0248 1 0>,
+					<DCC_READ 0x190E5008 1 0>,
+					<DCC_LOOP 0x6 0 0>,
+					<DCC_READ 0x190E5010 1 0>,
+					<DCC_READ 0x190E5014 1 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x190E5018 1 0>,
+					<DCC_READ 0x195F0008 1 0>,
+					<DCC_READ 0x195F0010 1 0>,
+					<DCC_READ 0x195F0018 1 0>,
+					<DCC_READ 0x195F0020 1 0>,
+					<DCC_READ 0x195F0024 1 0>,
+					<DCC_READ 0x195F0028 1 0>,
+					<DCC_READ 0x195F002C 1 0>,
+					<DCC_READ 0x195F0030 1 0>,
+					<DCC_READ 0x195F0034 1 0>,
+					<DCC_READ 0x195F0038 1 0>,
+					<DCC_READ 0x195F003C 1 0>,
+					<DCC_READ 0x195F0240 1 0>,
+					<DCC_READ 0x195F0248 1 0>,
+					<DCC_READ 0x195F2008 1 0>,
+					<DCC_LOOP 0x3 0 0>,
+					<DCC_READ 0x195F2010 1 0>,
+					<DCC_READ 0x195F2014 1 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x195F2018 1 0>,
+					<DCC_READ 0x199F0008 1 0>,
+					<DCC_READ 0x199F0010 1 0>,
+					<DCC_READ 0x199F0018 1 0>,
+					<DCC_READ 0x199F0020 1 0>,
+					<DCC_READ 0x199F0024 1 0>,
+					<DCC_READ 0x199F0028 1 0>,
+					<DCC_READ 0x199F002C 1 0>,
+					<DCC_READ 0x199F0030 1 0>,
+					<DCC_READ 0x199F0034 1 0>,
+					<DCC_READ 0x199F0038 1 0>,
+					<DCC_READ 0x199F003C 1 0>,
+					<DCC_READ 0x199F0240 1 0>,
+					<DCC_READ 0x199F0248 1 0>,
+					<DCC_READ 0x199F2008 1 0>,
+					<DCC_LOOP 0x3 0 0>,
+					<DCC_READ 0x199F2010 1 0>,
+					<DCC_READ 0x199F2014 1 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x199F2018 1 0>,
+					<DCC_READ 0x199F2008 1 0>,
+					<DCC_READ 0x199F2010 1 0>,
+					<DCC_READ 0x199F2014 1 0>,
+					<DCC_READ 0x199F2018 1 0>,
+					<DCC_READ 0x19DF0008 1 0>,
+					<DCC_READ 0x19DF0010 1 0>,
+					<DCC_READ 0x19DF0018 1 0>,
+					<DCC_READ 0x19DF0020 1 0>,
+					<DCC_READ 0x19DF0024 1 0>,
+					<DCC_READ 0x19DF0028 1 0>,
+					<DCC_READ 0x19DF002C 1 0>,
+					<DCC_READ 0x19DF0030 1 0>,
+					<DCC_READ 0x19DF0034 1 0>,
+					<DCC_READ 0x19DF0038 1 0>,
+					<DCC_READ 0x19DF003C 1 0>,
+					<DCC_READ 0x19DF0240 1 0>,
+					<DCC_READ 0x19DF0248 1 0>,
+					<DCC_READ 0x19DF2008 1 0>,
+					<DCC_LOOP 0x3 0 0>,
+					<DCC_READ 0x19DF2010 1 0>,
+					<DCC_READ 0x19DF2014 1 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x19DF2018 1 0>,
+					<DCC_READ 0x1A1F0008 1 0>,
+					<DCC_READ 0x1A1F0010 1 0>,
+					<DCC_READ 0x1A1F0018 1 0>,
+					<DCC_READ 0x1A1F0020 1 0>,
+					<DCC_READ 0x1A1F0024 1 0>,
+					<DCC_READ 0x1A1F0028 1 0>,
+					<DCC_READ 0x1A1F002C 1 0>,
+					<DCC_READ 0x1A1F0030 1 0>,
+					<DCC_READ 0x1A1F0034 1 0>,
+					<DCC_READ 0x1A1F0038 1 0>,
+					<DCC_READ 0x1A1F003C 1 0>,
+					<DCC_READ 0x1A1F0240 1 0>,
+					<DCC_READ 0x1A1F0248 1 0>,
+					<DCC_READ 0x1A1F2008 1 0>,
+					<DCC_LOOP 0x3 0 0>,
+					<DCC_READ 0x1A1F2010 1 0>,
+					<DCC_READ 0x1A1F2014 1 0>,
+					<DCC_LOOP 0x1 0 0>,
+					<DCC_READ 0x1A1F2018 1 0>;
+			};
 	};
 
 	mem_dump {
diff --git a/qcom/cinder-thermal-modem.dtsi b/qcom/cinder-thermal-modem.dtsi
new file mode 100755
index 00000000..cd4ee84d
--- /dev/null
+++ b/qcom/cinder-thermal-modem.dtsi
@@ -0,0 +1,351 @@
+#include <dt-bindings/thermal/thermal_qti.h>
+
+&soc {
+	qmi_sensor: qmi-ts-sensors {
+		compatible = "qcom,qmi-sensors";
+		#thermal-sensor-cells = <1>;
+
+		modem {
+			qcom,instance-id = <QMI_MODEM_INST_ID>;
+			qcom,qmi-sensor-names = "sdr0",
+						"sdr1",
+						"sdr2",
+						"sdr3",
+						"sdr4",
+						"sdr5",
+						"sdr6",
+						"sdr7",
+						"sdr0_pa",
+						"sdr1_pa",
+						"sdr2_pa",
+						"sdr3_pa",
+						"sdr4_pa",
+						"sdr5_pa",
+						"sdr6_pa",
+						"sdr7_pa";
+		};
+	};
+};
+
+&thermal_zones {
+	sdr0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR0)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR1)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr2 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR2)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr3 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR3)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr4 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR4)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr5 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR5)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr6 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR6)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr7 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR7)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr0_pa {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR0_PA)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr1_pa {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR1_PA)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr2_pa {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+		(QMI_MODEM_INST_ID+QMI_SDR2_PA)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr3_pa {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR3_PA)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr4_pa {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR4_PA)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr5_pa {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR5_PA)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr6_pa {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR6_PA)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sdr7_pa {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_INST_ID+QMI_SDR7_PA)>;
+		trips {
+			thermal-engine-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+};
+
diff --git a/qcom/cinder-thermal.dtsi b/qcom/cinder-thermal.dtsi
index 29dee327..8ea903ac 100755
--- a/qcom/cinder-thermal.dtsi
+++ b/qcom/cinder-thermal.dtsi
@@ -65,6 +65,8 @@
     };
 };
 
+#include "cinder-thermal-modem.dtsi"
+
 &thermal_zones {
 	aoss-0 {
 		polling-delay-passive = <0>;
diff --git a/qcom/cinder.dtsi b/qcom/cinder.dtsi
index 7a075ddd..11247a10 100755
--- a/qcom/cinder.dtsi
+++ b/qcom/cinder.dtsi
@@ -19,7 +19,7 @@
 
 
 	chosen: chosen {
-			bootargs = "cpufreq.default_governor=performance msm_rtb.filter=0x237";
+			bootargs = "cpufreq.default_governor=performance msm_rtb.filter=0x237 ftrace_dump_on_oops";
 	};
 
 	aliases {
@@ -244,6 +244,14 @@
 		size = <0x0 0x1000000>;
 	};
 
+	ramoops_mem: ramoops_region {
+		compatible = "ramoops";
+		alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
+		size = <0x0 0x200000>;
+		pmsg-size = <0x200000>;
+		mem-type = <2>;
+	};
+
 };
 
 &soc {
@@ -385,6 +393,7 @@
 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&CLUSTER_PD>;
 
 		apps_rsc_drv2: drv@2 {
 			qcom,drv-id = <2>;
@@ -868,6 +877,32 @@
 		power-domains = <&CLUSTER_PD>;
 	};
 
+	cpuss-sleep-stats@17800054 {
+		compatible = "qcom,cpuss-sleep-stats-v2";
+		reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>,
+		      <0x17830054 0x4>, <0x17880098 0x4>, <0x178C0000 0x10000>;
+		reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1",
+			    "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3",
+			    "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
+		num-cpus = <4>;
+	};
+
+	soc-sleep-stats@c3f0000 {
+		compatible = "qcom,rpmh-sleep-stats";
+		reg = <0xc3f0000 0x400>;
+		qcom,drv-max = <0x14>;
+		ss-name = "modem", "apss";
+		mboxes = <&qmp_aop 0>;
+		mbox-names = "aop";
+		ddr-freq-update;
+	};
+
+	subsystem-sleep-stats@c3f0000 {
+		compatible = "qcom,subsystem-sleep-stats";
+		reg = <0xc3f0000 0x400>;
+		ddr-freq-update;
+	};
+
 	vendor_hooks: qcom,cpu-vendor-hooks {
 		compatible = "qcom,cpu-vendor-hooks";
 	};
@@ -1485,6 +1520,7 @@
 
 	mhi_net_device: qcom,mhi_net_dev {
 		compatible = "qcom,msm-mhi-dev-net";
+		qcom,mhi-ethernet-interface-channel = <50>;
 		status = "ok";
 	};
 
diff --git a/qcom/direwolf-pinctrl.dtsi b/qcom/direwolf-pinctrl.dtsi
new file mode 100755
index 00000000..1b667faf
--- /dev/null
+++ b/qcom/direwolf-pinctrl.dtsi
@@ -0,0 +1,3619 @@
+&tlmm {
+	qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
+		qupv3_se0_i2c_active: qupv3_se0_i2c_active {
+			mux {
+				pins = "gpio135", "gpio136";
+				function = "qup0";
+			};
+
+			config {
+				pins = "gpio135", "gpio136";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
+			mux {
+				pins = "gpio135", "gpio136";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio135", "gpio136";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se0_spi_pins: qupv3_se0_spi_pins {
+		qupv3_se0_spi_active: qupv3_se0_spi_active {
+			mux {
+				pins = "gpio135", "gpio136",
+						"gpio137", "gpio138";
+				function = "qup0";
+			};
+
+			config {
+				pins = "gpio135", "gpio136",
+						"gpio137", "gpio138";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
+			mux {
+				pins = "gpio135", "gpio136",
+						"gpio137", "gpio138";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio135", "gpio136",
+						"gpio137", "gpio138";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
+		qupv3_se1_i2c_active: qupv3_se1_i2c_active {
+			mux {
+				pins = "gpio158", "gpio159";
+				function = "qup1";
+			};
+
+			config {
+				pins = "gpio158", "gpio159";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
+			mux {
+				pins = "gpio158", "gpio159";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio158", "gpio159";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se1_spi_pins: qupv3_se1_spi_pins {
+		qupv3_se1_spi_active: qupv3_se1_spi_active {
+			mux {
+				pins = "gpio158", "gpio159",
+						"gpio160", "gpio161";
+				function = "qup1";
+			};
+
+			config {
+				pins = "gpio158", "gpio159",
+						"gpio160", "gpio161";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
+			mux {
+				pins = "gpio158", "gpio159",
+						"gpio160", "gpio161";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio158", "gpio159",
+						"gpio160", "gpio161";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
+		qupv3_se2_i2c_active: qupv3_se2_i2c_active {
+			mux {
+				pins = "gpio121", "gpio122";
+				function = "qup2";
+			};
+
+			config {
+				pins = "gpio121", "gpio122";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
+			mux {
+				pins = "gpio121", "gpio122";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio121", "gpio122";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se2_spi_pins: qupv3_se2_spi_pins {
+		qupv3_se2_spi_active: qupv3_se2_spi_active {
+			mux {
+				pins = "gpio121", "gpio122",
+						"gpio123", "gpio124";
+				function = "qup2";
+			};
+
+			config {
+				pins = "gpio121", "gpio122",
+						"gpio123", "gpio124";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
+			mux {
+				pins = "gpio121", "gpio122",
+						"gpio123", "gpio124";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio121", "gpio122",
+						"gpio123", "gpio124";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se2_4uart_pins: qupv3_se2_4uart_pins {
+		qupv3_se2_default_cts:
+				qupv3_se2_default_cts {
+			mux {
+				pins = "gpio121";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio121";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se2_default_rtsrx:
+			qupv3_se2_default_rtsrx {
+			mux {
+				pins = "gpio122", "gpio124";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio122", "gpio124";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se2_default_tx:
+			qupv3_se2_default_tx {
+			mux {
+				pins = "gpio123";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio123";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se2_ctsrx: qupv3_se2_ctsrx {
+			mux {
+				pins = "gpio121", "gpio124";
+				function = "qup2";
+			};
+
+			config {
+				pins = "gpio121", "gpio124";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se2_rts: qupv3_se2_rts {
+			mux {
+				pins = "gpio122";
+				function = "qup2";
+			};
+
+			config {
+				pins = "gpio122";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se2_tx: qupv3_se2_tx {
+			mux {
+				pins = "gpio123";
+				function = "qup2";
+			};
+
+			config {
+				pins = "gpio123";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+	};
+
+	qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
+		qupv3_se3_i2c_active: qupv3_se3_i2c_active {
+			mux {
+				pins = "gpio137", "gpio138";
+				function = "qup3";
+			};
+
+			config {
+				pins = "gpio137", "gpio138";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
+			mux {
+				pins = "gpio137", "gpio138";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio137", "gpio138";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se3_spi_pins: qupv3_se3_spi_pins {
+		qupv3_se3_spi_active: qupv3_se3_spi_active {
+			mux {
+				pins = "gpio137", "gpio138",
+						"gpio135", "gpio136";
+				function = "qup3";
+			};
+
+			config {
+				pins = "gpio137", "gpio138",
+						"gpio135", "gpio136";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
+			mux {
+				pins = "gpio137", "gpio138",
+						"gpio135", "gpio136";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio137", "gpio138",
+						"gpio135", "gpio136";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se3_4uart_pins: qupv3_se3_4uart_pins {
+		qupv3_se3_default_cts:
+				qupv3_se3_default_cts {
+			mux {
+				pins = "gpio137";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio137";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se3_default_rtsrx:
+			qupv3_se3_default_rtsrx {
+			mux {
+				pins = "gpio138", "gpio136";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio138", "gpio136";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se3_default_tx:
+			qupv3_se3_default_tx {
+			mux {
+				pins = "gpio135";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio135";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se3_ctsrx: qupv3_se3_ctsrx {
+			mux {
+				pins = "gpio137", "gpio136";
+				function = "qup2";
+			};
+
+			config {
+				pins = "gpio137", "gpio136";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se3_rts: qupv3_se3_rts {
+			mux {
+				pins = "gpio138";
+				function = "qup2";
+			};
+
+			config {
+				pins = "gpio138";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se3_tx: qupv3_se3_tx {
+			mux {
+				pins = "gpio135";
+				function = "qup2";
+			};
+
+			config {
+				pins = "gpio135";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+	};
+
+	qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
+		qupv3_se4_i2c_active: qupv3_se4_i2c_active {
+			mux {
+				pins = "gpio171", "gpio172";
+				function = "qup4";
+			};
+
+			config {
+				pins = "gpio171", "gpio172";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
+			mux {
+				pins = "gpio171", "gpio172";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio171", "gpio172";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se4_spi_pins: qupv3_se4_spi_pins {
+		qupv3_se4_spi_active: qupv3_se4_spi_active {
+			mux {
+				pins = "gpio171", "gpio172",
+						"gpio173", "gpio174";
+				function = "qup4";
+			};
+
+			config {
+				pins = "gpio171", "gpio172",
+						"gpio173", "gpio174";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
+			mux {
+				pins = "gpio171", "gpio172",
+						"gpio173", "gpio174";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio171", "gpio172",
+						"gpio173", "gpio174";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
+		qupv3_se5_i2c_active: qupv3_se5_i2c_active {
+			mux {
+				pins = "gpio111", "gpio112";
+				function = "qup5";
+			};
+
+			config {
+				pins = "gpio111", "gpio112";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
+			mux {
+				pins = "gpio111", "gpio112";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio111", "gpio112";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se5_spi_pins: qupv3_se5_spi_pins {
+		qupv3_se5_spi_active: qupv3_se5_spi_active {
+			mux {
+				pins = "gpio111", "gpio112",
+						"gpio145", "gpio146";
+				function = "qup5";
+			};
+
+			config {
+				pins = "gpio111", "gpio112",
+						"gpio145", "gpio146";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
+			mux {
+				pins = "gpio111", "gpio112",
+						"gpio145", "gpio146";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio111", "gpio112",
+						"gpio145", "gpio146";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
+		qupv3_se6_i2c_active: qupv3_se6_i2c_active {
+			mux {
+				pins = "gpio154", "gpio155";
+				function = "qup6";
+			};
+
+			config {
+				pins = "gpio154", "gpio155";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
+			mux {
+				pins = "gpio154", "gpio155";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio154", "gpio155";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se6_spi_pins: qupv3_se6_spi_pins {
+		qupv3_se6_spi_active: qupv3_se6_spi_active {
+			mux {
+				pins = "gpio154", "gpio155",
+						"gpio156", "gpio157";
+				function = "qup6";
+			};
+
+			config {
+				pins = "gpio154", "gpio155",
+						"gpio156", "gpio157";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
+			mux {
+				pins = "gpio154", "gpio155",
+						"gpio156", "gpio157";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio154", "gpio155",
+						"gpio156", "gpio157";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se6_4uart_pins: qupv3_se6_4uart_pins {
+		qupv3_se6_default_cts:
+			qupv3_se6_default_cts {
+			mux {
+				pins = "gpio154";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio154";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se6_default_rtsrx:
+			qupv3_se6_default_rtsrx {
+			mux {
+				pins = "gpio155", "gpio157";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio155", "gpio157";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se6_default_tx:
+			qupv3_se6_default_tx {
+			mux {
+				pins = "gpio156";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio156";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se6_ctsrx: qupv3_se6_ctsrx {
+			mux {
+				pins = "gpio154", "gpio157";
+				function = "qup6";
+			};
+
+			config {
+				pins = "gpio154", "gpio157";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se6_rts: qupv3_se6_rts {
+			mux {
+				pins = "gpio155";
+				function = "qup6";
+			};
+
+			config {
+				pins = "gpio155";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se6_tx: qupv3_se6_tx {
+			mux {
+				pins = "gpio156";
+				function = "qup6";
+			};
+
+			config {
+				pins = "gpio156";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+	};
+
+	qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
+		qupv3_se7_i2c_active: qupv3_se7_i2c_active {
+			mux {
+				pins = "gpio128", "gpio129";
+				function = "qup7";
+			};
+
+			config {
+				pins = "gpio128", "gpio129";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
+			mux {
+				pins = "gpio128", "gpio129";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio128", "gpio129";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se7_spi_pins: qupv3_se7_spi_pins {
+		qupv3_se7_spi_active: qupv3_se7_spi_active {
+			mux {
+				pins = "gpio128", "gpio129",
+						"gpio125", "gpio126";
+				function = "qup7";
+			};
+
+			config {
+				pins = "gpio128", "gpio129",
+						"gpio125", "gpio126";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se7_spi_sleep: qupv3_se7_spi_sleep {
+			mux {
+				pins = "gpio128", "gpio129",
+						"gpio125", "gpio126";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio128", "gpio129",
+						"gpio125", "gpio126";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
+		qupv3_se8_i2c_active: qupv3_se8_i2c_active {
+			mux {
+				pins = "gpio43", "gpio44";
+				function = "qup8";
+			};
+
+			config {
+				pins = "gpio43", "gpio44";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
+			mux {
+				pins = "gpio43", "gpio44";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio43", "gpio44";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se8_spi_pins: qupv3_se8_spi_pins {
+		qupv3_se8_spi_active: qupv3_se8_spi_active {
+			mux {
+				pins = "gpio43", "gpio44",
+						"gpio45", "gpio46";
+				function = "qup8";
+			};
+
+			config {
+				pins = "gpio43", "gpio44",
+						"gpio45", "gpio46";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
+			mux {
+				pins = "gpio43", "gpio44",
+						"gpio45", "gpio46";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio43", "gpio44",
+						"gpio45", "gpio46";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
+		qupv3_se9_i2c_active: qupv3_se9_i2c_active {
+			mux {
+				pins = "gpio41", "gpio42";
+				function = "qup9";
+			};
+
+			config {
+				pins = "gpio41", "gpio42";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
+			mux {
+				pins = "gpio41", "gpio42";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio41", "gpio42";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se9_spi_pins: qupv3_se9_spi_pins {
+		qupv3_se9_spi_active: qupv3_se9_spi_active {
+			mux {
+				pins = "gpio41", "gpio42",
+						"gpio43", "gpio44";
+				function = "qup9";
+			};
+
+			config {
+				pins = "gpio41", "gpio42",
+						"gpio43", "gpio44";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {
+			mux {
+				pins = "gpio41", "gpio42",
+						"gpio43", "gpio44";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio41", "gpio42",
+						"gpio43", "gpio44";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
+		qupv3_se10_i2c_active: qupv3_se10_i2c_active {
+			mux {
+				pins = "gpio22", "gpio23";
+				function = "qup10";
+			};
+
+			config {
+				pins = "gpio22", "gpio23";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
+			mux {
+				pins = "gpio22", "gpio23";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio22", "gpio23";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se10_spi_pins: qupv3_se10_spi_pins {
+		qupv3_se10_spi_active: qupv3_se10_spi_active {
+			mux {
+				pins = "gpio22", "gpio23",
+						"gpio24", "gpio25";
+				function = "qup10";
+			};
+
+			config {
+				pins = "gpio22", "gpio23",
+						"gpio24", "gpio25";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
+			mux {
+				pins = "gpio22", "gpio23",
+						"gpio24", "gpio25";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio22", "gpio23",
+						"gpio24", "gpio25";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se10_4uart_pins: qupv3_se10_4uart_pins {
+		qupv3_se10_default_cts:
+				qupv3_se10_default_cts {
+			mux {
+				pins = "gpio22";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio22";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se10_default_rtsrx:
+			qupv3_se10_default_rtsrx {
+			mux {
+				pins = "gpio23", "gpio25";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio23", "gpio25";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se10_default_tx:
+			qupv3_se10_default_tx {
+			mux {
+				pins = "gpio24";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio24";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se10_ctsrx: qupv3_se10_ctsrx {
+			mux {
+				pins = "gpio22", "gpio25";
+				function = "qup10";
+			};
+
+			config {
+				pins = "gpio22", "gpio25";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se10_rts: qupv3_se10_rts {
+			mux {
+				pins = "gpio23";
+				function = "qup10";
+			};
+
+			config {
+				pins = "gpio23";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se10_tx: qupv3_se10_tx {
+			mux {
+				pins = "gpio24";
+				function = "qup10";
+			};
+
+			config {
+				pins = "gpio24";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+	};
+
+	qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
+		qupv3_se11_i2c_active: qupv3_se11_i2c_active {
+			mux {
+				pins = "gpio18", "gpio19";
+				function = "qup11";
+			};
+
+			config {
+				pins = "gpio18", "gpio19";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
+			mux {
+				pins = "gpio18", "gpio19";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio18", "gpio19";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se11_spi_pins: qupv3_se11_spi_pins {
+		qupv3_se11_spi_active: qupv3_se11_spi_active {
+			mux {
+				pins = "gpio18", "gpio19",
+						"gpio20", "gpio21";
+				function = "qup11";
+			};
+
+			config {
+				pins = "gpio18", "gpio19",
+						"gpio20", "gpio21";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se11_spi_sleep: qupv3_se11_spi_sleep {
+			mux {
+				pins = "gpio18", "gpio19",
+						"gpio20", "gpio21";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio18", "gpio19",
+						"gpio20", "gpio21";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se12_i2c_pins: qupv3_se12_i2c_pins {
+		qupv3_se12_i2c_active: qupv3_se12_i2c_active {
+			mux {
+				pins = "gpio0", "gpio1";
+				function = "qup12";
+			};
+
+			config {
+				pins = "gpio0", "gpio1";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep {
+			mux {
+				pins = "gpio0", "gpio1";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio0", "gpio1";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se12_spi_pins: qupv3_se12_spi_pins {
+		qupv3_se12_spi_active: qupv3_se12_spi_active {
+			mux {
+				pins = "gpio0", "gpio1",
+						"gpio2", "gpio3";
+				function = "qup12";
+			};
+
+			config {
+				pins = "gpio0", "gpio1",
+						"gpio2", "gpio3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se12_spi_sleep: qupv3_se12_spi_sleep {
+			mux {
+				pins = "gpio0", "gpio1",
+						"gpio2", "gpio3";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio0", "gpio1",
+						"gpio2", "gpio3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se13_i2c_pins: qupv3_se13_i2c_pins {
+		qupv3_se13_i2c_active: qupv3_se13_i2c_active {
+			mux {
+				pins = "gpio26", "gpio27";
+				function = "qup13";
+			};
+
+			config {
+				pins = "gpio26", "gpio27";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep {
+			mux {
+				pins = "gpio26", "gpio27";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio26", "gpio27";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se13_spi_pins: qupv3_se13_spi_pins {
+		qupv3_se13_spi_active: qupv3_se13_spi_active {
+			mux {
+				pins = "gpio26", "gpio27",
+						"gpio28", "gpio29";
+				function = "qup13";
+			};
+
+			config {
+				pins = "gpio26", "gpio27",
+						"gpio28", "gpio29";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se13_spi_sleep: qupv3_se13_spi_sleep {
+			mux {
+				pins = "gpio26", "gpio27",
+						"gpio28", "gpio29";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio26", "gpio27",
+						"gpio28", "gpio29";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se13_2uart_pins: qupv3_se13_2uart_pins {
+		qupv3_se13_2uart_default: qupv3_se13_2uart_default {
+			mux {
+				pins = "gpio28", "gpio29";
+				function = "qup13";
+			};
+
+			config {
+				pins = "gpio28", "gpio29";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se13_2uart_active: qupv3_se13_2uart_active {
+			mux {
+				pins = "gpio28", "gpio29";
+				function = "qup13";
+			};
+
+			config {
+				pins = "gpio28", "gpio29";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se13_2uart_sleep: qupv3_se13_2uart_sleep {
+			mux {
+				pins = "gpio28", "gpio29";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio28", "gpio29";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		 qupv3_se13_2uart_disable: qupv3_se13_2uart_disable {
+			rtr {
+				pins = "gpio27";
+				drive-strength = <2>;
+				bias-disable;
+				input-enable;
+			};
+
+			cts {
+				pins = "gpio26";
+				drive-strength = <0>;
+				bias-pull-up;
+			};
+		};
+	};
+
+	qupv3_se14_i2c_pins: qupv3_se14_i2c_pins {
+		qupv3_se14_i2c_active: qupv3_se14_i2c_active {
+			mux {
+				pins = "gpio4", "gpio5";
+				function = "qup14";
+			};
+
+			config {
+				pins = "gpio4", "gpio5";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep {
+			mux {
+				pins = "gpio4", "gpio5";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio4", "gpio5";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se14_spi_pins: qupv3_se14_spi_pins {
+		qupv3_se14_spi_active: qupv3_se14_spi_active {
+			mux {
+				pins = "gpio4", "gpio5",
+						"gpio6", "gpio7";
+				function = "qup14";
+			};
+
+			config {
+				pins = "gpio4", "gpio5",
+						"gpio6", "gpio7";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se14_spi_sleep: qupv3_se14_spi_sleep {
+			mux {
+				pins = "gpio4", "gpio5",
+						"gpio6", "gpio7";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio4", "gpio5",
+						"gpio6", "gpio7";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se15_i2c_pins: qupv3_se15_i2c_pins {
+		qupv3_se15_i2c_active: qupv3_se15_i2c_active {
+			mux {
+				pins = "gpio36", "gpio37";
+				function = "qup15";
+			};
+
+			config {
+				pins = "gpio36", "gpio37";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep {
+			mux {
+				pins = "gpio36", "gpio37";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio36", "gpio37";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se15_spi_pins: qupv3_se15_spi_pins {
+		qupv3_se15_spi_active: qupv3_se15_spi_active {
+			mux {
+				pins = "gpio36", "gpio37",
+						"gpio38", "gpio39";
+				function = "qup15";
+			};
+
+			config {
+				pins = "gpio36", "gpio37",
+						"gpio38", "gpio39";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se15_spi_sleep: qupv3_se15_spi_sleep {
+			mux {
+				pins = "gpio36", "gpio37",
+						"gpio38", "gpio39";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio36", "gpio37",
+						"gpio38", "gpio39";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se17_2uart_pins: qupv3_se17_2uart_pins {
+		qupv3_se17_2uart_active: qupv3_se17_2uart_active {
+			mux {
+				pins = "gpio63", "gpio64";
+				function = "qup17";
+			};
+
+			config {
+				pins = "gpio63", "gpio64";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se17_2uart_sleep: qupv3_se17_2uart_sleep {
+			mux {
+				pins = "gpio63", "gpio64";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio63", "gpio64";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+	};
+
+	qupv3_se16_i2c_pins: qupv3_se16_i2c_pins {
+		qupv3_se16_i2c_active: qupv3_se16_i2c_active {
+			mux {
+				pins = "gpio70", "gpio71";
+				function = "qup16";
+			};
+
+			config {
+				pins = "gpio70", "gpio71";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se16_i2c_sleep: qupv3_se16_i2c_sleep {
+			mux {
+				pins = "gpio70", "gpio71";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio70", "gpio71";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se16_spi_pins: qupv3_se16_spi_pins {
+		qupv3_se16_spi_active: qupv3_se16_spi_active {
+			mux {
+				pins = "gpio70", "gpio71",
+						"gpio72", "gpio73";
+				function = "qup16";
+			};
+
+			config {
+				pins = "gpio70", "gpio71",
+						"gpio72", "gpio73";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se16_spi_sleep: qupv3_se16_spi_sleep {
+			mux {
+				pins = "gpio70", "gpio71",
+						"gpio72", "gpio73";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio70", "gpio71",
+						"gpio72", "gpio73";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se17_i2c_pins: qupv3_se17_i2c_pins {
+		qupv3_se17_i2c_active: qupv3_se17_i2c_active {
+			mux {
+				pins = "gpio61", "gpio62";
+				function = "qup17";
+			};
+
+			config {
+				pins = "gpio61", "gpio62";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se17_i2c_sleep: qupv3_se17_i2c_sleep {
+			mux {
+				pins = "gpio61", "gpio62";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio61", "gpio62";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se17_spi_pins: qupv3_se17_spi_pins {
+		qupv3_se17_spi_active: qupv3_se17_spi_active {
+			mux {
+				pins = "gpio61", "gpio62",
+						"gpio63", "gpio64";
+				function = "qup17";
+			};
+
+			config {
+				pins = "gpio61", "gpio62",
+						"gpio63", "gpio64";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se17_spi_sleep: qupv3_se17_spi_sleep {
+			mux {
+				pins = "gpio61", "gpio62",
+						"gpio63", "gpio64";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio61", "gpio62",
+						"gpio63", "gpio64";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se18_i2c_pins: qupv3_se18_i2c_pins {
+		qupv3_se18_i2c_active: qupv3_se18_i2c_active {
+			mux {
+				pins = "gpio66", "gpio67";
+				function = "qup18";
+			};
+
+			config {
+				pins = "gpio66", "gpio67";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se18_i2c_sleep: qupv3_se18_i2c_sleep {
+			mux {
+				pins = "gpio66", "gpio67";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio66", "gpio67";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se18_spi_pins: qupv3_se18_spi_pins {
+		qupv3_se18_spi_active: qupv3_se18_spi_active {
+			mux {
+				pins = "gpio66", "gpio67",
+						"gpio68", "gpio69";
+				function = "qup18";
+			};
+
+			config {
+				pins = "gpio66", "gpio67",
+						"gpio68", "gpio69";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se18_spi_sleep: qupv3_se18_spi_sleep {
+			mux {
+				pins = "gpio66", "gpio67",
+						"gpio68", "gpio69";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio66", "gpio67",
+						"gpio68", "gpio69";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se19_i2c_pins: qupv3_se19_i2c_pins {
+		qupv3_se19_i2c_active: qupv3_se19_i2c_active {
+			mux {
+				pins = "gpio55", "gpio56";
+				function = "qup19";
+			};
+
+			config {
+				pins = "gpio55", "gpio56";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se19_i2c_sleep: qupv3_se19_i2c_sleep {
+			mux {
+				pins = "gpio55", "gpio56";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio55", "gpio56";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se19_spi_pins: qupv3_se19_spi_pins {
+		qupv3_se19_spi_active: qupv3_se19_spi_active {
+			mux {
+				pins = "gpio55", "gpio56",
+						"gpio57", "gpio58";
+				function = "qup19";
+			};
+
+			config {
+				pins = "gpio55", "gpio56",
+						"gpio57", "gpio58";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se19_spi_sleep: qupv3_se19_spi_sleep {
+			mux {
+				pins = "gpio55", "gpio56",
+						"gpio57", "gpio58";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio55", "gpio56",
+						"gpio57", "gpio58";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se20_i2c_pins: qupv3_se20_i2c_pins {
+		qupv3_se20_i2c_active: qupv3_se20_i2c_active {
+			mux {
+				pins = "gpio87", "gpio88";
+				function = "qup20";
+			};
+
+			config {
+				pins = "gpio87", "gpio88";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se20_i2c_sleep: qupv3_se20_i2c_sleep {
+			mux {
+				pins = "gpio87", "gpio88";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio87", "gpio88";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se20_spi_pins: qupv3_se20_spi_pins {
+		qupv3_se20_spi_active: qupv3_se20_spi_active {
+			mux {
+				pins = "gpio87", "gpio88",
+						"gpio89", "gpio90";
+				function = "qup20";
+			};
+
+			config {
+				pins = "gpio87", "gpio88",
+						"gpio89", "gpio90";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se20_spi_sleep: qupv3_se20_spi_sleep {
+			mux {
+				pins = "gpio87", "gpio88",
+						"gpio89", "gpio90";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio87", "gpio88",
+						"gpio89", "gpio90";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se21_i2c_pins: qupv3_se21_i2c_pins {
+		qupv3_se21_i2c_active: qupv3_se21_i2c_active {
+			mux {
+				pins = "gpio81", "gpio82";
+				function = "qup21";
+			};
+
+			config {
+				pins = "gpio81", "gpio82";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se21_i2c_sleep: qupv3_se21_i2c_sleep {
+			mux {
+				pins = "gpio81", "gpio82";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio81", "gpio82";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se21_spi_pins: qupv3_se21_spi_pins {
+		qupv3_se21_spi_active: qupv3_se21_spi_active {
+			mux {
+				pins = "gpio81", "gpio82",
+						"gpio83", "gpio84";
+				function = "qup21";
+			};
+
+			config {
+				pins = "gpio81", "gpio82",
+						"gpio83", "gpio84";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se21_spi_sleep: qupv3_se21_spi_sleep {
+			mux {
+				pins = "gpio81", "gpio82",
+						"gpio83", "gpio84";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio81", "gpio82",
+						"gpio83", "gpio84";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se22_i2c_pins: qupv3_se22_i2c_pins {
+		qupv3_se22_i2c_active: qupv3_se22_i2c_active {
+			mux {
+				pins = "gpio85", "gpio85";
+				function = "qup22";
+			};
+
+			config {
+				pins = "gpio85", "gpio85";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se22_i2c_sleep: qupv3_se22_i2c_sleep {
+			mux {
+				pins = "gpio85", "gpio85";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio85", "gpio85";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se22_spi_pins: qupv3_se22_spi_pins {
+		qupv3_se22_spi_active: qupv3_se22_spi_active {
+			mux {
+				pins = "gpio85", "gpio86",
+						"gpio83", "gpio84";
+				function = "qup22";
+			};
+
+			config {
+				pins = "gpio85", "gpio86",
+						"gpio83", "gpio84";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se22_spi_sleep: qupv3_se22_spi_sleep {
+			mux {
+				pins = "gpio85", "gpio86",
+						"gpio83", "gpio84";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio85", "gpio86",
+						"gpio83", "gpio84";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se23_i2c_pins: qupv3_se23_i2c_pins {
+		qupv3_se23_i2c_active: qupv3_se23_i2c_active {
+			mux {
+				pins = "gpio59", "gpio60";
+				function = "qup23";
+			};
+
+			config {
+				pins = "gpio59", "gpio60";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se23_i2c_sleep: qupv3_se23_i2c_sleep {
+			mux {
+				pins = "gpio59", "gpio60";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio59", "gpio60";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se23_spi_pins: qupv3_se23_spi_pins {
+		qupv3_se23_spi_active: qupv3_se23_spi_active {
+			mux {
+				pins = "gpio59", "gpio60",
+						"gpio61", "gpio62";
+				function = "qup23";
+			};
+
+			config {
+				pins = "gpio59", "gpio60",
+						"gpio61", "gpio62";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se23_spi_sleep: qupv3_se23_spi_sleep {
+			mux {
+				pins = "gpio59", "gpio60",
+						"gpio61", "gpio62";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio59", "gpio60",
+						"gpio61", "gpio62";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	tps_i2c_intr: tps_i2c_intr {
+		mux {
+			pins = "gpio138";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio138";
+			drive-strength = <2>;
+			bias-pull-up;
+			input-enable;
+		};
+	};
+
+	pcie0 {
+		pcie2a_perst_default: pcie2a_perst_default {
+			mux {
+				pins = "gpio143";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio143";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		pcie2a_clkreq_default: pcie2a_clkreq_default {
+			mux {
+				pins = "gpio142";
+				function = "pcie2a_clkreq";
+			};
+
+			config {
+				pins = "gpio142";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie2a_wake_default: pcie2a_wake_default {
+			mux {
+				pins = "gpio145";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio145";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie2a_clkreq_sleep: pcie2a_clkreq_sleep {
+			mux {
+				pins = "gpio142";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio142";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+	};
+
+	pcie1 {
+		pcie2b_perst_default: pcie2b_perst_default {
+			mux {
+				pins = "gpio147";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio147";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		pcie2b_clkreq_default: pcie2b_clkreq_default {
+			mux {
+				pins = "gpio144";
+				function = "pcie2b_clkreq";
+			};
+
+			config {
+				pins = "gpio144";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie2b_wake_default: pcie2b_wake_default {
+			mux {
+				pins = "gpio146";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio146";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie2b_clkreq_sleep: pcie2b_clkreq_sleep {
+			mux {
+				pins = "gpio144";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio144";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+	};
+
+	pcie2 {
+		pcie3a_perst_default: pcie3a_perst_default {
+			mux {
+				pins = "gpio151";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio151";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		pcie3a_clkreq_default: pcie3a_clkreq_default {
+			mux {
+				pins = "gpio150";
+				function = "pcie3a_clkreq";
+			};
+
+			config {
+				pins = "gpio150";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie3a_wake_default: pcie3a_wake_default {
+			mux {
+				pins = "gpio56";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio56";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie3a_clkreq_sleep: pcie3a_clkreq_sleep {
+			mux {
+				pins = "gpio150";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio150";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+	};
+
+	pcie3 {
+		pcie3b_perst_default: pcie3b_perst_default {
+			mux {
+				pins = "gpio153";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio153";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		pcie3b_clkreq_default: pcie3b_clkreq_default {
+			mux {
+				pins = "gpio152";
+				function = "pcie3b_clkreq";
+			};
+
+			config {
+				pins = "gpio152";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie3b_wake_default: pcie3b_wake_default {
+			mux {
+				pins = "gpio130";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio130";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie3b_clkreq_sleep: pcie3b_clkreq_sleep {
+			mux {
+				pins = "gpio152";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio152";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+	};
+
+	pcie4 {
+		pcie4_perst_default: pcie4_perst_default {
+			mux {
+				pins = "gpio141";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio141";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		pcie4_clkreq_default: pcie4_clkreq_default {
+			mux {
+				pins = "gpio140";
+				function = "pcie4_clkreq";
+			};
+
+			config {
+				pins = "gpio140";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie4_wake_default: pcie4_wake_default {
+			mux {
+				pins = "gpio139";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio139";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		pcie4_clkreq_sleep: pcie4_clkreq_sleep {
+			mux {
+				pins = "gpio140";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio140";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+	};
+
+	cnss_pins: cnss_pins {
+		cnss_wlan_en_active: cnss_wlan_en_active {
+			mux {
+				pins = "gpio125";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio125";
+				drive-strength = <16>;
+				output-high;
+				bias-pull-up;
+			};
+		};
+
+		cnss_wlan_en_sleep: cnss_wlan_en_sleep {
+			mux {
+				pins = "gpio125";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio125";
+				drive-strength = <2>;
+				output-low;
+				bias-pull-down;
+			};
+		};
+	};
+
+	bt_en_active: bt_en_active {
+		mux {
+			pins = "gpio126";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio126";
+			drive-strength = <2>;
+			bias-pull-down;
+		};
+	};
+
+	conn_power_1p8_active: conn_power_1p8_active {
+		mux {
+			pins = "gpio128";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio128";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	conn_power_pa_active: conn_power_pa_active {
+		mux {
+			pins = "gpio129";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio129";
+			drive-strength = <2>;
+			bias-pull-up;
+		};
+	};
+
+	emac {
+		emac_mdc: emac_mdc {
+			mux {
+				pins = "gpio175";
+				function = "rgmii_0";
+			};
+
+			config {
+				pins = "gpio175";
+				bias-pull-up;
+				drive-strength = <16>;
+			};
+		};
+
+		emac_mdio: emac_mdio {
+			mux {
+				pins = "gpio176";
+				function = "rgmii_0";
+			};
+
+			config {
+				pins = "gpio176";
+				bias-pull-up;
+				drive-strength = <16>;
+			};
+		};
+
+		emac_rgmii_txd0: emac_rgmii_txd0 {
+			mux {
+				pins = "gpio185";
+				function = "rgmii_0";
+			};
+
+			config {
+				pins = "gpio185";
+				bias-pull-up;
+				drive-strength = <16>;
+			};
+		};
+
+		emac_rgmii_txd1: emac_rgmii_txd1 {
+			mux {
+				pins = "gpio186";
+				function = "rgmii_0";
+			};
+
+			config {
+				pins = "gpio186";
+				bias-pull-up;
+				drive-strength = <16>;
+			};
+		};
+
+		emac_rgmii_txd2: emac_rgmii_txd2 {
+			mux {
+				pins = "gpio187";
+				function = "rgmii_0";
+			};
+
+			config {
+				pins = "gpio187";
+				bias-pull-up;
+				drive-strength = <16>;
+			};
+		};
+
+		emac_rgmii_txd3: emac_rgmii_txd3 {
+			mux {
+				pins = "gpio188";
+				function = "rgmii_0";
+			};
+
+			config {
+				pins = "gpio188";
+				bias-pull-up;
+				drive-strength = <16>;
+			};
+		};
+
+		emac_rgmii_txc: emac_rgmii_txc {
+			mux {
+				pins = "gpio183";
+				function = "rgmii_0";
+			};
+
+			config {
+				pins = "gpio183";
+				bias-pull-up;
+				drive-strength = <16>;
+			};
+		};
+
+		emac_rgmii_tx_ctl: emac_rgmii_tx_ctl {
+			mux {
+				pins = "gpio184";
+				function = "rgmii_0";
+			};
+
+			config {
+				pins = "gpio184";
+				bias-pull-up;
+				drive-strength = <16>;
+			};
+		};
+
+		emac_rgmii_rxd0: emac_rgmii_rxd0 {
+			mux {
+				pins = "gpio179";
+				function = "rgmii_0";
+			};
+
+			config {
+				pins = "gpio179";
+				bias-disable;  /* NO pull */
+				drive-strength = <16>;  /* 16MA */
+			};
+		};
+
+		emac_rgmii_rxd1: emac_rgmii_rxd1 {
+			mux {
+				pins = "gpio180";
+				function = "rgmii_0";
+			};
+
+			config {
+				pins = "gpio180";
+				bias-disable;  /* NO pull */
+				drive-strength = <16>;
+			};
+		};
+
+		emac_rgmii_rxd2: emac_rgmii_rxd2 {
+			mux {
+				pins = "gpio181";
+				function = "rgmii_0";
+			};
+
+			config {
+				pins = "gpio181";
+				bias-disable;	/* NO pull */
+				drive-strength = <16>;
+			};
+		};
+
+		emac_rgmii_rxd3: emac_rgmii_rxd3 {
+			mux {
+				pins = "gpio182";
+				function = "rgmii_0";
+			};
+
+			config {
+				pins = "gpio182";
+				bias-disable;	/* NO pull */
+				drive-strength = <16>;
+			};
+		};
+
+		emac_rgmii_rxc: emac_rgmii_rxc {
+			mux {
+				pins = "gpio177";
+				function = "rgmii_0";
+			};
+
+			config {
+				pins = "gpio177";
+				bias-disable;	/* NO pull */
+				drive-strength = <16>;
+			};
+		};
+
+		emac_rgmii_rx_ctl: emac_rgmii_rx_ctl {
+			mux {
+				pins = "gpio178";
+				function = "rgmii_0";
+			};
+
+			config {
+				pins = "gpio178";
+				bias-disable;  /* NO pull */
+				drive-strength = <16>;
+			};
+		};
+
+	};
+
+	pri_tdm {
+		pri_tdm_sck_sleep: pri_tdm_sck_sleep {
+			mux {
+				pins = "gpio93";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio93";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		pri_tdm_sck_active: pri_tdm_sck_active {
+			mux {
+				pins = "gpio93";
+				function = "mi2s0_sck";
+			};
+
+			config {
+				pins = "gpio93";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+
+		pri_tdm_ws_sleep: pri_tdm_ws_sleep {
+			mux {
+				pins = "gpio94";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio94";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		pri_tdm_ws_active: pri_tdm_ws_active {
+			mux {
+				pins = "gpio94";
+				function = "mi2s0_ws";
+			};
+
+			config {
+				pins = "gpio94";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	pri_tdm_din {
+		pri_tdm_din_sleep: pri_tdm_din_sleep {
+			mux {
+				pins = "gpio95";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio95";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		pri_tdm_din_active: pri_tdm_din_active {
+			mux {
+				pins = "gpio95";
+				function = "mi2s0_data0";
+			};
+
+			config {
+				pins = "gpio95";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	pri_tdm_dout {
+		pri_tdm_dout_sleep: pri_tdm_dout_sleep {
+			mux {
+				pins = "gpio96";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio96";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		pri_tdm_dout_active: pri_tdm_dout_active {
+			mux {
+				pins = "gpio96";
+				function = "mi2s0_data1";
+			};
+
+			config {
+				pins = "gpio96";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+
+	tert_tdm {
+		tert_tdm_sck_sleep: tert_tdm_sck_sleep {
+			mux {
+				pins = "gpio212";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio212";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_tdm_sck_active: tert_tdm_sck_active {
+			mux {
+				pins = "gpio212";
+				function = "mi2s2_sck";
+			};
+
+			config {
+				pins = "gpio212";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+
+		tert_tdm_ws_sleep: tert_tdm_ws_sleep {
+			mux {
+				pins = "gpio213";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio213";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_tdm_ws_active: tert_tdm_ws_active {
+			mux {
+				pins = "gpio213";
+				function = "mi2s2_ws";
+			};
+
+			config {
+				pins = "gpio213";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	tert_tdm_din {
+		tert_tdm_din_sleep: tert_tdm_din_sleep {
+			mux {
+				pins = "gpio214";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio214";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_tdm_din_active: tert_tdm_din_active {
+			mux {
+				pins = "gpio214";
+				function = "mi2s2_data0";
+			};
+
+			config {
+				pins = "gpio214";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+			};
+		};
+	};
+
+	tert_tdm_dout {
+		tert_tdm_dout_sleep: tert_tdm_dout_sleep {
+			mux {
+				pins = "gpio215";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio215";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		tert_tdm_dout_active: tert_tdm_dout_active {
+			mux {
+				pins = "gpio215";
+				function = "mi2s2_data1";
+			};
+
+			config {
+				pins = "gpio215";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	audio_internal_mclk1_active: audio_internal_mclk1_active {
+		mux {
+			pins = "gpio80";
+			function = "mi2s_mclk1";
+		};
+
+		config {
+			pins = "gpio80";
+			drive-strength = <8>;
+			bias-disable;
+			output-high;
+		};
+	};
+
+	audio_internal_mclk1_sleep: audio_internal_mclk1_sleep {
+		mux {
+			pins = "gpio80";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio80";
+			drive-strength = <2>;
+			bias-pull-down;
+		};
+	};
+
+	cci0_active: cci0_active {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio113","gpio114";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio113","gpio114";
+			bias-pull-up; /* PULL UP*/
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci0_suspend: cci0_suspend {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio113","gpio114";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio113","gpio114";
+			bias-pull-down; /* PULL DOWN */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci1_active: cci1_active {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio115","gpio116";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio115","gpio116";
+			bias-pull-up; /* PULL UP*/
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci1_suspend: cci1_suspend {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio115","gpio116";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio115","gpio116";
+			bias-pull-down; /* PULL DOWN */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci2_active: cci2_active {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio10","gpio11";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio10","gpio11";
+			bias-pull-up; /* PULL UP*/
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci2_suspend: cci2_suspend {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio10","gpio11";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio10","gpio11";
+			bias-pull-down; /* PULL DOWN */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci3_active: cci3_active {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio123","gpio124";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio123","gpio124";
+			bias-pull-up; /* PULL UP*/
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci3_suspend: cci3_suspend {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio123","gpio124";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio123","gpio124";
+			bias-pull-down; /* PULL DOWN */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci4_active: cci4_active {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio117","gpio118";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio117","gpio118";
+			bias-pull-up; /* PULL UP*/
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci4_suspend: cci4_suspend {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio117","gpio118";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio117","gpio118";
+			bias-pull-down; /* PULL DOWN */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci5_active: cci5_active {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio12","gpio13";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio12","gpio13";
+			bias-pull-up; /* PULL UP*/
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci5_suspend: cci5_suspend {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio12","gpio13";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio12","gpio13";
+			bias-pull-down; /* PULL DOWN */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci6_active: cci6_active {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio145","gpio146";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio145","gpio146";
+			bias-pull-up; /* PULL UP*/
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci6_suspend: cci6_suspend {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio145","gpio146";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio145","gpio146";
+			bias-pull-down; /* PULL DOWN */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci7_active: cci7_active {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio164","gpio165";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio164","gpio165";
+			bias-pull-up; /* PULL UP*/
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cci7_suspend: cci7_suspend {
+		mux {
+			/* CLK, DATA */
+			pins = "gpio164","gpio165";
+			function = "cci_i2c";
+		};
+
+		config {
+			pins = "gpio164","gpio165";
+			bias-pull-down; /* PULL DOWN */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cam_sensor0_active: cam_sensor0_active {
+		/* intr gpio for bridge chip 0 */
+		mux {
+			pins = "gpio162";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio162";
+			bias-pull-up; /* PULL UP */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cam_sensor0_suspend: cam_sensor0_suspend {
+		/* intr gpio for bridge chip 0 */
+		mux {
+			pins = "gpio162";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio162";
+			bias-pull-down; /* PULL DOWN */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cam_sensor1_active: cam_sensor1_active {
+		/* intr gpio for bridge chip 1 */
+		mux {
+			pins = "gpio163";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio163";
+			bias-pull-up; /* PULL UP*/
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cam_sensor1_suspend: cam_sensor1_suspend {
+		/* intr gpio for bridge chip 1 */
+		mux {
+			pins = "gpio163";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio163";
+			bias-pull-down; /* PULL DOWN */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cam_sensor2_active: cam_sensor2_active {
+		/* intr gpio for bridge chip 2 */
+		mux {
+			pins = "gpio16";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio16";
+			bias-pull-up; /* PULL UP */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cam_sensor2_suspend: cam_sensor2_suspend {
+		/* intr gpio for bridge chip 2 */
+		mux {
+			pins = "gpio16";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio16";
+			bias-pull-down; /* PULL DOWN */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cam_sensor3_active: cam_sensor3_active {
+		/* intr gpio for bridge chip 3 */
+		mux {
+			pins = "gpio17";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio17";
+			bias-pull-up; /* PULL UP */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	cam_sensor3_suspend: cam_sensor3_suspend {
+		/* intr gpio for bridge chip 3 */
+		mux {
+			pins = "gpio17";
+			function = "gpio";
+		};
+
+		config {
+			pins = "gpio17";
+			bias-pull-down; /* PULL DOWN */
+			drive-strength = <2>; /* 2 MA */
+		};
+	};
+
+	usb0_phy_ps: usb0_phy_ps {
+		usb3phy0_portselect_default: usb3phy0_portselect_default {
+			mux {
+				pins = "gpio166";
+				function = "usb0_phy";
+			};
+
+			config {
+				pins = "gpio166";
+				bias-disable;
+				drive-strength = <2>;
+			};
+		};
+	};
+
+	usb1_phy_ps: usb1_phy_ps {
+		usb3phy1_portselect_default: usb3phy1_portselect_default {
+			mux {
+				pins = "gpio49";
+				function = "usb1_phy";
+			};
+
+			config {
+				pins = "gpio49";
+				bias-disable;
+				drive-strength = <2>;
+			};
+		};
+	};
+
+	hs1_i2s_sck {
+		hs1_i2s_sck_sleep: hs1_i2s_sck_sleep {
+			mux {
+				pins = "gpio208";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio208";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs1_i2s_sck_active: hs1_i2s_sck_active {
+			mux {
+				pins = "gpio208";
+				function = "hs1_mi2s";
+			};
+
+			config {
+				pins = "gpio208";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs1_i2s_ws {
+		hs1_i2s_ws_sleep: hs1_i2s_ws_sleep {
+			mux {
+				pins = "gpio209";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio209";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs1_i2s_ws_active: hs1_i2s_ws_active {
+			mux {
+				pins = "gpio209";
+				function = "hs1_mi2s";
+			};
+
+			config {
+				pins = "gpio209";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs1_i2s_data0 {
+		hs1_i2s_data0_sleep: hs1_i2s_data0_sleep {
+			mux {
+				pins = "gpio210";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio210";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs1_i2s_data0_active: hs1_i2s_data0_active {
+			mux {
+				pins = "gpio210";
+				function = "hs1_mi2s";
+			};
+
+			config {
+				pins = "gpio210";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs1_i2s_data1 {
+		hs1_i2s_data1_sleep: hs1_i2s_data1_sleep {
+			mux {
+				pins = "gpio211";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio211";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs1_i2s_data1_active: hs1_i2s_data1_active {
+			mux {
+				pins = "gpio211";
+				function = "hs1_mi2s";
+			};
+
+			config {
+				pins = "gpio211";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				input-enable;
+			};
+		};
+	};
+
+	hs2_i2s_sck {
+		hs2_i2s_sck_sleep: hs2_i2s_sck_sleep {
+			mux {
+				pins = "gpio92";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio92";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs2_i2s_sck_active: hs2_i2s_sck_active {
+			mux {
+				pins = "gpio92";
+				function = "hs2_mi2s";
+			};
+
+			config {
+				pins = "gpio92";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs2_i2s_ws {
+		hs2_i2s_ws_sleep: hs2_i2s_ws_sleep {
+			mux {
+				pins = "gpio91";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio91";
+				drive-strength = <2>;   /* 8 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs2_i2s_ws_active: hs2_i2s_ws_active {
+			mux {
+				pins = "gpio91";
+				function = "hs2_mi2s";
+			};
+
+			config {
+				pins = "gpio91";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs2_i2s_data0 {
+		hs2_i2s_data0_sleep: hs2_i2s_data0_sleep {
+			mux {
+				pins = "gpio218";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio218";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs2_i2s_data0_active: hs2_i2s_data0_active {
+			mux {
+				pins = "gpio218";
+				function = "hs2_mi2s";
+			};
+
+			config {
+				pins = "gpio218";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs2_i2s_data1 {
+		hs2_i2s_data1_sleep: hs2_i2s_data1_sleep {
+			mux {
+				pins = "gpio219";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio219";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs2_i2s_data1_active: hs2_i2s_data1_active {
+			mux {
+				pins = "gpio219";
+				function = "hs2_mi2s";
+			};
+
+			config {
+				pins = "gpio219";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				input-enable;
+			};
+		};
+	};
+
+	hs3_i2s_sck {
+		hs3_i2s_sck_sleep: hs3_i2s_sck_sleep {
+			mux {
+				pins = "gpio224";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio224";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs3_i2s_sck_active: hs3_i2s_sck_active {
+			mux {
+				pins = "gpio224";
+				function = "hs3_mi2s";
+			};
+
+			config {
+				pins = "gpio224";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs3_i2s_ws {
+		hs3_i2s_ws_sleep: hs3_i2s_ws_sleep {
+			mux {
+				pins = "gpio225";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio225";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs3_i2s_ws_active: hs3_i2s_ws_active {
+			mux {
+				pins = "gpio225";
+				function = "hs3_mi2s";
+			};
+
+			config {
+				pins = "gpio225";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs3_i2s_data0 {
+		hs3_i2s_data0_sleep: hs3_i2s_data0_sleep {
+			mux {
+				pins = "gpio226";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio226";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs3_i2s_data0_active: hs3_i2s_data0_active {
+			mux {
+				pins = "gpio226";
+				function = "hs3_mi2s";
+			};
+
+			config {
+				pins = "gpio226";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs3_i2s_data1 {
+		hs3_i2s_data1_sleep: hs3_i2s_data1_sleep {
+			mux {
+				pins = "gpio227";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio227";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs3_i2s_data1_active: hs3_i2s_data1_active {
+			mux {
+				pins = "gpio227";
+				function = "hs3_mi2s";
+			};
+
+			config {
+				pins = "gpio227";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				input-enable;
+			};
+		};
+	};
+
+	hs4_i2s_sck {
+		hs4_i2s_sck_sleep: hs4_i2s_sck_sleep {
+			mux {
+				pins = "gpio220";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio220";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs4_i2s_sck_active: hs4_i2s_sck_active {
+			mux {
+				pins = "gpio220";
+				function = "mi2s1_sck";
+			};
+
+			config {
+				pins = "gpio220";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs4_i2s_ws {
+		hs4_i2s_ws_sleep: hs4_i2s_ws_sleep {
+			mux {
+				pins = "gpio221";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio221";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs4_i2s_ws_active: hs4_i2s_ws_active {
+			mux {
+				pins = "gpio221";
+				function = "mi2s1_ws";
+			};
+
+			config {
+				pins = "gpio221";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs4_i2s_data0 {
+		hs4_i2s_data0_sleep: hs4_i2s_data0_sleep {
+			mux {
+				pins = "gpio222";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio222";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs4_i2s_data0_active: hs4_i2s_data0_active {
+			mux {
+				pins = "gpio222";
+				function = "mi2s1_data0";
+			};
+
+			config {
+				pins = "gpio222";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs4_i2s_data1 {
+		hs4_i2s_data1_sleep: hs4_i2s_data1_sleep {
+			mux {
+				pins = "gpio223";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio223";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs4_i2s_data1_active: hs4_i2s_data1_active {
+			mux {
+				pins = "gpio223";
+				function = "mi2s1_data1";
+			};
+
+			config {
+				pins = "gpio223";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				input-enable;
+			};
+		};
+	};
+
+	hs5_i2s_sck {
+		hs5_i2s_sck_sleep: hs5_i2s_sck_sleep {
+			mux {
+				pins = "gpio212";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio212";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs5_i2s_sck_active: hs5_i2s_sck_active {
+			mux {
+				pins = "gpio212";
+				function = "mi2s2_sck";
+			};
+
+			config {
+				pins = "gpio212";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs5_i2s_ws {
+		hs5_i2s_ws_sleep: hs5_i2s_ws_sleep {
+			mux {
+				pins = "gpio213";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio213";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs5_i2s_ws_active: hs5_i2s_ws_active {
+			mux {
+				pins = "gpio213";
+				function = "mi2s2_ws";
+			};
+
+			config {
+				pins = "gpio213";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs5_i2s_data0 {
+		hs5_i2s_data0_sleep: hs5_i2s_data0_sleep {
+			mux {
+				pins = "gpio214";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio214";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs5_i2s_data0_active: hs5_i2s_data0_active {
+			mux {
+				pins = "gpio214";
+				function = "mi2s2_data0";
+			};
+
+			config {
+				pins = "gpio214";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				output-high;
+			};
+		};
+	};
+
+	hs5_i2s_data1 {
+		hs5_i2s_data1_sleep: hs5_i2s_data1_sleep {
+			mux {
+				pins = "gpio215";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio215";
+				drive-strength = <2>;   /* 2 mA */
+				bias-pull-down;         /* PULL DOWN */
+				input-enable;
+			};
+		};
+
+		hs5_i2s_data1_active: hs5_i2s_data1_active {
+			mux {
+				pins = "gpio215";
+				function = "mi2s2_data1";
+			};
+
+			config {
+				pins = "gpio215";
+				drive-strength = <8>;   /* 8 mA */
+				bias-disable;           /* NO PULL */
+				input-enable;
+			};
+		};
+	};
+};
diff --git a/qcom/direwolf-qupv3.dtsi b/qcom/direwolf-qupv3.dtsi
new file mode 100755
index 00000000..a9926ffe
--- /dev/null
+++ b/qcom/direwolf-qupv3.dtsi
@@ -0,0 +1,995 @@
+&soc {
+	/* QUPv3 SE Instances
+	 * Qup0 0: SE 0
+	 * Qup0 1: SE 1
+	 * Qup0 2: SE 2
+	 * Qup0 3: SE 3
+	 * Qup0 4: SE 4
+	 * Qup0 5: SE 5
+	 * Qup0 6: SE 6
+	 * Qup0 7: SE 7
+	 * Qup1 0: SE 8
+	 * Qup1 1: SE 9
+	 * Qup1 2: SE 10
+	 * Qup1 3: SE 11
+	 * Qup1 4: SE 12
+	 * Qup1 5: SE 13
+	 * Qup1 6: SE 14
+	 * Qup1 7: SE 15
+	 * Qup2 0: SE 16
+	 * Qup2 1: SE 17
+	 * Qup2 2: SE 18
+	 * Qup2 3: SE 19
+	 * Qup2 4: SE 20
+	 * Qup2 5: SE 21
+	 * Qup2 6: SE 22
+	 * Qup2 7: SE 23
+	 */
+
+	/* GPI Instance */
+	gpi_dma0: qcom,gpi-dma@900000 {
+		compatible = "qcom,gpi-dma";
+		#dma-cells = <5>;
+		reg = <0x900000 0x60000>;
+		reg-names = "gpi-top";
+		iommus = <&apps_smmu 0x576 0x0>;
+		qcom,max-num-gpii = <12>;
+		interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,gpii-mask = <0xfff>;
+		qcom,ev-factor = <2>;
+		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+		qcom,gpi-ee-offset = <0x10000>;
+		dma-coherent;
+		status = "ok";
+	};
+
+	/* QUPv3_0  wrapper  instance */
+	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0x9c0000 0x2000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		iommus = <&apps_smmu 0x563 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		status = "ok";
+
+		qupv3_se0_i2c: i2c@980000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x980000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se0_i2c_active>;
+			pinctrl-1 = <&qupv3_se0_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se0_spi: spi@980000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x980000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se0_spi_active>;
+			pinctrl-1 = <&qupv3_se0_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se1_i2c: i2c@984000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x984000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se1_i2c_active>;
+			pinctrl-1 = <&qupv3_se1_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se1_spi: spi@984000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x984000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se1_spi_active>;
+			pinctrl-1 = <&qupv3_se1_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se2_i2c: i2c@988000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x988000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se2_i2c_active>;
+			pinctrl-1 = <&qupv3_se2_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se2_spi: spi@988000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x988000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se2_spi_active>;
+			pinctrl-1 = <&qupv3_se2_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		/* 4-wire HSUART Instance */
+		qupv3_se2_4uart: qcom,qup_uart@988000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0x988000 0x4000>;
+			reg-names = "se_phys";
+			interrupts-extended = <&intc GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
+							<&tlmm 124 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+			pinctrl-names = "default", "active", "sleep";
+			pinctrl-0 = <&qupv3_se2_default_cts>,
+						<&qupv3_se2_default_rtsrx>, <&qupv3_se2_default_tx>;
+			pinctrl-1 = <&qupv3_se2_ctsrx>, <&qupv3_se2_rts>,
+						<&qupv3_se2_tx>;
+			pinctrl-2 = <&qupv3_se2_ctsrx>, <&qupv3_se2_rts>,
+						<&qupv3_se2_tx>;
+			qcom,wakeup-byte = <0xFD>;
+			status = "disabled";
+		};
+
+		qupv3_se3_i2c: i2c@98c000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x98c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se3_i2c_active>;
+			pinctrl-1 = <&qupv3_se3_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se3_spi: spi@98c000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x98c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se3_spi_active>;
+			pinctrl-1 = <&qupv3_se3_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		/* HS UART Instance */
+		qupv3_se3_4uart: qcom,qup_uart@98c000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0x98c000 0x4000>;
+			reg-names = "se_phys";
+			interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
+					<&tlmm 135 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+			pinctrl-names = "default", "active", "sleep", "shutdown";
+			pinctrl-0 = <&qupv3_se3_default_cts>,
+			<&qupv3_se3_default_rtsrx>, <&qupv3_se3_default_tx>;
+			pinctrl-1 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>,
+			<&qupv3_se3_tx>;
+			pinctrl-2 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>,
+			<&qupv3_se3_tx>;
+			pinctrl-3 = <&qupv3_se3_default_cts>,
+			<&qupv3_se3_default_rtsrx>, <&qupv3_se3_default_tx>;
+			qcom,wakeup-byte = <0xFD>;
+			status = "disabled";
+		};
+
+		qupv3_se4_i2c: i2c@990000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x990000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se4_i2c_active>;
+			pinctrl-1 = <&qupv3_se4_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se4_spi: spi@990000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x990000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se4_spi_active>;
+			pinctrl-1 = <&qupv3_se4_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se5_i2c: i2c@994000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x994000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se5_i2c_active>;
+			pinctrl-1 = <&qupv3_se5_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se5_spi: spi@994000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x994000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se5_spi_active>;
+			pinctrl-1 = <&qupv3_se5_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se6_i2c: i2c@998000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x998000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se6_i2c_active>;
+			pinctrl-1 = <&qupv3_se6_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se6_spi: spi@998000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x998000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se6_spi_active>;
+			pinctrl-1 = <&qupv3_se6_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se6_4uart: qcom,qup_uart@998000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0x998000 0x4000>;
+			reg-names = "se_phys";
+			interrupts = <&intc GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+			pinctrl-names = "default", "active", "sleep", "shutdown";
+			pinctrl-0 = <&qupv3_se6_default_cts>,
+			<&qupv3_se6_default_rtsrx>, <&qupv3_se6_default_tx>;
+			pinctrl-1 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
+			<&qupv3_se6_tx>;
+			pinctrl-2 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
+			<&qupv3_se6_tx>;
+			pinctrl-3 = <&qupv3_se6_default_cts>,
+			<&qupv3_se6_default_rtsrx>, <&qupv3_se6_default_tx>;
+			qcom,wakeup-byte = <0xFD>;
+			status = "disabled";
+		};
+
+		qupv3_se7_i2c: i2c@99c000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x99c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se7_i2c_active>;
+			pinctrl-1 = <&qupv3_se7_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se7_spi: spi@99c000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x99c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se7_spi_active>;
+			pinctrl-1 = <&qupv3_se7_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+	};
+
+	/* GPI Instance */
+	gpi_dma1: qcom,gpi-dma@a00000  {
+		compatible = "qcom,gpi-dma";
+		#dma-cells = <5>;
+		reg = <0xa00000  0x60000>;
+		reg-names = "gpi-top";
+		iommus = <&apps_smmu 0x96 0x0>;
+		qcom,max-num-gpii = <12>;
+		interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,gpii-mask = <0xfff>;
+		qcom,ev-factor = <2>;
+		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+		qcom,gpi-ee-offset = <0x10000>;
+		dma-coherent;
+		status = "ok";
+	};
+
+	/* QUPv3_1  wrapper  instance */
+	qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0xac0000 0x2000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		iommus = <&apps_smmu 0x83 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		status = "ok";
+
+		qupv3_se8_i2c: i2c@a80000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa80000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se8_i2c_active>;
+			pinctrl-1 = <&qupv3_se8_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se8_spi: spi@a80000 {
+			compatible = "qcom,spi-geni";
+			reg = <0xa80000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se8_spi_active>;
+			pinctrl-1 = <&qupv3_se8_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se9_i2c: i2c@a84000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa84000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se9_i2c_active>;
+			pinctrl-1 = <&qupv3_se9_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se9_spi: spi@a84000 {
+			compatible = "qcom,spi-geni";
+			reg = <0xa84000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se9_spi_active>;
+			pinctrl-1 = <&qupv3_se9_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se10_i2c: i2c@a88000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa88000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se10_i2c_active>;
+			pinctrl-1 = <&qupv3_se10_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se10_spi: spi@a88000 {
+			compatible = "qcom,spi-geni";
+			reg = <0xa88000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se10_spi_active>;
+			pinctrl-1 = <&qupv3_se10_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se10_4uart: qcom,qup_uart@a88000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0xa88000 0x4000>;
+			reg-names = "se_phys";
+			interrupts = <&intc GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts-extended = <&intc GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
+					<&tlmm 25 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+			pinctrl-names = "default", "active", "sleep", "shutdown";
+			pinctrl-0 = <&qupv3_se10_default_cts>,
+			<&qupv3_se10_default_rtsrx>, <&qupv3_se10_default_tx>;
+			pinctrl-1 = <&qupv3_se10_ctsrx>, <&qupv3_se10_rts>,
+			<&qupv3_se10_tx>;
+			pinctrl-2 = <&qupv3_se10_ctsrx>, <&qupv3_se10_rts>,
+			<&qupv3_se10_tx>;
+			pinctrl-3 = <&qupv3_se10_default_cts>,
+			<&qupv3_se10_default_rtsrx>, <&qupv3_se10_default_tx>;
+			qcom,wakeup-byte = <0xFD>;
+			status = "disabled";
+		};
+
+		qupv3_se11_i2c: i2c@a8c000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa8c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se11_i2c_active>;
+			pinctrl-1 = <&qupv3_se11_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se11_spi: spi@a8c000 {
+			compatible = "qcom,spi-geni";
+			reg = <0xa8c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se11_spi_active>;
+			pinctrl-1 = <&qupv3_se11_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se12_i2c: i2c@a90000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa90000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se12_i2c_active>;
+			pinctrl-1 = <&qupv3_se12_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se12_spi: spi@a90000 {
+			compatible = "qcom,spi-geni";
+			reg = <0xa90000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se12_spi_active>;
+			pinctrl-1 = <&qupv3_se12_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se13_i2c: i2c@a94000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa94000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se13_i2c_active>;
+			pinctrl-1 = <&qupv3_se13_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se13_spi: spi@a94000 {
+			compatible = "qcom,spi-geni";
+			reg = <0xa94000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se13_spi_active>;
+			pinctrl-1 = <&qupv3_se13_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se13_2uart: qcom,qup_uart@a94000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0xa94000 0x4000>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se13_2uart_default>;
+			pinctrl-1 = <&qupv3_se13_2uart_active>;
+			pinctrl-2 = <&qupv3_se13_2uart_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se14_i2c: i2c@a98000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa98000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se14_i2c_active>;
+			pinctrl-1 = <&qupv3_se14_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se14_spi: spi@a98000 {
+			compatible = "qcom,spi-geni";
+			reg = <0xa98000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se14_spi_active>;
+			pinctrl-1 = <&qupv3_se14_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se15_i2c: i2c@a9c000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa9c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se15_i2c_active>;
+			pinctrl-1 = <&qupv3_se15_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se15_spi: spi@a9c000 {
+			compatible = "qcom,spi-geni";
+			reg = <0xa9c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se15_spi_active>;
+			pinctrl-1 = <&qupv3_se15_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+	};
+
+	/* GPI Instance */
+	gpi_dma2: qcom,gpi-dma@800000  {
+		compatible = "qcom,gpi-dma";
+		#dma-cells = <5>;
+		reg = <0x800000  0x60000>;
+		reg-names = "gpi-top";
+		iommus = <&apps_smmu 0xb6 0x0>;
+		qcom,max-num-gpii = <12>;
+		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,gpii-mask = <0xfff>;
+		qcom,ev-factor = <2>;
+		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+		qcom,gpi-ee-offset = <0x10000>;
+		dma-coherent;
+		status = "ok";
+	};
+
+	/* QUPv3_2  wrapper  instance */
+	qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0x8c0000 0x2000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		iommus = <&apps_smmu 0xa3  0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		status = "ok";
+
+		qupv3_se16_i2c: i2c@880000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x880000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se16_i2c_active>;
+			pinctrl-1 = <&qupv3_se16_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se16_spi: spi@880000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x880000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se16_spi_active>;
+			pinctrl-1 = <&qupv3_se16_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se17_i2c: i2c@884000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x884000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se17_i2c_active>;
+			pinctrl-1 = <&qupv3_se17_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se17_spi: spi@884000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x884000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se17_spi_active>;
+			pinctrl-1 = <&qupv3_se17_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		/* Debug UART Instance */
+		qupv3_se17_2uart: qcom,qup_uart@884000 {
+			compatible = "qcom,geni-debug-uart";
+			reg = <0x884000 0x4000>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se17_2uart_active>;
+			pinctrl-1 = <&qupv3_se17_2uart_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se18_i2c: i2c@888000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x888000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se18_i2c_active>;
+			pinctrl-1 = <&qupv3_se18_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se18_spi: spi@888000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x888000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se18_spi_active>;
+			pinctrl-1 = <&qupv3_se18_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se19_i2c: i2c@88c000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x88c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se19_i2c_active>;
+			pinctrl-1 = <&qupv3_se19_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se19_spi: spi@88c000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x88c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se19_spi_active>;
+			pinctrl-1 = <&qupv3_se19_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se20_i2c: i2c@890000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x890000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se20_i2c_active>;
+			pinctrl-1 = <&qupv3_se20_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se20_spi: spi@890000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x890000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se20_spi_active>;
+			pinctrl-1 = <&qupv3_se20_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se21_i2c: i2c@894000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x894000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se21_i2c_active>;
+			pinctrl-1 = <&qupv3_se21_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se21_spi: spi@894000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x894000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se21_spi_active>;
+			pinctrl-1 = <&qupv3_se21_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se22_i2c: i2c@898000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x898000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se22_i2c_active>;
+			pinctrl-1 = <&qupv3_se22_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se22_spi: spi@898000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x898000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se22_spi_active>;
+			pinctrl-1 = <&qupv3_se22_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se23_i2c: i2c@89c000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x89c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se23_i2c_active>;
+			pinctrl-1 = <&qupv3_se23_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se23_spi: spi@89c000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x89c000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se23_spi_active>;
+			pinctrl-1 = <&qupv3_se23_spi_sleep>;
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/qcom/direwolf-vm-la-overlay.dts b/qcom/direwolf-vm-la-overlay.dts
index d2cf8a1e..712e4032 100755
--- a/qcom/direwolf-vm-la-overlay.dts
+++ b/qcom/direwolf-vm-la-overlay.dts
@@ -1,9 +1,6 @@
 /dts-v1/;
 /plugin/;
 
-#include "direwolf-vm.dtsi"
-#include "direwolf-vm-la.dtsi"
-
 / {
 	model = "Qualcomm Technologies, Inc. Direwolf Single LA Virtual Machine";
 	compatible = "qcom,direwolf", "qcom,quinvm";
diff --git a/qcom/direwolf-vm-la.dtsi b/qcom/direwolf-vm-la.dtsi
index c9f71ee7..23ba2342 100755
--- a/qcom/direwolf-vm-la.dtsi
+++ b/qcom/direwolf-vm-la.dtsi
@@ -23,3 +23,24 @@
 &qcom_rng_ee3 {
 	status = "okay";
 };
+
+/ {
+	rename_devices: rename_devices {
+		compatible = "qcom,rename-devices";
+		rename_blk: rename_blk {
+			device-type = "block";
+			actual-dev = "vda", "vdb", "vdc",
+					"vdd", "vde", "vdf",
+					"vdg", "vdh", "vdi",
+					"vdj", "vdk", "vdl",
+					"vdm", "vdn", "vdo",
+					"vdp", "vdq";
+			rename-dev = "super", "userdata", "metadata",
+					"persist", "modem_a","bluetooth_a",
+					"misc", "vbmeta_a", "vbmeta_b",
+					"boot_a", "dtbo_a","dsp_a",
+					"modem_b", "bluetooth_b", "boot_b",
+					"dtbo_b", "dsp_b";
+		};
+	};
+};
diff --git a/qcom/direwolf-vm-lv-overlay.dts b/qcom/direwolf-vm-lv-overlay.dts
index db42d935..e19fce27 100755
--- a/qcom/direwolf-vm-lv-overlay.dts
+++ b/qcom/direwolf-vm-lv-overlay.dts
@@ -1,8 +1,6 @@
 /dts-v1/;
 /plugin/;
 
-#include "direwolf-vm.dtsi"
-#include "direwolf-vm-lv.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. Direwolf Single LV Virtual Machine";
diff --git a/qcom/direwolf-vm-lv.dtsi b/qcom/direwolf-vm-lv.dtsi
index 7e6cf28a..5d003425 100755
--- a/qcom/direwolf-vm-lv.dtsi
+++ b/qcom/direwolf-vm-lv.dtsi
@@ -18,8 +18,74 @@
 };
 
 &soc {
+	tlmm: pinctrl@f000000 {
+		compatible = "qcom,direwolf-pinctrl";
+		reg = <0x0F000000 0x1000000>;
+		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
 };
 
 &hab {
 	vmid = <3>;
 };
+&usb0 {
+	status = "okay";
+};
+
+&usb2_phy0 {
+	status = "okay";
+};
+
+&usb_qmp_dp_phy0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
+
+&usb2_phy1 {
+	status = "okay";
+};
+
+&usb_qmp_dp_phy1 {
+	status = "okay";
+};
+
+&usb2 {
+	status = "disabled";
+};
+
+&usb2_phy2 {
+	status = "disabled";
+};
+
+&usb2_phy3 {
+	status = "disabled";
+};
+
+&usb2_phy4 {
+	status = "disabled";
+};
+
+&pcie0 {
+	status = "okay";
+	qcom,boot-option = <0x0>;
+};
+
+&pcie2a_msi_snps {
+	status = "okay";
+};
+
+&pcie4 {
+	status = "okay";
+	qcom,boot-option = <0x0>;
+};
+
+&pcie4_msi_snps {
+	status = "okay";
+};
diff --git a/qcom/direwolf-vm-pcie.dtsi b/qcom/direwolf-vm-pcie.dtsi
new file mode 100755
index 00000000..69249b1c
--- /dev/null
+++ b/qcom/direwolf-vm-pcie.dtsi
@@ -0,0 +1,1143 @@
+&soc {
+	pcie0: qcom,pcie@0x1c20000 {
+		compatible = "qcom,pci-msm";
+
+		reg = <0x01c20000 0x3000>,
+			<0x01c24000 0x2000>,
+			<0x3c000000 0xf1d>,
+			<0x3c000f20 0xa8>,
+			<0x3c001000 0x1000>,
+			<0x3c100000 0x100000>;
+		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
+
+		cell-index = <0>;
+		linux,pci-domain = <0>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x3c200000 0x3c200000 0x0 0x100000>,
+			<0x02000000 0x0 0x3c300000 0x3c300000 0x0 0x1d00000>;
+
+		interrupt-parent = <&pcie0>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
+
+		msi-parent = <&pcie2a_msi_snps>;
+
+		perst-gpio = <&tlmm 143 0>;
+		wake-gpio = <&tlmm 145 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie2a_perst_default
+				&pcie2a_clkreq_default
+				&pcie2a_wake_default>;
+
+		gdsc-core-vdd-supply = <&gcc_pcie_2a_gdsc>;
+		vreg-1p2-supply = <&L3A0>;
+		vreg-0p9-supply = <&L11A0>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 25000>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 99000>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				100000000>;
+
+		clocks = <&gcc GCC_PCIE_2A_PIPE_CLK>,
+			<&rpmh_cxo_clk>,
+			<&gcc GCC_PCIE_2A_AUX_CLK>,
+			<&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
+			<&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
+			<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
+			<&gcc GCC_PCIE_2A_PIPE_CLK_SRC>,
+			<&pcie_2a_pipe_clk>,
+			<&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
+			<&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
+
+		clock-names = "pcie_pipe_clk", "pcie_0_ref_clk_src",
+				"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
+				"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
+				"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
+				"pcie_phy_refgen_clk",
+				"pcie_ddrss_sf_tbu_clk",
+				"pcie_aggre_noc_4_axi_clk", "pcie_pipe_clk_mux",
+				"pcie_pipe_clk_ext_src",
+				"pcie_aggre_noc_south_sf_axi_clk", "pcie_0_pipediv2_clk";
+
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <100000000>, <0>,
+					<0>, <0>, <0>;
+
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_2A_BCR>,
+			<&gcc GCC_PCIE_2A_PHY_BCR>,
+			<&gcc GCC_PCIE_2A_PHY_NOCSR_COM_PHY_BCR>;
+		reset-names = "pcie_0_core_reset",
+				"pcie_0_phy_reset",
+				"pcie_phy_nocsr_com_phy_reset";
+
+		dma-coherent;
+
+		qcom,boot-option = <0x1>;
+		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
+		qcom,l1-2-th-scale = <2>;
+		qcom,l1-2-th-value = <70>;
+		qcom,slv-addr-space-size = <0x2000000>;
+		qcom,ep-latency = <10>;
+		qcom,core-preset = <0x77777777>;
+
+		qcom,pcie-phy-ver = <1106>;
+		qcom,phy-status-offset = <0x214>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0x240>;
+		qcom,phy-sequence = <0x0240 0x03 0x0
+				0x0044 0x14 0x0
+				0x0010 0x00 0x0
+				0x001c 0x31 0x0
+				0x0020 0x01 0x0
+				0x0024 0xde 0x0
+				0x0028 0x07 0x0
+				0x0030 0x4c 0x0
+				0x0034 0x06 0x0
+				0x0048 0x90 0x0
+				0x0058 0x0f 0x0
+				0x0074 0x06 0x0
+				0x0078 0x06 0x0
+				0x007c 0x16 0x0
+				0x0080 0x16 0x0
+				0x0084 0x36 0x0
+				0x0088 0x36 0x0
+				0x0094 0x08 0x0
+				0x00a4 0x42 0x0
+				0x00ac 0x0a 0x0
+				0x00b0 0x1a 0x0
+				0x00b4 0x14 0x0
+				0x00b8 0x34 0x0
+				0x00bc 0x82 0x0
+				0x00c4 0x68 0x0
+				0x00cc 0x55 0x0
+				0x00d0 0x55 0x0
+				0x00d4 0x03 0x0
+				0x00d8 0xab 0x0
+				0x00dc 0xaa 0x0
+				0x00e0 0x02 0x0
+				0x010c 0x02 0x0
+				0x0110 0x24 0x0
+				0x0118 0xb4 0x0
+				0x011c 0x03 0x0
+				0x0154 0x34 0x0
+				0x0158 0x01 0x0
+				0x016c 0x08 0x0
+				0x01ac 0xb9 0x0
+				0x01b0 0x1e 0x0
+				0x01b4 0x94 0x0
+				0x01b8 0x18 0x0
+				0x01bc 0x11 0x0
+				0x0ee4 0x02 0x0
+				0x16e4 0x04 0x0
+				0x0e84 0xd5 0x0
+				0x1684 0xd5 0x0
+				0x0e90 0x3f 0x0
+				0x1690 0x3f 0x0
+				0x0e3c 0x11 0x0
+				0x163c 0x11 0x0
+				0x0e40 0x0c 0x0
+				0x1640 0x0c 0x0
+				0x115c 0x7f 0x0
+				0x1160 0xff 0x0
+				0x1164 0x7f 0x0
+				0x1168 0x34 0x0
+				0x116c 0xd8 0x0
+				0x195c 0x7f 0x0
+				0x1960 0xff 0x0
+				0x1964 0x7f 0x0
+				0x1968 0x34 0x0
+				0x196c 0xd8 0x0
+				0x1170 0xdc 0x0
+				0x1174 0xdc 0x0
+				0x1178 0x5c 0x0
+				0x117c 0x34 0x0
+				0x1180 0xa6 0x0
+				0x1970 0xdc 0x0
+				0x1974 0xdc 0x0
+				0x1978 0x5c 0x0
+				0x197c 0x34 0x0
+				0x1980 0xa6 0x0
+				0x1190 0x34 0x0
+				0x1990 0x34 0x0
+				0x10d8 0x0f 0x0
+				0x18d8 0x0f 0x0
+				0x10dc 0x00 0x0
+				0x18dc 0x00 0x0
+				0x104c 0x08 0x0
+				0x184c 0x08 0x0
+				0x1050 0x08 0x0
+				0x1850 0x08 0x0
+				0x1044 0xf0 0x0
+				0x1844 0xf0 0x0
+				0x11a4 0x38 0x0
+				0x19a4 0x38 0x0
+				0x02dc 0x05 0x0
+				0x0388 0x88 0x0
+				0x0398 0x0b 0x0
+				0x03e4 0x0f 0x0
+				0x060c 0x1d 0x0
+				0x0614 0x07 0x0
+				0x0620 0xc1 0x0
+				0x0694 0x00 0x0
+				0x0200 0x00 0x0
+				0x0244 0x03 0x0>;
+
+		status = "disabled";
+
+		pcie0_rp: pcie0_rp {
+			reg = <0 0 0 0 0>;
+		};
+	};
+
+	pcie1: qcom,pcie@0x01c18000 {
+		compatible = "qcom,pci-msm";
+
+		reg = <0x01c18000 0x3000>,
+			<0x01c1e000 0x2000>,
+			<0x38000000 0xf1d>,
+			<0x38000f20 0xa8>,
+			<0x38001000 0x1000>,
+			<0x38100000 0x100000>;
+		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
+
+		cell-index = <1>;
+		linux,pci-domain = <1>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x38200000 0x38200000 0x0 0x100000>,
+			<0x02000000 0x0 0x38300000 0x38300000 0x0 0x1d00000>;
+
+		interrupt-parent = <&pcie1>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
+
+		msi-parent = <&pcie2b_msi_snps>;
+
+		perst-gpio = <&tlmm 147 0>;
+		wake-gpio = <&tlmm 146 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie2b_perst_default
+				&pcie2b_clkreq_default
+				&pcie2b_wake_default>;
+
+		gdsc-core-vdd-supply = <&gcc_pcie_2b_gdsc>;
+		vreg-1p2-supply = <&L3A0>;
+		vreg-0p9-supply = <&L11A0>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 25000>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 99000>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				100000000>;
+
+		clocks = <&gcc GCC_PCIE_2B_PIPE_CLK>,
+			<&rpmh_cxo_clk>,
+			<&gcc GCC_PCIE_2B_AUX_CLK>,
+			<&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
+			<&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
+			<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
+			<&gcc GCC_PCIE_2B_PIPE_CLK_SRC>,
+			<&pcie_2b_pipe_clk>,
+			<&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
+			<&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
+
+		clock-names = "pcie_pipe_clk", "pcie_1_ref_clk_src",
+				"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
+				"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
+				"pcie_1_ldo", "pcie_1_slv_q2a_axi_clk",
+				"pcie_phy_refgen_clk",
+				"pcie_ddrss_sf_tbu_clk",
+				"pcie_aggre_noc_4_axi_clk", "pcie_pipe_clk_mux",
+				"pcie_pipe_clk_ext_src",
+				"pcie_aggre_noc_south_sf_axi_clk", "pcie_1_pipediv2_clk";
+
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <100000000>, <0>,
+					<0>, <0>, <0>;
+
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_2B_BCR>,
+			<&gcc GCC_PCIE_2B_PHY_BCR>,
+			<&gcc GCC_PCIE_2B_PHY_NOCSR_COM_PHY_BCR>;
+		reset-names = "pcie_1_core_reset",
+				"pcie_1_phy_reset",
+				"pcie_phy_nocsr_com_phy_reset";
+
+		dma-coherent;
+
+		qcom,boot-option = <0x1>;
+		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
+		qcom,l1-2-th-scale = <2>;
+		qcom,l1-2-th-value = <70>;
+		qcom,slv-addr-space-size = <0x2000000>;
+		qcom,ep-latency = <10>;
+		qcom,core-preset = <0x77777777>;
+
+		qcom,pcie-phy-ver = <1106>;
+		qcom,phy-status-offset = <0x214>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0x240>;
+		qcom,phy-sequence = <0x0240 0x03 0x0
+				0x0044 0x14 0x0
+				0x0010 0x00 0x0
+				0x001c 0x31 0x0
+				0x0020 0x01 0x0
+				0x0024 0xde 0x0
+				0x0028 0x07 0x0
+				0x0030 0x4c 0x0
+				0x0034 0x06 0x0
+				0x0048 0x90 0x0
+				0x0058 0x0f 0x0
+				0x0074 0x06 0x0
+				0x0078 0x06 0x0
+				0x007c 0x16 0x0
+				0x0080 0x16 0x0
+				0x0084 0x36 0x0
+				0x0088 0x36 0x0
+				0x0094 0x08 0x0
+				0x00a4 0x42 0x0
+				0x00ac 0x0a 0x0
+				0x00b0 0x1a 0x0
+				0x00b4 0x14 0x0
+				0x00b8 0x34 0x0
+				0x00bc 0x82 0x0
+				0x00c4 0x68 0x0
+				0x00cc 0x55 0x0
+				0x00d0 0x55 0x0
+				0x00d4 0x03 0x0
+				0x00d8 0xab 0x0
+				0x00dc 0xaa 0x0
+				0x00e0 0x02 0x0
+				0x010c 0x02 0x0
+				0x0110 0x24 0x0
+				0x0118 0xb4 0x0
+				0x011c 0x03 0x0
+				0x0154 0x34 0x0
+				0x0158 0x01 0x0
+				0x016c 0x08 0x0
+				0x01ac 0xb9 0x0
+				0x01b0 0x1e 0x0
+				0x01b4 0x94 0x0
+				0x01b8 0x18 0x0
+				0x01bc 0x11 0x0
+				0x0ee4 0x02 0x0
+				0x16e4 0x04 0x0
+				0x0e84 0xd5 0x0
+				0x1684 0xd5 0x0
+				0x0e90 0x3f 0x0
+				0x1690 0x3f 0x0
+				0x0e3c 0x11 0x0
+				0x163c 0x11 0x0
+				0x0e40 0x0c 0x0
+				0x1640 0x0c 0x0
+				0x115c 0x7f 0x0
+				0x1160 0xff 0x0
+				0x1164 0x7f 0x0
+				0x1168 0x34 0x0
+				0x116c 0xd8 0x0
+				0x195c 0x7f 0x0
+				0x1960 0xff 0x0
+				0x1964 0x7f 0x0
+				0x1968 0x34 0x0
+				0x196c 0xd8 0x0
+				0x1170 0xdc 0x0
+				0x1174 0xdc 0x0
+				0x1178 0x5c 0x0
+				0x117c 0x34 0x0
+				0x1180 0xa6 0x0
+				0x1970 0xdc 0x0
+				0x1974 0xdc 0x0
+				0x1978 0x5c 0x0
+				0x197c 0x34 0x0
+				0x1980 0xa6 0x0
+				0x1190 0x34 0x0
+				0x1990 0x34 0x0
+				0x10d8 0x0f 0x0
+				0x18d8 0x0f 0x0
+				0x10dc 0x00 0x0
+				0x18dc 0x00 0x0
+				0x104c 0x08 0x0
+				0x184c 0x08 0x0
+				0x1050 0x08 0x0
+				0x1850 0x08 0x0
+				0x1044 0xf0 0x0
+				0x1844 0xf0 0x0
+				0x11a4 0x38 0x0
+				0x19a4 0x38 0x0
+				0x02dc 0x05 0x0
+				0x0388 0x88 0x0
+				0x0398 0x0b 0x0
+				0x03e4 0x0f 0x0
+				0x060c 0x1d 0x0
+				0x0614 0x07 0x0
+				0x0620 0xc1 0x0
+				0x0694 0x00 0x0
+				0x0200 0x00 0x0
+				0x0244 0x03 0x0>;
+
+		status = "disabled";
+
+		pcie1_rp: pcie1_rp {
+			reg = <0 0 0 0 0>;
+		};
+	};
+
+	pcie2: qcom,pcie@0x1c10000 {
+		compatible = "qcom,pci-msm";
+
+		reg = <0x01c10000 0x3000>,
+			<0x01c14000 0x2000>,
+			<0x40000000 0xf1d>,
+			<0x40000f20 0xa8>,
+			<0x40001000 0x1000>,
+			<0x40100000 0x100000>;
+		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
+
+		cell-index = <2>;
+		linux,pci-domain = <2>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
+			<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1d00000>;
+
+		interrupt-parent = <&pcie2>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = <0 0 0 &intc 0 GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
+
+		msi-parent = <&pcie3a_msi_snps>;
+
+		perst-gpio = <&tlmm 151 0>;
+		wake-gpio = <&tlmm 56 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie3a_perst_default
+				&pcie3a_clkreq_default
+				&pcie3a_wake_default>;
+
+		gdsc-core-vdd-supply = <&gcc_pcie_3a_gdsc>;
+		vreg-1p2-supply = <&L3A0>;
+		vreg-0p9-supply = <&L11A0>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 25000>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 99000>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				100000000>;
+
+		clocks = <&gcc GCC_PCIE_3A_PIPE_CLK>,
+			<&rpmh_cxo_clk>,
+			<&gcc GCC_PCIE_3A_AUX_CLK>,
+			<&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
+			<&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
+			<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
+			<&gcc GCC_PCIE_3A_PIPE_CLK_SRC>,
+			<&pcie_3a_pipe_clk>,
+			<&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
+			<&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
+
+		clock-names = "pcie_pipe_clk", "pcie_2_ref_clk_src",
+				"pcie_2_aux_clk", "pcie_2_cfg_ahb_clk",
+				"pcie_2_mstr_axi_clk", "pcie_2_slv_axi_clk",
+				"pcie_2_ldo", "pcie_2_slv_q2a_axi_clk",
+				"pcie_phy_refgen_clk",
+				"pcie_ddrss_sf_tbu_clk",
+				"pcie_aggre_noc_4_axi_clk", "pcie_pipe_clk_mux",
+				"pcie_pipe_clk_ext_src",
+				"pcie_aggre_noc_south_sf_axi_clk", "pcie_2_pipediv2_clk";
+
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <100000000>, <0>,
+					<0>, <0>, <0>;
+
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_3A_BCR>,
+			<&gcc GCC_PCIE_3A_PHY_BCR>,
+			<&gcc GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR>;
+		reset-names = "pcie_2_core_reset",
+				"pcie_2_phy_reset",
+				"pcie_phy_nocsr_com_phy_reset";
+
+		dma-coherent;
+
+		qcom,boot-option = <0x1>;
+		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
+		qcom,l1-2-th-scale = <2>;
+		qcom,l1-2-th-value = <70>;
+		qcom,slv-addr-space-size = <0x2000000>;
+		qcom,ep-latency = <10>;
+		qcom,core-preset = <0x77777777>;
+
+		qcom,pcie-phy-ver = <1106>;
+		qcom,phy-status-offset = <0x214>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0x240>;
+		qcom,phy-sequence = <0x0240 0x03 0x0
+				0x0010 0x01 0x0
+				0x001c 0x31 0x0
+				0x0020 0x01 0x0
+				0x0024 0xde 0x0
+				0x0028 0x07 0x0
+				0x0030 0x4c 0x0
+				0x0034 0x06 0x0
+				0x0048 0x90 0x0
+				0x0058 0x0f 0x0
+				0x0074 0x06 0x0
+				0x0078 0x06 0x0
+				0x007c 0x16 0x0
+				0x0080 0x16 0x0
+				0x0084 0x36 0x0
+				0x0088 0x36 0x0
+				0x0094 0x08 0x0
+				0x00a4 0x42 0x0
+				0x00ac 0x0a 0x0
+				0x00b0 0x1a 0x0
+				0x00b4 0x14 0x0
+				0x00b8 0x34 0x0
+				0x00bc 0x82 0x0
+				0x00c4 0x68 0x0
+				0x00cc 0x55 0x0
+				0x00d0 0x55 0x0
+				0x00d4 0x03 0x0
+				0x00d8 0xab 0x0
+				0x00dc 0xaa 0x0
+				0x00e0 0x02 0x0
+				0x010c 0x02 0x0
+				0x0110 0x24 0x0
+				0x0118 0xb4 0x0
+				0x011c 0x03 0x0
+				0x0154 0x34 0x0
+				0x0158 0x01 0x0
+				0x016c 0x08 0x0
+				0x01ac 0xca 0x0
+				0x01b0 0x1e 0x0
+				0x01b4 0xa2 0x0
+				0x01b8 0x18 0x0
+				0x01bc 0x11 0x0
+				0x0ee4 0x02 0x0
+				0x16e4 0x04 0x0
+				0x1684 0xd5 0x0
+				0x0e84 0xd5 0x0
+				0x1690 0x3f 0x0
+				0x0e90 0x3f 0x0
+				0x115c 0x7f 0x0
+				0x1160 0xff 0x0
+				0x1164 0x7f 0x0
+				0x1168 0x34 0x0
+				0x116c 0xd8 0x0
+				0x1170 0xdc 0x0
+				0x1174 0xdc 0x0
+				0x1178 0x5c 0x0
+				0x117c 0x34 0x0
+				0x1180 0xa6 0x0
+				0x195c 0x7f 0x0
+				0x1960 0xff 0x0
+				0x1964 0x7f 0x0
+				0x1968 0x34 0x0
+				0x196c 0xd8 0x0
+				0x1970 0xdc 0x0
+				0x1974 0xdc 0x0
+				0x1978 0x5c 0x0
+				0x197c 0x34 0x0
+				0x1980 0xa6 0x0
+				0x10cc 0xf0 0x0
+				0x18cc 0xf0 0x0
+				0x10d8 0x0f 0x0
+				0x18d8 0x0f 0x0
+				0x10dc 0x00 0x0
+				0x18dc 0x00 0x0
+				0x11a4 0x38 0x0
+				0x19a4 0x38 0x0
+				0x0e3c 0x1d 0x0
+				0x163c 0x1d 0x0
+				0x0e40 0x0c 0x0
+				0x1640 0x0c 0x0
+				0x1190 0x34 0x0
+				0x1990 0x34 0x0
+				0x104c 0x08 0x0
+				0x184c 0x08 0x0
+				0x1050 0x08 0x0
+				0x1850 0x08 0x0
+				0x02dc 0x05 0x0
+				0x0388 0x77 0x0
+				0x0398 0x0b 0x0
+				0x03e0 0x0f 0x0
+				0x060c 0x1d 0x0
+				0x0614 0x07 0x0
+				0x0620 0xc1 0x0
+				0x0694 0x00 0x0
+				0x0200 0x00 0x0
+				0x0244 0x03 0x0>;
+
+		status = "disabled";
+
+		pcie2_rp: pcie2_rp {
+			reg = <0 0 0 0 0>;
+		};
+	};
+
+	pcie3: qcom,pcie@0x01c08000 {
+		compatible = "qcom,pci-msm";
+
+		reg = <0x01c08000 0x3000>,
+			<0x01c0e000 0x2000>,
+			<0x32000000 0xf1d>,
+			<0x32000f20 0xa8>,
+			<0x32001000 0x1000>,
+			<0x32100000 0x100000>;
+		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
+
+		cell-index = <3>;
+		linux,pci-domain = <3>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x32200000 0x32200000 0x0 0x100000>,
+			<0x02000000 0x0 0x32300000 0x32300000 0x0 0x1d00000>;
+
+		interrupt-parent = <&pcie3>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
+
+		msi-parent = <&pcie3b_msi_snps>;
+
+		perst-gpio = <&tlmm 153 0>;
+		wake-gpio = <&tlmm 130 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie3b_perst_default
+				&pcie3b_clkreq_default
+				&pcie3b_wake_default>;
+
+		gdsc-core-vdd-supply = <&gcc_pcie_3b_gdsc>;
+		vreg-1p2-supply = <&L3A0>;
+		vreg-0p9-supply = <&L11A0>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 25000>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 99000>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				100000000>;
+
+		clocks = <&gcc GCC_PCIE_3B_PIPE_CLK>,
+			<&rpmh_cxo_clk>,
+			<&gcc GCC_PCIE_3B_AUX_CLK>,
+			<&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
+			<&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
+			<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
+			<&gcc GCC_PCIE_3B_PIPE_CLK_SRC>,
+			<&pcie_3b_pipe_clk>,
+			<&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
+			<&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
+
+		clock-names = "pcie_pipe_clk", "pcie_3_ref_clk_src",
+				"pcie_3_aux_clk", "pcie_3_cfg_ahb_clk",
+				"pcie_3_mstr_axi_clk", "pcie_3_slv_axi_clk",
+				"pcie_3_ldo", "pcie_3_slv_q2a_axi_clk",
+				"pcie_phy_refgen_clk",
+				"pcie_ddrss_sf_tbu_clk",
+				"pcie_aggre_noc_4_axi_clk", "pcie_pipe_clk_mux",
+				"pcie_pipe_clk_ext_src",
+				"pcie_aggre_noc_south_sf_axi_clk", "pcie_3_pipediv2_clk";
+
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <100000000>, <0>,
+					<0>, <0>, <0>;
+
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_3B_BCR>,
+			<&gcc GCC_PCIE_3B_PHY_BCR>,
+			<&gcc GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR>;
+		reset-names = "pcie_3_core_reset",
+				"pcie_3_phy_reset",
+				"pcie_phy_nocsr_com_phy_reset";
+
+		dma-coherent;
+
+		qcom,boot-option = <0x1>;
+		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
+		qcom,l1-2-th-scale = <2>;
+		qcom,l1-2-th-value = <70>;
+		qcom,slv-addr-space-size = <0x2000000>;
+		qcom,ep-latency = <10>;
+		qcom,core-preset = <0x77777777>;
+
+		qcom,pcie-phy-ver = <1106>;
+		qcom,phy-status-offset = <0x214>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0x240>;
+		qcom,phy-sequence = <0x0240 0x03 0x0
+				0x0044 0x14 0x0
+				0x0010 0x00 0x0
+				0x001c 0x31 0x0
+				0x0020 0x01 0x0
+				0x0024 0xde 0x0
+				0x0028 0x07 0x0
+				0x0030 0x4c 0x0
+				0x0034 0x06 0x0
+				0x0048 0x90 0x0
+				0x0058 0x0f 0x0
+				0x0074 0x06 0x0
+				0x0078 0x06 0x0
+				0x007c 0x16 0x0
+				0x0080 0x16 0x0
+				0x0084 0x36 0x0
+				0x0088 0x36 0x0
+				0x0094 0x08 0x0
+				0x00a4 0x42 0x0
+				0x00ac 0x0a 0x0
+				0x00b0 0x1a 0x0
+				0x00b4 0x14 0x0
+				0x00b8 0x34 0x0
+				0x00bc 0x82 0x0
+				0x00c4 0x68 0x0
+				0x00cc 0x55 0x0
+				0x00d0 0x55 0x0
+				0x00d4 0x03 0x0
+				0x00d8 0xab 0x0
+				0x00dc 0xaa 0x0
+				0x00e0 0x02 0x0
+				0x010c 0x02 0x0
+				0x0110 0x24 0x0
+				0x0118 0xb4 0x0
+				0x011c 0x03 0x0
+				0x0154 0x34 0x0
+				0x0158 0x01 0x0
+				0x016c 0x08 0x0
+				0x01ac 0xb9 0x0
+				0x01b0 0x1e 0x0
+				0x01b4 0x94 0x0
+				0x01b8 0x18 0x0
+				0x01bc 0x11 0x0
+				0x0ee4 0x02 0x0
+				0x16e4 0x04 0x0
+				0x0e84 0xd5 0x0
+				0x1684 0xd5 0x0
+				0x0e90 0x3f 0x0
+				0x1690 0x3f 0x0
+				0x0e3c 0x11 0x0
+				0x163c 0x11 0x0
+				0x0e40 0x0c 0x0
+				0x1640 0x0c 0x0
+				0x115c 0x7f 0x0
+				0x1160 0xff 0x0
+				0x1164 0x7f 0x0
+				0x1168 0x34 0x0
+				0x116c 0xd8 0x0
+				0x195c 0x7f 0x0
+				0x1960 0xff 0x0
+				0x1964 0x7f 0x0
+				0x1968 0x34 0x0
+				0x196c 0xd8 0x0
+				0x1170 0xdc 0x0
+				0x1174 0xdc 0x0
+				0x1178 0x5c 0x0
+				0x117c 0x34 0x0
+				0x1180 0xa6 0x0
+				0x1970 0xdc 0x0
+				0x1974 0xdc 0x0
+				0x1978 0x5c 0x0
+				0x197c 0x34 0x0
+				0x1980 0xa6 0x0
+				0x1190 0x34 0x0
+				0x1990 0x34 0x0
+				0x10d8 0x0f 0x0
+				0x18d8 0x0f 0x0
+				0x10dc 0x00 0x0
+				0x18dc 0x00 0x0
+				0x104c 0x08 0x0
+				0x184c 0x08 0x0
+				0x1050 0x08 0x0
+				0x1850 0x08 0x0
+				0x1044 0xf0 0x0
+				0x1844 0xf0 0x0
+				0x11a4 0x38 0x0
+				0x19a4 0x38 0x0
+				0x02dc 0x05 0x0
+				0x0388 0x88 0x0
+				0x0398 0x0b 0x0
+				0x03e4 0x0f 0x0
+				0x060c 0x1d 0x0
+				0x0614 0x07 0x0
+				0x0620 0xc1 0x0
+				0x0694 0x00 0x0
+				0x0200 0x00 0x0
+				0x0244 0x03 0x0>;
+
+		status = "disabled";
+
+		pcie3_rp: pcie3_rp {
+			reg = <0 0 0 0 0>;
+		};
+	};
+
+	pcie4: qcom,pcie@1c00000 {
+		compatible = "qcom,pci-msm";
+
+		reg = <0x01c00000 0x3000>,
+			<0x01c06000 0x2000>,
+			<0x30000000 0xf1d>,
+			<0x30000f20 0xa8>,
+			<0x30001000 0x1000>,
+			<0x30100000 0x100000>;
+		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
+
+		cell-index = <4>;
+		linux,pci-domain = <4>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x30200000 0x30200000 0x0 0x100000>,
+			<0x02000000 0x0 0x30300000 0x30300000 0x0 0x1d00000>;
+
+		interrupt-parent = <&pcie4>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+
+		msi-parent = <&pcie4_msi_snps>;
+		qcom,target-link-speed = <0x3>;
+		qcom,core-preset = <0x77777777>;
+
+		perst-gpio = <&tlmm 141 0>;
+		wake-gpio = <&tlmm 139 0>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&pcie4_perst_default
+				&pcie4_clkreq_default
+				&pcie4_wake_default>;
+		pinctrl-1 = <&pcie4_perst_default
+				&pcie4_clkreq_sleep
+				&pcie4_wake_default>;
+
+		gdsc-core-vdd-supply = <&gcc_pcie_4_gdsc>;
+		vreg-1p2-supply = <&L3A0>;
+		vreg-0p9-supply = <&L11A0>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 25000>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 97200>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				100000000>;
+
+		clocks = <&gcc GCC_PCIE_4_PIPE_CLK>,
+			<&rpmh_cxo_clk>,
+			<&gcc GCC_PCIE_4_AUX_CLK>,
+			<&gcc GCC_PCIE_4_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_4_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_4_CLKREF_CLK>,
+			<&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
+			<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
+			<&gcc GCC_PCIE_4_PIPE_CLK_SRC>,
+			<&pcie_4_pipe_clk>,
+			<&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
+			<&gcc GCC_CNOC_PCIE4_QX_CLK>,
+			<&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
+
+		clock-names = "pcie_pipe_clk", "pcie_4_ref_clk_src",
+				"pcie_4_aux_clk", "pcie_4_cfg_ahb_clk",
+				"pcie_4_mstr_axi_clk", "pcie_4_slv_axi_clk",
+				"pcie_4_ldo", "pcie_4_slv_q2a_axi_clk",
+				"pcie_phy_refgen_clk",
+				"pcie_ddrss_sf_tbu_clk",
+				"pcie_aggre_noc_4_axi_clk", "pcie_pipe_clk_mux",
+				"pcie_pipe_clk_ext_src",
+				"pcie_aggre_noc_south_sf_axi_clk", "pcie_cnoc_4_qx",
+				"pcie_4_pipediv2_clk";
+
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <100000000>, <0>,
+					<0>, <0>, <0>, <0>;
+
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_4_BCR>,
+			<&gcc GCC_PCIE_4_PHY_BCR>,
+			<&gcc GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR>;
+		reset-names = "pcie_4_core_reset",
+				"pcie_4_phy_reset",
+				"pcie_phy_nocsr_com_phy_reset";
+
+		dma-coherent;
+
+		qcom,boot-option = <0x1>;
+		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
+		qcom,l1-2-th-scale = <2>;
+		qcom,l1-2-th-value = <70>;
+		qcom,slv-addr-space-size = <0x2000000>;
+		qcom,ep-latency = <10>;
+
+		qcom,pcie-phy-ver = <10102>;
+		qcom,phy-status-offset = <0x214>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0x240>;
+		qcom,phy-sequence = <0x0240 0x03 0x0
+				0x0094 0x08 0x0
+				0x0154 0x34 0x0
+				0x016c 0x08 0x0
+				0x0058 0x0f 0x0
+				0x00a4 0x42 0x0
+				0x0110 0x24 0x0
+				0x011c 0x03 0x0
+				0x0118 0xb4 0x0
+				0x010c 0x02 0x0
+				0x01bc 0x11 0x0
+				0x00bc 0x82 0x0
+				0x00d4 0x03 0x0
+				0x00d0 0x55 0x0
+				0x00cc 0x55 0x0
+				0x00b0 0x1a 0x0
+				0x00ac 0x0a 0x0
+				0x00c4 0x68 0x0
+				0x00e0 0x02 0x0
+				0x00dc 0xaa 0x0
+				0x00d8 0xab 0x0
+				0x00b8 0x34 0x0
+				0x00b4 0x14 0x0
+				0x0158 0x01 0x0
+				0x0074 0x06 0x0
+				0x007c 0x16 0x0
+				0x0084 0x36 0x0
+				0x0078 0x06 0x0
+				0x0080 0x16 0x0
+				0x0088 0x36 0x0
+				0x01b0 0x1e 0x0
+				0x01ac 0xb9 0x0
+				0x01b8 0x18 0x0
+				0x01b4 0x94 0x0
+				0x0050 0x07 0x0
+				0x0010 0x00 0x0
+				0x001c 0x31 0x0
+				0x0020 0x01 0x0
+				0x0024 0xde 0x0
+				0x0028 0x07 0x0
+				0x0030 0x4c 0x0
+				0x0034 0x06 0x0
+				0x0ee4 0x20 0x0
+				0x0e84 0x75 0x0
+				0x0e90 0x3f 0x0
+				0x115c 0x7f 0x0
+				0x1160 0xff 0x0
+				0x1164 0xbf 0x0
+				0x1168 0x3f 0x0
+				0x116c 0xd8 0x0
+				0x1170 0xdc 0x0
+				0x1174 0xdc 0x0
+				0x1178 0x5c 0x0
+				0x117c 0x34 0x0
+				0x1180 0xa6 0x0
+				0x1190 0x34 0x0
+				0x10d8 0x07 0x0
+				0x0e3c 0x1d 0x0
+				0x0e40 0x0c 0x0
+				0x10dc 0x00 0x0
+				0x104c 0x08 0x0
+				0x1050 0x08 0x0
+				0x1044 0xf0 0x0
+				0x11a4 0x38 0x0
+				0x10cc 0xf0 0x0
+				0x0694 0x00 0x0
+				0x0654 0x00 0x0
+				0x06a8 0x0f 0x0
+				0x0048 0x90 0x0
+				0x0620 0xc1 0x0
+				0x0388 0x77 0x0
+				0x0398 0x0b 0x0
+				0x02dc 0x05 0x0
+				0x0200 0x00 0x0
+				0x0244 0x03 0x0>;
+
+		status = "disabled";
+
+		pcie4_rp: pcie4_rp {
+			reg = <0 0 0 0 0>;
+		};
+	};
+
+	pcie2a_msi_snps: qcom,pcie2a_msi@a0000000 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0xa0000000 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,snps;
+		status = "disabled";
+	};
+
+	pcie2b_msi_snps: qcom,pcie2b_msi@a0000000 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0xa0000000 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,snps;
+		status = "disabled";
+	};
+
+	pcie3a_msi_snps: qcom,pcie3a_msi@a0000000 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0xa0000000 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,snps;
+		status = "disabled";
+	};
+
+	pcie3b_msi_snps: qcom,pcie3b_msi@a0000000 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0xa0000000 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,snps;
+		status = "disabled";
+	};
+
+	pcie4_msi_snps: qcom,pcie4_msi@a0000000 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0xa0000000 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,snps;
+		status = "disabled";
+	};
+};
diff --git a/qcom/direwolf-vm-usb.dtsi b/qcom/direwolf-vm-usb.dtsi
new file mode 100755
index 00000000..0f79e7e9
--- /dev/null
+++ b/qcom/direwolf-vm-usb.dtsi
@@ -0,0 +1,1008 @@
+#include <dt-bindings/phy/qcom,usb3-5nm-qmp-uni.h>
+#include <dt-bindings/phy/qcom,usb4-5nm-qmp-combo.h>
+
+&soc {
+	usb0: ssusb@a600000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0xa600000 0x100000>;
+		reg-names = "core_base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		dma-ranges;
+
+		interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>,
+					<&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
+					<&pdc 138 IRQ_TYPE_LEVEL_HIGH>,
+					<&pdc 15 IRQ_TYPE_EDGE_RISING>;
+
+		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+				"ss_phy_irq", "dm_hs_phy_irq";
+		qcom,use-pdc-interrupts;
+
+		USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
+		clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+			<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+			<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+			<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+			<&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
+			<&gcc GCC_SYS_NOC_USB_AXI_CLK>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+				"utmi_clk", "sleep_clk", "noc_aggr_clk",
+				"noc_aggr_north_clk", "noc_aggr_south_clk",
+				"noc_sys_clk";
+
+		resets = <&gcc GCC_USB30_PRIM_BCR>;
+		reset-names = "core_reset";
+
+		qcom,core-clk-rate = <200000000>;
+		qcom,core-clk-rate-hs = <66666667>;
+
+		qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
+		qcom,host-poweroff-in-pm-suspend;
+
+		status = "disabled";
+
+		dwc3@a600000 {
+			compatible = "snps,dwc3";
+			reg = <0xa600000 0xd93c>;
+			iommus = <&apps_smmu 0x0820 0x0>;
+			qcom,iommu-dma = "bypass";
+			interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
+			usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy0>;
+			snps,disable-clk-gating;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,ssp-u3-u0-quirk;
+			snps,is-utmi-l1-suspend;
+			snps,usb2-gadget-lpm-disable;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			tx-fifo-resize;
+			maximum-speed = "super-speed-plus";
+			dr_mode = "otg";
+			usb-role-switch;
+		};
+	};
+
+	/* Primary USB port related High Speed PHY */
+	usb2_phy0: hsphy@88e5000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x088e5000 0x120>;
+		reg-names = "hsusb_phy_base";
+
+		vdd-supply = <&L5A0>;
+		vdda18-supply = <&L7A0>;
+		vdda33-supply = <&L13A0>;
+
+		qcom,vdd-voltage-level = <0 912000 912000>;
+
+		clocks = <&dummycc RPMH_CXO_CLK>;
+		clock-names = "ref_clk_src";
+
+		resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+		reset-names = "phy_reset";
+		qcom,param-override-seq =
+			<0x63 0x6c	/* override_x0 */
+			 0xC8 0x70	/* override_x1 */
+			 0x17 0x74>;	/* override x2 */
+
+		status = "disabled";
+	};
+
+	/* Primary USB port related USB4-USB3-DP PHY */
+	usb_qmp_dp_phy0: ssphy@88eb000 {
+		compatible = "qcom,usb-ssphy-qmp-dp-combo";
+		reg = <0x88eb000 0x4000>;
+		reg-names = "qmp_phy_base";
+
+		vdd-supply = <&L5A0>;
+		qcom,vdd-voltage-level = <0 912000 912000>;
+		qcom,vdd-max-load-uA = <47000>;
+		core-supply = <&L3A0>;
+
+		clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+			 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+			 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
+			 <&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
+			 <&dummycc RPMH_CXO_CLK>,
+			 <&gcc GCC_USB4_EUD_CLKREF_CLK>,
+			 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+		clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
+				"pipe_clk_ext_src", "ref_clk_src",
+				"ref_clk", "com_aux_clk";
+
+		resets = <&gcc GCC_USB4_DP_PHY_PRIM_BCR>,
+				<&gcc GCC_USB3_PHY_PRIM_BCR>;
+		reset-names = "global_phy_reset", "phy_reset";
+
+		qcom,qmp-phy-reg-offset =
+			<USB3_PCS_PCS_STATUS1
+			 USB3_PCS_USB3_AUTONOMOUS_MODE_CTRL
+			 USB3_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
+			 USB3_PCS_POWER_DOWN_CONTROL
+			 USB3_PCS_SW_RESET
+			 USB3_PCS_START_CONTROL
+			 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
+			 USB43DP_COM_POWER_DOWN_CTRL
+			 USB43DP_COM_SW_RESET
+			 USB43DP_COM_RESET_OVRD_CTRL1
+			 USB43DP_COM_PHY_MODE_CTRL
+			 USB43DP_COM_TYPEC_CTRL
+			 USB3_PCS_CLAMP_ENABLE
+			 USB43DP_COM_TYPEC_STATUS>;
+
+		qcom,qmp-phy-init-seq =
+			/* <reg_offset, value> */
+			<USB3_QSERDES_PLL_SSC_EN_CENTER	0x01
+			USB3_QSERDES_PLL_SSC_PER1	0x31
+			USB3_QSERDES_PLL_SSC_PER2	0x01
+			USB3_QSERDES_PLL_SSC_STEP_SIZE1_MODE0	0xFD
+			USB3_QSERDES_PLL_SSC_STEP_SIZE2_MODE0	0x0D
+			USB3_QSERDES_PLL_SSC_STEP_SIZE1_MODE1	0xFD
+			USB3_QSERDES_PLL_SSC_STEP_SIZE2_MODE1	0x0D
+			USB3_QSERDES_PLL_SYSCLK_BUF_ENABLE	0x0A
+			USB3_QSERDES_PLL_CP_CTRL_MODE0	0x02
+			USB3_QSERDES_PLL_CP_CTRL_MODE1	0x02
+			USB3_QSERDES_PLL_PLL_RCTRL_MODE0	0x16
+			USB3_QSERDES_PLL_PLL_RCTRL_MODE1	0x16
+			USB3_QSERDES_PLL_PLL_CCTRL_MODE0	0x36
+			USB3_QSERDES_PLL_PLL_CCTRL_MODE1	0x36
+			USB3_QSERDES_PLL_SYSCLK_EN_SEL	0x1A
+			USB3_QSERDES_PLL_LOCK_CMP_EN	0x04
+			USB3_QSERDES_PLL_LOCK_CMP1_MODE0	0x14
+			USB3_QSERDES_PLL_LOCK_CMP2_MODE0	0x34
+			USB3_QSERDES_PLL_LOCK_CMP1_MODE1	0x34
+			USB3_QSERDES_PLL_LOCK_CMP2_MODE1	0x82
+			USB3_QSERDES_PLL_DEC_START_MODE0	0x04
+			USB3_QSERDES_PLL_DEC_START_MSB_MODE0	0x01
+			USB3_QSERDES_PLL_DEC_START_MODE1	0x04
+			USB3_QSERDES_PLL_DEC_START_MSB_MODE1	0x01
+			USB3_QSERDES_PLL_DIV_FRAC_START1_MODE0	0x55
+			USB3_QSERDES_PLL_DIV_FRAC_START2_MODE0	0xD5
+			USB3_QSERDES_PLL_DIV_FRAC_START3_MODE0	0x05
+			USB3_QSERDES_PLL_DIV_FRAC_START1_MODE1	0x55
+			USB3_QSERDES_PLL_DIV_FRAC_START2_MODE1	0xD5
+			USB3_QSERDES_PLL_DIV_FRAC_START3_MODE1	0x05
+			USB3_QSERDES_PLL_VCO_TUNE_MAP	0x02
+			USB3_QSERDES_PLL_VCO_TUNE1_MODE0	0xD4
+			USB3_QSERDES_PLL_VCO_TUNE2_MODE0	0x00
+			USB3_QSERDES_PLL_VCO_TUNE1_MODE1	0xD4
+			USB3_QSERDES_PLL_VCO_TUNE2_MODE1	0x00
+			USB3_QSERDES_PLL_HSCLK_SEL	0x13
+			USB3_QSERDES_PLL_HSCLK_HS_SWITCH_SEL	0x00
+			USB3_QSERDES_PLL_CORECLK_DIV_MODE0	0x0A
+			USB3_QSERDES_PLL_CORECLK_DIV_MODE1	0x04
+			USB3_QSERDES_PLL_CORE_CLK_EN	0x60
+			USB3_QSERDES_PLL_CMN_CONFIG	0x76
+			USB3_QSERDES_PLL_PLL_IVCO	0xFF
+			USB3_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0	0x20
+			USB3_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1	0x20
+			USB3_QSERDES_PLL_VCO_TUNE_INITVAL2	0x00
+			USB3_QSERDES_PLL_VCO_TUNE_MAXVAL2	0x01
+			USB3_QSERDES_PLL_SVS_MODE_CLK_SEL	0x0A
+			USB43DP_QSERDES_TXA_LANE_MODE_1	0x05
+			USB43DP_QSERDES_TXA_LANE_MODE_2	0xC2
+			USB43DP_QSERDES_TXA_LANE_MODE_3	0x10
+			USB43DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX	0x1F
+			USB43DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX	0x0A
+			USB43DP_QSERDES_RXA_SIGDET_CNTRL	0x04
+			USB43DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL	0x0E
+			USB43DP_QSERDES_RXA_SIGDET_ENABLES	0x00
+			USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B0	0xD2
+			USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B1	0xD2
+			USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B2	0xDB
+			USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B3	0x21
+			USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B4	0x3F
+			USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B5	0x80
+			USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B6	0x45
+			USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B7	0x00
+			USB43DP_QSERDES_RXA_RX_MODE_RATE2_B0	0x6B
+			USB43DP_QSERDES_RXA_RX_MODE_RATE2_B1	0x63
+			USB43DP_QSERDES_RXA_RX_MODE_RATE2_B2	0xB6
+			USB43DP_QSERDES_RXA_RX_MODE_RATE2_B3	0x23
+			USB43DP_QSERDES_RXA_RX_MODE_RATE2_B4	0x35
+			USB43DP_QSERDES_RXA_RX_MODE_RATE2_B5	0x30
+			USB43DP_QSERDES_RXA_RX_MODE_RATE2_B6	0x8E
+			USB43DP_QSERDES_RXA_RX_MODE_RATE2_B7	0x00
+			USB43DP_QSERDES_RXA_RX_IVCM_CAL_CODE_OVERRIDE	0x00
+			USB43DP_QSERDES_RXA_RX_IVCM_CAL_CTRL2	0x80
+			USB43DP_QSERDES_RXA_RX_SUMMER_CAL_SPD_MODE	0x1B
+			USB43DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET	0x38
+			USB43DP_QSERDES_RXA_UCDR_PI_CONTROLS	0x15
+			USB43DP_QSERDES_RXA_UCDR_SB2_GAIN2_RATE2	0x0A
+			USB43DP_QSERDES_RXA_RX_IVCM_POSTCAL_OFFSET	0x7C
+			USB43DP_QSERDES_RXA_VGA_CAL_CNTRL1	0x00
+			USB43DP_QSERDES_RXA_VGA_CAL_MAN_VAL	0x0D
+			USB43DP_QSERDES_RXA_DFE_DAC_ENABLE1	0x00
+			USB43DP_QSERDES_RXA_DFE_3	0x45
+			USB43DP_QSERDES_RXA_GM_CAL	0x09
+			USB43DP_QSERDES_RXA_UCDR_FO_GAIN_RATE2	0x09
+			USB43DP_QSERDES_RXA_UCDR_SO_GAIN_RATE2	0x05
+			USB43DP_QSERDES_RXA_Q_PI_INTRINSIC_BIAS_RATE32	0x3F
+			USB43DP_QSERDES_TXB_LANE_MODE_1	0x05
+			USB43DP_QSERDES_TXB_LANE_MODE_2	0xC2
+			USB43DP_QSERDES_TXB_LANE_MODE_3	0x10
+			USB43DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX	0x1F
+			USB43DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX	0x0A
+			USB43DP_QSERDES_RXB_SIGDET_CNTRL	0x04
+			USB43DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL	0x0E
+			USB43DP_QSERDES_RXB_SIGDET_ENABLES	0x00
+			USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B0	0xD2
+			USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B1	0xD2
+			USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B2	0xDB
+			USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B3	0x21
+			USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B4	0x3F
+			USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B5	0x80
+			USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B6	0x45
+			USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B7	0x00
+			USB43DP_QSERDES_RXB_RX_MODE_RATE2_B0	0x6B
+			USB43DP_QSERDES_RXB_RX_MODE_RATE2_B1	0x63
+			USB43DP_QSERDES_RXB_RX_MODE_RATE2_B2	0xB6
+			USB43DP_QSERDES_RXB_RX_MODE_RATE2_B3	0x23
+			USB43DP_QSERDES_RXB_RX_MODE_RATE2_B4	0x35
+			USB43DP_QSERDES_RXB_RX_MODE_RATE2_B5	0x30
+			USB43DP_QSERDES_RXB_RX_MODE_RATE2_B6	0x8E
+			USB43DP_QSERDES_RXB_RX_MODE_RATE2_B7	0x00
+			USB43DP_QSERDES_RXB_RX_IVCM_CAL_CODE_OVERRIDE	0x00
+			USB43DP_QSERDES_RXB_RX_IVCM_CAL_CTRL2	0x80
+			USB43DP_QSERDES_RXB_RX_SUMMER_CAL_SPD_MODE	0x1B
+			USB43DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET	0x38
+			USB43DP_QSERDES_RXB_UCDR_PI_CONTROLS	0x15
+			USB43DP_QSERDES_RXB_UCDR_SB2_GAIN2_RATE2	0x0A
+			USB43DP_QSERDES_RXB_RX_IVCM_POSTCAL_OFFSET	0x7C
+			USB43DP_QSERDES_RXB_VGA_CAL_CNTRL1	0x00
+			USB43DP_QSERDES_RXB_VGA_CAL_MAN_VAL	0x0D
+			USB43DP_QSERDES_RXB_DFE_DAC_ENABLE1	0x00
+			USB43DP_QSERDES_RXB_DFE_3	0x45
+			USB43DP_QSERDES_RXB_GM_CAL	0x09
+			USB43DP_QSERDES_RXB_UCDR_FO_GAIN_RATE2	0x09
+			USB43DP_QSERDES_RXB_UCDR_SO_GAIN_RATE2	0x05
+			USB43DP_QSERDES_RXB_Q_PI_INTRINSIC_BIAS_RATE32	0x3F
+			USB3_PCS_RCVR_DTCT_DLY_P1U2_L	0xE7
+			USB3_PCS_RCVR_DTCT_DLY_P1U2_H	0x03
+			USB3_PCS_LOCK_DETECT_CONFIG1	0xD0
+			USB3_PCS_LOCK_DETECT_CONFIG2	0x07
+			USB3_PCS_LOCK_DETECT_CONFIG3	0x20
+			USB3_PCS_LOCK_DETECT_CONFIG6	0x13
+			USB3_PCS_REFGEN_REQ_CONFIG1	0x21
+			USB3_PCS_RX_SIGDET_LVL	0xAA
+			USB3_PCS_RX_CONFIG	0x0A
+			USB3_PCS_ALIGN_DETECT_CONFIG1	0x88
+			USB3_PCS_ALIGN_DETECT_CONFIG2	0x13
+			USB3_PCS_PCS_TX_RX_CONFIG	0x0C
+			USB3_PCS_EQ_CONFIG1	0x4B
+			USB3_PCS_EQ_CONFIG5	0x10
+			USB3_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL	0xF8
+			USB3_PCS_USB3_RXEQTRAINING_DFE_TIME_S2	0x07>;
+
+		status = "disabled";
+	};
+
+	usb_nop_phy: usb_nop_phy {
+		compatible = "usb-nop-xceiv";
+	};
+
+	usb1: ssusb@a800000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0xa800000 0x100000>;
+		reg-names = "core_base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		dma-ranges;
+
+		interrupts-extended = <&pdc 12 IRQ_TYPE_EDGE_RISING>,
+					<&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
+					<&pdc 136 IRQ_TYPE_LEVEL_HIGH>,
+					<&pdc 13 IRQ_TYPE_EDGE_RISING>;
+
+		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+				"ss_phy_irq", "dm_hs_phy_irq";
+		qcom,use-pdc-interrupts;
+
+		USB3_GDSC-supply = <&gcc_usb30_sec_gdsc>;
+		clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
+			<&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+			<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+			<&gcc GCC_USB30_SEC_SLEEP_CLK>,
+			<&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
+			<&gcc GCC_SYS_NOC_USB_AXI_CLK>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+				"utmi_clk", "sleep_clk", "noc_aggr_clk",
+				"noc_aggr_north_clk", "noc_aggr_south_clk",
+				"noc_sys_clk";
+
+		resets = <&gcc GCC_USB30_SEC_BCR>;
+		reset-names = "core_reset";
+
+		qcom,core-clk-rate = <200000000>;
+		qcom,core-clk-rate-hs = <66666667>;
+
+		qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
+		qcom,host-poweroff-in-pm-suspend;
+		qcom,default-mode-host;
+		status = "disabled";
+
+		dwc3@a800000 {
+			compatible = "snps,dwc3";
+			reg = <0xa800000 0xd93c>;
+			iommus = <&apps_smmu 0x0860 0x0>;
+			qcom,iommu-dma = "bypass";
+			interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
+			usb-phy = <&usb2_phy1>, <&usb_qmp_dp_phy1>;
+			snps,disable-clk-gating;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,ssp-u3-u0-quirk;
+			snps,is-utmi-l1-suspend;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,usb2-gadget-lpm-disable;
+			tx-fifo-resize;
+			maximum-speed = "super-speed-plus";
+			dr_mode = "otg";
+			usb-role-switch;
+		};
+	};
+
+	/* Secondary USB port related High Speed PHY */
+	usb2_phy1: hsphy@8902000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x08902000 0x120>;
+		reg-names = "hsusb_phy_base";
+
+		vdd-supply = <&L1C0>;
+		vdda18-supply = <&L7C0>;
+		vdda33-supply = <&L2C0>;
+
+		qcom,vdd-voltage-level = <0 912000 912000>;
+
+		clocks = <&dummycc RPMH_CXO_CLK>;
+		clock-names = "ref_clk_src";
+
+		resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
+		reset-names = "phy_reset";
+		qcom,param-override-seq =
+			<0x63 0x6c	/* override_x0 */
+			 0xC8 0x70	/* override_x1 */
+			 0x17 0x74>;	/* override x2 */
+
+		status = "disabled";
+	};
+
+	/* Secondary USB port related USB4-USB3-DP PHY */
+	usb_qmp_dp_phy1: ssphy@8903000 {
+		compatible = "qcom,usb-ssphy-qmp-dp-combo";
+		reg = <0x8903000 0x4000>;
+		reg-names = "qmp_phy_base";
+
+		vdd-supply = <&L1C0>;
+		qcom,vdd-voltage-level = <0 912000 912000>;
+		qcom,vdd-max-load-uA = <47000>;
+		core-supply = <&L4C0>;
+
+		clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
+			 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
+			 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK_SRC>,
+			 <&usb3_uni_phy_sec_gcc_usb30_pipe_clk>,
+			 <&dummycc RPMH_CXO_CLK>,
+			 <&gcc GCC_USB4_CLKREF_CLK>,
+			 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
+		clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
+				"pipe_clk_ext_src", "ref_clk_src",
+				"ref_clk", "com_aux_clk";
+
+		resets = <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>,
+				<&gcc GCC_USB3_PHY_SEC_BCR>;
+		reset-names = "global_phy_reset", "phy_reset";
+
+		qcom,qmp-phy-reg-offset =
+			<USB3_PCS_PCS_STATUS1
+			 USB3_PCS_USB3_AUTONOMOUS_MODE_CTRL
+			 USB3_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
+			 USB3_PCS_POWER_DOWN_CONTROL
+			 USB3_PCS_SW_RESET
+			 USB3_PCS_START_CONTROL
+			 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
+			 USB43DP_COM_POWER_DOWN_CTRL
+			 USB43DP_COM_SW_RESET
+			 USB43DP_COM_RESET_OVRD_CTRL1
+			 USB43DP_COM_PHY_MODE_CTRL
+			 USB43DP_COM_TYPEC_CTRL
+			 USB3_PCS_CLAMP_ENABLE
+			 USB43DP_COM_TYPEC_STATUS>;
+
+		qcom,qmp-phy-init-seq =
+			/* <reg_offset, value, delay> */
+			<USB3_QSERDES_PLL_SSC_EN_CENTER	0x01
+			USB3_QSERDES_PLL_SSC_PER1	0x31
+			USB3_QSERDES_PLL_SSC_PER2	0x01
+			USB3_QSERDES_PLL_SSC_STEP_SIZE1_MODE0	0xFD
+			USB3_QSERDES_PLL_SSC_STEP_SIZE2_MODE0	0x0D
+			USB3_QSERDES_PLL_SSC_STEP_SIZE1_MODE1	0xFD
+			USB3_QSERDES_PLL_SSC_STEP_SIZE2_MODE1	0x0D
+			USB3_QSERDES_PLL_SYSCLK_BUF_ENABLE	0x0A
+			USB3_QSERDES_PLL_CP_CTRL_MODE0	0x02
+			USB3_QSERDES_PLL_CP_CTRL_MODE1	0x02
+			USB3_QSERDES_PLL_PLL_RCTRL_MODE0	0x16
+			USB3_QSERDES_PLL_PLL_RCTRL_MODE1	0x16
+			USB3_QSERDES_PLL_PLL_CCTRL_MODE0	0x36
+			USB3_QSERDES_PLL_PLL_CCTRL_MODE1	0x36
+			USB3_QSERDES_PLL_SYSCLK_EN_SEL	0x1A
+			USB3_QSERDES_PLL_LOCK_CMP_EN	0x04
+			USB3_QSERDES_PLL_LOCK_CMP1_MODE0	0x14
+			USB3_QSERDES_PLL_LOCK_CMP2_MODE0	0x34
+			USB3_QSERDES_PLL_LOCK_CMP1_MODE1	0x34
+			USB3_QSERDES_PLL_LOCK_CMP2_MODE1	0x82
+			USB3_QSERDES_PLL_DEC_START_MODE0	0x04
+			USB3_QSERDES_PLL_DEC_START_MSB_MODE0	0x01
+			USB3_QSERDES_PLL_DEC_START_MODE1	0x04
+			USB3_QSERDES_PLL_DEC_START_MSB_MODE1	0x01
+			USB3_QSERDES_PLL_DIV_FRAC_START1_MODE0	0x55
+			USB3_QSERDES_PLL_DIV_FRAC_START2_MODE0	0xD5
+			USB3_QSERDES_PLL_DIV_FRAC_START3_MODE0	0x05
+			USB3_QSERDES_PLL_DIV_FRAC_START1_MODE1	0x55
+			USB3_QSERDES_PLL_DIV_FRAC_START2_MODE1	0xD5
+			USB3_QSERDES_PLL_DIV_FRAC_START3_MODE1	0x05
+			USB3_QSERDES_PLL_VCO_TUNE_MAP	0x02
+			USB3_QSERDES_PLL_VCO_TUNE1_MODE0	0xD4
+			USB3_QSERDES_PLL_VCO_TUNE2_MODE0	0x00
+			USB3_QSERDES_PLL_VCO_TUNE1_MODE1	0xD4
+			USB3_QSERDES_PLL_VCO_TUNE2_MODE1	0x00
+			USB3_QSERDES_PLL_HSCLK_SEL	0x13
+			USB3_QSERDES_PLL_HSCLK_HS_SWITCH_SEL	0x00
+			USB3_QSERDES_PLL_CORECLK_DIV_MODE0	0x0A
+			USB3_QSERDES_PLL_CORECLK_DIV_MODE1	0x04
+			USB3_QSERDES_PLL_CORE_CLK_EN	0x60
+			USB3_QSERDES_PLL_CMN_CONFIG	0x76
+			USB3_QSERDES_PLL_PLL_IVCO	0xFF
+			USB3_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0	0x20
+			USB3_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1	0x20
+			USB3_QSERDES_PLL_VCO_TUNE_INITVAL2	0x00
+			USB3_QSERDES_PLL_VCO_TUNE_MAXVAL2	0x01
+			USB3_QSERDES_PLL_SVS_MODE_CLK_SEL	0x0A
+			USB43DP_QSERDES_TXA_LANE_MODE_1	0x05
+			USB43DP_QSERDES_TXA_LANE_MODE_2	0xC2
+			USB43DP_QSERDES_TXA_LANE_MODE_3	0x10
+			USB43DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX	0x1F
+			USB43DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX	0x0A
+			USB43DP_QSERDES_RXA_SIGDET_CNTRL	0x04
+			USB43DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL	0x0E
+			USB43DP_QSERDES_RXA_SIGDET_ENABLES	0x00
+			USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B0	0xD2
+			USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B1	0xD2
+			USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B2	0xDB
+			USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B3	0x21
+			USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B4	0x3F
+			USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B5	0x80
+			USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B6	0x45
+			USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B7	0x00
+			USB43DP_QSERDES_RXA_RX_MODE_RATE2_B0	0x6B
+			USB43DP_QSERDES_RXA_RX_MODE_RATE2_B1	0x63
+			USB43DP_QSERDES_RXA_RX_MODE_RATE2_B2	0xB6
+			USB43DP_QSERDES_RXA_RX_MODE_RATE2_B3	0x23
+			USB43DP_QSERDES_RXA_RX_MODE_RATE2_B4	0x35
+			USB43DP_QSERDES_RXA_RX_MODE_RATE2_B5	0x30
+			USB43DP_QSERDES_RXA_RX_MODE_RATE2_B6	0x8E
+			USB43DP_QSERDES_RXA_RX_MODE_RATE2_B7	0x00
+			USB43DP_QSERDES_RXA_RX_IVCM_CAL_CODE_OVERRIDE	0x00
+			USB43DP_QSERDES_RXA_RX_IVCM_CAL_CTRL2	0x80
+			USB43DP_QSERDES_RXA_RX_SUMMER_CAL_SPD_MODE	0x1B
+			USB43DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET	0x38
+			USB43DP_QSERDES_RXA_UCDR_PI_CONTROLS	0x15
+			USB43DP_QSERDES_RXA_UCDR_SB2_GAIN2_RATE2	0x0A
+			USB43DP_QSERDES_RXA_RX_IVCM_POSTCAL_OFFSET	0x7C
+			USB43DP_QSERDES_RXA_VGA_CAL_CNTRL1	0x00
+			USB43DP_QSERDES_RXA_VGA_CAL_MAN_VAL	0x0D
+			USB43DP_QSERDES_RXA_DFE_DAC_ENABLE1	0x00
+			USB43DP_QSERDES_RXA_DFE_3	0x45
+			USB43DP_QSERDES_RXA_GM_CAL	0x09
+			USB43DP_QSERDES_RXA_UCDR_FO_GAIN_RATE2	0x09
+			USB43DP_QSERDES_RXA_UCDR_SO_GAIN_RATE2	0x05
+			USB43DP_QSERDES_RXA_Q_PI_INTRINSIC_BIAS_RATE32	0x3F
+			USB43DP_QSERDES_TXB_LANE_MODE_1	0x05
+			USB43DP_QSERDES_TXB_LANE_MODE_2	0xC2
+			USB43DP_QSERDES_TXB_LANE_MODE_3	0x10
+			USB43DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX	0x1F
+			USB43DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX	0x0A
+			USB43DP_QSERDES_RXB_SIGDET_CNTRL	0x04
+			USB43DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL	0x0E
+			USB43DP_QSERDES_RXB_SIGDET_ENABLES	0x00
+			USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B0	0xD2
+			USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B1	0xD2
+			USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B2	0xDB
+			USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B3	0x21
+			USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B4	0x3F
+			USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B5	0x80
+			USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B6	0x45
+			USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B7	0x00
+			USB43DP_QSERDES_RXB_RX_MODE_RATE2_B0	0x6B
+			USB43DP_QSERDES_RXB_RX_MODE_RATE2_B1	0x63
+			USB43DP_QSERDES_RXB_RX_MODE_RATE2_B2	0xB6
+			USB43DP_QSERDES_RXB_RX_MODE_RATE2_B3	0x23
+			USB43DP_QSERDES_RXB_RX_MODE_RATE2_B4	0x35
+			USB43DP_QSERDES_RXB_RX_MODE_RATE2_B5	0x30
+			USB43DP_QSERDES_RXB_RX_MODE_RATE2_B6	0x8E
+			USB43DP_QSERDES_RXB_RX_MODE_RATE2_B7	0x00
+			USB43DP_QSERDES_RXB_RX_IVCM_CAL_CODE_OVERRIDE	0x00
+			USB43DP_QSERDES_RXB_RX_IVCM_CAL_CTRL2	0x80
+			USB43DP_QSERDES_RXB_RX_SUMMER_CAL_SPD_MODE	0x1B
+			USB43DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET	0x38
+			USB43DP_QSERDES_RXB_UCDR_PI_CONTROLS	0x15
+			USB43DP_QSERDES_RXB_UCDR_SB2_GAIN2_RATE2	0x0A
+			USB43DP_QSERDES_RXB_RX_IVCM_POSTCAL_OFFSET	0x7C
+			USB43DP_QSERDES_RXB_VGA_CAL_CNTRL1	0x00
+			USB43DP_QSERDES_RXB_VGA_CAL_MAN_VAL	0x0D
+			USB43DP_QSERDES_RXB_DFE_DAC_ENABLE1	0x00
+			USB43DP_QSERDES_RXB_DFE_3	0x45
+			USB43DP_QSERDES_RXB_GM_CAL	0x09
+			USB43DP_QSERDES_RXB_UCDR_FO_GAIN_RATE2	0x09
+			USB43DP_QSERDES_RXB_UCDR_SO_GAIN_RATE2	0x05
+			USB43DP_QSERDES_RXB_Q_PI_INTRINSIC_BIAS_RATE32	0x3F
+			USB3_PCS_RCVR_DTCT_DLY_P1U2_L	0xE7
+			USB3_PCS_RCVR_DTCT_DLY_P1U2_H	0x03
+			USB3_PCS_LOCK_DETECT_CONFIG1	0xD0
+			USB3_PCS_LOCK_DETECT_CONFIG2	0x07
+			USB3_PCS_LOCK_DETECT_CONFIG3	0x20
+			USB3_PCS_LOCK_DETECT_CONFIG6	0x13
+			USB3_PCS_REFGEN_REQ_CONFIG1	0x21
+			USB3_PCS_RX_SIGDET_LVL	0xAA
+			USB3_PCS_RX_CONFIG	0x0A
+			USB3_PCS_ALIGN_DETECT_CONFIG1	0x88
+			USB3_PCS_ALIGN_DETECT_CONFIG2	0x13
+			USB3_PCS_PCS_TX_RX_CONFIG	0x0C
+			USB3_PCS_EQ_CONFIG1	0x4B
+			USB3_PCS_EQ_CONFIG5	0x10
+			USB3_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL	0xF8
+			USB3_PCS_USB3_RXEQTRAINING_DFE_TIME_S2	0x07>;
+
+		status = "disabled";
+	};
+
+	/* Tertiary USB port related controller */
+	usb2: ssusb@a400000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0xa400000 0x100000>;
+		reg-names = "core_base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		dma-ranges;
+
+		interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>,
+				<&pdc 126 IRQ_TYPE_EDGE_RISING>,
+				<&pdc 129 IRQ_TYPE_EDGE_RISING>,
+				<&pdc 128 IRQ_TYPE_EDGE_RISING>,
+				<&pdc 131 IRQ_TYPE_EDGE_RISING>,
+				<&pdc 130 IRQ_TYPE_EDGE_RISING>,
+				<&pdc 133 IRQ_TYPE_EDGE_RISING>,
+				<&pdc 132 IRQ_TYPE_EDGE_RISING>,
+				<&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
+				<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq",
+				"dp_hs_phy_irq1", "dm_hs_phy_irq1",
+				"dp_hs_phy_irq2", "dm_hs_phy_irq2",
+				"dp_hs_phy_irq3", "dm_hs_phy_irq3",
+				"ss_phy_irq", "ss_phy_irq1";
+		qcom,use-pdc-interrupts;
+
+		USB3_GDSC-supply = <&gcc_usb30_mp_gdsc>;
+		clocks = <&gcc GCC_USB30_MP_MASTER_CLK>,
+			<&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
+			<&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
+			<&gcc GCC_USB30_MP_SLEEP_CLK>,
+			<&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
+			<&gcc GCC_SYS_NOC_USB_AXI_CLK>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+				"utmi_clk", "sleep_clk", "noc_aggr_clk",
+				"noc_aggr_north_clk", "noc_aggr_south_clk",
+				"noc_sys_clk";
+
+		resets = <&gcc GCC_USB30_MP_BCR>;
+		reset-names = "core_reset";
+
+		qcom,core-clk-rate = <200000000>;
+		qcom,host-poweroff-in-pm-suspend;
+
+		status = "disabled";
+
+		dwc3@a400000 {
+			compatible = "snps,dwc3";
+			reg = <0xa400000 0xd93c>;
+			iommus = <&apps_smmu 0x0800 0x0>;
+			qcom,iommu-dma = "bypass";
+			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+			usb-phy = <&usb2_phy2>, <&usb_qmp_phy0>,
+				<&usb2_phy3>, <&usb_qmp_phy1>,
+				<&usb2_phy4>, <&usb_nop_phy>,
+				<&usb2_phy5>, <&usb_nop_phy>;
+			snps,disable-clk-gating;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,ssp-u3-u0-quirk;
+			snps,is-utmi-l1-suspend;
+			snps,dis_u3_susphy_quirk;
+			maximum-speed = "super-speed-plus";
+			dr_mode = "host";
+		};
+	};
+
+	/* Tertiary USB port 0 related High Speed PHY */
+	usb2_phy2: hsphy@88e7000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x88e7000 0x120>;
+		reg-names = "hsusb_phy_base";
+
+		vdd-supply = <&L5A0>;
+		vdda18-supply = <&L7G0>;
+		vdda33-supply = <&L13A0>;
+		qcom,vdd-voltage-level = <0 912000 912000>;
+
+		clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
+		clock-names = "ref_clk_src";
+
+		resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
+		reset-names = "phy_reset";
+		qcom,param-override-seq =
+			<0x63 0x6c	/* override_x0 */
+			 0xC8 0x70	/* override_x1 */
+			 0x17 0x74>;	/* override x2 */
+
+		status = "disabled";
+	};
+
+	/* Tertiary USB port 0 related QMP PHY */
+	usb_qmp_phy0: ssphy@88ef000 {
+		compatible = "qcom,usb-ssphy-qmp-v2";
+		reg = <0x88ef000 0x2000>,
+		    <0x088ef28c 0x4>;
+		reg-names = "qmp_phy_base",
+			"pcs_clamp_enable_reg";
+
+		vdd-supply = <&L5A0>;
+		qcom,vdd-voltage-level = <0 912000 912000>;
+		qcom,vdd-max-load-uA = <47000>;
+		core-supply = <&L3A0>;
+
+		clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
+			 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>,
+			 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK_SRC>,
+			 <&usb3_uni_phy_mp_gcc_usb30_pipe_0_clk>,
+			 <&dummycc RPMH_CXO_CLK>,
+			 <&gcc GCC_USB3_MP0_CLKREF_CLK>,
+			 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>;
+		clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
+				"pipe_clk_ext_src", "ref_clk_src",
+				"ref_clk", "com_aux_clk";
+
+		resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
+				<&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
+		reset-names = "phy_reset", "phy_phy_reset";
+
+		qcom,qmp-phy-reg-offset =
+				<USB3_UNI_PCS_PCS_STATUS1
+				USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
+				USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
+				USB3_UNI_PCS_POWER_DOWN_CONTROL
+				USB3_UNI_PCS_SW_RESET
+				USB3_UNI_PCS_START_CONTROL>;
+
+		qcom,qmp-phy-init-seq =
+				/* <reg_offset, value, delay> */
+				<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1A
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11
+				USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01
+				USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E
+				USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x06
+				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16
+				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36
+				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24
+				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34
+				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14
+				USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04
+				USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A
+				USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02
+				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24
+				USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08
+				USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02
+				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82
+				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34
+				USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06
+				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16
+				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E
+				USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01
+				USB3_UNI_QSERDES_COM_SSC_PER1 0x31
+				USB3_UNI_QSERDES_COM_SSC_PER2 0x01
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07
+				USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xDC
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xBD
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xFF
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7F
+				USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xFF
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xA9
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7B
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0xE4
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0x24
+				USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0x64
+				USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99
+				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x08
+				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x00
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x04
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2F
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xFF
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0F
+				USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A
+				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54
+				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0F
+				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0F
+				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0A
+				USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
+				USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80
+				USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04
+				USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0E
+				USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38
+				USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x05
+				USB3_UNI_QSERDES_RX_GM_CAL 0x00
+				USB3_UNI_QSERDES_RX_SIGDET_ENABLES 0x00
+				USB3_UNI_QSERDES_TX_LANE_MODE_1 0xA5
+				USB3_UNI_QSERDES_TX_LANE_MODE_2 0x82
+				USB3_UNI_QSERDES_TX_LANE_MODE_3 0x3F
+				USB3_UNI_QSERDES_TX_LANE_MODE_4 0x3F
+				USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x21
+				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10
+				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x0E
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xD0
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13
+				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
+				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
+				USB3_UNI_PCS_RX_SIGDET_LVL 0xAA
+				USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0C
+				USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07
+				USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
+				USB3_UNI_PCS_CDR_RESET_TIME 0x0A
+				USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88
+				USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13
+				USB3_UNI_PCS_EQ_CONFIG1	0x4B
+				USB3_UNI_PCS_EQ_CONFIG5 0x10
+				USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21>;
+
+		status = "disabled";
+	};
+
+	/* Tertiary USB port 1 related High Speed PHY */
+	usb2_phy3: hsphy@88e8000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x88e8000 0x120>;
+		reg-names = "hsusb_phy_base";
+
+		vdd-supply = <&L5A0>;
+		vdda18-supply = <&L7G0>;
+		vdda33-supply = <&L13A0>;
+		qcom,vdd-voltage-level = <0 912000 912000>;
+
+		clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
+		clock-names = "ref_clk_src";
+
+		resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
+		reset-names = "phy_reset";
+		qcom,param-override-seq =
+			<0x63 0x6c	/* override_x0 */
+			 0xC8 0x70	/* override_x1 */
+			 0x17 0x74>;	/* override x2 */
+
+		status = "disabled";
+	};
+
+	/* Tertiary USB port 1 related QMP PHY */
+	usb_qmp_phy1: ssphy@88f1000 {
+		compatible = "qcom,usb-ssphy-qmp-v2";
+		reg = <0x88f1000 0x2000>,
+		    <0x088f128c 0x4>;
+		reg-names = "qmp_phy_base",
+			"pcs_clamp_enable_reg";
+
+		vdd-supply = <&L5A0>;
+		qcom,vdd-voltage-level = <0 912000 912000>;
+		qcom,vdd-max-load-uA = <47000>;
+		core-supply = <&L3A0>;
+
+		clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
+			 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>,
+			 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK_SRC>,
+			 <&usb3_uni_phy_mp_gcc_usb30_pipe_1_clk>,
+			 <&dummycc RPMH_CXO_CLK>,
+			 <&gcc GCC_USB3_MP1_CLKREF_CLK>,
+			 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>;
+		clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
+				"pipe_clk_ext_src", "ref_clk_src",
+				"ref_clk", "com_aux_clk";
+
+		resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
+				<&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
+		reset-names = "phy_reset", "phy_phy_reset";
+
+		qcom,qmp-phy-reg-offset =
+				<USB3_UNI_PCS_PCS_STATUS1
+				USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
+				USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
+				USB3_UNI_PCS_POWER_DOWN_CONTROL
+				USB3_UNI_PCS_SW_RESET
+				USB3_UNI_PCS_START_CONTROL>;
+
+		qcom,qmp-phy-init-seq =
+				/* <reg_offset, value, delay> */
+				<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1A
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11
+				USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01
+				USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E
+				USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x06
+				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16
+				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36
+				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24
+				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34
+				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14
+				USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04
+				USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A
+				USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02
+				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24
+				USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08
+				USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02
+				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82
+				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34
+				USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06
+				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16
+				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E
+				USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01
+				USB3_UNI_QSERDES_COM_SSC_PER1 0x31
+				USB3_UNI_QSERDES_COM_SSC_PER2 0x01
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07
+				USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xDC
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xBD
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xFF
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7F
+				USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xFF
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xA9
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7B
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0xE4
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0x24
+				USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0x64
+				USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99
+				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x08
+				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x00
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x04
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2F
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xFF
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0F
+				USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A
+				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54
+				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0F
+				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0F
+				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0A
+				USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
+				USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80
+				USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04
+				USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0E
+				USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38
+				USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x05
+				USB3_UNI_QSERDES_RX_GM_CAL 0x00
+				USB3_UNI_QSERDES_RX_SIGDET_ENABLES 0x00
+				USB3_UNI_QSERDES_TX_LANE_MODE_1 0xA5
+				USB3_UNI_QSERDES_TX_LANE_MODE_2 0x82
+				USB3_UNI_QSERDES_TX_LANE_MODE_3 0x3F
+				USB3_UNI_QSERDES_TX_LANE_MODE_4 0x3F
+				USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x21
+				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10
+				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x0E
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xD0
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13
+				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
+				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
+				USB3_UNI_PCS_RX_SIGDET_LVL 0xAA
+				USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0C
+				USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07
+				USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
+				USB3_UNI_PCS_CDR_RESET_TIME 0x0A
+				USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88
+				USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13
+				USB3_UNI_PCS_EQ_CONFIG1 0x4B
+				USB3_UNI_PCS_EQ_CONFIG5 0x10
+				USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21>;
+
+		status = "disabled";
+	};
+
+	/* Tertiary USB port 2 related High Speed PHY */
+	usb2_phy4: hsphy@88e9000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x88e9000 0x120>;
+		reg-names = "hsusb_phy_base";
+
+		vdd-supply = <&L5A0>;
+		vdda18-supply = <&L7G0>;
+		vdda33-supply = <&L13A0>;
+		qcom,vdd-voltage-level = <0 912000 912000>;
+
+		clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
+		clock-names = "ref_clk_src";
+
+		resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
+		reset-names = "phy_reset";
+		qcom,param-override-seq =
+			<0x63 0x6c	/* override_x0 */
+			 0xC8 0x70	/* override_x1 */
+			 0x17 0x74>;	/* override x2 */
+
+		status = "disabled";
+	};
+
+	/* Tertiary USB port 3 related High Speed PHY */
+	usb2_phy5: hsphy@88ea000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x88ea000 0x120>;
+		reg-names = "hsusb_phy_base";
+
+		vdd-supply = <&L5A0>;
+		vdda18-supply = <&L7G0>;
+		vdda33-supply = <&L13A0>;
+		qcom,vdd-voltage-level = <0 912000 912000>;
+
+		clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
+		clock-names = "ref_clk_src";
+
+		resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
+		reset-names = "phy_reset";
+		qcom,param-override-seq =
+			<0x63 0x6c	/* override_x0 */
+			 0xC8 0x70	/* override_x1 */
+			 0x17 0x74>;	/* override x2 */
+
+		status = "disabled";
+	};
+};
diff --git a/qcom/direwolf-vm.dtsi b/qcom/direwolf-vm.dtsi
index 25c6cf8e..a38f885d 100755
--- a/qcom/direwolf-vm.dtsi
+++ b/qcom/direwolf-vm.dtsi
@@ -1,9 +1,25 @@
+#include <dt-bindings/clock/qcom,gcc-direwolf.h>
 #include "quin-vm-common.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. Direwolf Virtual Machine";
 	qcom,msm-name = "SA_DIREWOLF_IVI";
 	qcom,msm-id = <460 0x10000>;
+
+	aliases {
+		hsuart0 = &qupv3_se2_4uart;
+		pci-domain0 = &pcie0; /* PCIe0 domain */
+		pci-domain1 = &pcie1; /* PCIe1 domain */
+		pci-domain2 = &pcie2; /* PCIe2 domain */
+		pci-domain3 = &pcie3; /* PCIe3 domain */
+		pci-domain4 = &pcie4; /* PCIe4 domain */
+	};
+};
+
+&firmware {
+	scm {
+		compatible = "qcom,scm";
+	};
 };
 
 &soc {
@@ -158,6 +174,26 @@
 		memory-region = <&system_cma>;
 	};
 
+	qtee_shmbridge {
+		compatible = "qcom,tee-shared-memory-bridge";
+		/*Boolean property to disable shmbridge*/
+		qcom,disable-shmbridge-support;
+	};
+
+	qcom_qseecom: qseecom@c1800000 {
+		compatible = "qcom,qseecom";
+		reg = <0xc1800000 0x3900000>;
+		reg-names = "secapp-region";
+		memory-region = <&qseecom_mem>;
+		qcom,hlos-num-ce-hw-instances = <1>;
+		qcom,hlos-ce-hw-instance = <0>;
+		qcom,qsee-ce-hw-instance = <0>;
+		qcom,disk-encrypt-pipe-pair = <2>;
+		qcom,no-clock-support;
+		qcom,commonlib-loaded-by-hostvm;
+		qcom,qsee-reentrancy-support = <2>;
+	};
+
 	qcom_rng_ee3: qrng@10d3000 {
 		compatible = "qcom,msm-rng";
 		reg = <0x10d3000 0x1000>;
@@ -184,118 +220,349 @@
 		interrupt-parent = <&intc>;
 		interrupt-controller;
 	};
+
+	tlmm: pinctrl@f000000 {
+		compatible = "qcom,direwolf-pinctrl";
+		reg = <0x0F000000 0x1000000>;
+		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	VDD_CX_LEVEL:
+	S1A0_LEVEL: pm8540_a0_s1_level: regulator-pm8540_a0-s1-level {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8540_a0_s1_level";
+		regulator-min-microvolt =
+			<RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt =
+			<RPMH_REGULATOR_LEVEL_MAX>;
+	};
+
+	pcie_2a_pipe_clk: pcie_2a_pipe_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <1000>;
+		clock-output-names = "pcie_2a_pipe_clk";
+		#clock-cells = <0>;
+	};
+
+	pcie_2b_pipe_clk: pcie_2b_pipe_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <1000>;
+		clock-output-names = "pcie_2b_pipe_clk";
+		#clock-cells = <0>;
+	};
+
+	pcie_3a_pipe_clk: pcie_3a_pipe_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <1000>;
+		clock-output-names = "pcie_3a_pipe_clk";
+		#clock-cells = <0>;
+	};
+
+	pcie_3b_pipe_clk: pcie_3b_pipe_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <1000>;
+		clock-output-names = "pcie_3b_pipe_clk";
+		#clock-cells = <0>;
+	};
+
+	pcie_4_pipe_clk: pcie_4_pipe_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <1000>;
+		clock-output-names = "pcie_4_pipe_clk";
+		#clock-cells = <0>;
+	};
+
+	usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <1000>;
+		clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
+		#clock-cells = <0>;
+	};
+
+	usb3_uni_phy_mp_gcc_usb30_pipe_0_clk: usb3_uni_phy_mp_gcc_usb30_pipe_0_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <1000>;
+		clock-output-names = "usb3_uni_phy_mp_gcc_usb30_pipe_0_clk";
+		#clock-cells = <0>;
+	};
+
+	usb3_uni_phy_mp_gcc_usb30_pipe_1_clk: usb3_uni_phy_mp_gcc_usb30_pipe_1_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <1000>;
+		clock-output-names = "usb3_uni_phy_mp_gcc_usb30_pipe_1_clk";
+		#clock-cells = <0>;
+	};
+
+	usb3_uni_phy_sec_gcc_usb30_pipe_clk: usb3_uni_phy_sec_gcc_usb30_pipe_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <1000>;
+		clock-output-names = "usb3_uni_phy_sec_gcc_usb30_pipe_clk";
+		#clock-cells = <0>;
+	};
+
+	rpmh_cxo_clk: rpmh_cxo_clk {
+		compatible = "qcom,dummycc";
+		clock-output-names = "bi_tcxo";
+		#clock-cells = <0>;
+	};
+
+	/* PWR_CTR2_VDD_1P8 supply */
+	vreg_conn_1p8: vreg_conn_1p8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vreg_conn_1p8";
+		pinctrl-names = "default";
+		pinctrl-0 = <&conn_power_1p8_active>;
+		startup-delay-us = <4000>;
+		enable-active-high;
+		gpio = <&tlmm 128 0>;
+	};
+
+	/* PWR_CTR1_VDD_PA supply */
+	vreg_conn_pa: vreg_conn_pa {
+		compatible = "regulator-fixed";
+		regulator-name = "vreg_conn_pa";
+		pinctrl-names = "default";
+		pinctrl-0 = <&conn_power_pa_active>;
+		startup-delay-us = <4000>;
+		enable-active-high;
+		gpio = <&tlmm 129 0>;
+	};
 };
 
 &regulator {
-	virt_regulator {
-		compatible = "virtio,device31";
+	gcc_usb30_prim_gdsc: gcc_usb30_prim_gdsc {
+		regulator-name = "gcc_usb30_prim_gdsc";
+	};
 
-		gcc_usb30_prim_gdsc: gcc_usb30_prim_gdsc {
-			regulator-name = "gcc_usb30_prim_gdsc";
-		};
+	gcc_usb30_sec_gdsc: gcc_usb30_sec_gdsc {
+		regulator-name = "gcc_usb30_sec_gdsc";
+	};
 
-		gcc_usb30_sec_gdsc: gcc_usb30_sec_gdsc {
-			regulator-name = "gcc_usb30_sec_gdsc";
-		};
+	gcc_usb30_mp_gdsc: gcc_usb30_mp_gdsc {
+		regulator-name = "gcc_usb30_mp_gdsc";
+	};
 
-		gcc_usb30_mp_gdsc: gcc_usb30_mp_gdsc {
-			regulator-name = "gcc_usb30_mp_gdsc";
-		};
+	gcc_pcie_2a_gdsc: gcc_pcie_2a_gdsc {
+		regulator-name = "gcc_pcie_2a_gdsc";
+	};
 
-		gcc_pcie_2a_gdsc: gcc_pcie_2a_gdsc {
-			regulator-name = "gcc_pcie_2a_gdsc";
-		};
+	gcc_pcie_2b_gdsc: gcc_pcie_2b_gdsc {
+		regulator-name = "gcc_pcie_2b_gdsc";
+	};
 
-		gcc_pcie_2b_gdsc: gcc_pcie_2b_gdsc {
-			regulator-name = "gcc_pcie_2b_gdsc";
-		};
+	gcc_pcie_3a_gdsc: gcc_pcie_3a_gdsc {
+		regulator-name = "gcc_pcie_3a_gdsc";
+	};
 
-		gcc_pcie_3a_gdsc: gcc_pcie_3a_gdsc {
-			regulator-name = "gcc_pcie_3a_gdsc";
-		};
+	gcc_pcie_3b_gdsc: gcc_pcie_3b_gdsc {
+		regulator-name = "gcc_pcie_3b_gdsc";
+	};
 
-		gcc_pcie_3b_gdsc: gcc_pcie_3b_gdsc {
-			regulator-name = "gcc_pcie_3b_gdsc";
-		};
+	gcc_pcie_4_gdsc: gcc_pcie_4_gdsc {
+		regulator-name = "gcc_pcie_4_gdsc";
+	};
 
-		gcc_pcie_4_gdsc: gcc_pcie_4_gdsc {
-			regulator-name = "gcc_pcie_4_gdsc";
-		};
+	L3A0: pm8540_a0_l3: regulator-pm8540_a0-l3 {
+		regulator-name = "ldoa3";
+		regulator-min-microvolt = <1140000>;
+		regulator-max-microvolt = <1260000>;
+	};
 
-		L3A0: pm8540_a0_l3: regulator-pm8540_a0-l3 {
-			regulator-name = "ldoa3";
-			regulator-min-microvolt = <1140000>;
-			regulator-max-microvolt = <1260000>;
-		};
+	S4E0: pm8540_e0_s4: regulator-pm8540_e0-s4 {
+		regulator-name = "smpe4";
+		regulator-min-microvolt = <320000>;
+		regulator-max-microvolt = <2040000>;
+	};
 
-		S4E0: pm8540_e0_s4: regulator-pm8540_e0-s4 {
-			regulator-name = "smpe4";
-			regulator-min-microvolt = <320000>;
-			regulator-max-microvolt = <2040000>;
-		};
+	L5A0: pm8540_a0_l5: regulator-pm8540_a0-l5 {
+		regulator-name = "ldoa5";
+		regulator-min-microvolt = <720000>;
+		regulator-max-microvolt = <950000>;
+	};
 
-		L5A0: pm8540_a0_l5: regulator-pm8540_a0-l5 {
-			regulator-name = "ldoa5";
-			regulator-min-microvolt = <720000>;
-			regulator-max-microvolt = <950000>;
-		};
+	L6G0: pm8540_g0_l6: regulator-pm8540_g0-l6 {
+		regulator-name = "ldog6";
+	};
 
-		L6G0: pm8540_g0_l6: regulator-pm8540_g0-l6 {
-			regulator-name = "ldog6";
-		};
+	L7A0: pm8540_a0_l7: regulator-pm8540_a0-l7 {
+		regulator-name = "ldoa7";
+		regulator-min-microvolt = <1620000>;
+		regulator-max-microvolt = <1980000>;
+	};
 
-		L7A0: pm8540_a0_l7: regulator-pm8540_a0-l7 {
-			regulator-name = "ldoa7";
-			regulator-min-microvolt = <1620000>;
-			regulator-max-microvolt = <1980000>;
-		};
+	L11A0: pm8540_a0_l11: regulator-pm8540_a0-l11 {
+		regulator-name = "ldoa11";
+		regulator-min-microvolt = <830000>;
+		regulator-max-microvolt = <920000>;
+	};
 
-		L11A0: pm8540_a0_l11: regulator-pm8540_a0-l11 {
-			regulator-name = "ldoa11";
-			regulator-min-microvolt = <830000>;
-			regulator-max-microvolt = <920000>;
-		};
+	L13A0: pm8540_a0_l13: regulator-pm8540_a0-l13 {
+		regulator-name = "ldoa13";
+		regulator-min-microvolt = <2970000>;
+		regulator-max-microvolt = <3544000>;
+	};
 
-		L13A0: pm8540_a0_l13: regulator-pm8540_a0-l13 {
-			regulator-name = "ldoa13";
-			regulator-min-microvolt = <2970000>;
-			regulator-max-microvolt = <3544000>;
-		};
+	L1C0: pm8540_c0_l1: regulator-pm8540_c0-l1 {
+		regulator-name = "ldoc1";
+		regulator-min-microvolt = <720000>;
+		regulator-max-microvolt = <950000>;
+	};
 
-		L1C0: pm8540_c0_l1: regulator-pm8540_c0-l1 {
-			regulator-name = "ldoc1";
-			regulator-min-microvolt = <720000>;
-			regulator-max-microvolt = <950000>;
-		};
+	L7C0: pm8540_c0_l7: regulator-pm8540_c0-l7 {
+		regulator-name = "ldoc7";
+		regulator-min-microvolt = <1620000>;
+		regulator-max-microvolt = <1980000>;
+	};
 
-		L7C0: pm8540_c0_l7: regulator-pm8540_c0-l7 {
-			regulator-name = "ldoc7";
-			regulator-min-microvolt = <1620000>;
-			regulator-max-microvolt = <1980000>;
-		};
+	L2C0: pm8540_c0_l2: regulator-pm8540_c0-l2 {
+		regulator-name = "ldoc2";
+		regulator-min-microvolt = <2970000>;
+		regulator-max-microvolt = <3544000>;
+	};
 
-		L2C0: pm8540_c0_l2: regulator-pm8540_c0-l2 {
-			regulator-name = "ldoc2";
-			regulator-min-microvolt = <2970000>;
-			regulator-max-microvolt = <3544000>;
+	L15A0: pm8540_a0_l15: regulator-pm8540_a0-l15 {
+		regulator-name = "ldoa15";
+	};
+
+	L7G0: pm8540_g0_l7: regulator-pm8540_g0-l7 {
+		regulator-name = "ldog7";
+		regulator-min-microvolt = <1620000>;
+		regulator-max-microvolt = <1980000>;
+	};
+
+	L4C0: pm8540_c0_l4: regulator-pm8540_c0-l4 {
+		regulator-name = "ldoc4";
+		regulator-min-microvolt = <1140000>;
+		regulator-max-microvolt = <1260000>;
+	};
+};
+
+&soc {
+	tcsr_compute_signal_glb: syscon@0x1fd8000 {
+		compatible = "syscon";
+		reg = <0x1fd8000 0x1000>;
+	};
+
+	tcsr_compute_signal_sender0: syscon@0x1fd9000 {
+		compatible = "syscon";
+		reg = <0x1fd9000 0x1000>;
+	};
+
+	tcsr_compute_signal_sender1: syscon@0x1fdd000 {
+		compatible = "syscon";
+		reg = <0x1fdd000 0x1000>;
+	};
+
+	tcsr_compute_signal_receiver0: syscon@0x1fdb000 {
+		compatible = "syscon";
+		reg = <0x1fdb000 0x1000>;
+	};
+
+	tcsr_compute_signal_receiver1: syscon@0x1fdf000 {
+		compatible = "syscon";
+		reg = <0x1fdf000 0x1000>;
+	};
+
+	hgsl_tcsr_sender0: hgsl_tcsr_sender0 {
+		compatible = "qcom,hgsl-tcsr-sender";
+		syscon = <&tcsr_compute_signal_sender0>;
+		syscon-glb = <&tcsr_compute_signal_glb>;
+	};
+
+	hgsl_tcsr_sender1: hgsl_tcsr_sender1 {
+		compatible = "qcom,hgsl-tcsr-sender";
+		syscon = <&tcsr_compute_signal_sender1>;
+		syscon-glb = <&tcsr_compute_signal_glb>;
+	};
+
+	hgsl_tcsr_receiver0: hgsl_tcsr_receiver0 {
+		compatible = "qcom,hgsl-tcsr-receiver";
+		syscon = <&tcsr_compute_signal_receiver0>;
+		interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	hgsl_tcsr_receiver1: hgsl_tcsr_receiver1 {
+		compatible = "qcom,hgsl-tcsr-receiver";
+		syscon = <&tcsr_compute_signal_receiver1>;
+		interrupts = <0 239 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	msm_gpu_hyp: qcom,hgsl@0x2c00000 {
+		compatible = "qcom,hgsl";
+		reg = <0x2c00000 0x8>, <0x2c8f000 0x4>;
+		reg-names = "hgsl_reg_hwinf", "hgsl_reg_gmucx";
+
+		qcom,glb-db-senders = <&hgsl_tcsr_sender0
+					&hgsl_tcsr_sender1>;
+		qcom,glb-db-receivers = <&hgsl_tcsr_receiver0
+					&hgsl_tcsr_receiver1>;
+	};
+};
+
+#include "pm8540-vm.dtsi"
+#include "direwolf-pinctrl.dtsi"
+#include "direwolf-vm-pcie.dtsi"
+#include "direwolf-qupv3.dtsi"
+#include "direwolf-vm-usb.dtsi"
+
+&qupv3_0 {
+	qcom,iommu-dma = "bypass";
+};
+
+&qupv3_1 {
+	qcom,iommu-dma = "bypass";
+};
+
+&qupv3_2 {
+	qcom,iommu-dma = "bypass";
+};
+
+&pm8540_2_gpios {
+	usb20_vbus_boost {
+		usb20_vbus_boost_default: usb20_vbus_boost_default {
+			pins = "gpio9";
+			function = "normal";
+			output-high;
+			power-source = <0>;
 		};
+	};
+};
 
-		L15A0: pm8540_a0_l15: regulator-pm8540_a0-l15 {
-			regulator-name = "ldoa15";
+&pm8540_3_gpios {
+	usb21_vbus_boost {
+		usb21_vbus_boost_default: usb21_vbus_boost_default {
+			pins = "gpio5";
+			function = "normal";
+			output-high;
+			power-source = <0>;
 		};
+	};
+};
 
-		L7G0: pm8540_g0_l7: regulator-pm8540_g0-l7 {
-			regulator-name = "ldog7";
-			regulator-min-microvolt = <1620000>;
-			regulator-max-microvolt = <1980000>;
+&pm8540_4_gpios {
+	usb223_vbus_boost {
+		usb22_vbus_boost_default: usb22_vbus_boost_default {
+			pins = "gpio5";
+			function = "normal";
+			output-high;
+			power-source = <0>;
 		};
 
-		L4C0: pm8540_c0_l4: regulator-pm8540_c0-l4 {
-			regulator-name = "ldoc4";
-			regulator-min-microvolt = <1140000>;
-			regulator-max-microvolt = <1260000>;
+		usb23_vbus_boost_default: usb23_vbus_boost_default {
+			pins = "gpio9";
+			function = "normal";
+			output-high;
+			power-source = <0>;
 		};
 	};
 };
 
-#include "pm8540-vm.dtsi"
+&usb2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb20_vbus_boost_default &usb21_vbus_boost_default
+				&usb22_vbus_boost_default &usb23_vbus_boost_default>;
+};
diff --git a/qcom/fg-gen4-batterydata-atl466274-3650mah.dtsi b/qcom/fg-gen4-batterydata-atl466274-3650mah.dtsi
new file mode 100755
index 00000000..f5e78e3a
--- /dev/null
+++ b/qcom/fg-gen4-batterydata-atl466274-3650mah.dtsi
@@ -0,0 +1,138 @@
+
+qcom,atl466274_3650mah_averaged_masterslave_may14th2019 {
+	/* #ATL466274_3650mAh_averaged_MasterSlave_May14th2019*/
+	qcom,max-voltage-uv = <4400000>;
+	qcom,fg-cc-cv-threshold-mv = <4390>;
+	qcom,fastchg-current-ma = <5325>;
+	qcom,batt-id-kohm = <31>;
+	/* COLD = 0 DegC, HOT = 55 DegC */
+	qcom,jeita-hard-thresholds = <0x58cd 0x181d>;
+	/* COOL = 10 DegC, WARM = 45 DegC */
+	qcom,jeita-soft-thresholds = <0x4ccc 0x20b8>;
+	/* COOL hys = 13 DegC, WARM hys = 42 DegC */
+	qcom,jeita-soft-hys-thresholds = <0x48d4 0x23c0>;
+	qcom,jeita-fcc-ranges = <0  100  1065000
+				101 200  1775000
+				201 450  5325000
+				451 550  1775000>;
+	qcom,jeita-fv-ranges = <0   100  4400000
+				101 200  4400000
+				201 450  4400000
+				451 550  4050000>;
+	qcom,jeita-soft-fcc-ua = <1065000 1775000>;
+	qcom,jeita-soft-fv-uv = <4400000 4050000>;
+	qcom,battery-beta = <4250>;
+	qcom,battery-type = "ATL466274_3650mah_masterslave_may14th2019";
+	qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>;
+	qcom,therm-center-offset = <0x70>;
+	qcom,rslow-normal-coeffs = <0xb1 0xfa 0x99 0x13>;
+	qcom,rslow-low-coeffs = <0x79 0x15 0x21 0xfa>;
+	qcom,checksum = <0xCC95>;
+	qcom,gui-version = "PM855GUI - 1.0.0.13";
+	qcom,fg-profile-data = [
+		 09 00 CB E3
+		 B1 DD D0 DB
+		 31 D4 00 00
+		 9F BD BE 83
+		 FE 87 38 9C
+		 6C 87 9B 80
+		 1A 00 B1 FA
+		 99 13 B9 06
+		 13 FA CE 07
+		 32 00 3D EB
+		 F9 ED BF D5
+		 38 0A 45 DB
+		 BD 9C 6F 12
+		 8B E3 55 C4
+		 60 00 4A 00
+		 47 00 43 00
+		 34 00 31 00
+		 34 00 43 00
+		 40 00 42 00
+		 44 00 60 00
+		 33 00 3D 00
+		 47 00 3F 00
+		 37 00 75 00
+		 5D 64 49 00
+		 40 00 40 08
+		 60 00 50 00
+		 4C 00 58 08
+		 4C 10 45 00
+		 84 28 5D 48
+		 4F 58 48 0E
+		 45 00 D8 08
+		 6F 20 6F 14
+		 61 03 7F FD
+		 A0 1C E7 02
+		 0D 04 24 22
+		 9B 17 2C 42
+		 B2 55 61 03
+		 71 13 44 22
+		 57 05 4B 0A
+		 5F 04 06 1D
+		 D3 02 A2 05
+		 F5 02 30 18
+		 25 23 6C 45
+		 E4 52 95 12
+		 D5 1F 3F E5
+		 D9 CA DF BD
+		 E0 1C 8B C9
+		 5B 05 43 BB
+		 55 17 B2 8B
+		 E2 84 97 93
+		 84 98 09 80
+		 A3 03 CD 05
+		 66 05 3D F2
+		 00 F8 58 D5
+		 E3 E2 F7 07
+		 D5 EB 0A C5
+		 37 18 17 00
+		 33 E7 CB 02
+		 36 07 5E 03
+		 CE 07 32 00
+		 2B 03 07 04
+		 3D 05 D6 02
+		 EB 05 73 03
+		 9F 03 33 03
+		 02 05 4C 00
+		 3D 00 42 00
+		 42 64 46 00
+		 4A 00 3E 08
+		 44 F8 46 00
+		 46 00 3B 10
+		 3E 10 3B 00
+		 49 28 4A 48
+		 52 60 64 0D
+		 40 00 48 00
+		 50 08 4C 00
+		 39 00 3E 00
+		 3D 10 48 10
+		 42 00 51 20
+		 65 40 43 58
+		 4D 0E 48 00
+		 38 00 20 08
+		 D8 00 2D 20
+		 39 05 B1 0A
+		 33 0C BD 1C
+		 71 23 97 45
+		 8D 52 5C 18
+		 22 02 7F 05
+		 0C 02 6A 11
+		 3F 0A 36 20
+		 E5 04 25 03
+		 8D 05 C5 1C
+		 FD 02 FA 05
+		 37 02 88 18
+		 B2 03 1A 04
+		 DA 02 6C 00
+		 78 20 8C 04
+		 75 03 37 05
+		 D7 1C 3B 02
+		 84 05 BF 02
+		 93 18 11 03
+		 4E 05 45 03
+		 7A 00 1D 01
+		 C0 00 FA 00
+		 47 0E 00 00
+	];
+};
diff --git a/qcom/fg-gen4-batterydata-mlp466274-3650mah.dtsi b/qcom/fg-gen4-batterydata-mlp466274-3650mah.dtsi
new file mode 100755
index 00000000..5c823942
--- /dev/null
+++ b/qcom/fg-gen4-batterydata-mlp466274-3650mah.dtsi
@@ -0,0 +1,135 @@
+qcom,mlp466274_3650mah_averaged_masterslave_jan21st2019 {
+	/* #mlp466274_3650mAh_averaged_MasterSlave_Jan21st2019*/
+	qcom,max-voltage-uv = <4400000>;
+	qcom,fg-cc-cv-threshold-mv = <4390>;
+	qcom,fastchg-current-ma = <5325>;
+	qcom,batt-id-kohm = <44>;
+	/* COLD = 0 DegC, HOT = 55 DegC */
+	qcom,jeita-hard-thresholds = <0x58cd 0x181d>;
+	/* COOL = 15 DegC, WARM = 45 DegC */
+	qcom,jeita-soft-thresholds = <0x4621 0x20b8>;
+	/* COOL hys = 18 DegC, WARM hys = 42 DegC */
+	qcom,jeita-soft-hys-thresholds = <0x4206 0x23c0>;
+	qcom,jeita-fcc-ranges = <0  150  710000
+				151 450  5325000
+				451 550  1775000>;
+	qcom,jeita-fv-ranges = <0   150  4150000
+				151 450  4400000
+				451 550  4150000>;
+	qcom,jeita-soft-fcc-ua = <710000 1775000>;
+	qcom,jeita-soft-fv-uv = <4150000 4150000>;
+	qcom,battery-beta = <4250>;
+	qcom,battery-type = "mlp466274_3650mah_masterslave_jan21st2019";
+	qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>;
+	qcom,therm-center-offset = <0x70>;
+	qcom,rslow-normal-coeffs = <0xa9 0x15 0x87 0x0d>;
+	qcom,rslow-low-coeffs = <0xae 0x0c 0x65 0xfc>;
+	qcom,checksum = <0x393C>;
+	qcom,gui-version = "PM855GUI - 1.0.0.13";
+	qcom,fg-profile-data = [
+		 09 00 15 EA
+		 CA DC 05 E3
+		 99 DC 00 00
+		 A6 BD 4F 8A
+		 F9 87 88 9D
+		 79 9A E7 87
+		 48 00 A9 15
+		 87 0D 7C 04
+		 30 02 CE 07
+		 32 00 BF EB
+		 95 ED 67 D5
+		 16 0A 1A EB
+		 5C B2 FE 0D
+		 A9 06 23 BB
+		 60 00 3E 00
+		 3D 00 3E 00
+		 38 00 32 00
+		 33 00 38 00
+		 40 00 4A 00
+		 5A 00 60 00
+		 51 00 41 00
+		 36 00 31 00
+		 2E 00 3C 00
+		 45 64 43 00
+		 47 00 40 00
+		 60 00 54 00
+		 45 00 50 08
+		 53 08 3F 00
+		 66 28 61 48
+		 51 58 4A 0E
+		 47 00 D8 00
+		 F6 1F 7F 0D
+		 FA 03 53 07
+		 73 1C DE 0A
+		 82 0C 64 23
+		 1A 17 4E 42
+		 8C 55 99 03
+		 7D 13 79 1F
+		 98 05 91 0A
+		 2B 06 BE 1C
+		 32 02 67 05
+		 F4 02 F9 17
+		 27 23 72 45
+		 DB 52 72 13
+		 FE 1F 14 ED
+		 F1 CA CA 85
+		 D3 1C 8C C1
+		 78 05 11 BB
+		 4C 17 80 8B
+		 33 85 0F 9B
+		 88 80 09 80
+		 01 F2 F2 05
+		 FE 03 AC FB
+		 00 F8 51 DD
+		 44 EB F4 07
+		 89 F5 8C CA
+		 33 18 2A 00
+		 11 DD AB 01
+		 86 05 2F 03
+		 CE 07 32 00
+		 3D 03 D9 03
+		 45 05 01 07
+		 23 02 17 05
+		 C8 03 9F 07
+		 33 03 50 00
+		 3F 00 3F 00
+		 41 64 43 00
+		 42 F8 3F 00
+		 45 00 44 00
+		 42 00 3B 10
+		 45 10 3D 00
+		 44 20 43 40
+		 45 58 4B 0F
+		 39 00 3A 00
+		 44 08 56 00
+		 4B 00 3E 00
+		 3A 10 48 10
+		 45 00 4D 20
+		 5F 40 40 58
+		 42 10 4E 00
+		 4B 08 2C 10
+		 D8 08 B3 1F
+		 41 FC B9 03
+		 EF 06 C5 1C
+		 57 23 D8 45
+		 2D 52 7D 18
+		 86 03 8C 04
+		 5C 02 6C 12
+		 3F 0A 68 20
+		 D1 04 1D 03
+		 A0 05 B9 1C
+		 1B 03 FB 05
+		 1F 02 94 18
+		 4E 03 DD 04
+		 14 02 70 00
+		 9D 23 A2 04
+		 D6 02 A4 05
+		 E6 1C D7 03
+		 78 04 CB 03
+		 84 18 F7 02
+		 88 05 D7 02
+		 95 00 58 01
+		 C0 00 FA 00
+		 29 0E 00 00
+	];
+};
diff --git a/qcom/kalama-atp-overlay.dts b/qcom/kalama-atp-overlay.dts
index fc77e033..76da30d0 100755
--- a/qcom/kalama-atp-overlay.dts
+++ b/qcom/kalama-atp-overlay.dts
@@ -6,6 +6,6 @@
 / {
 	model = "Qualcomm Technologies, Inc. Kalama ATP";
 	compatible = "qcom,kalama-atp", "qcom,kalama", "qcom,atp";
-	qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>, <600 0x20000>, <601 0x20000>;
+	qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>, <600 0x20000>, <601 0x20000>, <603 0x20000>, <604 0x20000>;
 	qcom,board-id = <0x10021 0>;
 };
diff --git a/qcom/kalama-cdp-nfc-overlay.dts b/qcom/kalama-cdp-nfc-overlay.dts
index 3466ee6a..c87537b5 100755
--- a/qcom/kalama-cdp-nfc-overlay.dts
+++ b/qcom/kalama-cdp-nfc-overlay.dts
@@ -6,6 +6,6 @@
 / {
 	model = "Qualcomm Technologies, Inc. Kalama CDP ST54K NFC";
 	compatible = "qcom,kalama-cdp", "qcom,kalama", "qcom,cdp";
-	qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>, <600 0x20000>, <601 0x20000>;
+	qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>, <600 0x20000>, <601 0x20000>, <603 0x20000>, <604 0x20000>;
 	qcom,board-id = <0x02010001 0>;
 };
diff --git a/qcom/kalama-cdp-overlay.dts b/qcom/kalama-cdp-overlay.dts
index 0b0e2b26..09196d61 100755
--- a/qcom/kalama-cdp-overlay.dts
+++ b/qcom/kalama-cdp-overlay.dts
@@ -6,6 +6,6 @@
 / {
 	model = "Qualcomm Technologies, Inc. Kalama CDP";
 	compatible = "qcom,kalama-cdp", "qcom,kalama", "qcom,cdp";
-	qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>, <600 0x20000>, <601 0x20000>;
+	qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>, <600 0x20000>, <601 0x20000>, <603 0x20000>, <604 0x20000>;
 	qcom,board-id = <0x10001 0>;
 };
diff --git a/qcom/kalama-cdp-wsa883x-overlay.dts b/qcom/kalama-cdp-wsa883x-overlay.dts
index e211712a..e808ecc9 100755
--- a/qcom/kalama-cdp-wsa883x-overlay.dts
+++ b/qcom/kalama-cdp-wsa883x-overlay.dts
@@ -6,6 +6,6 @@
 / {
 	model = "Qualcomm Technologies, Inc. Kalama CDP WSA883x";
 	compatible = "qcom,kalama-cdp", "qcom,kalama", "qcom,cdp";
-	qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>, <600 0x20000>, <601 0x20000>;
+	qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>, <600 0x20000>, <601 0x20000>, <603 0x20000>, <604 0x20000>;
 	qcom,board-id = <0x1010001 0>;
 };
diff --git a/qcom/kalama-coresight.dtsi b/qcom/kalama-coresight.dtsi
index 5f70e773..7c7abc95 100755
--- a/qcom/kalama-coresight.dtsi
+++ b/qcom/kalama-coresight.dtsi
@@ -4404,4 +4404,40 @@
 			};
 		};
 	};
+
+	spmi_tgu0: tgu@10b0f000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb999>;
+
+		reg = <0x10b0f000 0x1000>;
+		reg-names = "tgu-base";
+
+		tgu-steps = <3>;
+		tgu-conditions = <4>;
+		tgu-regs = <9>;
+		tgu-timer-counters = <8>;
+
+		coresight-name = "coresight-tgu-spmi0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	spmi_tgu1: tgu@10b10000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb999>;
+
+		reg = <0x10b10000 0x1000>;
+		reg-names = "tgu-base";
+
+		tgu-steps = <3>;
+		tgu-conditions = <4>;
+		tgu-regs = <9>;
+		tgu-timer-counters = <8>;
+
+		coresight-name = "coresight-tgu-spmi1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
 };
diff --git a/qcom/kalama-dma-heaps.dtsi b/qcom/kalama-dma-heaps.dtsi
index fbd8e20d..d5e24548 100755
--- a/qcom/kalama-dma-heaps.dtsi
+++ b/qcom/kalama-dma-heaps.dtsi
@@ -61,5 +61,17 @@
 			memory-region = <&spu_tz_shared_mem>;
 			qcom,token = <0x01000000>;
 		};
+
+		qcom,audio_ml {
+			qcom,dma-heap-name = "qcom,audio-ml";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&audio_cma_mem>;
+		};
+
+		qcom,adsp {
+			qcom,dma-heap-name = "qcom,adsp";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&sdsp_mem>;
+		};
 	};
 };
diff --git a/qcom/kalama-mtp-nfc-overlay.dts b/qcom/kalama-mtp-nfc-overlay.dts
index 608bc9ce..959f3ec7 100755
--- a/qcom/kalama-mtp-nfc-overlay.dts
+++ b/qcom/kalama-mtp-nfc-overlay.dts
@@ -6,6 +6,6 @@
 / {
 	model = "Qualcomm Technologies, Inc. Kalama MTP ST54K NFC";
 	compatible = "qcom,kalama-mtp", "qcom,kalama", "qcom,mtp";
-	qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>, <600 0x20000>, <601 0x20000>;
+	qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>, <600 0x20000>, <601 0x20000>, <604 0x20000>;
 	qcom,board-id = <0x1010008 0>;
 };
diff --git a/qcom/kalama-mtp-overlay.dts b/qcom/kalama-mtp-overlay.dts
index b4305ec3..a1c9ccfa 100755
--- a/qcom/kalama-mtp-overlay.dts
+++ b/qcom/kalama-mtp-overlay.dts
@@ -6,6 +6,6 @@
 / {
 	model = "Qualcomm Technologies, Inc. Kalama MTP";
 	compatible = "qcom,kalama-mtp", "qcom,kalama", "qcom,mtp";
-	qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>, <600 0x20000>, <601 0x20000>;
+	qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>, <600 0x20000>, <601 0x20000>, <604 0x20000>;
 	qcom,board-id = <0x10008 0>;
 };
diff --git a/qcom/kalama-mtp.dtsi b/qcom/kalama-mtp.dtsi
index b5c540d4..d78cfeb9 100755
--- a/qcom/kalama-mtp.dtsi
+++ b/qcom/kalama-mtp.dtsi
@@ -251,3 +251,208 @@
 	periph-d45-supply = <&L6N>;
 	periph-d46-supply = <&L7N>;
 };
+
+&pcie1 {
+		qcom,pcie-phy-ver = <104>;
+
+		qcom,phy-sequence = <0x1240 0x03 0x0
+				0x0030 0x18 0x0
+				0x0034 0x03 0x0
+				0x0078 0x01 0x0
+				0x007c 0x00 0x0
+				0x0080 0x51 0x0
+				0x0090 0x12 0x0
+				0x00ac 0x34 0x0
+				0x00b0 0x00 0x0
+				0x00cc 0x00 0x0
+				0x0208 0x0c 0x0
+				0x020c 0x0a 0x0
+				0x0218 0x04 0x0
+				0x0220 0x16 0x0
+				0x0234 0x00 0x0
+				0x029c 0x80 0x0
+				0x02a0 0x7c 0x0
+				0x02ac 0x00 0x0
+				0x02b0 0x20 0x0
+				0x02b4 0x05 0x0
+				0x02b8 0x00 0x0
+				0x02e0 0x40 0x0
+				0x02e4 0x00 0x0
+				0x02e8 0x0a 0x0
+				0x030c 0x0d 0x0
+				0x0318 0x80 0x0
+				0x031c 0x0a 0x0
+				0x0320 0x0f 0x0 /* setting for ultra short channel */
+				0x033c 0x74 0x0
+				0x0340 0x00 0x0
+				0x0348 0x1c 0x0
+				0x034c 0x24 0x0
+				0x0354 0x0e 0x0
+				0x0388 0x20 0x0
+				0x0390 0x28 0x0
+				0x0394 0x30 0x0
+				0x039c 0x0c 0x0
+				0x03dc 0x09 0x0
+				0x03f4 0x14 0x0
+				0x03f8 0xb3 0x0
+				0x03fc 0x58 0x0
+				0x0400 0x9a 0x0
+				0x0404 0x26 0x0
+				0x0408 0xb6 0x0
+				0x040c 0xee 0x0
+				0x0410 0xdb 0x0
+				0x0414 0xdb 0x0
+				0x0418 0xa0 0x0
+				0x041c 0xdf 0x0
+				0x0420 0x78 0x0
+				0x0424 0x76 0x0
+				0x0428 0xff 0x0
+				0x0830 0x18 0x0
+				0x0834 0x03 0x0
+				0x0878 0x01 0x0
+				0x087c 0x00 0x0
+				0x0880 0x51 0x0
+				0x0890 0x12 0x0
+				0x08ac 0x34 0x0
+				0x08b0 0x00 0x0
+				0x08cc 0x00 0x0
+				0x0a08 0x0c 0x0
+				0x0a0c 0x0a 0x0
+				0x0a18 0x04 0x0
+				0x0a20 0x16 0x0
+				0x0a34 0x00 0x0
+				0x0a9c 0x80 0x0
+				0x0aa0 0x7c 0x0
+				0x0aac 0x00 0x0
+				0x0ab0 0x20 0x0
+				0x0ab4 0x05 0x0
+				0x0ab8 0x00 0x0
+				0x0ae0 0x40 0x0
+				0x0ae4 0x00 0x0
+				0x0ae8 0x0a 0x0
+				0x0b0c 0x0d 0x0
+				0x0b18 0x80 0x0
+				0x0b1c 0x0a 0x0
+				0x0b20 0x0f 0x0 /* setting for ultra short channel */
+				0x0b3c 0x74 0x0
+				0x0b40 0x00 0x0
+				0x0b48 0x1c 0x0
+				0x0b4c 0x24 0x0
+				0x0b54 0x0e 0x0
+				0x0b88 0x20 0x0
+				0x0b90 0x28 0x0
+				0x0b94 0x30 0x0
+				0x0b9c 0x0c 0x0
+				0x0bdc 0x09 0x0
+				0x0bf4 0x14 0x0
+				0x0bf8 0xb3 0x0
+				0x0bfc 0x58 0x0
+				0x0c00 0x9a 0x0
+				0x0c04 0x26 0x0
+				0x0c08 0xb6 0x0
+				0x0c0c 0xee 0x0
+				0x0c10 0xdb 0x0
+				0x0c14 0xdb 0x0
+				0x0c18 0xa0 0x0
+				0x0c1c 0xdf 0x0
+				0x0c20 0x78 0x0
+				0x0c24 0x76 0x0
+				0x0c28 0xff 0x0
+				0x0ea0 0x01 0x0
+				0x0eb4 0x00 0x0
+				0x0eb8 0x08 0x0
+				0x0ebc 0x3e 0x0
+				0x0ec0 0x1e 0x0
+				0x0ec4 0x00 0x0
+				0x0ec8 0x1f 0x0
+				0x0ed4 0x12 0x0
+				0x0ed8 0x12 0x0
+				0x0edc 0xdb 0x0
+				0x0ee0 0x9a 0x0
+				0x0ee4 0x3f 0x0 /* setting for ultra short channel */
+				0x0ee8 0xb6 0x0
+				0x0eec 0x64 0x0
+				0x0ef0 0x1f 0x0
+				0x0ef4 0x1f 0x0
+				0x0ef8 0x1f 0x0
+				0x0efc 0x1f 0x0
+				0x0f00 0x1f 0x0
+				0x0f04 0x1f 0x0
+				0x0f0c 0x1f 0x0
+				0x0f14 0x1f 0x0
+				0x0f1c 0x1f 0x0
+				0x0f28 0x5b 0x0
+				0x1000 0x26 0x0
+				0x1004 0x03 0x0
+				0x1010 0x06 0x0
+				0x1014 0x16 0x0
+				0x1018 0x36 0x0
+				0x101c 0x04 0x0
+				0x1020 0x0a 0x0
+				0x1024 0x1a 0x0
+				0x1028 0x68 0x0
+				0x1030 0xab 0x0
+				0x1034 0xaa 0x0
+				0x1038 0x02 0x0
+				0x103c 0x12 0x0
+				0x1060 0xf8 0x0
+				0x1064 0x01 0x0
+				0x1070 0x06 0x0
+				0x1074 0x16 0x0
+				0x1078 0x36 0x0
+				0x107c 0x0a 0x0
+				0x1080 0x04 0x0
+				0x1084 0x0d 0x0
+				0x1088 0x41 0x0
+				0x1090 0xab 0x0
+				0x1094 0xaa 0x0
+				0x1098 0x01 0x0
+				0x109c 0x00 0x0
+				0x10bc 0x0a 0x0
+				0x10c0 0x01 0x0
+				0x10cc 0x62 0x0
+				0x10d0 0x02 0x0
+				0x10d8 0x40 0x0
+				0x10dc 0x14 0x0
+				0x10e0 0x90 0x0
+				0x10e4 0x82 0x0
+				0x10f4 0x0f 0x0
+				0x1110 0x08 0x0
+				0x1120 0x46 0x0
+				0x1124 0x04 0x0
+				0x1140 0x14 0x0
+				0x1164 0x34 0x0
+				0x1170 0xa0 0x0
+				0x1174 0x06 0x0
+				0x1184 0x88 0x0
+				0x1188 0x14 0x0
+				0x118c 0x00 0x0
+				0x1190 0x64 0x0
+				0x1194 0x00 0x0
+				0x1198 0x0f 0x0
+				0x1378 0x2e 0x0
+				0x1390 0xcc 0x0
+				0x13f0 0x0d 0x0
+				0x13f8 0x00 0x0
+				0x13fc 0x22 0x0
+				0x141c 0xc1 0x0
+				0x1490 0x00 0x0
+				0x14a0 0x16 0x0
+				0x14f0 0x27 0x0
+				0x14f4 0x27 0x0
+				0x14fc 0x0d 0x0
+				0x1508 0x02 0x0
+				0x155c 0x2e 0x0
+				0x157c 0x03 0x0
+				0x1584 0x28 0x0
+				0x13dc 0x04 0x0
+				0x13e0 0x02 0x0
+				0x1418 0xc0 0x0
+				0x140c 0x1d 0x0
+				0x158c 0x0f 0x0
+				0x1370 0x0f 0x0 /* setting for ultra short channel */
+				0x15ac 0xf2 0x0
+				0x15c0 0xf2 0x0
+				0x1200 0x00 0x0
+				0x1244 0x03 0x0>;
+};
diff --git a/qcom/kalama-pcie.dtsi b/qcom/kalama-pcie.dtsi
index 7921c42f..b000b559 100755
--- a/qcom/kalama-pcie.dtsi
+++ b/qcom/kalama-pcie.dtsi
@@ -109,7 +109,6 @@
 		qcom,boot-option = <0x1>;
 		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
 		qcom,drv-name = "lpass";
-		qcom,no-l0s-supported;
 		qcom,drv-l1ss-timeout-us = <5000>;
 		qcom,l1-2-th-scale = <2>;
 		qcom,l1-2-th-value = <150>;
diff --git a/qcom/kalama-qcm.dts b/qcom/kalama-qcm.dts
new file mode 100755
index 00000000..5eb9a88f
--- /dev/null
+++ b/qcom/kalama-qcm.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "kalama-qcm.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Kalama QCM SoC";
+	compatible = "qcom,kalama";
+	qcom,board-id = <0 0>;
+};
diff --git a/qcom/kalama-qcm.dtsi b/qcom/kalama-qcm.dtsi
new file mode 100755
index 00000000..701f84a5
--- /dev/null
+++ b/qcom/kalama-qcm.dtsi
@@ -0,0 +1,7 @@
+#include "kalama-v2.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Kalama QCM";
+	compatible = "qcom,kalama";
+	qcom,msm-id = <604 0x20000>;
+};
diff --git a/qcom/kalama-qrd.dtsi b/qcom/kalama-qrd.dtsi
index 3b68e1d4..97bf468f 100755
--- a/qcom/kalama-qrd.dtsi
+++ b/qcom/kalama-qrd.dtsi
@@ -191,8 +191,8 @@
 		qts,touch-environment = "pvm";
 		qts,trusted-touch-type = "primary";
 		qts,trusted-touch-spi-irq = <569>;
-		qts,trusted-touch-io-bases = <0xa90000>;
-		qts,trusted-touch-io-sizes = <0x1000>;
+		qts,trusted-touch-io-bases = <0xa90000 0xac0000>;
+		qts,trusted-touch-io-sizes = <0x1000 0x1000>;
 		qts,trusted-touch-vm-gpio-list = <&tlmm 44 0 &tlmm 45 0 &tlmm 46 0
 						&tlmm 47 0 &tlmm 24 0 &tlmm 25 0x2008>;
 	};
@@ -364,11 +364,11 @@
 					0x0018 0x36 0x0
 					0x0110 0x08 0x0
 					0x00bc 0x0a 0x0
-					0x0120 0x42 0x0
-					0x0080 0x04 0x0
-					0x0084 0x0d 0x0
-					0x0020 0x0a 0x0
-					0x0024 0x1a 0x0
+					0x0120 0x40 0x0
+					0x0080 0x0a 0x0
+					0x0084 0x1a 0x0
+					0x0020 0x14 0x0
+					0x0024 0x34 0x0
 					0x0088 0x41 0x0
 					0x0028 0x34 0x0
 					0x0090 0xab 0x0
@@ -394,7 +394,7 @@
 					0x1174 0x5c 0x0
 					0x1178 0x9c 0x0
 					0x117c 0x1a 0x0
-					0x1180 0x89 0x0
+					0x1180 0x8f 0x0
 					0x1170 0xdc 0x0
 					0x1188 0x94 0x0
 					0x118c 0x5b 0x0
@@ -424,7 +424,7 @@
 					0x1974 0x5c 0x0
 					0x1978 0x9c 0x0
 					0x197c 0x1a 0x0
-					0x1980 0x89 0x0
+					0x1980 0x8f 0x0
 					0x1970 0xdc 0x0
 					0x1988 0x94 0x0
 					0x198c 0x5b 0x0
@@ -452,17 +452,11 @@
 					0x060c 0x1d 0x0
 					0x0614 0x07 0x0
 					0x0620 0xc1 0x0
-					0x0368 0x0f 0x0
-					0x1180 0x8f 0x0
-					0x1980 0x8f 0x0
-					0x0120 0x40 0x0
-					0x0080 0x0a 0x0
-					0x0084 0x1a 0x0
-					0x0020 0x14 0x0
-					0x0024 0x34 0x0
-					0x0624 0x05 0x0
 					0x0694 0x00 0x0
 					0x03d0 0x8c 0x0
+					0x0368 0x0f 0x0
+					0x1424 0x00 0x0
+					0x1428 0x00 0x0
 					0x0200 0x00 0x0
 					0x0244 0x03 0x0>;
 
diff --git a/qcom/kalama-sg-hhg.dtsi b/qcom/kalama-sg-hhg.dtsi
index 6af80349..8bdefc2c 100755
--- a/qcom/kalama-sg-hhg.dtsi
+++ b/qcom/kalama-sg-hhg.dtsi
@@ -4,6 +4,11 @@
 	status = "disabled";
 };
 
+&qcom_qbt {
+	status = "disabled";
+};
+
+
 &pm8550_flash {
 	/delete-node/ qcom,flash_0;
 	/delete-node/ qcom,flash_1;
@@ -123,6 +128,7 @@
 		compatible = "maxim,max31760";
 		reg = <0x50>;
 		#cooling-cells = <2>;
+		maxim,fan-num = <1>;
 		maxim,vdd-supply = <&L4N>;
 		maxim,vcca-supply = <&L15B>;
 		regulator-name = "maxim,vdd", "maxim,vcca";
@@ -131,6 +137,11 @@
 		maxim,pwr-en-gpio = <&pm8550_gpios 9 GPIO_ACTIVE_LOW>;
 		status = "ok";
 	};
+
+	//disable FM
+	nq@64 {
+		status = "disabled";
+	};
 };
 
 &thermal_zones {
@@ -187,12 +198,12 @@
 		cooling-maps {
 			fan_cdev_0 {
 				trip = <&fan_cpu19_config0>;
-				cooling-device = <&fancontroller 2 2>;
+				cooling-device = <&fancontroller 50 50>;
 			};
 
 			fan_cdev_1 {
 				trip = <&fan_cpu19_config1>;
-				cooling-device = <&fancontroller 3 3>;
+				cooling-device = <&fancontroller 80 80>;
 			};
 		};
 	};
@@ -227,12 +238,12 @@
 		cooling-maps {
 			fan_cdev_0 {
 				trip = <&fan_cpu1a_config0>;
-				cooling-device = <&fancontroller 2 2>;
+				cooling-device = <&fancontroller 50 50>;
 			};
 
 			fan_cdev_1 {
 				trip = <&fan_cpu1a_config1>;
-				cooling-device = <&fancontroller 3 3>;
+				cooling-device = <&fancontroller 80 80>;
 			};
 		};
 	};
@@ -267,12 +278,12 @@
 		cooling-maps {
 			fan_cdev_0 {
 				trip = <&fan_gpuss0_config0>;
-				cooling-device = <&fancontroller 3 3>;
+				cooling-device = <&fancontroller 80 80>;
 			};
 
 			fan_cdev_1 {
 				trip = <&fan_gpuss0_config1>;
-				cooling-device = <&fancontroller 4 4>;
+				cooling-device = <&fancontroller 100 100>;
 			};
 		};
 	};
@@ -307,12 +318,12 @@
 		cooling-maps {
 			fan_cdev_0 {
 				trip = <&fan_gpuss1_config0>;
-				cooling-device = <&fancontroller 3 3>;
+				cooling-device = <&fancontroller 80 80>;
 			};
 
 			fan_cdev_1 {
 				trip = <&fan_gpuss1_config1>;
-				cooling-device = <&fancontroller 4 4>;
+				cooling-device = <&fancontroller 100 100>;
 			};
 		};
 	};
@@ -335,12 +346,12 @@
 		cooling-maps {
 			fan_cdev_0 {
 				trip = <&fan_thmbat0_config0>;
-				cooling-device = <&fancontroller 3 3>;
+				cooling-device = <&fancontroller 80 80>;
 			};
 
 			fan_cdev_1 {
 				trip = <&fan_thmbat1_config1>;
-				cooling-device = <&fancontroller 4 4>;
+				cooling-device = <&fancontroller 100 100>;
 			};
 		};
 	};
diff --git a/qcom/kalama-thermal-modem.dtsi b/qcom/kalama-thermal-modem.dtsi
index 7582e87d..f1eef0b6 100755
--- a/qcom/kalama-thermal-modem.dtsi
+++ b/qcom/kalama-thermal-modem.dtsi
@@ -57,7 +57,6 @@
 				#cooling-cells = <2>;
 			};
 
-
 			pa_lte_sdr1_dsc: pa_lte_sdr1_dsc {
 				qcom,qmi-dev-name = "pa_lte_sdr1_dsc";
 				#cooling-cells = <2>;
@@ -122,6 +121,41 @@
 				qcom,qmi-dev-name = "cpuv_restriction_cold";
 				#cooling-cells = <2>;
 			};
+
+			modem_lte_sub1_dsc: modem_lte_sub1_dsc {
+				qcom,qmi-dev-name = "modem_lte_sub1_dsc";
+				#cooling-cells = <2>;
+			};
+
+			modem_nr_sub1_dsc: modem_nr_sub1_dsc {
+				qcom,qmi-dev-name = "modem_nr_sub1_dsc";
+				#cooling-cells = <2>;
+			};
+
+			modem_nr_scg_sub1_dsc: modem_nr_scg_sub1_dsc {
+				qcom,qmi-dev-name = "modem_nr_scg_sub1_dsc";
+				#cooling-cells = <2>;
+			};
+
+			pa_lte_sdr0_sub1_dsc: pa_lte_sdr0_sub1_dsc {
+				qcom,qmi-dev-name = "pa_lte_sdr0_sub1_dsc";
+				#cooling-cells = <2>;
+			};
+
+			pa_lte_sdr1_sub1_dsc: pa_lte_sdr1_sub1_dsc {
+				qcom,qmi-dev-name = "pa_lte_sdr1_sub1_dsc";
+				#cooling-cells = <2>;
+			};
+
+			pa_nr_sdr0_sub1_dsc: pa_nr_sdr0_sub1_dsc {
+				qcom,qmi-dev-name = "pa_nr_sdr0_sub1_dsc";
+				#cooling-cells = <2>;
+			};
+
+			pa_nr_sdr1_sub1_dsc: pa_nr_sdr1_sub1_dsc {
+				qcom,qmi-dev-name = "pa_nr_sdr1_sub1_dsc";
+				#cooling-cells = <2>;
+			};
 		};
 	};
 
diff --git a/qcom/kalama-vm-dma-heaps.dtsi b/qcom/kalama-vm-dma-heaps.dtsi
index 7ffd57ec..1155678e 100755
--- a/qcom/kalama-vm-dma-heaps.dtsi
+++ b/qcom/kalama-vm-dma-heaps.dtsi
@@ -7,7 +7,6 @@
 		qcom,tui {
 			qcom,dma-heap-name = "qcom,tui";
 			qcom,dma-heap-type = <HEAP_TYPE_TUI_CARVEOUT>;
-			qcom,dynamic-heap;
 		};
 	};
 };
diff --git a/qcom/kalama-vm-qrd.dtsi b/qcom/kalama-vm-qrd.dtsi
index 5cc3e41b..8ec9b182 100755
--- a/qcom/kalama-vm-qrd.dtsi
+++ b/qcom/kalama-vm-qrd.dtsi
@@ -21,8 +21,8 @@
 		qts,touch-environment = "tvm";
 		qts,trusted-touch-type = "primary";
 		qts,trusted-touch-spi-irq = <569>;
-		qts,trusted-touch-io-bases = <0xa90000>;
-		qts,trusted-touch-io-sizes = <0x1000>;
+		qts,trusted-touch-io-bases = <0xa90000 0xac0000>;
+		qts,trusted-touch-io-sizes = <0x1000 0x1000>;
 		qts,trusted-touch-vm-gpio-list = <&tlmm 44 0 &tlmm 45 0 &tlmm 46 0
 						&tlmm 47 0 &tlmm 24 0 &tlmm 25 0x2008>;
 	};
diff --git a/qcom/kalama-vm.dtsi b/qcom/kalama-vm.dtsi
index 993c89e7..c3abaa1b 100755
--- a/qcom/kalama-vm.dtsi
+++ b/qcom/kalama-vm.dtsi
@@ -648,6 +648,11 @@
 		msgq-label = <3>;
 	};
 
+	qrtr-genpool {
+		compatible = "qcom,qrtr-genpool";
+		gen-pool = <&fastrpc_compute_cb1>;
+	};
+
 	qcom_smcinvoke {
 		compatible = "qcom,smcinvoke";
 	};
diff --git a/qcom/kalama.dtsi b/qcom/kalama.dtsi
index d592845b..7b7c182f 100755
--- a/qcom/kalama.dtsi
+++ b/qcom/kalama.dtsi
@@ -661,6 +661,22 @@
 		mem-type = <2>;
 	};
 
+	audio_cma_mem: audio_cma_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x1C00000>;
+	};
+
+	sdsp_mem: sdsp_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x800000>;
+	};
+
 	/* global autoconfigured region for contiguous allocations */
 	system_cma: linux,cma {
 		compatible = "shared-dma-pool";
@@ -3621,7 +3637,7 @@
 	thermal_zones: thermal-zones {
 	};
 
-	qcom,qbt_handler {
+	qcom_qbt: qcom,qbt_handler {
 		compatible = "qcom,qbt-handler";
 		qcom,ipc-gpio = <&tlmm 40 0>;
 		qcom,finger-detect-gpio = <&tlmm 41 0>;
diff --git a/qcom/kalamap-hdk-overlay.dts b/qcom/kalamap-hdk-overlay.dts
index 09cdcb8e..fb6319e7 100755
--- a/qcom/kalamap-hdk-overlay.dts
+++ b/qcom/kalamap-hdk-overlay.dts
@@ -6,6 +6,6 @@
 / {
 	model = "Qualcomm Technologies, Inc. KalamaP HDK";
 	compatible = "qcom,kalamap-hdk", "qcom,kalamap", "qcom,hdk";
-	qcom,msm-id = <536 0x10000>, <536 0x20000>, <601 0x20000>;
+	qcom,msm-id = <536 0x10000>, <536 0x20000>, <601 0x20000>, <603 0x20000>;
 	qcom,board-id = <0x1001f 0>;
 };
diff --git a/qcom/kalamap-qcs.dts b/qcom/kalamap-qcs.dts
new file mode 100755
index 00000000..902a9a23
--- /dev/null
+++ b/qcom/kalamap-qcs.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kalamap-qcs.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. KalamaP QCS SoC";
+	compatible = "qcom,kalamap";
+	qcom,board-id = <0 0>;
+};
+
diff --git a/qcom/kalamap-qcs.dtsi b/qcom/kalamap-qcs.dtsi
new file mode 100755
index 00000000..3519daec
--- /dev/null
+++ b/qcom/kalamap-qcs.dtsi
@@ -0,0 +1,7 @@
+#include "kalamap-v2.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. KalamaP QCS";
+	compatible = "qcom,kalamap";
+	qcom,msm-id = <603 0x20000>;
+};
diff --git a/qcom/khaje-atp.dtsi b/qcom/khaje-atp.dtsi
index 8f0eb87b..a6974fa2 100755
--- a/qcom/khaje-atp.dtsi
+++ b/qcom/khaje-atp.dtsi
@@ -1,6 +1,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/iio/qcom,spmi-vadc.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/clock/qcom,gcc-khaje.h>
 #include "khaje-pm7250b.dtsi"
 
 &pm6125_gpios {
@@ -94,6 +95,7 @@
 	qcom,vddp-ref-clk-max-microamp = <100>;
 
 	reset-gpios = <&tlmm 113 GPIO_ACTIVE_LOW>;
+	resets = <&gcc GCC_UFS_PHY_BCR>;
 	reset-names = "rst";
 	status = "ok";
 };
diff --git a/qcom/khaje-idp.dtsi b/qcom/khaje-idp.dtsi
index 213382a9..89ccd1e3 100755
--- a/qcom/khaje-idp.dtsi
+++ b/qcom/khaje-idp.dtsi
@@ -1,6 +1,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/iio/qcom,spmi-vadc.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/clock/qcom,gcc-khaje.h>
 #include "bengal-thermal-overlay.dtsi"
 
 &qupv3_se4_2uart {
@@ -221,6 +222,7 @@
 	qcom,vddp-ref-clk-max-microamp = <100>;
 
 	reset-gpios = <&tlmm 113 GPIO_ACTIVE_LOW>;
+	resets = <&gcc GCC_UFS_PHY_BCR>;
 	reset-names = "rst";
 
 	status = "ok";
diff --git a/qcom/khaje-qrd.dtsi b/qcom/khaje-qrd.dtsi
index c628fabd..fd9b11d6 100755
--- a/qcom/khaje-qrd.dtsi
+++ b/qcom/khaje-qrd.dtsi
@@ -1,6 +1,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/iio/qcom,spmi-vadc.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/clock/qcom,gcc-khaje.h>
 #include "bengal-thermal-overlay.dtsi"
 
 &pm6125_gpios {
@@ -170,6 +171,7 @@
 	qcom,vddp-ref-clk-max-microamp = <100>;
 
 	reset-gpios = <&tlmm 113 GPIO_ACTIVE_LOW>;
+	resets = <&gcc GCC_UFS_PHY_BCR>;
 	reset-names = "rst";
 
 	status = "ok";
diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi
index b361d4e4..198dede6 100755
--- a/qcom/khaje.dtsi
+++ b/qcom/khaje.dtsi
@@ -587,7 +587,7 @@
 	};
 
 	chosen {
-		bootargs = "lpm_levels.sleep_disabled=1 console=ttyMSM0,115200n8 msm_rtb.filter=0x237 service_locator.enable=1 swiotlb=2048 loop.max_part=7 cpufreq.default_governor=performance rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off export_pmu_events movable_node ftrace_dump_on_oops ssbd=force-off";
+		bootargs = "lpm_levels.sleep_disabled=1 console=ttyMSM0,115200n8 msm_rtb.filter=0x237 service_locator.enable=1 swiotlb=2048 loop.max_part=7 cpufreq.default_governor=performance rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off export_pmu_events movable_node ftrace_dump_on_oops ssbd=force-off disable_dma32=on cgroup.memory=nokmem,nosocket";
 	};
 
 	soc: soc { };
@@ -3993,6 +3993,14 @@ tpdm_turing_llm: tpdm@8861000 {
 #include "khaje-pinctrl.dtsi"
 #include "bengal-qupv3.dtsi"
 
+/*
+ * Each QUP device that's a parent to PMIC must be listed as a critical device
+ * to GCC.
+ */
+&gcc {
+	qcom,critical-devices = <&qupv3_se1_i2c>;
+};
+
 &qupv3_se1_i2c {
 	status = "ok";
 	qcom,leica-used-i2c;
diff --git a/qcom/khajeg.dtsi b/qcom/khajeg.dtsi
index bbaad82c..1ad1d79f 100755
--- a/qcom/khajeg.dtsi
+++ b/qcom/khajeg.dtsi
@@ -6,7 +6,59 @@
 	model = "Qualcomm Technologies, Inc. Khajeg SoC";
 	compatible = "qcom,khajeg";
 	qcom,msm-id = <585 0x10000>;
+
+reserved_memory: reserved-memory {
+	/delete-node/ modem_region@4ab00000;
+	/delete-node/ wlan_msa_region@51900000;
+	/delete-node/ cdsp_regions@51a00000;
+	/delete-node/ pil_adsp_region@53800000;
+	/delete-node/ ipa_fw_region@55600000;
+	/delete-node/ ipa_gsi_region@55610000;
+	/delete-node/ gpu_region@55615000;
+	/delete-node/ video_region@55617000;
+
+	pil_modem_mem: modem_region@4ab00000 {
+		no-map;
+		reg = <0x0 0x4ab00000 0x0 0x2c00000>;
+	};
+
+	pil_cdsp_mem: cdsp_regions@4d700000 {
+		no-map;
+		reg = <0x0 0x4d700000 0x0 0x1e00000>;
+	};
+
+	pil_adsp_mem: pil_adsp_region@4f500000 {
+		no-map;
+		reg = <0x0 0x4f500000 0x0 0x1e00000>;
+	};
+
+	pil_ipa_fw_mem: ipa_fw_region@51300000 {
+		no-map;
+		reg = <0x0 0x51300000 0x0 0x10000>;
+	};
+
+	pil_ipa_gsi_mem: ipa_gsi_region@51310000 {
+		no-map;
+		reg = <0x0 0x51310000 0x0 0x5000>;
+	};
+
+	pil_gpu_mem: gpu_region@51315000 {
+		no-map;
+		reg = <0x0 0x51315000 0x0 0x2000>;
+	};
+
+	wlan_msa_mem: wlan_msa_region@51900000 {
+		no-map;
+		reg = <0x0 0x51900000 0x0 0x100000>;
+	};
+
+	video_mem: video_region@51a00000 {
+		no-map;
+		reg = <0x0 0x51a00000 0x0 0x700000>;
+	};
 };
+};
+
 &soc {
 	qcom,msm_gsi {
 		status = "disabled";
diff --git a/qcom/kona-7230-iot-cpu.dtsi b/qcom/kona-7230-iot-cpu.dtsi
new file mode 100755
index 00000000..870694df
--- /dev/null
+++ b/qcom/kona-7230-iot-cpu.dtsi
@@ -0,0 +1,329 @@
+/ {
+	/delete-node/ cpus;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_0>;
+			qcom,freq-domain = <&cpufreq_hw 0 4>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			#cooling-cells = <2>;
+			L2_0: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+
+				L3_0: l3-cache {
+				      compatible = "arm,arch-cache";
+				      cache-level = <3>;
+				};
+			};
+
+			L1_I_0: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L1_D_0: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU1: cpu@100 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_1>;
+			qcom,freq-domain = <&cpufreq_hw 0 4>;
+			capacity-dmips-mhz = <1024>;
+			dynamic-power-coefficient = <100>;
+			L2_1: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+
+			L1_I_100: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L1_D_100: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU2: cpu@400 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x400>;
+			enable-method = "psci";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_4>;
+			qcom,freq-domain = <&cpufreq_hw 1 4>;
+			capacity-dmips-mhz = <1894>;
+			dynamic-power-coefficient = <514>;
+			#cooling-cells = <2>;
+			L2_4: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+
+			L1_I_400: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L1_D_400: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU3: cpu@500 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x500>;
+			enable-method = "psci";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_5>;
+			qcom,freq-domain = <&cpufreq_hw 1 4>;
+			capacity-dmips-mhz = <1894>;
+			dynamic-power-coefficient = <514>;
+			L2_5: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+
+			L1_I_500: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L1_D_500: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU4: cpu@600 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x600>;
+			enable-method = "psci";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_6>;
+			qcom,freq-domain = <&cpufreq_hw 1 4>;
+			capacity-dmips-mhz = <1894>;
+			dynamic-power-coefficient = <514>;
+			L2_6: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+
+			L1_I_600: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L1_D_600: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		CPU5: cpu@700 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x700>;
+			enable-method = "psci";
+			cpu-release-addr = <0x0 0x90000000>;
+			next-level-cache = <&L2_7>;
+			qcom,freq-domain = <&cpufreq_hw 2 4>;
+			capacity-dmips-mhz = <1894>;
+			dynamic-power-coefficient = <598>;
+			#cooling-cells = <2>;
+			L2_7: l2-cache {
+			      compatible = "arm,arch-cache";
+			      cache-level = <2>;
+			      next-level-cache = <&L3_0>;
+			};
+
+			L1_I_700: l1-icache {
+				compatible = "arm,arch-cache";
+			};
+
+			L1_D_700: l1-dcache {
+				compatible = "arm,arch-cache";
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&CPU2>;
+				};
+
+				core1 {
+					cpu = <&CPU3>;
+				};
+
+				core2 {
+					cpu = <&CPU4>;
+				};
+			};
+
+			cluster2 {
+				core0 {
+					cpu = <&CPU5>;
+				};
+			};
+		};
+	};
+
+};
+
+&soc {
+	/delete-node/ dsu_pmu@0;
+	/delete-node/ jtagmm@7240000;
+	/delete-node/ jtagmm@7340000;
+	/delete-node/ cti@7220000;
+	/delete-node/ cti@7320000;
+	/delete-node/ etm@7240000;
+	/delete-node/ etm@7340000;
+
+	dsu_pmu@0 {
+		compatible = "arm,dsu-pmu";
+		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+		cpus = <&CPU0>, <&CPU1>,
+			<&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
+	};
+
+	qcom,lpm-levels {
+		qcom,pm-cluster@0 {
+			qcom,pm-cpu@0 {
+				/delete-property/  qcom,cpu;
+				qcom,cpu = <&CPU0 &CPU1>;
+			};
+
+			qcom,pm-cpu@1 {
+				/delete-property/  qcom,cpu;
+				qcom,cpu = <&CPU2 &CPU3 &CPU4 &CPU5>;
+
+			};
+		};
+	};
+
+};
+
+&cpufreq_hw {
+	/delete-node/ qcom,cpu-isolation;
+	qcom,cpu-isolation {
+		compatible = "qcom,cpu-isolate";
+		cpu0_isolate: cpu0-isolate {
+			qcom,cpu = <&CPU0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu1_isolate: cpu1-isolate {
+			qcom,cpu = <&CPU1>;
+			#cooling-cells = <2>;
+		};
+
+		cpu4_isolate: cpu4-isolate {
+			qcom,cpu = <&CPU2>;
+			#cooling-cells = <2>;
+		};
+
+		cpu5_isolate: cpu5-isolate {
+			qcom,cpu = <&CPU3>;
+			#cooling-cells = <2>;
+		};
+
+		cpu6_isolate: cpu6-isolate {
+			qcom,cpu = <&CPU4>;
+			#cooling-cells = <2>;
+		};
+
+		cpu7_isolate: cpu7-isolate {
+			qcom,cpu = <&CPU5>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	/delete-node/ cpu7-notify;
+	cpu7_notify: cpu7-notify {
+		qcom,cooling-cpu = <&CPU5>;
+		#cooling-cells = <2>;
+	};
+};
+
+&qcom_memlat {
+	ddr {
+		silver {
+			/delete-property/  qcom,cpulist;
+			qcom,cpulist = <&CPU0 &CPU1>;
+		};
+
+		gold {
+			/delete-property/  qcom,cpulist;
+			qcom,cpulist = <&CPU2 &CPU3 &CPU4>;
+		};
+
+		gold-compute {
+			/delete-property/  qcom,cpulist;
+			qcom,cpulist = <&CPU2 &CPU3 &CPU4>;
+		};
+	};
+
+	llcc {
+		silver {
+			/delete-property/  qcom,cpulist;
+			qcom,cpulist = <&CPU0 &CPU1>;
+		};
+
+		gold {
+			/delete-property/  qcom,cpulist;
+			qcom,cpulist = <&CPU2 &CPU3 &CPU4>;
+		};
+	};
+
+	l3 {
+		silver {
+			/delete-property/  qcom,cpulist;
+			qcom,cpulist = <&CPU0 &CPU1>;
+		};
+
+		gold {
+			/delete-property/  qcom,cpulist;
+			qcom,cpulist = <&CPU2 &CPU3 &CPU4>;
+		};
+
+		prime {
+			/delete-property/  qcom,cpulist;
+			qcom,cpulist = <&CPU5>;
+		};
+	};
+
+	ddrqos {
+		ddrqos_gold_lat: gold {
+			/delete-property/  qcom,cpulist;
+			qcom,cpulist = <&CPU2 &CPU3 &CPU4>;
+		};
+	};
+};
diff --git a/qcom/kona-7230-iot-v2.1.dts b/qcom/kona-7230-iot-v2.1.dts
new file mode 100755
index 00000000..321e2313
--- /dev/null
+++ b/qcom/kona-7230-iot-v2.1.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "kona-7230-iot-v2.1.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. kona-7230-iot v2.1 SoC";
+	compatible = "qcom,kona-iot";
+	qcom,board-id = <0 0>;
+};
diff --git a/qcom/kona-7230-iot-v2.1.dtsi b/qcom/kona-7230-iot-v2.1.dtsi
new file mode 100755
index 00000000..8f7fc605
--- /dev/null
+++ b/qcom/kona-7230-iot-v2.1.dtsi
@@ -0,0 +1,8 @@
+#include "kona-iot-v2.1.dtsi"
+#include "kona-7230-iot-cpu.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Kona-7230-iot v2.1";
+	compatible = "qcom,kona-iot";
+	qcom,msm-id = <548 0x20001>;
+};
diff --git a/qcom/kona-dma-heaps.dtsi b/qcom/kona-dma-heaps.dtsi
new file mode 100755
index 00000000..ae79493d
--- /dev/null
+++ b/qcom/kona-dma-heaps.dtsi
@@ -0,0 +1,51 @@
+#include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h>
+
+&soc {
+	qcom,dma-heaps {
+		compatible = "qcom,dma-heaps";
+
+		qcom,adsp {
+			qcom,dma-heap-name = "qcom,adsp";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&sdsp_mem>;
+		};
+
+		qcom,secure_cdsp {
+			qcom,dma-heap-name = "qcom,secure-cdsp";
+			qcom,dma-heap-type = <HEAP_TYPE_SECURE_CARVEOUT>;
+			memory-region = <&cdsp_secure_heap>;
+			qcom,token = <0x20000000>;
+		};
+
+		qcom,sp_hlos {
+			qcom,dma-heap-name = "qcom,sp-hlos";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&sp_mem>;
+		};
+
+		qcom,user_contig {
+			qcom,dma-heap-name = "qcom,user-contig";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&user_contig_mem>;
+		};
+
+		qcom,qseecom {
+			qcom,dma-heap-name = "qcom,qseecom";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&qseecom_mem>;
+		};
+
+		qcom,qseecom_ta {
+			qcom,dma-heap-name = "qcom,qseecom-ta";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			memory-region = <&qseecom_ta_mem>;
+		};
+
+		qcom,display {
+			qcom,dma-heap-name = "qcom,display";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+			qcom,max-align = <9>;
+			memory-region = <&secure_display_memory>;
+		};
+	};
+};
diff --git a/qcom/kona-iot-v2.1-rb5-overlay.dts b/qcom/kona-iot-v2.1-rb5-overlay.dts
new file mode 100755
index 00000000..4d654379
--- /dev/null
+++ b/qcom/kona-iot-v2.1-rb5-overlay.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+/plugin/;
+
+#include "kona-iot-v2.1-rb5.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. kona-iot RB5";
+	compatible = "qcom,kona-iot-qrd", "qcom,kona-iot", "qcom,kona-qrd";
+	qcom,board-id = <0x301000b 0x0>;
+};
diff --git a/qcom/kona-iot-v2.1-rb5.dtsi b/qcom/kona-iot-v2.1-rb5.dtsi
new file mode 100755
index 00000000..d90c7e44
--- /dev/null
+++ b/qcom/kona-iot-v2.1-rb5.dtsi
@@ -0,0 +1,16 @@
+#include <dt-bindings/gpio/gpio.h>
+
+&tlmm {
+	key_factory_reset {
+		key_factory_reset_default: key_factory_reset_default {
+			pins = "gpio22";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+		};
+	};
+};
+
+&qupv3_se12_2uart {
+		status = "ok";
+};
diff --git a/qcom/kona-iot-vc.dtsi b/qcom/kona-iot-vc.dtsi
index fa9050d0..21036bd0 100755
--- a/qcom/kona-iot-vc.dtsi
+++ b/qcom/kona-iot-vc.dtsi
@@ -1,4 +1,13 @@
 #include <dt-bindings/gpio/gpio.h>
+#include "kona-pmic-overlay.dtsi"
+
+&vendor {
+	kona_qrd_batterydata: qcom,battery-data {
+		qcom,batt-id-range-pct = <15>;
+		#include "fg-gen4-batterydata-mlp466274-3650mah.dtsi"
+		#include "fg-gen4-batterydata-atl466274-3650mah.dtsi"
+	};
+};
 
 &tlmm {
 	key_factory_reset {
@@ -10,3 +19,634 @@
 		};
 	};
 };
+
+&qupv3_se12_2uart {
+		status = "ok";
+};
+
+&ufsphy_mem {
+		compatible = "qcom,ufs-phy-qmp-v4";
+		vdda-phy-supply = <&pm8150_l5>;
+		vdda-pll-supply = <&pm8150_l9>;
+		vdda-phy-max-microamp = <89900>;
+		vdda-pll-max-microamp = <18800>;
+		status = "ok";
+};
+
+&ufshc_mem {
+		vdd-hba-supply = <&ufs_phy_gdsc>;
+		vcc-supply = <&pm8150_l17>;
+		vccq-supply = <&pm8150_l6>;
+		vccq2-supply = <&pm8150_s4>;
+		vcc-max-microamp = <800000>;
+		vccq-max-microamp = <800000>;
+		vccq2-max-microamp = <800000>;
+
+		qcom,vddp-ref-clk-supply = <&pm8150_l6>;
+		qcom,vddp-ref-clk-max-microamp = <100>;
+		qcom,vccq-parent-supply = <&pm8150a_s8>;
+		qcom,vccq-parent-max-microamp = <210000>;
+		status = "ok";
+};
+
+&vreg_hap_boost {
+	status = "ok";
+};
+
+&pm8150b_pdphy {
+	#io-channel-cells = <1>;
+	io-channels = <&pm8150b_charger PSY_IIO_PD_ACTIVE>,
+		      <&pm8150b_charger PSY_IIO_TYPEC_CC_ORIENTATION>,
+		      <&pm8150b_charger PSY_IIO_CONNECTOR_TYPE>,
+		      <&pm8150b_charger PSY_IIO_TYPEC_POWER_ROLE>,
+		      <&pm8150b_charger PSY_IIO_PD_USB_SUSPEND_SUPPORTED>,
+		      <&pm8150b_charger PSY_IIO_TYPEC_SRC_RP>,
+		      <&pm8150b_charger PSY_IIO_PD_IN_HARD_RESET>,
+		      <&pm8150b_charger PSY_IIO_PD_CURRENT_MAX>,
+		      <&pm8150b_charger PSY_IIO_PR_SWAP>,
+		      <&pm8150b_charger PSY_IIO_PD_VOLTAGE_MIN>,
+		      <&pm8150b_charger PSY_IIO_PD_VOLTAGE_MAX>,
+		      <&pm8150b_charger PSY_IIO_USB_REAL_TYPE>,
+		      <&pm8150b_charger PSY_IIO_TYPEC_MODE>,
+		      <&pm8150b_charger PSY_IIO_PE_START>;
+	io-channel-names = "pd_active",
+			   "typec_cc_orientation",
+			   "connector_type",
+			   "typec_power_role",
+			   "pd_usb_suspend_supported",
+			   "typec_src_rp",
+			   "pd_in_hard_reset",
+			   "pr_current_max",
+			   "pr_swap",
+			   "pd_voltage_min",
+			   "pd_voltage_max",
+			   "real_type",
+			   "typec_mode",
+			   "pe_start";
+};
+
+&pm8150b_haptics {
+	qcom,vmax-mv = <1697>;
+	qcom,play-rate-us = <5882>;
+	vdd-supply = <&vreg_hap_boost>;
+
+	wf_0 {
+		/* CLICK */
+		qcom,wf-play-rate-us = <5882>;
+		qcom,wf-vmax-mv = <1697>;
+	};
+
+	wf_1 {
+		/* DOUBLE CLICK */
+		qcom,wf-play-rate-us = <5882>;
+		qcom,wf-vmax-mv = <1697>;
+	};
+
+	wf_2 {
+		/* TICK */
+		qcom,wf-play-rate-us = <5882>;
+		qcom,wf-vmax-mv = <1697>;
+	};
+
+	wf_3 {
+		/* THUD */
+		qcom,wf-play-rate-us = <5882>;
+		qcom,wf-vmax-mv = <1697>;
+	};
+
+	wf_4 {
+		/* POP */
+		qcom,wf-play-rate-us = <5882>;
+		qcom,wf-vmax-mv = <1697>;
+	};
+
+	wf_5 {
+		/* HEAVY CLICK */
+		qcom,wf-play-rate-us = <5882>;
+		qcom,wf-vmax-mv = <1697>;
+	};
+};
+
+&pm8150b_charger {
+	status = "ok";
+	qcom,sec-charger-config = <1>;
+	qcom,auto-recharge-soc = <98>;
+	io-channels = <&pm8150b_vadc ADC5_USB_IN_V_16>,
+		      <&pm8150b_vadc ADC5_USB_IN_I>,
+		      <&pm8150b_vadc ADC5_SBUx>,
+		      <&pm8150b_vadc ADC5_VPH_PWR>,
+		      <&pm8150b_vadc ADC5_DIE_TEMP>,
+		      <&pm8150b_vadc ADC5_MID_CHG_DIV6>,
+		      <&pm8150b_vadc ADC5_CHG_TEMP>;
+	io-channel-names = "usb_in_voltage",
+			   "usb_in_current",
+			   "sbux_res",
+			   "vph_voltage",
+			   "die_temp",
+			   "mid_voltage",
+			   "chg_temp";
+	qcom,battery-data = <&kona_qrd_batterydata>;
+	qcom,sw-jeita-enable;
+	qcom,wd-bark-time-secs = <16>;
+	qcom,suspend-input-on-debug-batt;
+	qcom,fcc-stepping-enable;
+	qcom,smb-internal-pull-kohm = <0>;
+	qcom,thermal-mitigation = <5325000 4500000 4000000 3500000 3000000
+				2500000 2000000 1500000 1000000 500000>;
+};
+
+&pm8150b_fg {
+	status = "ok";
+	qcom,battery-data = <&kona_qrd_batterydata>;
+	qcom,hold-soc-while-full;
+	qcom,linearize-soc;
+	qcom,five-pin-battery;
+	qcom,cl-wt-enable;
+	qcom,soc-scale-mode-en;
+	/* ESR fast calibration */
+	qcom,fg-esr-timer-chg-fast = <0 7>;
+	qcom,fg-esr-timer-dischg-fast = <0 7>;
+	qcom,fg-esr-timer-chg-slow = <0 96>;
+	qcom,fg-esr-timer-dischg-slow = <0 96>;
+	qcom,fg-esr-cal-soc-thresh = <26 230>;
+	qcom,fg-esr-cal-temp-thresh = <10 40>;
+};
+
+&pm8150l_vadc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	vph_pwr@83 {
+		reg = <ADC5_VPH_PWR>;
+		label = "vph_pwr";
+		qcom,pre-scaling = <1 3>;
+	};
+
+	camera_flash_therm@4d {
+		reg = <ADC5_AMUX_THM1_100K_PU>;
+		label = "camera_flash_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	skin_msm_therm@4e {
+		reg = <ADC5_AMUX_THM2_100K_PU>;
+		label = "skin_msm_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pa_therm2@4f {
+		reg = <ADC5_AMUX_THM3_100K_PU>;
+		label = "pa_therm2";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+};
+
+&pm8150b_vadc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	conn_therm@4f {
+		reg = <ADC5_AMUX_THM3_100K_PU>;
+		label = "conn_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	mid_chg_div6@1e {
+		reg = <ADC5_MID_CHG_DIV6>;
+		label = "chg_mid";
+		qcom,pre-scaling = <1 6>;
+	};
+};
+
+&pm8150_vadc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	vph_pwr@83 {
+		reg = <ADC5_VPH_PWR>;
+		label = "vph_pwr";
+		qcom,pre-scaling = <1 3>;
+	};
+
+	vcoin@85 {
+		reg = <ADC5_VCOIN>;
+		label = "vcoin";
+		qcom,pre-scaling = <1 3>;
+	};
+
+	xo_therm@4c {
+		reg = <ADC5_XO_THERM_100K_PU>;
+		label = "xo_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	skin_therm@4d {
+		reg = <ADC5_AMUX_THM1_100K_PU>;
+		label = "skin_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pa_therm1@4e {
+		reg = <ADC5_AMUX_THM2_100K_PU>;
+		label = "pa_therm1";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+};
+
+&pm8150b_adc_tm {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	io-channels = <&pm8150b_vadc ADC5_AMUX_THM3_100K_PU>;
+
+	conn_therm@4f {
+		reg = <ADC5_AMUX_THM3_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+};
+
+&pm8150_adc_tm {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	io-channels = <&pm8150_vadc ADC5_XO_THERM_100K_PU>,
+			<&pm8150_vadc ADC5_AMUX_THM1_100K_PU>,
+			<&pm8150_vadc ADC5_AMUX_THM2_100K_PU>;
+
+	xo_therm@4c {
+		reg = <ADC5_XO_THERM_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	skin_therm@4d {
+		reg = <ADC5_AMUX_THM1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	pa_therm1@4e {
+		reg = <ADC5_AMUX_THM2_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+};
+
+&pm8150l_adc_tm {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	camera_flash_therm@4d {
+		reg = <ADC5_AMUX_THM1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	skin_msm_therm@4e {
+		reg = <ADC5_AMUX_THM2_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+
+	pa_therm2@4f {
+		reg = <ADC5_AMUX_THM3_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+	};
+};
+
+&thermal_zones {
+	status = "ok";
+	conn-therm-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm8150b_adc_tm ADC5_AMUX_THM3_100K_PU>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	xo-therm-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm8150_adc_tm ADC5_XO_THERM_100K_PU>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	skin-therm-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm8150_adc_tm ADC5_AMUX_THM1_100K_PU>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	mmw-pa1-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm8150_adc_tm ADC5_AMUX_THM2_100K_PU>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	camera-therm-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm8150l_adc_tm ADC5_AMUX_THM1_100K_PU>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	skin-msm-therm-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm8150l_adc_tm ADC5_AMUX_THM2_100K_PU>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	mmw-pa2-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pm8150l_adc_tm ADC5_AMUX_THM3_100K_PU>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	skin-msm-therm-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8150l_adc_tm ADC5_AMUX_THM2_100K_PU>;
+		wake-capable-sensor;
+		trips {
+			skin_trip: skin-config0 {
+				temperature = <46000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+		};
+
+	};
+
+	xo-therm-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8150_adc_tm ADC5_XO_THERM_100K_PU>;
+
+		trips {
+			xo_lvl0: active-config0 {
+				temperature = <42000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+
+			xo_lvl1: active-config1 {
+				temperature = <46000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+
+			xo_lvl2: active-config2 {
+				temperature = <56000>;
+				hysteresis = <6000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			xo_skin_lvl0 {
+				trip = <&xo_lvl0>;
+				cooling-device = <&modem_mmw_skin2 1 1>;
+			};
+
+			xo_skin_lvl1 {
+				trip = <&xo_lvl1>;
+				cooling-device = <&modem_mmw_skin2 2 2>;
+			};
+
+			xo_skin_lvl2 {
+				trip = <&xo_lvl2>;
+				cooling-device = <&modem_mmw_skin2 3 3>;
+			};
+		};
+	};
+
+	mmw-pa1-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8150_adc_tm ADC5_AMUX_THM2_100K_PU>;
+
+		trips {
+			pa1_lvl0: active-config0 {
+				temperature = <44000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			pa1_lvl1: active-config1 {
+				temperature = <48000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+
+			pa1_lvl2: active-config2 {
+				temperature = <56000>;
+				hysteresis = <6000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			pa1_skin_lvl0 {
+				trip = <&pa1_lvl0>;
+				cooling-device = <&modem_mmw_skin0 1 1>;
+			};
+
+			pa1_skin_lvl1 {
+				trip = <&pa1_lvl1>;
+				cooling-device = <&modem_mmw_skin0 2 2>;
+			};
+
+			pa1_skin_lvl2 {
+				trip = <&pa1_lvl2>;
+				cooling-device = <&modem_mmw_skin0 3 3>;
+			};
+		};
+	};
+
+	mmw-pa2-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8150l_adc_tm ADC5_AMUX_THM3_100K_PU>;
+
+		trips {
+			pa2_lvl0: active-config0 {
+				temperature = <42000>;
+				hysteresis = <4000>;
+				type = "passive";
+			};
+
+			pa2_lvl1: active-config1 {
+				temperature = <46000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+
+			pa2_lvl2: active-config2 {
+				temperature = <56000>;
+				hysteresis = <6000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			pa2_skin_lvl0 {
+				trip = <&pa2_lvl0>;
+				cooling-device = <&modem_mmw_skin1 1 1>;
+			};
+
+			pa2_skin_lvl1 {
+				trip = <&pa2_lvl1>;
+				cooling-device = <&modem_mmw_skin1 2 2>;
+			};
+
+			pa2_skin_lvl2 {
+				trip = <&pa2_lvl2>;
+				cooling-device = <&modem_mmw_skin1 3 3>;
+			};
+		};
+	};
+
+	skin-therm-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8150_adc_tm ADC5_AMUX_THM1_100K_PU>;
+		wake-capable-sensor;
+		disable-thermal-zone;
+
+		trips {
+			skin_therm0: active-config0 {
+				temperature = <62000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			skin_therm1: active-config1 {
+				temperature = <65000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			skin_therm2: active-config2 {
+				temperature = <72000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			skin_lvl0 {
+				trip = <&skin_therm0>;
+				cooling-device = <&modem_skin 1 1>;
+			};
+
+			skin_lvl1 {
+				trip = <&skin_therm1>;
+				cooling-device = <&modem_skin 2 2>;
+			};
+
+			skin_lvl2 {
+				trip = <&skin_therm2>;
+				cooling-device = <&modem_skin 3 3>;
+			};
+		};
+
+	};
+};
+
+&sdhc_2 {
+		vdd-supply = <&pm8150a_l9>;
+		qcom,vdd-voltage-level = <2950000 2960000>;
+		qcom,vdd-current-level = <200 800000>;
+
+		vdd-io-supply = <&pm8150a_l6>;
+		qcom,vdd-io-voltage-level = <1808000 2960000>;
+		qcom,vdd-io-current-level = <200 22000>;
+
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&sdc2_on>;
+		pinctrl-1 = <&sdc2_off>;
+
+		cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
+
+		status = "ok";
+};
diff --git a/qcom/kona-pcie.dtsi b/qcom/kona-pcie.dtsi
new file mode 100755
index 00000000..e2e5d57a
--- /dev/null
+++ b/qcom/kona-pcie.dtsi
@@ -0,0 +1,891 @@
+#include <dt-bindings/clock/qcom,gcc-sm8250.h>
+#include <dt-bindings/gpio/gpio.h>
+
+&soc {
+	pcie0: qcom,pcie@1c00000 {
+		compatible = "qcom,pci-msm";
+
+		reg = <0x01c00000 0x3000>,
+			<0x01c06000 0x1000>,
+			<0x60000000 0xf1d>,
+			<0x60000f20 0xa8>,
+			<0x60001000 0x1000>,
+			<0x60100000 0x100000>;
+		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
+
+		cell-index = <0>;
+		linux,pci-domain = <0>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
+			<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
+
+		interrupt-parent = <&pcie0>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+		msi-parent = <&pcie0_msi>;
+
+		perst-gpio = <&tlmm 79 GPIO_ACTIVE_HIGH>;
+		wake-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&pcie0_clkreq_default
+				&pcie0_perst_default
+				&pcie0_wake_default>;
+		pinctrl-1 = <&pcie0_clkreq_sleep
+				&pcie0_perst_default
+				&pcie0_wake_default>;
+
+		gdsc-core-vdd-supply = <&pcie_0_gdsc>;
+		vreg-1p2-supply = <&pm8150_l9>;
+		vreg-0p9-supply = <&pm8150_l5>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 16000>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 73500>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_NOM
+				100000000>;
+
+		interconnect-names = "icc_path";
+		interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
+
+		clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+			<&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_PCIE_0_AUX_CLK>,
+			<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_WIFI_CLKREF_EN>,
+			<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+			<&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
+			<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+			<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
+			<&pcie_0_pipe_clk>;
+		clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
+				"pcie_aux_clk", "pcie_cfg_ahb_clk",
+				"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
+				"pcie_ldo", "pcie_slv_q2a_axi_clk",
+				"pcie_tbu_clk", "pcie_phy_refgen_clk",
+				"pcie_ddrss_sf_tbu_clk","pcie_pipe_clk_mux",
+				"pcie_pipe_clk_ext_src";
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <100000000>, <0>, <0>;
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
+					<0>, <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_0_BCR>,
+			<&gcc GCC_PCIE_0_PHY_BCR>;
+		reset-names = "pcie_0_core_reset",
+				"pcie_0_phy_reset";
+
+		dma-coherent;
+		qcom,smmu-sid-base = <0x1c00>;
+		iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+			<0x100 &apps_smmu 0x1c01 0x1>;
+
+		qcom,boot-option = <0x1>;
+		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
+		qcom,drv-name = "lpass";
+		qcom,no-l0s-supported;
+		qcom,drv-l1ss-timeout-us = <10000>; /* 10ms */
+		qcom,l1-2-th-scale = <2>; /* 1us */
+		qcom,l1-2-th-value = <70>;
+		qcom,slv-addr-space-size = <0x4000000>;
+		qcom,ep-latency = <10>;
+		qcom,num-parf-testbus-sel = <0xb9>;
+
+		qcom,pcie-phy-ver = <1102>;
+		qcom,phy-status-offset = <0x814>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0x840>;
+		qcom,phy-sequence = <0x0840 0x03 0x0
+				0x0094 0x08 0x0
+				0x0154 0x34 0x0
+				0x016c 0x08 0x0
+				0x0058 0x0f 0x0
+				0x00a4 0x42 0x0
+				0x0110 0x24 0x0
+				0x011c 0x03 0x0
+				0x0118 0xb4 0x0
+				0x010c 0x02 0x0
+				0x01bc 0x11 0x0
+				0x00bc 0x82 0x0
+				0x00d4 0x03 0x0
+				0x00d0 0x55 0x0
+				0x00cc 0x55 0x0
+				0x00b0 0x1a 0x0
+				0x00ac 0x0a 0x0
+				0x00c4 0x68 0x0
+				0x00e0 0x02 0x0
+				0x00dc 0xaa 0x0
+				0x00d8 0xab 0x0
+				0x00b8 0x34 0x0
+				0x00b4 0x14 0x0
+				0x0158 0x01 0x0
+				0x0074 0x06 0x0
+				0x007c 0x16 0x0
+				0x0084 0x36 0x0
+				0x0078 0x06 0x0
+				0x0080 0x16 0x0
+				0x0088 0x36 0x0
+				0x01b0 0x1e 0x0
+				0x01ac 0xca 0x0
+				0x01b8 0x18 0x0
+				0x01b4 0xa2 0x0
+				0x0050 0x07 0x0
+				0x0010 0x01 0x0
+				0x001c 0x31 0x0
+				0x0020 0x01 0x0
+				0x0024 0xde 0x0
+				0x0028 0x07 0x0
+				0x0030 0x4c 0x0
+				0x0034 0x06 0x0
+				0x029c 0x12 0x0
+				0x0284 0x35 0x0
+				0x023c 0x11 0x0
+				0x051c 0x03 0x0
+				0x0518 0x1c 0x0
+				0x0524 0x1e 0x0
+				0x04e8 0x00 0x0
+				0x04ec 0x0e 0x0
+				0x04f0 0x4a 0x0
+				0x04f4 0x0f 0x0
+				0x05b4 0x04 0x0
+				0x0434 0x7f 0x0
+				0x0444 0x70 0x0
+				0x0510 0x17 0x0
+				0x04d4 0x04 0x0
+				0x04d8 0x07 0x0
+				0x0598 0xd4 0x0
+				0x059c 0x54 0x0
+				0x05a0 0xdb 0x0
+				0x05a4 0x3b 0x0
+				0x05a8 0x31 0x0
+				0x0584 0x24 0x0
+				0x0588 0xe4 0x0
+				0x058c 0xec 0x0
+				0x0590 0x3b 0x0
+				0x0594 0x36 0x0
+				0x0570 0x3f 0x0
+				0x0574 0x3f 0x0
+				0x0578 0xff 0x0
+				0x057c 0x7f 0x0
+				0x0580 0x14 0x0
+				0x04fc 0x00 0x0
+				0x04f8 0xc0 0x0
+				0x0460 0x30 0x0
+				0x0464 0x00 0x0
+				0x05bc 0x0c 0x0
+				0x04dc 0x1b 0x0
+				0x0408 0x0c 0x0
+				0x0414 0x03 0x0
+				0x05b8 0x30 0x0
+				0x09a4 0x01 0x0
+				0x0c90 0x00 0x0
+				0x0c40 0x01 0x0
+				0x0c48 0x01 0x0
+				0x0c50 0x00 0x0
+				0x0cb4 0x33 0x0
+				0x0cbc 0x00 0x0
+				0x0ce0 0x58 0x0
+				0x0ca4 0x0f 0x0
+				0x0048 0x90 0x0
+				0x0c1c 0xc1 0x0
+				0x0988 0x77 0x0
+				0x0998 0x0b 0x0
+				0x08dc 0x0d 0x0
+				0x09ec 0x12 0x0
+				0x0800 0x00 0x0
+				0x0844 0x03 0x0>;
+
+		qcom,parf-debug-reg = <0x01B0 0x0024 0x0028 0x0224 0x0500
+					0x04D0 0x04D4 0x03C0 0x0630 0x0230
+					0x0000>;
+		qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x01F4 0x0730
+					0x0734 0x0738 0x073C>;
+		qcom,phy-debug-reg = <0x0068 0x0140 0x0144 0x0148 0x014C
+					0x0150 0x0160 0x0178 0x02f0 0x06f0
+					0x02fC 0x06fC 0x05fc 0x09fc 0x1000
+					0x1400 0x1004 0x1404 0x1008 0x1408
+					0x100c 0x140C 0x1010 0x1410 0x1014
+					0x1414 0x1018 0x1418 0x1220 0x1620
+					0x0a14 0x0a18 0x0a1C 0x0a20 0x0a24
+					0x0a28 0x0a2C 0x0a30 0x0a34 0x0a38
+					0x0a3C 0x0e00 0x0e04>;
+
+		pcie0_rp: pcie0_rp {
+			reg = <0 0 0 0 0>;
+		};
+	};
+
+	pcie0_msi: qcom,pcie0_msi@17a10040 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0x17a10040 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
+	};
+
+	pcie1: qcom,pcie@1c08000 {
+		compatible = "qcom,pci-msm";
+
+		reg = <0x01c08000 0x3000>,
+			<0x01c0e000 0x2000>,
+			<0x40000000 0xf1d>,
+			<0x40000f20 0xa8>,
+			<0x40001000 0x1000>,
+			<0x40100000 0x100000>;
+		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
+
+		cell-index = <1>;
+		linux,pci-domain = <1>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
+			<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
+
+		interrupt-parent = <&pcie1>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
+		msi-parent = <&pcie1_msi>;
+
+		perst-gpio = <&tlmm 82 GPIO_ACTIVE_HIGH>;
+		wake-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie1_clkreq_default
+				&pcie1_perst_default
+				&pcie1_wake_default>;
+
+		gdsc-core-vdd-supply = <&pcie_1_gdsc>;
+		vreg-1p2-supply = <&pm8150_l9>;
+		vreg-0p9-supply = <&pm8150_l5>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 25000>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 98800>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_NOM
+				100000000>;
+
+		interconnect-names = "icc_path";
+		interconnects = <&aggre2_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
+
+		clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
+			<&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_PCIE_1_AUX_CLK>,
+			<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
+			<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+			<&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
+			<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+			<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
+			<&pcie_1_pipe_clk>;
+		clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
+				"pcie_aux_clk", "pcie_cfg_ahb_clk",
+				"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
+				"pcie_ldo", "pcie_slv_q2a_axi_clk",
+				"pcie_tbu_clk", "pcie_phy_refgen_clk",
+				"pcie_ddrss_sf_tbu_clk", "pcie_pipe_clk_mux",
+				"pcie_pipe_clk_ext_src";
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <100000000>, <0>, <0>;
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
+					<0>, <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_1_BCR>,
+			<&gcc GCC_PCIE_1_PHY_BCR>;
+		reset-names = "pcie_1_core_reset",
+				"pcie_1_phy_reset";
+
+		dma-coherent;
+		qcom,smmu-sid-base = <0x1c80>;
+		iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+			<0x100 &apps_smmu 0x1c81 0x1>;
+
+		qcom,boot-option = <0x1>;
+		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
+		qcom,drv-name = "lpass";
+		qcom,no-l0s-supported;
+		qcom,drv-l1ss-timeout-us = <5000>;
+		qcom,slv-addr-space-size = <0x20000000>;
+		qcom,ep-latency = <10>;
+		qcom,num-parf-testbus-sel = <0xb9>;
+
+		qcom,pcie-phy-ver = <1102>;
+		qcom,phy-status-offset = <0xa14>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0xa40>;
+		qcom,phy-sequence = <0x0a40 0x03 0x0
+				0x0010 0x01 0x0
+				0x001c 0x31 0x0
+				0x0020 0x01 0x0
+				0x0024 0xde 0x0
+				0x0028 0x07 0x0
+				0x0030 0x4c 0x0
+				0x0034 0x06 0x0
+				0x0048 0x90 0x0
+				0x0058 0x0f 0x0
+				0x0074 0x06 0x0
+				0x0078 0x06 0x0
+				0x007c 0x16 0x0
+				0x0080 0x16 0x0
+				0x0084 0x36 0x0
+				0x0088 0x36 0x0
+				0x0094 0x08 0x0
+				0x00a4 0x42 0x0
+				0x00ac 0x0a 0x0
+				0x00b0 0x1a 0x0
+				0x00b4 0x14 0x0
+				0x00b8 0x34 0x0
+				0x00bc 0x82 0x0
+				0x00c4 0x68 0x0
+				0x00cc 0x55 0x0
+				0x00d0 0x55 0x0
+				0x00d4 0x03 0x0
+				0x00d8 0xab 0x0
+				0x00dc 0xaa 0x0
+				0x00e0 0x02 0x0
+				0x010c 0x02 0x0
+				0x0110 0x24 0x0
+				0x0118 0xb4 0x0
+				0x011c 0x03 0x0
+				0x0154 0x34 0x0
+				0x0158 0x01 0x0
+				0x016c 0x08 0x0
+				0x01ac 0xca 0x0
+				0x01b0 0x1e 0x0
+				0x01b4 0xa2 0x0
+				0x01b8 0x18 0x0
+				0x01bc 0x11 0x0
+				0x023c 0x11 0x0
+				0x0284 0x75 0x0
+				0x029c 0x12 0x0
+				0x0304 0x02 0x0
+				0x0408 0x0c 0x0
+				0x0414 0x03 0x0
+				0x0434 0x7f 0x0
+				0x0444 0x70 0x0
+				0x0460 0x30 0x0
+				0x04d4 0x04 0x0
+				0x04d8 0x07 0x0
+				0x04dc 0x1b 0x0
+				0x04e8 0x04 0x0
+				0x04ec 0x0e 0x0
+				0x04f0 0x4a 0x0
+				0x04f4 0x0f 0x0
+				0x04f8 0xc0 0x0
+				0x04fc 0x00 0x0
+				0x0510 0x17 0x0
+				0x0518 0x1c 0x0
+				0x051c 0x03 0x0
+				0x0524 0x1e 0x0
+				0x0570 0xbf 0x0
+				0x0574 0x3f 0x0
+				0x0578 0xff 0x0
+				0x057c 0x7f 0x0
+				0x0580 0x15 0x0
+				0x0584 0x24 0x0
+				0x0588 0xe4 0x0
+				0x058c 0xec 0x0
+				0x0590 0x3b 0x0
+				0x0594 0x36 0x0
+				0x0598 0xd4 0x0
+				0x059c 0x54 0x0
+				0x05a0 0xdb 0x0
+				0x05a4 0x3b 0x0
+				0x05a8 0x31 0x0
+				0x05bc 0x0c 0x0
+				0x05b8 0x38 0x0
+				0x063c 0x11 0x0
+				0x0684 0x75 0x0
+				0x069c 0x12 0x0
+				0x0704 0x20 0x0
+				0x0808 0x0c 0x0
+				0x0814 0x03 0x0
+				0x0834 0x7f 0x0
+				0x0844 0x70 0x0
+				0x0860 0x30 0x0
+				0x08d4 0x04 0x0
+				0x08d8 0x07 0x0
+				0x08dc 0x1b 0x0
+				0x08e8 0x04 0x0
+				0x08ec 0x0e 0x0
+				0x08f0 0x4a 0x0
+				0x08f4 0x0f 0x0
+				0x08f8 0xc0 0x0
+				0x08fc 0x00 0x0
+				0x0910 0x17 0x0
+				0x0918 0x1c 0x0
+				0x091c 0x03 0x0
+				0x0924 0x1e 0x0
+				0x0970 0xbf 0x0
+				0x0974 0x3f 0x0
+				0x0978 0xff 0x0
+				0x097c 0x7f 0x0
+				0x0980 0x15 0x0
+				0x0984 0x24 0x0
+				0x0988 0xe4 0x0
+				0x098c 0xec 0x0
+				0x0990 0x3b 0x0
+				0x0994 0x36 0x0
+				0x0998 0xd4 0x0
+				0x099c 0x54 0x0
+				0x09a0 0xdb 0x0
+				0x09a4 0x3b 0x0
+				0x09a8 0x31 0x0
+				0x09bc 0x0c 0x0
+				0x09b8 0x38 0x0
+				0x0adc 0x05 0x0
+				0x0b88 0x77 0x0
+				0x0b98 0x0b 0x0
+				0x0ba4 0x01 0x0
+				0x0be0 0x0f 0x0
+				0x0e0c 0x0d 0x0
+				0x0e14 0x07 0x0
+				0x0e1c 0xc1 0x0
+				0x0e40 0x01 0x0
+				0x0e48 0x01 0x0
+				0x0e90 0x00 0x0
+				0x0eb4 0x33 0x0
+				0x0ebc 0x00 0x0
+				0x0ee0 0x58 0x0
+				0x0a00 0x00 0x0
+				0x0a44 0x03 0x0>;
+		qcom,parf-debug-reg = <0x01B0 0x0024 0x0028 0x0224 0x0500
+								0x04D0 0x04D4 0x03C0 0x0630 0x0230
+								0x0000>;
+		qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x01F4 0x0730
+								0x0734 0x0738 0x073C>;
+		qcom,phy-debug-reg = <0x0068 0x0140 0x0144 0x0148 0x014C
+								0x0150 0x0160 0x0178 0x02f0 0x06f0
+								0x02fC 0x06fC 0x05fc 0x09fc 0x1000
+								0x1400 0x1004 0x1404 0x1008 0x1408
+								0x100c 0x140C 0x1010 0x1410 0x1014
+								0x1414 0x1018 0x1418 0x1220 0x1620
+								0x0a14 0x0a18 0x0a1C 0x0a20 0x0a24
+								0x0a28 0x0a2C 0x0a30 0x0a34 0x0a38
+								0x0a3C 0x0e00 0x0e04>;
+
+		pcie1_rp: pcie1_rp {
+			reg = <0 0 0 0 0>;
+		};
+	};
+
+	pcie1_msi: qcom,pcie1_msi@17a10040 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0x17a10040 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 800 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 801 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 802 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 803 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 804 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 805 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 806 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 807 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 808 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 809 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 810 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 811 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 812 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 813 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 814 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 815 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 816 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 817 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 818 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 819 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 820 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 821 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 822 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 823 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 824 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 825 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 826 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 827 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 828 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 829 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 830 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 831 IRQ_TYPE_EDGE_RISING>;
+	};
+
+	pcie2: qcom,pcie@1c10000 {
+		compatible = "qcom,pci-msm";
+
+		reg = <0x01c10000 0x3000>,
+			<0x01c16000 0x2000>,
+			<0x64000000 0xf1d>,
+			<0x64000f20 0xa8>,
+			<0x64001000 0x1000>,
+			<0x64100000 0x100000>;
+		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
+
+		cell-index = <2>;
+		linux,pci-domain = <2>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x64200000 0x64200000 0x0 0x100000>,
+			<0x02000000 0x0 0x64300000 0x64300000 0x0 0x3d00000>;
+
+		interrupt-parent = <&pcie2>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
+		msi-parent = <&pcie2_msi>;
+
+		perst-gpio = <&tlmm 85 GPIO_ACTIVE_HIGH>;
+		wake-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie2_clkreq_default
+				&pcie2_perst_default
+				&pcie2_wake_default>;
+
+		gdsc-core-vdd-supply = <&pcie_2_gdsc>;
+		vreg-1p2-supply = <&pm8150_l9>;
+		vreg-0p9-supply = <&pm8150_l5>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 25500>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 98800>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+		qcom,bw-scale = /* Gen1 */
+				<RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen2 */
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				RPMH_REGULATOR_LEVEL_LOW_SVS
+				19200000
+				/* Gen3 */
+				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_NOM
+				100000000>;
+		interconnect-names = "icc_path";
+		interconnects = <&aggre1_noc MASTER_PCIE_2 &mc_virt SLAVE_EBI1>;
+
+		clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
+			<&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_PCIE_2_AUX_CLK>,
+			<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_2_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_MDM_CLKREF_EN>,
+			<&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+			<&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
+			<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+			<&gcc GCC_PCIE_2_PIPE_CLK_SRC>,
+			<&pcie_2_pipe_clk>;
+		clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
+				"pcie_aux_clk", "pcie_cfg_ahb_clk",
+				"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
+				"pcie_ldo", "pcie_slv_q2a_axi_clk",
+				"pcie_tbu_clk", "pcie_phy_refgen_clk",
+				"pcie_ddrss_sf_tbu_clk", "pcie_pipe_clk_mux",
+				"pcie_pipe_clk_ext_src";
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <100000000>, <0>, <0>;
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
+					<0>, <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_2_BCR>,
+			<&gcc GCC_PCIE_2_PHY_BCR>;
+		reset-names = "pcie_2_core_reset",
+				"pcie_2_phy_reset";
+
+		dma-coherent;
+		qcom,smmu-sid-base = <0x1d00>;
+		iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
+			<0x100 &apps_smmu 0x1d01 0x1>;
+
+		qcom,boot-option = <0x1>;
+		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
+		qcom,drv-name = "lpass";
+		qcom,no-l0s-supported;
+		qcom,drv-l1ss-timeout-us = <5000>;
+		qcom,slv-addr-space-size = <0x4000000>;
+		qcom,ep-latency = <10>;
+		qcom,num-parf-testbus-sel = <0xb9>;
+
+		qcom,pcie-phy-ver = <1102>;
+		qcom,phy-status-offset = <0xa14>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0xa40>;
+		qcom,phy-sequence = <0x0a40 0x03 0x0
+				0x0010 0x01 0x0
+				0x001c 0x31 0x0
+				0x0020 0x01 0x0
+				0x0024 0xde 0x0
+				0x0028 0x07 0x0
+				0x0030 0x4c 0x0
+				0x0034 0x06 0x0
+				0x0048 0x90 0x0
+				0x0058 0x0f 0x0
+				0x0074 0x06 0x0
+				0x0078 0x06 0x0
+				0x007c 0x16 0x0
+				0x0080 0x16 0x0
+				0x0084 0x36 0x0
+				0x0088 0x36 0x0
+				0x0094 0x08 0x0
+				0x00a4 0x42 0x0
+				0x00ac 0x0a 0x0
+				0x00b0 0x1a 0x0
+				0x00b4 0x14 0x0
+				0x00b8 0x34 0x0
+				0x00bc 0x82 0x0
+				0x00c4 0x68 0x0
+				0x00cc 0x55 0x0
+				0x00d0 0x55 0x0
+				0x00d4 0x03 0x0
+				0x00d8 0xab 0x0
+				0x00dc 0xaa 0x0
+				0x00e0 0x02 0x0
+				0x010c 0x02 0x0
+				0x0110 0x24 0x0
+				0x0118 0xb4 0x0
+				0x011c 0x03 0x0
+				0x0154 0x34 0x0
+				0x0158 0x01 0x0
+				0x016c 0x08 0x0
+				0x01ac 0xca 0x0
+				0x01b0 0x1e 0x0
+				0x01b4 0xa2 0x0
+				0x01b8 0x18 0x0
+				0x01bc 0x11 0x0
+				0x023c 0x11 0x0
+				0x0284 0x75 0x0
+				0x029c 0x12 0x0
+				0x0304 0x02 0x0
+				0x0408 0x0c 0x0
+				0x0414 0x03 0x0
+				0x0434 0x7f 0x0
+				0x0444 0x70 0x0
+				0x0460 0x30 0x0
+				0x04d4 0x04 0x0
+				0x04d8 0x07 0x0
+				0x04dc 0x1b 0x0
+				0x04e8 0x04 0x0
+				0x04ec 0x0e 0x0
+				0x04f0 0x4a 0x0
+				0x04f4 0x0f 0x0
+				0x04f8 0xc0 0x0
+				0x04fc 0x00 0x0
+				0x0510 0x17 0x0
+				0x0518 0x1c 0x0
+				0x051c 0x03 0x0
+				0x0524 0x1e 0x0
+				0x0570 0xbf 0x0
+				0x0574 0x3f 0x0
+				0x0578 0xff 0x0
+				0x057c 0x7f 0x0
+				0x0580 0x15 0x0
+				0x0584 0x24 0x0
+				0x0588 0xe4 0x0
+				0x058c 0xec 0x0
+				0x0590 0x3b 0x0
+				0x0594 0x36 0x0
+				0x0598 0xd4 0x0
+				0x059c 0x54 0x0
+				0x05a0 0xdb 0x0
+				0x05a4 0x3b 0x0
+				0x05a8 0x31 0x0
+				0x05bc 0x0c 0x0
+				0x05b8 0x38 0x0
+				0x063c 0x11 0x0
+				0x0684 0x75 0x0
+				0x069c 0x12 0x0
+				0x0704 0x20 0x0
+				0x0808 0x0c 0x0
+				0x0814 0x03 0x0
+				0x0834 0x7f 0x0
+				0x0844 0x70 0x0
+				0x0860 0x30 0x0
+				0x08d4 0x04 0x0
+				0x08d8 0x07 0x0
+				0x08dc 0x1b 0x0
+				0x08e8 0x04 0x0
+				0x08ec 0x0e 0x0
+				0x08f0 0x4a 0x0
+				0x08f4 0x0f 0x0
+				0x08f8 0xc0 0x0
+				0x08fc 0x00 0x0
+				0x0910 0x17 0x0
+				0x0918 0x1c 0x0
+				0x091c 0x03 0x0
+				0x0924 0x1e 0x0
+				0x0970 0xbf 0x0
+				0x0974 0x3f 0x0
+				0x0978 0xff 0x0
+				0x097c 0x7f 0x0
+				0x0980 0x15 0x0
+				0x0984 0x24 0x0
+				0x0988 0xe4 0x0
+				0x098c 0xec 0x0
+				0x0990 0x3b 0x0
+				0x0994 0x36 0x0
+				0x0998 0xd4 0x0
+				0x099c 0x54 0x0
+				0x09a0 0xdb 0x0
+				0x09a4 0x3b 0x0
+				0x09a8 0x31 0x0
+				0x09bc 0x0c 0x0
+				0x09b8 0x38 0x0
+				0x0adc 0x05 0x0
+				0x0b88 0x77 0x0
+				0x0b98 0x0b 0x0
+				0x0ba4 0x01 0x0
+				0x0be0 0x0f 0x0
+				0x0e0c 0x0d 0x0
+				0x0e14 0x07 0x0
+				0x0e1c 0xc1 0x0
+				0x0e40 0x01 0x0
+				0x0e48 0x01 0x0
+				0x0e90 0x00 0x0
+				0x0eb4 0x33 0x0
+				0x0ebc 0x00 0x0
+				0x0ee0 0x58 0x0
+				0x0a00 0x00 0x0
+				0x0a44 0x03 0x0>;
+
+		qcom,parf-debug-reg = <0x01B0 0x0024 0x0028 0x0224 0x0500
+					0x04D0 0x04D4 0x03C0 0x0630 0x0230
+					0x0000>;
+		qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x01F4 0x0730
+					0x0734 0x0738 0x073C>;
+		qcom,phy-debug-reg = <0x0068 0x0140 0x0144 0x0148 0x014C
+					0x0150 0x0160 0x0178 0x02f0 0x06f0
+					0x02fC 0x06fC 0x05fc 0x09fc 0x1000
+					0x1400 0x1004 0x1404 0x1008 0x1408
+					0x100c 0x140C 0x1010 0x1410 0x1014
+					0x1414 0x1018 0x1418 0x1220 0x1620
+					0x0a14 0x0a18 0x0a1C 0x0a20 0x0a24
+					0x0a28 0x0a2C 0x0a30 0x0a34 0x0a38
+					0x0a3C 0x0e00 0x0e04>;
+
+		pcie2_rp: pcie2_rp {
+			reg = <0 0 0 0 0>;
+		};
+	};
+
+	pcie2_msi: qcom,pcie2_msi@17a10040 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0x17a10040 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 832 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 833 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 834 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 835 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 836 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 837 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 838 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 839 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 840 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 841 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 842 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 843 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 844 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 845 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 846 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 847 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 848 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 849 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 850 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 851 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 852 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 853 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 854 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 856 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 857 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 858 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 859 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 860 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 861 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 862 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 863 IRQ_TYPE_EDGE_RISING>;
+	};
+};
diff --git a/qcom/kona-pmic-overlay.dtsi b/qcom/kona-pmic-overlay.dtsi
new file mode 100755
index 00000000..a3a9b2d0
--- /dev/null
+++ b/qcom/kona-pmic-overlay.dtsi
@@ -0,0 +1,190 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/iio/qti_power_supply_iio.h>
+
+#include "pm8150.dtsi"
+#include "pm8150b.dtsi"
+#include "pm8150l.dtsi"
+#include "pm8009.dtsi"
+
+&spmi_bus {
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	qcom,pmxprairie@8 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0x8 SPMI_USID>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		qcom,power-on@800 {
+			compatible = "qcom,qpnp-power-on";
+			reg = <0x800 0x100>;
+			qcom,modem-reset;
+		};
+	};
+
+	qcom,pmxprairie@9 {
+		compatible ="qcom,spmi-pmic";
+		reg = <0x9 SPMI_USID>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+	};
+};
+
+&pm8150_gpios {
+	key_home {
+		key_home_default: key_home_default {
+			pins = "gpio1";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+			power-source = <0>;
+		};
+	};
+
+	imu_clkin {
+		imu_clkin_default: imu_clkin_default {
+			pins = "gpio3";
+			function = "func1";
+			output-low;
+			power-source = <0>;
+			bias-disable;
+			qcom,dtest-buffer = <1>;
+			qcom,drive-strength = <1>;
+		};
+
+		imu_clkin_sleep: imu_clkin_sleep {
+			pins = "gpio3";
+			function = "func1";
+			input-enable;
+			bias-pull-down;
+			power-source = <0>;
+			qcom,dtest-buffer = <1>;
+			qcom,drive-strength = <1>;
+		};
+	};
+
+	key_vol_up {
+		key_vol_up_default: key_vol_up_default {
+			pins = "gpio6";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+			power-source = <1>;
+		};
+	};
+
+	key_confirm {
+		key_confirm_default: key_confirm_default {
+			pins = "gpio7";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+			power-source = <0>;
+		};
+	};
+
+	usb2_vbus_boost {
+		usb2_vbus_boost_default: usb2_vbus_boost_default {
+			pins = "gpio9";
+			function = "normal";
+			output-low;
+			power-source = <1>;	/* 1.8V input supply */
+		};
+	};
+
+	usb2_vbus_det {
+		usb2_vbus_det_default: usb2_vbus_det_default {
+			pins = "gpio10";
+			function = "normal";
+			input-enable;
+			bias-pull-down;
+			power-source = <1>;	/* 1.8V input supply */
+		};
+	};
+};
+
+&pm8150b_gpios {
+	qnovo_fet_ctrl {
+		qnovo_fet_ctrl_state1: qnovo_fet_ctrl_state1 {
+			pins = "gpio8";
+			function = "normal";
+			input-enable;
+			output-disable;
+			bias-disable;
+			power-source = <0>;
+		};
+
+		qnovo_fet_ctrl_state2: qnovo_fet_ctrl_state2 {
+			pins = "gpio8";
+			function = "normal";
+			input-enable;
+			output-disable;
+			bias-pull-down;
+			power-source = <0>;
+		};
+	};
+
+	smb_stat {
+		smb_stat_default: smb_stat_default {
+			  pins = "gpio6";
+			  function = "normal";
+			  input-enable;
+			  bias-pull-up;
+			  qcom,pull-up-strength = <PMIC_GPIO_PULL_UP_30>;
+			  power-source = <0>;
+		  };
+	};
+};
+
+&pm8150b_qnovo {
+	pinctrl-names = "q_state1", "q_state2";
+	pinctrl-0 = <&qnovo_fet_ctrl_state1>;
+	pinctrl-1 = <&qnovo_fet_ctrl_state2>;
+};
+
+&pm8150b_fg {
+	nvmem-names = "fg_sdam";
+	nvmem = <&pm8150_sdam_2>;
+};
+
+&pm8150b_gpios {
+	haptics_boost {
+		haptics_boost_default: haptics_boost_default {
+			pins = "gpio5";
+			function = "normal";
+			output-enable;
+			input-disable;
+			bias-disable;
+			qcom,drive-strength = <3>; /* high */
+			power-source = <1>; /* 1.8 V */
+		};
+	};
+};
+
+&soc {
+	vreg_tof: regulator-dbb1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_tof";
+		regulator-min-microvolt = <3600000>;
+		regulator-max-microvolt = <3600000>;
+		gpio = <&pm8009_gpios 1 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <1000>;
+		enable-active-high;
+	};
+
+	vreg_hap_boost: regulator-haptics-boost {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_hap_boost";
+		gpio = <&pm8150b_gpios 5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&haptics_boost_default>;
+		startup-delay-us = <1000>;
+		enable-active-high;
+		status = "okay";
+	};
+};
diff --git a/qcom/kona-qupv3.dtsi b/qcom/kona-qupv3.dtsi
new file mode 100755
index 00000000..cdebd8d6
--- /dev/null
+++ b/qcom/kona-qupv3.dtsi
@@ -0,0 +1,1195 @@
+&soc {
+	/* QUPv3 SE Instances
+	 * Qup0 0: SE 0
+	 * Qup0 1: SE 1
+	 * Qup0 2: SE 2
+	 * Qup0 3: SE 3
+	 * Qup0 4: SE 4
+	 * Qup0 5: SE 5
+	 * Qup0 6: SE 6
+	 * Qup0 7: SE 7
+	 * Qup1 0: SE 8
+	 * Qup1 1: SE 9
+	 * Qup1 2: SE 10
+	 * Qup1 3: SE 11
+	 * Qup1 4: SE 12
+	 * Qup1 5: SE 13
+	 * Qup2 0: SE 14
+	 * Qup2 1: SE 15
+	 * Qup2 2: SE 16
+	 * Qup2 3: SE 17
+	 * Qup2 4: SE 18
+	 * Qup2 5: SE 19
+	 */
+
+	/* GPI Instance */
+	gpi_dma0: qcom,gpi-dma@900000 {
+		#dma-cells = <5>;
+		compatible = "qcom,gpi-dma";
+		reg = <0x900000 0x70000>;
+		reg-names = "gpi-top";
+		interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,max-num-gpii = <15>;
+		qcom,gpii-mask = <0x7ff>;
+		qcom,ev-factor = <2>;
+		qcom,gpi-ee-offset = <0x1000>;
+		iommus = <&apps_smmu 0x5b6 0x0>;
+		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+		dma-coherent;
+		status = "ok";
+	};
+
+	gpi_dma1: qcom,gpi-dma@a00000 {
+		#dma-cells = <5>;
+		compatible = "qcom,gpi-dma";
+		reg = <0xa00000 0x70000>;
+		reg-names = "gpi-top";
+		interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,max-num-gpii = <10>;
+		qcom,gpii-mask = <0x3f>;
+		qcom,ev-factor = <2>;
+		qcom,gpi-ee-offset = <0x6000>;
+		iommus = <&apps_smmu 0x56 0x0>;
+		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+		dma-coherent;
+		status = "ok";
+	};
+
+	gpi_dma2: qcom,gpi-dma@800000 {
+		#dma-cells = <5>;
+		compatible = "qcom,gpi-dma";
+		reg = <0x800000 0x70000>;
+		reg-names = "gpi-top";
+		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,max-num-gpii = <10>;
+		qcom,gpii-mask = <0x3f>;
+		qcom,ev-factor = <2>;
+		qcom,gpi-ee-offset = <0x6000>;
+		iommus = <&apps_smmu 0x76 0x0>;
+		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+		dma-coherent;
+		status = "ok";
+	};
+
+	/* QUPv3_0  wrapper  instance : North QUP*/
+	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0x9c0000 0x2000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		iommus = <&apps_smmu 0x5a3 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+		qcom,iommu-dma = "fastmap";
+		dma-coherent;
+		ranges;
+		status = "ok";
+
+		/* Debug UART Instance for RUMI platform */
+		qupv3_se2_2uart: qcom,qup_uart@988000 {
+			compatible = "qcom,geni-debug-uart";
+			reg = <0x988000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se2_2uart_active>;
+			pinctrl-1 = <&qupv3_se2_2uart_sleep>;
+			interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		/*
+		 * HS UART instances. HS UART usecases can be supported on these
+		 * instances only.
+		 */
+		qupv3_se6_4uart: qcom,qup_uart@998000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0x998000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "active", "sleep";
+			pinctrl-0 = <&qupv3_se6_default_cts>,
+				<&qupv3_se6_default_rtsrx>, <&qupv3_se6_default_tx>;
+			pinctrl-1 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
+								<&qupv3_se6_tx>;
+			pinctrl-2 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
+								<&qupv3_se6_tx>;
+			interrupts-extended = <&intc GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>,
+						<&tlmm 19 GPIO_ACTIVE_HIGH>;
+			qcom,wakeup-byte = <0xFD>;
+			status = "disabled";
+		};
+
+		/* I2C */
+		qupv3_se0_i2c: i2c@980000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x980000 0x4000>;
+			interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma0 0 0 3 64 0>,
+				<&gpi_dma0 1 0 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se0_i2c_active>;
+			pinctrl-1 = <&qupv3_se0_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se1_i2c: i2c@984000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x984000 0x4000>;
+			interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma0 0 1 3 64 0>,
+				<&gpi_dma0 1 1 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se1_i2c_active>;
+			pinctrl-1 = <&qupv3_se1_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se2_i2c: i2c@988000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x988000 0x4000>;
+			interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma0 0 2 3 64 0>,
+				<&gpi_dma0 1 2 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se2_i2c_active>;
+			pinctrl-1 = <&qupv3_se2_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se3_i2c: i2c@98c000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x98c000 0x4000>;
+			interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma0 0 3 3 64 0>,
+				<&gpi_dma0 1 3 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se3_i2c_active>;
+			pinctrl-1 = <&qupv3_se3_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se4_i2c: i2c@990000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x990000 0x4000>;
+			interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma0 0 4 3 64 0>,
+				<&gpi_dma0 1 4 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se4_i2c_active>;
+			pinctrl-1 = <&qupv3_se4_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se5_i2c: i2c@994000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x994000 0x4000>;
+			interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma0 0 5 3 64 0>,
+				<&gpi_dma0 1 5 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se5_i2c_active>;
+			pinctrl-1 = <&qupv3_se5_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se6_i2c: i2c@998000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x998000 0x4000>;
+			interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma0 0 6 3 64 0>,
+				<&gpi_dma0 1 6 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se6_i2c_active>;
+			pinctrl-1 = <&qupv3_se6_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se7_i2c: i2c@99c000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x99c000 0x4000>;
+			interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma0 0 7 3 64 0>,
+				<&gpi_dma0 1 7 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se7_i2c_active>;
+			pinctrl-1 = <&qupv3_se7_i2c_sleep>;
+			status = "disabled";
+		};
+
+		/* SPI */
+		qupv3_se0_spi: spi@980000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x980000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se0_spi_active>;
+			pinctrl-1 = <&qupv3_se0_spi_sleep>;
+			interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma0 0 0 1 64 0>,
+				<&gpi_dma0 1 0 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se1_spi: spi@984000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x984000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se1_spi_active>;
+			pinctrl-1 = <&qupv3_se1_spi_sleep>;
+			interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma0 0 1 1 64 0>,
+				<&gpi_dma0 1 1 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se2_spi: spi@988000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x988000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se2_spi_active>;
+			pinctrl-1 = <&qupv3_se2_spi_sleep>;
+			interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma0 0 2 1 64 0>,
+				<&gpi_dma0 1 2 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se3_spi: spi@98c000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x98c000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se3_spi_active>;
+			pinctrl-1 = <&qupv3_se3_spi_sleep>;
+			interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma0 0 3 1 64 0>,
+				<&gpi_dma0 1 3 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se4_spi: spi@990000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x990000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se4_spi_active>;
+			pinctrl-1 = <&qupv3_se4_spi_sleep>;
+			interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma0 0 4 1 64 0>,
+				<&gpi_dma0 1 4 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se5_spi: spi@994000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x994000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se5_spi_active>;
+			pinctrl-1 = <&qupv3_se5_spi_sleep>;
+			interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma0 0 5 1 64 0>,
+				<&gpi_dma0 1 5 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se6_spi: spi@998000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x998000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se6_spi_active>;
+			pinctrl-1 = <&qupv3_se6_spi_sleep>;
+			interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma0 0 6 1 64 0>,
+				<&gpi_dma0 1 6 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se7_spi: spi@99c000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x99c000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>,
+			<&aggre2_noc MASTER_QUP_0 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se7_spi_active>;
+			pinctrl-1 = <&qupv3_se7_spi_sleep>;
+			interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma0 0 7 1 64 0>,
+				<&gpi_dma0 1 7 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+	};
+
+	/* QUPv3_1  wrapper  instance : South_1 QUP */
+	qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0xac0000 0x2000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		iommus = <&apps_smmu 0x43 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+		qcom,iommu-dma = "fastmap";
+		dma-coherent;
+		ranges;
+		status = "ok";
+
+		/* Debug UART Instance */
+		qupv3_se12_2uart: qcom,qup_uart@a90000 {
+			compatible = "qcom,geni-debug-uart";
+			reg = <0xa90000 0x4000>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se12_2uart_active>;
+			pinctrl-1 = <&qupv3_se12_2uart_sleep>;
+			status = "disabled";
+		};
+
+		/*  I2C  */
+		qupv3_se8_i2c: i2c@a80000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa80000 0x4000>;
+			interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma1 0 0 3 64 0>,
+				<&gpi_dma1 1 0 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se8_i2c_active>;
+			pinctrl-1 = <&qupv3_se8_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se9_i2c: i2c@a84000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa84000 0x4000>;
+			interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma1 0 1 3 64 0>,
+				<&gpi_dma1 1 1 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se9_i2c_active>;
+			pinctrl-1 = <&qupv3_se9_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se10_i2c: i2c@a88000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa88000 0x4000>;
+			interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma1 0 2 3 64 0>,
+				<&gpi_dma1 1 2 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se10_i2c_active>;
+			pinctrl-1 = <&qupv3_se10_i2c_sleep>;
+			qcom,wrapper-core = <&qupv3_1>;
+			status = "disabled";
+		};
+
+		qupv3_se11_i2c: i2c@a8c000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa8c000 0x4000>;
+			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma1 0 3 3 64 0>,
+				<&gpi_dma1 1 3 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se11_i2c_active>;
+			pinctrl-1 = <&qupv3_se11_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se12_i2c: i2c@a90000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa90000 0x4000>;
+			interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma1 0 4 3 64 0>,
+				<&gpi_dma1 1 4 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se12_i2c_active>;
+			pinctrl-1 = <&qupv3_se12_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se13_i2c: i2c@a94000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa94000 0x4000>;
+			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma1 0 5 3 64 0>,
+				<&gpi_dma1 1 5 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se13_i2c_active>;
+			pinctrl-1 = <&qupv3_se13_i2c_sleep>;
+			status = "disabled";
+		};
+
+		/* SPI */
+		qupv3_se8_spi: spi@a80000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xa80000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se8_spi_active>;
+			pinctrl-1 = <&qupv3_se8_spi_active>;
+			interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma1 0 0 1 64 0>,
+				<&gpi_dma1 1 0 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se9_spi: spi@a84000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xa84000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se9_spi_active>;
+			pinctrl-1 = <&qupv3_se9_spi_sleep>;
+			interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma1 0 1 1 64 0>,
+				<&gpi_dma1 1 1 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se10_spi: spi@a88000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xa88000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se10_spi_active>;
+			pinctrl-1 = <&qupv3_se10_spi_sleep>;
+			interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma1 0 2 1 64 0>,
+				<&gpi_dma1 1 2 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se11_spi: spi@a8c000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xa8c000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se11_spi_active>;
+			pinctrl-1 = <&qupv3_se11_spi_sleep>;
+			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma1 0 3 1 64 0>,
+				<&gpi_dma1 1 3 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se12_spi: spi@a90000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xa90000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se12_spi_active>;
+			pinctrl-1 = <&qupv3_se12_spi_sleep>;
+			interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma1 0 4 1 64 0>,
+				<&gpi_dma1 1 4 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se13_spi: spi@a94000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xa94000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se13_spi_active>;
+			pinctrl-1 = <&qupv3_se13_spi_sleep>;
+			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma1 0 5 1 64 0>,
+				<&gpi_dma1 1 5 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+	};
+
+	/* QUPv3_2  wrapper  instance : South_2 QUP */
+	qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0x8c0000 0x2000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		iommus = <&apps_smmu 0x63 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+		qcom,iommu-dma = "fastmap";
+		dma-coherent;
+		ranges;
+		status = "ok";
+
+		/*
+		 * HS UART : Modem/Audio backup
+		 */
+		qupv3_se17_4uart: qcom,qup_uart@88c000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0x88c000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
+								<&qupv3_se17_tx>;
+			pinctrl-1 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
+								<&qupv3_se17_tx>;
+			interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
+						<&tlmm 55 GPIO_ACTIVE_HIGH>;
+			qcom,wakeup-byte = <0xFD>;
+			status = "disabled";
+		};
+
+		/*
+		 * HS UART : 2-wire Modem
+		 */
+		qupv3_se18_2uart: qcom,qup_uart@890000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0x890000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se18_rx>, <&qupv3_se18_tx>;
+			pinctrl-1 = <&qupv3_se18_rx>, <&qupv3_se18_tx>;
+			interrupts-extended = <&intc GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>,
+							<&tlmm 59 GPIO_ACTIVE_HIGH>;
+			qcom,wakeup-byte = <0xFD>;
+			status = "disabled";
+		};
+
+		/* I2C */
+		qupv3_se14_i2c: i2c@880000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x880000 0x4000>;
+			interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma2 0 0 3 64 0>,
+				<&gpi_dma2 1 0 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se14_i2c_active>;
+			pinctrl-1 = <&qupv3_se14_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se15_i2c: i2c@884000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x884000 0x4000>;
+			interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma2 0 1 3 64 0>,
+				<&gpi_dma2 1 1 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se15_i2c_active>;
+			pinctrl-1 = <&qupv3_se15_i2c_sleep>;
+			status = "ok";
+		};
+
+		qupv3_se16_i2c: i2c@888000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x888000 0x4000>;
+			interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma2 0 2 3 64 0>,
+				<&gpi_dma2 1 2 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se16_i2c_active>;
+			pinctrl-1 = <&qupv3_se16_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se17_i2c: i2c@88c000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x88c000 0x4000>;
+			interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma2 0 3 3 64 0>,
+				<&gpi_dma2 1 3 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se17_i2c_active>;
+			pinctrl-1 = <&qupv3_se17_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se18_i2c: i2c@890000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x890000 0x4000>;
+			interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma2 0 4 3 64 0>,
+				<&gpi_dma2 1 4 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se18_i2c_active>;
+			pinctrl-1 = <&qupv3_se18_i2c_sleep>;
+			status = "disabled";
+		};
+
+		qupv3_se19_i2c: i2c@894000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x894000 0x4000>;
+			interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>;
+			dmas = <&gpi_dma2 0 5 3 64 0>,
+				<&gpi_dma2 1 5 3 64 0>;
+			dma-names = "tx", "rx";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se19_i2c_active>;
+			pinctrl-1 = <&qupv3_se19_i2c_sleep>;
+			status = "disabled";
+		};
+
+		/* SPI */
+		qupv3_se14_spi: spi@880000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x880000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se14_spi_active>;
+			pinctrl-1 = <&qupv3_se14_spi_sleep>;
+			interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma2 0 0 1 64 0>,
+				<&gpi_dma2 1 0 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se15_spi: spi@884000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x884000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se15_spi_active>;
+			pinctrl-1 = <&qupv3_se15_spi_sleep>;
+			interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma2 0 1 1 64 0>,
+				<&gpi_dma2 1 1 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se16_spi: spi@888000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x888000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se16_spi_active>;
+			pinctrl-1 = <&qupv3_se16_spi_sleep>;
+			interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma2 0 2 1 64 0>,
+				<&gpi_dma2 1 2 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se17_spi: spi@88c000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x88c000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se17_spi_active>;
+			pinctrl-1 = <&qupv3_se17_spi_sleep>;
+			interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma2 0 3 1 64 0>,
+				<&gpi_dma2 1 3 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se18_spi: spi@890000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x890000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se18_spi_active>;
+			pinctrl-1 = <&qupv3_se18_spi_sleep>;
+			interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma2 0 4 1 64 0>,
+				<&gpi_dma2 1 4 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se19_spi: spi@894000 {
+			compatible = "qcom,spi-geni";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x894000 0x4000>;
+			reg-names = "se_phys";
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>,
+			<&aggre1_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se19_spi_active>;
+			pinctrl-1 = <&qupv3_se19_spi_sleep>;
+			interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+			spi-max-frequency = <50000000>;
+			dmas = <&gpi_dma2 0 5 1 64 0>,
+				<&gpi_dma2 1 5 1 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+	};
+};
diff --git a/qcom/kona-thermal.dtsi b/qcom/kona-thermal.dtsi
new file mode 100755
index 00000000..bf939ab6
--- /dev/null
+++ b/qcom/kona-thermal.dtsi
@@ -0,0 +1,1347 @@
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/thermal/qmi_thermal.h>
+
+&cpufreq_hw {
+	qcom,cpu-isolation {
+		compatible = "qcom,cpu-isolate";
+		cpu0_isolate: cpu0-isolate {
+			qcom,cpu = <&CPU0>;
+			#cooling-cells = <2>;
+		};
+
+		cpu1_isolate: cpu1-isolate {
+			qcom,cpu = <&CPU1>;
+			#cooling-cells = <2>;
+		};
+
+		cpu2_isolate: cpu2-isolate {
+			qcom,cpu = <&CPU2>;
+			#cooling-cells = <2>;
+		};
+
+		cpu3_isolate: cpu3-isolate {
+			qcom,cpu = <&CPU3>;
+			#cooling-cells = <2>;
+		};
+
+		cpu4_isolate: cpu4-isolate {
+			qcom,cpu = <&CPU4>;
+			#cooling-cells = <2>;
+		};
+
+		cpu5_isolate: cpu5-isolate {
+			qcom,cpu = <&CPU5>;
+			#cooling-cells = <2>;
+		};
+
+		cpu6_isolate: cpu6-isolate {
+			qcom,cpu = <&CPU6>;
+			#cooling-cells = <2>;
+		};
+
+		cpu7_isolate: cpu7-isolate {
+			qcom,cpu = <&CPU7>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	qcom,limits-dcvs {
+		compatible = "qcom,msm-hw-limits";
+		isens_vref_0p8-supply = <&pm8150_l5_ao>;
+		isens-vref-0p8-settings = <880000 880000 20000>;
+		isens_vref_1p8-supply = <&pm8150_l12_ao>;
+		isens-vref-1p8-settings = <1800000 1800000 20000>;
+	};
+};
+
+&soc {
+	qmi-tmd-devices {
+		compatible = "qcom,qmi-cooling-devices";
+
+		modem {
+			qcom,instance-id = <QMI_MODEM_NR_INST_ID>;
+
+			modem_pa: modem_pa {
+				qcom,qmi-dev-name = "pa";
+				#cooling-cells = <2>;
+			};
+
+			modem_pa_fr1: modem_pa_fr1 {
+				qcom,qmi-dev-name = "pa_fr1";
+				#cooling-cells = <2>;
+			};
+
+			modem_tj: modem_tj {
+				qcom,qmi-dev-name = "modem";
+				#cooling-cells = <2>;
+			};
+
+			modem_current: modem_current {
+				qcom,qmi-dev-name = "modem_current";
+				#cooling-cells = <2>;
+			};
+
+			modem_skin: modem_skin {
+				qcom,qmi-dev-name = "modem_skin";
+				#cooling-cells = <2>;
+			};
+
+			modem_mmw_skin0: modem_mmw_skin0 {
+				qcom,qmi-dev-name = "mmw_skin0";
+				#cooling-cells = <2>;
+			};
+
+			modem_mmw_skin1: modem_mmw_skin1 {
+				qcom,qmi-dev-name = "mmw_skin1";
+				#cooling-cells = <2>;
+			};
+
+			modem_mmw_skin2: modem_mmw_skin2 {
+				qcom,qmi-dev-name = "mmw_skin2";
+				#cooling-cells = <2>;
+			};
+
+			modem_mmw_skin3: modem_mmw_skin3 {
+				qcom,qmi-dev-name = "mmw_skin3";
+				#cooling-cells = <2>;
+			};
+
+			modem_mmw0: modem_mmw0 {
+				qcom,qmi-dev-name = "mmw0";
+				#cooling-cells = <2>;
+			};
+
+			modem_mmw1: modem_mmw1 {
+				qcom,qmi-dev-name = "mmw1";
+				#cooling-cells = <2>;
+			};
+
+			modem_mmw2: modem_mmw2 {
+				qcom,qmi-dev-name = "mmw2";
+				#cooling-cells = <2>;
+			};
+
+			modem_mmw3: modem_mmw3 {
+				qcom,qmi-dev-name = "mmw3";
+				#cooling-cells = <2>;
+			};
+
+			modem_bcl: modem_bcl {
+				qcom,qmi-dev-name = "vbatt_low";
+				#cooling-cells = <2>;
+			};
+
+			modem_charge_state: modem_charge_state {
+				qcom,qmi-dev-name = "charge_state";
+				#cooling-cells = <2>;
+			};
+		};
+	};
+
+	qmi_sensor: qmi-ts-sensors {
+		compatible = "qcom,qmi-sensors";
+		#thermal-sensor-cells = <1>;
+
+		modem {
+			qcom,instance-id = <QMI_MODEM_NR_INST_ID>;
+			qcom,qmi-sensor-names = "pa",
+						"pa_1",
+						"qfe_wtr0",
+						"modem_tsens",
+						"qfe_mmw0",
+						"qfe_mmw1",
+						"qfe_mmw2",
+						"qfe_mmw3",
+						"xo_therm",
+						"qfe_mmw_streamer0",
+						"qfe_mmw0_mod",
+						"qfe_mmw1_mod",
+						"qfe_mmw2_mod",
+						"qfe_mmw3_mod",
+						"qfe_ret_pa0",
+						"qfe_wtr_pa0",
+						"qfe_wtr_pa1",
+						"qfe_wtr_pa2",
+						"qfe_wtr_pa3",
+						"sys_therm1",
+						"sys_therm2",
+						"modem_tsens1";
+		};
+	};
+};
+
+&thermal_zones {
+	aoss0-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&tsens0 0>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-0-0-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&tsens0 1>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-0-1-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&tsens0 2>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-0-2-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&tsens0 3>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-0-3-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 4>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpuss-0-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 5>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpuss-1-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 6>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-1-0-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 7>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-1-1-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 8>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-1-2-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 9>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-1-3-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 10>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-1-4-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 11>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-1-5-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 12>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-1-6-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 13>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cpu-1-7-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 14>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	gpuss-0-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 15>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	aoss-1-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 0>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cwlan-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 1>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	video-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 2>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	ddr-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 3>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	q6-hvx-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 4>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	camera-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 5>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	cmpss-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 6>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	npu-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 7>;
+		thermal-governor = "user_space";
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	gpuss-1-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&tsens1 8>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <115000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	apc-0-max-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		wake-capable-sensor;
+		trips {
+			silver-trip {
+				temperature = <120000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+		};
+	};
+
+	apc-1-max-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		wake-capable-sensor;
+		trips {
+			gold-trip {
+				temperature = <120000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+		};
+	};
+
+	pop-mem-step {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 3>;
+		thermal-governor = "step_wise";
+		wake-capable-sensor;
+		trips {
+			pop_trip: pop-trip {
+				temperature = <95000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			pop_cdev4 {
+				trip = <&pop_trip>;
+				cooling-device =
+					<&CPU4 THERMAL_NO_LIMIT
+						THERMAL_NO_LIMIT>;
+			};
+
+		};
+	};
+
+	cpu-0-0-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&tsens0 1>;
+		wake-capable-sensor;
+		trips {
+			cpu00_config: cpu00-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu00_cdev {
+				trip = <&cpu00_config>;
+				cooling-device = <&cpu0_isolate 1 1>;
+			};
+		};
+	};
+
+	cpu-0-1-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&tsens0 2>;
+		wake-capable-sensor;
+		trips {
+			cpu01_config: cpu01-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpu01_cdev {
+				trip = <&cpu01_config>;
+				cooling-device = <&cpu1_isolate 1 1>;
+			};
+		};
+	};
+
+	cpu-0-2-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&tsens0 3>;
+		wake-capable-sensor;
+		trips {
+			cpu02_config: cpu02-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+	};
+
+	cpu-0-3-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 4>;
+		thermal-governor = "step_wise";
+		wake-capable-sensor;
+		trips {
+			cpu03_config: cpu03-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+	};
+
+	cpu-1-0-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 7>;
+		thermal-governor = "step_wise";
+		wake-capable-sensor;
+		trips {
+			cpufreq_10_config: cpufreq-10-config {
+				temperature = <75000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu10_config: cpu10-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpufreq_cdev {
+				trip = <&cpufreq_10_config>;
+				cooling-device = <&cpu7_notify 1 1>;
+			};
+
+			cpu10_cdev {
+				trip = <&cpu10_config>;
+				cooling-device = <&cpu4_isolate 1 1>;
+			};
+		};
+	};
+
+	cpu-1-1-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 8>;
+		thermal-governor = "step_wise";
+		wake-capable-sensor;
+		trips {
+			cpufreq_11_config: cpufreq-11-config {
+				temperature = <75000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu11_config: cpu11-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpufreq_cdev {
+				trip = <&cpufreq_11_config>;
+				cooling-device = <&cpu7_notify 1 1>;
+			};
+
+			cpu11_cdev {
+				trip = <&cpu11_config>;
+				cooling-device = <&cpu5_isolate 1 1>;
+			};
+		};
+	};
+
+	cpu-1-2-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 9>;
+		thermal-governor = "step_wise";
+		wake-capable-sensor;
+		trips {
+			cpufreq_12_config: cpufreq-12-config {
+				temperature = <75000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu12_config: cpu12-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpufreq_cdev {
+				trip = <&cpufreq_12_config>;
+				cooling-device = <&cpu7_notify 1 1>;
+			};
+
+			cpu12_cdev {
+				trip = <&cpu12_config>;
+				cooling-device = <&cpu6_isolate 1 1>;
+			};
+		};
+	};
+
+	cpu-1-3-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 10>;
+		thermal-governor = "step_wise";
+		wake-capable-sensor;
+		trips {
+			cpufreq_13_config: cpufreq-13-config {
+				temperature = <75000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu13_config: cpu13-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpufreq_cdev {
+				trip = <&cpufreq_13_config>;
+				cooling-device = <&cpu7_notify 1 1>;
+			};
+
+			cpu13_cdev {
+				trip = <&cpu13_config>;
+				cooling-device = <&cpu7_isolate 1 1>;
+			};
+		};
+	};
+
+	cpu-1-4-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 11>;
+		thermal-governor = "step_wise";
+		wake-capable-sensor;
+		trips {
+			cpufreq_14_config: cpufreq-14-config {
+				temperature = <75000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu14_config: cpu14-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpufreq_cdev {
+				trip = <&cpufreq_14_config>;
+				cooling-device = <&cpu7_notify 1 1>;
+			};
+
+			cpu14_cdev {
+				trip = <&cpu14_config>;
+				cooling-device = <&cpu4_isolate 1 1>;
+			};
+		};
+	};
+
+	cpu-1-5-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 12>;
+		thermal-governor = "step_wise";
+		wake-capable-sensor;
+		trips {
+			cpufreq_15_config: cpufreq-15-config {
+				temperature = <75000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu15_config: cpu15-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpufreq_cdev {
+				trip = <&cpufreq_15_config>;
+				cooling-device = <&cpu7_notify 1 1>;
+			};
+
+			cpu15_cdev {
+				trip = <&cpu15_config>;
+				cooling-device = <&cpu5_isolate 1 1>;
+			};
+		};
+	};
+
+	cpu-1-6-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 13>;
+		thermal-governor = "step_wise";
+		wake-capable-sensor;
+		trips {
+			cpufreq_16_config: cpufreq-16-config {
+				temperature = <75000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu16_config: cpu16-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpufreq_cdev {
+				trip = <&cpufreq_16_config>;
+				cooling-device = <&cpu7_notify 1 1>;
+			};
+
+			cpu16_cdev {
+				trip = <&cpu16_config>;
+				cooling-device = <&cpu6_isolate 1 1>;
+			};
+		};
+	};
+
+	cpu-1-7-step {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens0 14>;
+		thermal-governor = "step_wise";
+		wake-capable-sensor;
+		trips {
+			cpufreq_17_config: cpufreq-17-config {
+				temperature = <75000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+
+			cpu17_config: cpu17-config {
+				temperature = <110000>;
+				hysteresis = <10000>;
+				type = "passive";
+			};
+		};
+
+		cooling-maps {
+			cpufreq_cdev {
+				trip = <&cpufreq_17_config>;
+				cooling-device = <&cpu7_notify 1 1>;
+			};
+
+			cpu17_cdev {
+				trip = <&cpu17_config>;
+				cooling-device = <&cpu7_isolate 1 1>;
+			};
+		};
+	};
+
+	modem-lte-sub6-pa1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_NR_INST_ID+QMI_PA)>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	modem-lte-sub6-pa2 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_NR_INST_ID+QMI_PA_1)>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	modem-mmw0-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_0)>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	modem-mmw1-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_1)>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	modem-mmw2-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_2)>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	modem-mmw3-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_3)>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	modem-skin-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_NR_INST_ID+QMI_XO_THERM)>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	modem-wifi-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_NR_INST_ID+QMI_SYS_THERM_1)>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	modem-ambient-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_NR_INST_ID+QMI_SYS_THERM_2)>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	modem-0-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_NR_INST_ID+QMI_MODEM_TSENS)>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	modem-1-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_NR_INST_ID+QMI_MODEM_TSENS_1)>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	modem-streamer-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_STREAMER_0)>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	modem-mmw0-mod-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_0_MOD)>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	modem-mmw1-mod-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_1_MOD)>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	modem-mmw2-mod-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_2_MOD)>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	modem-mmw3-mod-usr {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&qmi_sensor
+				(QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_3_MOD)>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+};
diff --git a/qcom/kona-usb.dtsi b/qcom/kona-usb.dtsi
new file mode 100755
index 00000000..5c1c82a8
--- /dev/null
+++ b/qcom/kona-usb.dtsi
@@ -0,0 +1,553 @@
+#include <dt-bindings/clock/qcom,gcc-sm8250.h>
+#include <dt-bindings/phy/qcom,kona-qmp-usb3.h>
+
+&soc {
+	/* Primary USB port related controller */
+	usb0: ssusb@a600000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0x0a600000 0x100000>;
+		reg-names = "core_base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>,
+			     <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+			     <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+			     <&pdc 15 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+				"ss_phy_irq", "dm_hs_phy_irq";
+		qcom,use-pdc-interrupts;
+
+		USB3_GDSC-supply = <&usb30_prim_gdsc>;
+		dpdm-supply = <&usb2_phy0>;
+		clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+			<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+			<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+			<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+			/*
+			 * GCC_USB3_SEC_CLKREF_EN provides ref_clk for both
+			 * USB instances.
+			 */
+			 <&gcc GCC_USB3_SEC_CLKREF_EN>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+					"utmi_clk", "sleep_clk", "xo";
+
+		resets = <&gcc GCC_USB30_PRIM_BCR>;
+		reset-names = "core_reset";
+
+		qcom,core-clk-rate = <200000000>;
+		qcom,core-clk-rate-hs = <66666667>;
+		qcom,num-gsi-evt-buffs = <0x3>;
+		qcom,gsi-reg-offset =
+			<0x0fc /* GSI_GENERAL_CFG */
+			0x110 /* GSI_DBL_ADDR_L */
+			0x120 /* GSI_DBL_ADDR_H */
+			0x130 /* GSI_RING_BASE_ADDR_L */
+			0x144 /* GSI_RING_BASE_ADDR_H */
+			0x1a4>; /* GSI_IF_STS */
+
+		interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
+		interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
+				<&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>,
+				<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
+		dwc3@a600000 {
+			compatible = "snps,dwc3";
+			reg = <0x0a600000 0xd93c>;
+			iommus = <&apps_smmu 0x0 0x0>;
+			qcom,iommu-dma = "atomic";
+			qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
+
+			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+			usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x10>;
+			snps,usb3_lpm_capable;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,dis_u2_susphy_quirk;
+			tx-fifo-resize;
+			maximum-speed = "super-speed-plus";
+			dr_mode = "otg";
+			usb-role-switch;
+		};
+
+		qcom,usbbam@a704000 {
+			compatible = "qcom,usb-bam-msm";
+			reg = <0xa704000 0x17000>;
+			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+
+			qcom,usb-bam-fifo-baseaddr = <0x146bb000>;
+			qcom,usb-bam-num-pipes = <4>;
+			qcom,disable-clk-gating;
+			qcom,usb-bam-override-threshold = <0x4001>;
+			qcom,usb-bam-max-mbps-highspeed = <400>;
+			qcom,usb-bam-max-mbps-superspeed = <3600>;
+			qcom,reset-bam-on-connect;
+
+			qcom,pipe0 {
+				label = "ssusb-qdss-in-0";
+				qcom,usb-bam-mem-type = <2>;
+				qcom,dir = <1>;
+				qcom,pipe-num = <0>;
+				qcom,peer-bam = <0>;
+				qcom,peer-bam-physical-address = <0x6064000>;
+				qcom,src-bam-pipe-index = <0>;
+				qcom,dst-bam-pipe-index = <0>;
+				qcom,data-fifo-offset = <0x0>;
+				qcom,data-fifo-size = <0x1800>;
+				qcom,descriptor-fifo-offset = <0x1800>;
+				qcom,descriptor-fifo-size = <0x800>;
+			};
+		};
+	};
+
+	/* Primary USB port related High Speed PHY */
+	usb2_phy0: hsphy@88e3000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x88e3000 0x110>,
+			<0x088e2000 0x4>;
+		reg-names = "hsusb_phy_base",
+			"eud_enable_reg";
+
+		vdd-supply = <&pm8150_l5>;
+		vdda18-supply = <&pm8150_l12>;
+		vdda33-supply = <&pm8150_l2>;
+		qcom,vdd-voltage-level = <0 880000 880000>;
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "ref_clk_src";
+
+		resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+		reset-names = "phy_reset";
+		qcom,param-override-seq = <0x43 0x70>;
+	};
+
+	/* Primary USB port related QMP USB DP Combo PHY */
+	usb_qmp_dp_phy: ssphy@88e8000 {
+		compatible = "qcom,usb-ssphy-qmp-dp-combo";
+		reg = <0x88e8000 0x3000>;
+		reg-names = "qmp_phy_base";
+
+		vdd-supply = <&pm8150_l18>;
+		qcom,vdd-voltage-level = <0 912000 912000>;
+		qcom,vdd-max-load-uA = <47000>;
+		core-supply = <&pm8150_l9>;
+		qcom,qmp-phy-init-seq =
+			/* <reg_offset, value, delay> */
+			<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01
+			USB3_DP_QSERDES_COM_SSC_PER1 0x31
+			USB3_DP_QSERDES_COM_SSC_PER2 0x01
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07
+			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A
+			USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36
+			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A
+			USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82
+			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82
+			USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02
+			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24
+			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02
+			USB3_DP_QSERDES_COM_HSCLK_SEL 0x01
+			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x60
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x60
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x11
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x02
+			USB3_DP_QSERDES_TXA_LANE_MODE_1 0xD5
+			USB3_DP_QSERDES_TXA_LANE_MODE_2 0x00
+			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12
+			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x40
+			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x09
+			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F
+			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F
+			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0C
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00
+			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77
+			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04
+			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E
+			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xFF
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7F
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x7F
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x7F
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x97
+			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xDC
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x5C
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x7B
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xB4
+			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04
+			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38
+			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0
+			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C
+			USB3_DP_QSERDES_RXA_GM_CAL 0x1F
+			USB3_DP_QSERDES_RXA_VTH_CODE 0x10
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x60
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x60
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x11
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x02
+			USB3_DP_QSERDES_TXB_LANE_MODE_1 0xD5
+			USB3_DP_QSERDES_TXB_LANE_MODE_2 0x00
+			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12
+			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x54
+			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x09
+			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F
+			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F
+			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0C
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00
+			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77
+			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04
+			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E
+			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x7F
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xFF
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x3F
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x7F
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xA6
+			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xDC
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x5C
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x7B
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xB4
+			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04
+			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38
+			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0
+			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C
+			USB3_DP_QSERDES_RXB_GM_CAL 0x1F
+			USB3_DP_QSERDES_RXB_VTH_CODE 0x10
+			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0
+			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07
+			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20
+			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13
+			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21
+			USB3_DP_PCS_RX_SIGDET_LVL 0xA9
+			USB3_DP_PCS_CDR_RESET_TIME 0x0A
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13
+			USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C
+			USB3_DP_PCS_EQ_CONFIG1 0x4B
+			USB3_DP_PCS_EQ_CONFIG5 0x10
+			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
+			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07>;
+
+		qcom,qmp-phy-reg-offset =
+			<USB3_DP_PCS_PCS_STATUS1
+			 USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL
+			 USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
+			 USB3_DP_PCS_POWER_DOWN_CONTROL
+			 USB3_DP_PCS_SW_RESET
+			 USB3_DP_PCS_START_CONTROL
+			 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
+			 USB3_DP_COM_POWER_DOWN_CTRL
+			 USB3_DP_COM_SW_RESET
+			 USB3_DP_COM_RESET_OVRD_CTRL
+			 USB3_DP_COM_PHY_MODE_CTRL
+			 USB3_DP_COM_TYPEC_CTRL
+			 USB3_DP_PCS_CLAMP_ENABLE>;
+
+		clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+			<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+			<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
+			<&gcc USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK>,
+			<&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+		clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
+				"pipe_clk_ext_src", "ref_clk_src",
+				"com_aux_clk";
+
+		resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+			<&gcc GCC_USB3_PHY_PRIM_BCR>;
+		reset-names = "global_phy_reset", "phy_reset";
+	};
+
+	usb_audio_qmi_dev {
+		compatible = "qcom,usb-audio-qmi-dev";
+		iommus = <&apps_smmu 0x180f 0x0>;
+		qcom,iommu-dma = "disabled";
+		qcom,usb-audio-stream-id = <0xf>;
+		qcom,usb-audio-intr-num = <2>;
+	};
+
+	usb_nop_phy: usb_nop_phy {
+		compatible = "usb-nop-xceiv";
+	};
+
+	/* Secondary USB port related controller */
+	usb1: ssusb@a800000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0xa800000 0x100000>;
+		reg-names = "core_base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		interrupts-extended = <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
+			     <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+			     <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
+			     <&pdc 13 IRQ_TYPE_EDGE_BOTH>;
+		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+				"ss_phy_irq", "dm_hs_phy_irq";
+		qcom,use-pdc-interrupts;
+
+		USB3_GDSC-supply = <&usb30_sec_gdsc>;
+		clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
+		       <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+		       <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+		       <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+		       <&gcc GCC_USB30_SEC_SLEEP_CLK>,
+		       <&gcc GCC_USB3_SEC_CLKREF_EN>;
+
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+				"utmi_clk", "sleep_clk", "xo";
+
+		resets = <&gcc GCC_USB30_SEC_BCR>;
+		reset-names = "core_reset";
+
+		qcom,core-clk-rate = <200000000>;
+		qcom,core-clk-rate-hs = <66666667>;
+		qcom,num-gsi-evt-buffs = <0x3>;
+		qcom,gsi-reg-offset =
+			<0x0fc /* GSI_GENERAL_CFG */
+			 0x110 /* GSI_DBL_ADDR_L */
+			 0x120 /* GSI_DBL_ADDR_H */
+			 0x130 /* GSI_RING_BASE_ADDR_L */
+			 0x144 /* GSI_RING_BASE_ADDR_H */
+			 0x1a4>; /* GSI_IF_STS */
+		qcom,charging-disabled;
+
+		interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
+		interconnects = <&aggre1_noc MASTER_USB3_1 &mc_virt SLAVE_EBI1>,
+				<&aggre1_noc MASTER_USB3_1 &config_noc SLAVE_IPA_CFG>,
+				<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>;
+
+		dwc3@a800000 {
+			compatible = "snps,dwc3";
+			reg = <0xa800000 0xd93c>;
+			iommus = <&apps_smmu 0x20 0x0>;
+			qcom,iommu-dma = "atomic";
+			qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
+
+			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			usb-phy = <&usb2_phy1>, <&usb_qmp_phy>;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x10>;
+			snps,usb3_lpm_capable;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,dis_u2_susphy_quirk;
+			tx-fifo-resize;
+			maximum-speed = "super-speed";
+			dr_mode = "drd";
+		};
+	};
+
+	/* Primary USB port related High Speed PHY */
+	usb2_phy1: hsphy@88e4000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x88e4000 0x110>;
+		reg-names = "hsusb_phy_base";
+
+		vdd-supply = <&pm8150_l5>;
+		vdda18-supply = <&pm8150_l12>;
+		vdda33-supply = <&pm8150_l2>;
+		qcom,vdd-voltage-level = <0 880000 880000>;
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "ref_clk_src";
+
+		resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+		reset-names = "phy_reset";
+		qcom,param-override-seq = <0x43 0x70>;
+	};
+
+	/* Secondary USB port related QMP PHY */
+	usb_qmp_phy: ssphy@88eb000 {
+		compatible = "qcom,usb-ssphy-qmp-v2";
+		reg = <0x88eb000 0x1000>,
+		    <0x088eb88c 0x4>;
+		reg-names = "qmp_phy_base",
+			"pcs_clamp_enable_reg";
+
+		vdd-supply = <&pm8150_l18>;
+		qcom,vdd-voltage-level = <0 912000 912000>;
+		qcom,vdd-max-load-uA = <47000>;
+		core-supply = <&pm8150_l9>;
+		qcom,vbus-valid-override;
+		qcom,qmp-phy-init-seq =
+		    /* <reg_offset, value, delay> */
+		    <USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1a
+		     USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11
+		     USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01
+		     USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82
+		     USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab
+		     USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea
+		     USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02
+		     USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca
+		     USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e
+		     USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x06
+		     USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16
+		     USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36
+		     USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24
+		     USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34
+		     USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14
+		     USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04
+		     USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a
+		     USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02
+		     USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24
+		     USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08
+		     USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82
+		     USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab
+		     USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea
+		     USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02
+		     USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82
+		     USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34
+		     USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06
+		     USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16
+		     USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36
+		     USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca
+		     USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e
+		     USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20
+		     USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01
+		     USB3_UNI_QSERDES_COM_SSC_PER1 0x31
+		     USB3_UNI_QSERDES_COM_SSC_PER2 0x01
+		     USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde
+		     USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07
+		     USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde
+		     USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07
+		     USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02
+		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xb8
+		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xff
+		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xbf
+		     USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7f
+		     USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0x7f
+		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb4
+		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7b
+		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c
+		     USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc
+		     USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc
+		     USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99
+		     USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04
+		     USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08
+		     USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05
+		     USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05
+		     USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2f
+		     USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff
+		     USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f
+		     USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f
+		     USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A
+		     USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54
+		     USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0c
+		     USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f
+		     USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a
+		     USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a
+		     USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x04
+		     USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
+		     USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80
+		     USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04
+		     USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e
+		     USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00
+		     USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0
+		     USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38
+		     USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06
+		     USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c
+		     USB3_UNI_QSERDES_RX_GM_CAL 0x1f
+		     USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12
+		     USB3_UNI_QSERDES_TX_LANE_MODE_1 0xd5
+		     USB3_UNI_QSERDES_TX_LANE_MODE_2 0x82
+		     USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40
+		     USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x11
+		     USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x02
+		     USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0
+		     USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07
+		     USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20
+		     USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13
+		     USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7
+		     USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
+		     USB3_UNI_PCS_RX_SIGDET_LVL 0xa9
+		     USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c
+		     USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07
+		     USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8
+		     USB3_UNI_PCS_CDR_RESET_TIME 0x0a
+		     USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88
+		     USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13
+		     USB3_UNI_PCS_EQ_CONFIG1 0x4b
+		     USB3_UNI_PCS_EQ_CONFIG5 0x10
+		     USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21>;
+
+		qcom,qmp-phy-reg-offset =
+				<USB3_UNI_PCS_PCS_STATUS1
+				 USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
+				 USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
+				 USB3_UNI_PCS_POWER_DOWN_CONTROL
+				 USB3_UNI_PCS_SW_RESET
+				 USB3_UNI_PCS_START_CONTROL>;
+
+		clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
+			 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
+			 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK_SRC>,
+			 <&gcc USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK>,
+			 <&rpmhcc RPMH_CXO_CLK>,
+			 <&gcc GCC_USB3_SEC_CLKREF_EN>,
+			 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
+		clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
+				"pipe_clk_ext_src", "ref_clk_src",
+				"ref_clk", "com_aux_clk";
+
+		resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
+			<&gcc GCC_USB3PHY_PHY_SEC_BCR>;
+		reset-names = "phy_reset", "phy_phy_reset";
+	};
+};
diff --git a/qcom/kona.dtsi b/qcom/kona.dtsi
index 388bedfb..7ea3c798 100755
--- a/qcom/kona.dtsi
+++ b/qcom/kona.dtsi
@@ -1,6 +1,15 @@
+#include <dt-bindings/clock/qcom,gcc-sm8250.h>
+#include <dt-bindings/clock/qcom,videocc-sm8250.h>
+#include <dt-bindings/clock/qcom,camcc-sm8250.h>
+#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
+#include <dt-bindings/clock/qcom,gpucc-sm8250.h>
+#include <dt-bindings/clock/qcom,npucc-sm8250.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/soc/qcom,ipcc.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,kona.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -14,12 +23,19 @@
 	memory { device_type = "memory"; reg = <0 0 0 0>; };
 
 	chosen {
-		bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off";
+		bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off pcie_ports=compat";
 	};
 
 	reserved_memory: reserved-memory { };
 
-	aliases { };
+	aliases {
+		ufshc1 = &ufshc_mem; /* Embedded UFS slot */
+		serial0 = &qupv3_se12_2uart;
+		pci-domain0 = &pcie0; /* PCIe0 domain */
+		pci-domain1 = &pcie1; /* PCIe1 domain */
+		pci-domain2 = &pcie2; /* PCIe2 domain */
+		mmc1 = &sdhc_2; /* SDC2 SD card slot */
+	};
 
 	cpus {
 		#address-cells = <2>;
@@ -32,7 +48,7 @@
 			enable-method = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			next-level-cache = <&L2_0>;
-			qcom,freq-domain = <&cpufreq_hw 0 4>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			#cooling-cells = <2>;
@@ -63,7 +79,7 @@
 			enable-method = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			next-level-cache = <&L2_1>;
-			qcom,freq-domain = <&cpufreq_hw 0 4>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			L2_1: l2-cache {
@@ -88,7 +104,7 @@
 			enable-method = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			next-level-cache = <&L2_2>;
-			qcom,freq-domain = <&cpufreq_hw 0 4>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			L2_2: l2-cache {
@@ -113,7 +129,7 @@
 			enable-method = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			next-level-cache = <&L2_3>;
-			qcom,freq-domain = <&cpufreq_hw 0 4>;
+			qcom,freq-domain = <&cpufreq_hw 0>;
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <100>;
 			L2_3: l2-cache {
@@ -138,7 +154,7 @@
 			enable-method = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			next-level-cache = <&L2_4>;
-			qcom,freq-domain = <&cpufreq_hw 1 4>;
+			qcom,freq-domain = <&cpufreq_hw 1>;
 			capacity-dmips-mhz = <1894>;
 			dynamic-power-coefficient = <514>;
 			#cooling-cells = <2>;
@@ -164,7 +180,7 @@
 			enable-method = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			next-level-cache = <&L2_5>;
-			qcom,freq-domain = <&cpufreq_hw 1 4>;
+			qcom,freq-domain = <&cpufreq_hw 1>;
 			capacity-dmips-mhz = <1894>;
 			dynamic-power-coefficient = <514>;
 			L2_5: l2-cache {
@@ -189,7 +205,7 @@
 			enable-method = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			next-level-cache = <&L2_6>;
-			qcom,freq-domain = <&cpufreq_hw 1 4>;
+			qcom,freq-domain = <&cpufreq_hw 1>;
 			capacity-dmips-mhz = <1894>;
 			dynamic-power-coefficient = <514>;
 			L2_6: l2-cache {
@@ -214,7 +230,7 @@
 			enable-method = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			next-level-cache = <&L2_7>;
-			qcom,freq-domain = <&cpufreq_hw 2 4>;
+			qcom,freq-domain = <&cpufreq_hw 2>;
 			capacity-dmips-mhz = <1894>;
 			dynamic-power-coefficient = <598>;
 			#cooling-cells = <2>;
@@ -306,26 +322,6 @@
 	};
 
 	soc: soc {
-		cpufreq_hw: qcom,cpufreq-hw {
-			compatible = "qcom,cpufreq-epss";
-			reg = <0x18591000 0x1000>, <0x18592000 0x1000>,
-				<0x18593000 0x1000>;
-			reg-names = "freq-domain0", "freq-domain1",
-					"freq-domain2";
-
-			//clocks = <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GPLL0>;
-			//clock-names = "xo", "alternate";
-
-			qcom,lut-row-size = <4>;
-			qcom,skip-enable-check;
-
-			#freq-domain-cells = <2>;
-
-			cpu7_notify: cpu7-notify {
-				qcom,cooling-cpu = <&CPU7>;
-				#cooling-cells = <2>;
-			};
-		};
 	};
 
 	psci {
@@ -555,7 +551,7 @@
 	};
 
 	/* global autoconfigured region for contiguous allocations */
-	linux,cma {
+	system_cma:linux,cma {
 		compatible = "shared-dma-pool";
 		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
 		reusable;
@@ -571,6 +567,14 @@
 		alignment = <0x0 0x400000>;
 		size = <0x0 0x20000>;
 	};
+
+	vendor: vendor {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0 0xffffffff>;
+		compatible = "simple-bus";
+	};
+
 };
 
 &soc {
@@ -579,6 +583,9 @@
 	ranges = <0 0 0 0xffffffff>;
 	compatible = "simple-bus";
 
+	thermal_zones: thermal-zones {
+	};
+
 	intc: interrupt-controller@17a00000 {
 		compatible = "arm,gic-v3";
 		#interrupt-cells = <3>;
@@ -664,6 +671,25 @@
 		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
+	spmi_bus: qcom,spmi@c440000 {
+		compatible = "qcom,spmi-pmic-arb";
+		reg = <0xc440000 0x1100>,
+		      <0xc600000 0x2000000>,
+		      <0xe600000 0x100000>,
+		      <0xe700000 0xa0000>,
+		      <0xc40a000 0x26000>;
+		reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+		interrupt-names = "periph_irq";
+		interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,ee = <0>;
+		qcom,channel = <0>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		interrupt-controller;
+		#interrupt-cells = <4>;
+		cell-index = <0>;
+	};
+
 	apps_rsc: rsc@18200000 {
 		label = "apps_rsc";
 		compatible = "qcom,rpmh-rsc";
@@ -686,6 +712,15 @@
 						  <CONTROL_TCS   0>,
 						  <FAST_PATH_TCS 0>;
 			};
+
+			rpmhcc: clock-controller {
+				compatible = "qcom,sm8250-rpmh-clk";
+				#clock-cells = <1>;
+			};
+
+			apps_bcm_voter: bcm_voter {
+				compatible = "qcom,bcm-voter";
+			};
 		};
 	};
 
@@ -707,6 +742,11 @@
 						  <CONTROL_TCS   0>,
 						  <FAST_PATH_TCS 0>;
 			};
+
+			disp_bcm_voter: bcm_voter {
+				compatible = "qcom,bcm-voter";
+				qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
+			};
 		};
 	};
 
@@ -719,6 +759,814 @@
 		interrupt-controller;
 	};
 
+	clocks {
+		xo_board: xo-board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <38400000>;
+			clock-output-names = "xo_board";
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			clock-output-names = "chip_sleep_clk";
+			#clock-cells = <1>;
+		};
+	};
+
+	gcc: clock-controller@100000 {
+		compatible = "qcom,gcc-sm8250", "syscon";
+		reg = <0x100000 0x1f0000>;
+		reg-names = "cc_base";
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
+		vdd_mm-supply = <&VDD_MMCX_LEVEL>;
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			<&rpmhcc RPMH_CXO_CLK_A>,
+			<&pcie_0_pipe_clk>,
+			<&pcie_1_pipe_clk>,
+			<&pcie_2_pipe_clk>;
+		clock-names = "bi_tcxo",
+			"bi_tcxo_ao",
+			"pcie_0_pipe_clk",
+			"pcie_1_pipe_clk",
+			"pcie_2_pipe_clk";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	npucc: clock-controller@9800000 {
+		compatible = "qcom,sm8250-npucc", "syscon";
+		reg = <0x9800000 0x190000>;
+		reg-name = "cc_base";
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "bi_tcxo";
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	videocc: clock-controller@abf0000 {
+		compatible = "qcom,sm8250-videocc", "syscon";
+		reg = <0xabf0000 0x10000>;
+		reg-names = "cc_base";
+		vdd_mx-supply = <&VDD_MX_LEVEL>;
+		vdd_mm-supply = <&VDD_MMCX_LEVEL>;
+		clock-names = "cfg_ahb_clk";
+		clocks = <&gcc GCC_VIDEO_AHB_CLK>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	camcc: clock-controller@ad00000 {
+		compatible = "qcom,sm8250-camcc", "syscon";
+		reg = <0xad00000 0x10000>;
+		reg-names = "cc_base";
+		vdd_mx-supply = <&VDD_MX_LEVEL>;
+		vdd_mm-supply = <&VDD_MMCX_LEVEL>;
+		clock-names = "cfg_ahb_clk";
+		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	dispcc: clock-controller@af00000 {
+		compatible = "qcom,sm8250-dispcc", "syscon";
+		reg = <0xaf00000 0x20000>;
+		reg-names = "cc_base";
+		vdd_mm-supply = <&VDD_MMCX_LEVEL>;
+		clock-names = "cfg_ahb_clk";
+		clocks = <&gcc GCC_DISP_AHB_CLK>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	gpucc: clock-controller@3d90000 {
+		compatible = "qcom,sm8250-gpucc", "syscon";
+		reg = <0x3d90000 0x9000>;
+		reg-names = "cc_base";
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		vdd_mx-supply = <&VDD_MX_LEVEL>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	apsscc: syscon@182a0000 {
+		compatible = "syscon";
+		reg = <0x182a0000 0x1c>;
+	};
+
+	mccc: syscon@90ba000 {
+		compatible = "syscon";
+		reg = <0x90ba000 0x54>;
+	};
+
+	debugcc: clock-controller@0 {
+		compatible = "qcom,sm8250-debugcc";
+		qcom,apsscc = <&apsscc>;
+		qcom,camcc = <&camcc>;
+		qcom,dispcc = <&dispcc>;
+		qcom,gcc = <&gcc>;
+		qcom,gpucc = <&gpucc>;
+		qcom,npucc = <&npucc>;
+		qcom,videocc = <&videocc>;
+		qcom,mccc = <&mccc>;
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			<&camcc 0>,
+			<&dispcc 0>,
+			<&gcc 0>,
+			<&gpucc 0>,
+			<&npucc 0>,
+			<&videocc 0>;
+		clock-names = "xo_clk_src",
+			"camcc",
+			"dispcc",
+			"gcc",
+			"gpucc",
+			"npucc",
+			"videocc";
+			#clock-cells = <1>;
+	};
+
+	aggre1_noc: interconnect@16E0000 {
+		reg = <0x16E0000 0x1F180>;
+		compatible = "qcom,kona-aggre1_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+		clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>;
+	};
+
+	aggre2_noc: interconnect@1700000 {
+		reg = <0x1700000 0x3D180>;
+		compatible = "qcom,kona-aggre2_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	config_noc: interconnect@1500000 {
+		reg = <0x1500000 0x28000>;
+		compatible = "qcom,kona-config_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	dc_noc: interconnect@90C0000 {
+		reg = <0x90C0000 0x4200>;
+		compatible = "qcom,kona-dc_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	ipa_virt: interconnect@1 {
+		compatible = "qcom,kona-ipa_virt";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	mc_virt: interconnect@2 {
+		compatible = "qcom,kona-mc_virt";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos", "disp";
+		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
+	};
+
+	gem_noc: interconnect@9100000 {
+		reg = <0x9100000 0xB4000>;
+		compatible = "qcom,kona-gem_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos", "disp";
+		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
+	};
+
+	mmss_noc: interconnect@1740000 {
+		reg = <0x1740000 0x1f080>;
+		compatible = "qcom,kona-mmss_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos", "disp";
+		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
+	};
+
+	system_noc: interconnect@1620000 {
+		reg = <0x1620000 0x1C200>;
+		compatible = "qcom,kona-system_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	compute_noc: interconnect@3 {
+		compatible = "qcom,kona-compute_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	npu_noc: interconnect@9990000 {
+		reg = <0x9990000 0x1600>;
+		compatible = "qcom,kona-npu_noc";
+		#interconnect-cells = <1>;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	pcie_0_pipe_clk: pcie_0_pipe_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <1000>;
+		clock-output-names = "pcie_0_pipe_clk";
+		#clock-cells = <0>;
+	};
+
+	pcie_1_pipe_clk: pcie_1_pipe_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <1000>;
+		clock-output-names = "pcie_1_pipe_clk";
+		#clock-cells = <0>;
+	};
+
+	pcie_2_pipe_clk: pcie_2_pipe_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <1000>;
+		clock-output-names = "pcie_2_pipe_clk";
+		#clock-cells = <0>;
+	};
+
+	/* GCC GDSCs */
+	pcie_0_gdsc: qcom,gdsc@16b004 {
+		compatible = "qcom,gdsc";
+		reg = <0x16b004 0x4>;
+		regulator-name = "pcie_0_gdsc";
+		qcom,retain-regs;
+	};
+
+	pcie_1_gdsc: qcom,gdsc@18d004 {
+		compatible = "qcom,gdsc";
+		reg = <0x18d004 0x4>;
+		regulator-name = "pcie_1_gdsc";
+		qcom,retain-regs;
+	};
+
+	pcie_2_gdsc: qcom,gdsc@106004 {
+		compatible = "qcom,gdsc";
+		reg = <0x106004 0x4>;
+		regulator-name = "pcie_2_gdsc";
+		qcom,retain-regs;
+	};
+
+	ufs_phy_gdsc: qcom,gdsc@177004 {
+		compatible = "qcom,gdsc";
+		reg = <0x177004 0x4>;
+		regulator-name = "ufs_phy_gdsc";
+		qcom,retain-regs;
+	};
+
+	usb30_prim_gdsc: qcom,gdsc@10f004 {
+		compatible = "qcom,gdsc";
+		reg = <0x10f004 0x4>;
+		regulator-name = "usb30_prim_gdsc";
+		qcom,retain-regs;
+	};
+
+	usb30_sec_gdsc: qcom,gdsc@110004 {
+		compatible = "qcom,gdsc";
+		reg = <0x110004 0x4>;
+		regulator-name = "usb30_sec_gdsc";
+		qcom,retain-regs;
+	};
+
+	hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
+		compatible = "qcom,gdsc";
+		reg = <0x17d050 0x4>;
+		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
+		qcom,no-status-check-on-disable;
+		qcom,gds-timeout = <500>;
+	};
+
+	hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {
+		compatible = "qcom,gdsc";
+		reg = <0x17d058 0x4>;
+		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
+		qcom,no-status-check-on-disable;
+		qcom,gds-timeout = <500>;
+	};
+
+	hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 {
+		compatible = "qcom,gdsc";
+		reg = <0x17d054 0x4>;
+		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc";
+		qcom,no-status-check-on-disable;
+		qcom,gds-timeout = <500>;
+	};
+
+	hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc: qcom,gdsc@17d06c {
+		compatible = "qcom,gdsc";
+		reg = <0x17d06c 0x4>;
+		regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc";
+		qcom,no-status-check-on-disable;
+		qcom,gds-timeout = <500>;
+	};
+
+	/* CAM_CC GDSCs */
+	bps_gdsc: qcom,gdsc@ad07004 {
+		compatible = "qcom,gdsc";
+		reg = <0xad07004 0x4>;
+		regulator-name = "bps_gdsc";
+		clock-names = "ahb_clk";
+		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+		parent-supply = <&VDD_MMCX_LEVEL>;
+		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+		qcom,support-hw-trigger;
+		qcom,retain-regs;
+	};
+
+	ife_0_gdsc: qcom,gdsc@ad0a004 {
+		compatible = "qcom,gdsc";
+		reg = <0xad0a004 0x4>;
+		regulator-name = "ife_0_gdsc";
+		clock-names = "ahb_clk";
+		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+		parent-supply = <&VDD_MMCX_LEVEL>;
+		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+		qcom,retain-regs;
+	};
+
+	ife_1_gdsc: qcom,gdsc@ad0b004 {
+		compatible = "qcom,gdsc";
+		reg = <0xad0b004 0x4>;
+		regulator-name = "ife_1_gdsc";
+		clock-names = "ahb_clk";
+		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+		parent-supply = <&VDD_MMCX_LEVEL>;
+		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+		qcom,retain-regs;
+	};
+
+	ipe_0_gdsc: qcom,gdsc@ad08004 {
+		compatible = "qcom,gdsc";
+		reg = <0xad08004 0x4>;
+		regulator-name = "ipe_0_gdsc";
+		clock-names = "ahb_clk";
+		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+		parent-supply = <&VDD_MMCX_LEVEL>;
+		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+		qcom,support-hw-trigger;
+		qcom,retain-regs;
+	};
+
+	sbi_gdsc: qcom,gdsc@ad09004 {
+		compatible = "qcom,gdsc";
+		reg = <0xad09004 0x4>;
+		regulator-name = "sbi_gdsc";
+		clock-names = "ahb_clk";
+		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+		parent-supply = <&VDD_MMCX_LEVEL>;
+		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+		qcom,retain-regs;
+	};
+
+	titan_top_gdsc: qcom,gdsc@ad0c144 {
+		compatible = "qcom,gdsc";
+		reg = <0xad0c144 0x4>;
+		regulator-name = "titan_top_gdsc";
+		clock-names = "ahb_clk";
+		clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+		parent-supply = <&VDD_MMCX_LEVEL>;
+		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+		qcom,retain-regs;
+		qcom,gds-timeout = <500>;
+	};
+
+	/* DISP_CC GDSC */
+	mdss_core_gdsc: qcom,gdsc@af03000 {
+		compatible = "qcom,gdsc";
+		reg = <0xaf03000 0x4>;
+		regulator-name = "mdss_core_gdsc";
+		clock-names = "ahb_clk";
+		clocks = <&gcc GCC_DISP_AHB_CLK>;
+		parent-supply = <&VDD_MMCX_LEVEL>;
+		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+		qcom,support-hw-trigger;
+		qcom,retain-regs;
+		proxy-supply = <&mdss_core_gdsc>;
+		qcom,proxy-consumer-enable;
+	};
+
+	/* GPU_CC GDSCs */
+	gpu_cx_hw_ctrl: syscon@3d91540 {
+		compatible = "syscon";
+		reg = <0x3d91540 0x4>;
+	};
+
+	gpu_cx_gdsc: qcom,gdsc@3d9106c {
+		compatible = "qcom,gdsc";
+		reg = <0x3d9106c 0x4>;
+		regulator-name = "gpu_cx_gdsc";
+		hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
+		parent-supply = <&VDD_CX_LEVEL>;
+		vdd_parent-supply = <&VDD_CX_LEVEL>;
+		qcom,no-status-check-on-disable;
+		qcom,clk-dis-wait-val = <8>;
+		qcom,gds-timeout = <500>;
+		qcom,retain-regs;
+	};
+
+	gpu_gx_domain_addr: syscon@3d91508 {
+		compatible = "syscon";
+		reg = <0x3d91508 0x4>;
+	};
+
+	gpu_gx_sw_reset: syscon@3d91008 {
+		compatible = "syscon";
+		reg = <0x3d91008 0x4>;
+	};
+
+	gpu_gx_gdsc: qcom,gdsc@3d9100c {
+		compatible = "qcom,gdsc";
+		reg = <0x3d9100c 0x4>;
+		regulator-name = "gpu_gx_gdsc";
+		domain-addr = <&gpu_gx_domain_addr>;
+		sw-reset = <&gpu_gx_sw_reset>;
+		parent-supply = <&VDD_GFX_LEVEL>;
+		vdd_parent-supply = <&VDD_GFX_LEVEL>;
+		qcom,skip-disable-before-sw-enable;
+		qcom,reset-aon-logic;
+		qcom,retain-regs;
+	};
+
+	/* NPU GDSC */
+	npu_core_gdsc: qcom,gdsc@9981004 {
+		compatible = "qcom,gdsc";
+		reg = <0x9981004 0x4>;
+		regulator-name = "npu_core_gdsc";
+		clock-names = "ahb_clk";
+		clocks = <&gcc GCC_NPU_CFG_AHB_CLK>;
+		qcom,retain-regs;
+	};
+
+	qcom,sps {
+		compatible = "qcom,msm-sps-4k";
+		qcom,pipe-attr-ee;
+	};
+
+	/* VIDEO_CC GDSCs */
+	mvs0_gdsc: qcom,gdsc@abf0d18 {
+		compatible = "qcom,gdsc";
+		reg = <0xabf0d18 0x4>;
+		regulator-name = "mvs0_gdsc";
+		clock-names = "ahb_clk";
+		clocks = <&gcc GCC_VIDEO_AHB_CLK>;
+		parent-supply = <&VDD_MMCX_LEVEL>;
+		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+		qcom,support-hw-trigger;
+		qcom,retain-regs;
+	};
+
+	mvs0c_gdsc: qcom,gdsc@abf0bf8 {
+		compatible = "qcom,gdsc";
+		reg = <0xabf0bf8 0x4>;
+		regulator-name = "mvs0c_gdsc";
+		clock-names = "ahb_clk";
+		clocks = <&gcc GCC_VIDEO_AHB_CLK>;
+		parent-supply = <&VDD_MMCX_LEVEL>;
+		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+		qcom,retain-regs;
+	};
+
+	mvs1_gdsc: qcom,gdsc@abf0d98 {
+		compatible = "qcom,gdsc";
+		reg = <0xabf0d98 0x4>;
+		regulator-name = "mvs1_gdsc";
+		clock-names = "ahb_clk";
+		clocks = <&gcc GCC_VIDEO_AHB_CLK>;
+		parent-supply = <&VDD_MMCX_LEVEL>;
+		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+		qcom,support-hw-trigger;
+		qcom,retain-regs;
+	};
+
+	mvs1c_gdsc: qcom,gdsc@abf0c98 {
+		compatible = "qcom,gdsc";
+		reg = <0xabf0c98 0x4>;
+		regulator-name = "mvs1c_gdsc";
+		clock-names = "ahb_clk";
+		clocks = <&gcc GCC_VIDEO_AHB_CLK>;
+		parent-supply = <&VDD_MMCX_LEVEL>;
+		vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+		qcom,retain-regs;
+	};
+
+	cpufreq_hw: qcom,cpufreq-hw {
+		compatible = "qcom,cpufreq-epss";
+		reg = <0x18591000 0x1000>, <0x18592000 0x1000>,
+			<0x18593000 0x1000>;
+		reg-names = "freq-domain0", "freq-domain1",
+				"freq-domain2";
+		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+		clock-names = "xo", "alternate";
+		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int";
+		#freq-domain-cells = <1>;
+
+		cpu7_notify: cpu7-notify {
+			qcom,cooling-cpu = <&CPU7>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	llcc_pmu: llcc-pmu@9095000 {
+		compatible = "qcom,llcc-pmu-ver2";
+		reg = <0x09095000 0x300>;
+		reg-names = "lagg-base";
+	};
+
+	qcom_pmu: qcom,pmu {
+		compatible = "qcom,pmu";
+		qcom,long-counter;
+		qcom,pmu-events-tbl =
+			< 0x0008 0xFF 0xFF 0xFF >,
+			< 0x0011 0xFF 0xFF 0xFF >,
+			< 0x0017 0xFF 0xFF 0xFF >,
+			< 0x002A 0xFF 0xFF 0xFF >;
+	};
+
+	ddr_freq_table: ddr-freq-table {
+		qcom,freq-tbl =
+			<  200000 >,
+			<  300000 >,
+			<  451000 >,
+			<  547000 >,
+			<  681000 >,
+			<  768000 >,
+			< 1017000 >,
+			< 1353000 >,
+			< 1555000 >,
+			< 1804000 >,
+			< 2092000 >,
+			< 2736000 >;
+	};
+
+	llcc_freq_table: llcc-freq-table {
+		qcom,freq-tbl =
+			<  150000 >,
+			<  300000 >,
+			<  466000 >,
+			<  600000 >,
+			<  806000 >,
+			<  933000 >,
+			< 1000000 >;
+	};
+
+	ddrqos_freq_table: ddrqos-freq-table {
+		qcom,freq-tbl =
+			< 0 >,
+			< 1 >;
+	};
+
+	qcom_dcvs: qcom,dcvs {
+		compatible = "qcom,dcvs";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		qcom_l3_dcvs_hw: l3 {
+			compatible = "qcom,dcvs-hw";
+			qcom,dcvs-hw-type = <2>;
+			qcom,bus-width = <32>;
+			reg = <0x18590000 0x4>, <0x18590100 0xa0>;
+			reg-names = "l3-base", "l3tbl-base";
+
+			l3_dcvs_sp: sp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <0>;
+				qcom,shared-offset = <0x0090>;
+			};
+		};
+
+		qcom_ddr_dcvs_hw: ddr {
+			compatible = "qcom,dcvs-hw";
+			qcom,dcvs-hw-type = <0>;
+			qcom,bus-width = <4>;
+			qcom,freq-tbl = <&ddr_freq_table>;
+
+			ddr_dcvs_sp: sp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <0>;
+				interconnects = <&mc_virt MASTER_LLCC
+						&mc_virt SLAVE_EBI1>;
+			};
+		};
+
+		qcom_llcc_dcvs_hw: llcc {
+			compatible = "qcom,dcvs-hw";
+			qcom,dcvs-hw-type = <1>;
+			qcom,bus-width = <16>;
+			qcom,freq-tbl = <&llcc_freq_table>;
+
+			llcc_dcvs_sp: sp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <0>;
+				interconnects = <&gem_noc MASTER_APPSS_PROC
+						 &gem_noc SLAVE_LLCC>;
+			};
+		};
+
+		qcom_ddrqos_dcvs_hw: ddrqos {
+			compatible = "qcom,dcvs-hw";
+			qcom,dcvs-hw-type = <3>;
+			qcom,bus-width = <1>;
+			qcom,freq-tbl = <&ddrqos_freq_table>;
+
+			ddrqos_dcvs_sp: sp {
+				compatible = "qcom,dcvs-path";
+				qcom,dcvs-path-type = <0>;
+				interconnects = <&mc_virt MASTER_LLCC
+						 &mc_virt SLAVE_EBI1>;
+			};
+		};
+	};
+
+	qcom_memlat: qcom,memlat {
+		compatible = "qcom,memlat";
+
+		ddr {
+			compatible = "qcom,memlat-grp";
+			qcom,target-dev = <&qcom_ddr_dcvs_hw>;
+			qcom,sampling-path = <&ddr_dcvs_sp>;
+			qcom,miss-ev = <0x2A>;
+
+			silver {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+				qcom,sampling-enabled;
+				qcom,cpufreq-memfreq-tbl =
+					<  300000  200000 >,
+					<  729600  451000 >,
+					< 1132800  547000 >,
+					< 1497600  768000 >,
+					< 1670400 1017000 >;
+			};
+
+			gold {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
+				qcom,sampling-enabled;
+				qcom,cpufreq-memfreq-tbl =
+					<  300000  200000 >,
+					<  691200  451000 >,
+					<  806400  547000 >,
+					< 1017600  768000 >,
+					< 1228800 1017000 >,
+					< 1574400 1353000 >,
+					< 1804800 1555000 >,
+					< 2227200 1804000 >,
+					< 2380800 2094000 >;
+			};
+
+			gold-compute {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
+				qcom,sampling-enabled;
+				qcom,compute-mon;
+				qcom,cpufreq-memfreq-tbl =
+					< 1804800  200000 >,
+					< 2380800 1017000 >,
+					< 2500000 2092000 >;
+			};
+		};
+
+		llcc {
+			compatible = "qcom,memlat-grp";
+			qcom,target-dev = <&qcom_llcc_dcvs_hw>;
+			qcom,sampling-path = <&llcc_dcvs_sp>;
+			qcom,miss-ev = <0x2A>;
+
+			silver {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+				qcom,sampling-enabled;
+				qcom,cpufreq-memfreq-tbl =
+					<  300000  150000 >,
+					<  729600  300000 >,
+					< 1497600  466000 >,
+					< 1670400  600000 >;
+			};
+
+			gold {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
+				qcom,sampling-enabled;
+				qcom,cpufreq-memfreq-tbl =
+					<  300000  150000 >,
+					<  691200  300000 >,
+					< 1017600  466000 >,
+					< 1228800  600000 >,
+					< 1804800  806000 >,
+					< 2227200  933000 >,
+					< 2476800 1000000 >;
+			};
+		};
+
+		l3 {
+			compatible = "qcom,memlat-grp";
+			qcom,target-dev = <&qcom_l3_dcvs_hw>;
+			qcom,sampling-path = <&l3_dcvs_sp>;
+			qcom,miss-ev = <0x17>;
+
+			silver {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+				qcom,sampling-enabled;
+				qcom,cpufreq-memfreq-tbl =
+					<  300000  300000 >,
+					<  403200  403200 >,
+					<  518400  518400 >,
+					<  633600  614400 >,
+					<  825600  729600 >,
+					<  921600  825600 >,
+					< 1036800  921600 >,
+					< 1132800 1036800 >,
+					< 1228800 1132800 >,
+					< 1401600 1228800 >,
+					< 1497600 1305600 >,
+					< 1670400 1382400 >;
+			};
+
+			gold {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
+				qcom,sampling-enabled;
+				qcom,cpufreq-memfreq-tbl =
+					<  300000  300000 >,
+					<  806400  614400 >,
+					< 1017600  729600 >,
+					< 1228800  921600 >,
+					< 1689600 1228800 >,
+					< 1804800 1305600 >,
+					< 2227200 1382400 >;
+			};
+
+			prime {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU7>;
+				qcom,sampling-enabled;
+				qcom,cpufreq-memfreq-tbl =
+					<  300000  300000 >,
+					<  806400  614400 >,
+					< 1017600  729600 >,
+					< 1228800  921600 >,
+					< 1689600 1228800 >,
+					< 1804800 1305600 >,
+					< 2227200 1382400 >;
+			};
+		};
+
+		ddrqos {
+			compatible = "qcom,memlat-grp";
+			qcom,target-dev = <&qcom_ddrqos_dcvs_hw>;
+			qcom,sampling-path = <&ddrqos_dcvs_sp>;
+			qcom,miss-ev = <0x2A>;
+
+			ddrqos_gold_lat: gold {
+				compatible = "qcom,memlat-mon";
+				qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
+				qcom,sampling-enabled;
+				qcom,cpufreq-memfreq-tbl =
+					<  300000 1 >,
+					< 3000000 2 >;
+			};
+		};
+	};
+
+	bwmon_llcc: qcom,bwmon-llcc@90b6400 {
+		compatible = "qcom,bwmon4";
+		reg = <0x90b6400 0x300>, <0x90b6300 0x200>;
+		reg-names = "base", "global_base";
+		interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,mport = <0>;
+		qcom,hw-timer-hz = <19200000>;
+		qcom,count-unit = <0x10000>;
+		qcom,target-dev = <&qcom_llcc_dcvs_hw>;
+	};
+
+	bwmon_ddr: qcom,bwmon-ddr@9091000 {
+		compatible = "qcom,bwmon5";
+		reg = <0x9091000 0x1000>;
+		reg-names = "base";
+		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,hw-timer-hz = <19200000>;
+		qcom,count-unit = <0x10000>;
+		qcom,target-dev = <&qcom_ddr_dcvs_hw>;
+	};
+
 	qcom,chd_silver {
 		compatible = "qcom,core-hang-detect";
 		label = "silver";
@@ -738,12 +1586,216 @@
 	};
 
 	cache-controller@9200000 {
-		//compatible = "qcom,kona-llcc";
+		compatible = "qcom,kona-llcc";
 		reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;
 		reg-names = "llcc_base", "llcc_broadcast_base";
 		cap-based-alloc-and-pwr-collapse;
 	};
 
+	ufsphy_mem: ufsphy_mem@1d87000 {
+		reg = <0x1d87000 0xe00>; /* PHY regs */
+		reg-names = "phy_mem";
+		#phy-cells = <0>;
+
+		lanes-per-direction = <2>;
+
+		clock-names = "ref_clk_src",
+			"ref_aux_clk";
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+
+		resets = <&ufshc_mem 0>;
+		status = "disabled";
+	};
+
+	ufshc_mem: ufshc@1d84000 {
+		compatible = "qcom,ufshc";
+		reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>;
+		reg-names = "ufs_mem", "ufs_ice";
+		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+		phys = <&ufsphy_mem>;
+		phy-names = "ufsphy";
+		#reset-cells = <1>;
+
+		lanes-per-direction = <2>;
+		dev-ref-clk-freq = <0>; /* 19.2 MHz */
+
+		clock-names =
+			"core_clk",
+			"bus_aggr_clk",
+			"iface_clk",
+			"core_clk_unipro",
+			"core_clk_ice",
+			"ref_clk",
+			"tx_lane0_sync_clk",
+			"rx_lane0_sync_clk",
+			"rx_lane1_sync_clk";
+		clocks =
+			<&gcc GCC_UFS_PHY_AXI_CLK>,
+			<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+			<&gcc GCC_UFS_PHY_AHB_CLK>,
+			<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+			<&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+			<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+		freq-table-hz =
+			<37500000 300000000>,
+			<0 0>,
+			<0 0>,
+			<37500000 300000000>,
+			<37500000 300000000>,
+			<0 0>,
+			<0 0>,
+			<0 0>,
+			<0 0>;
+		interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
+		interconnect-names = "ufs-ddr", "cpu-ufs";
+
+		qcom,ufs-bus-bw,name = "ufshc_mem";
+		qcom,ufs-bus-bw,num-cases = <26>;
+		qcom,ufs-bus-bw,num-paths = <2>;
+		qcom,ufs-bus-bw,vectors-KBps =
+		/*
+		 * During HS G3 UFS runs at nominal voltage corner, vote
+		 * higher bandwidth to push other buses in the data path
+		 * to run at nominal to achieve max throughput.
+		 * 4GBps pushes BIMC to run at nominal.
+		 * 200MBps pushes CNOC to run at nominal.
+		 * Vote for half of this bandwidth for HS G3 1-lane.
+		 * For max bandwidth, vote high enough to push the buses
+		 * to run in turbo voltage corner.
+		 */
+		<0 0>, <0 0>,          /* No vote */
+		<922 0>, <1000 0>,     /* PWM G1 */
+		<1844 0>, <1000 0>,    /* PWM G2 */
+		<3688 0>, <1000 0>,    /* PWM G3 */
+		<7376 0>, <1000 0>,    /* PWM G4 */
+		<1844 0>, <1000 0>,    /* PWM G1 L2 */
+		<3688 0>, <1000 0>,    /* PWM G2 L2 */
+		<7376 0>, <1000 0>,    /* PWM G3 L2 */
+		<14752 0>, <1000 0>,   /* PWM G4 L2 */
+		<127796 0>, <1000 0>,  /* HS G1 RA */
+		<255591 0>, <1000 0>,  /* HS G2 RA */
+		<2097152 0>, <102400 0>,  /* HS G3 RA */
+		<4194304 0>, <204800 0>,  /* HS G4 RA */
+		<255591 0>, <1000 0>,  /* HS G1 RA L2 */
+		<511181 0>, <1000 0>,  /* HS G2 RA L2 */
+		<4194304 0>, <204800 0>, /* HS G3 RA L2 */
+		<8388608 0>, <409600 0>, /* HS G4 RA L2 */
+		<149422 0>, <1000 0>,  /* HS G1 RB */
+		<298189 0>, <1000 0>,  /* HS G2 RB */
+		<2097152 0>, <102400 0>,  /* HS G3 RB */
+		<4194304 0>, <204800 0>,  /* HS G4 RB */
+		<298189 0>, <1000 0>,  /* HS G1 RB L2 */
+		<596378 0>, <1000 0>,  /* HS G2 RB L2 */
+		/* As UFS working in HS G3 RB L2 mode, aggregated
+		 * bandwidth (AB) should take care of providing
+		 * optimum throughput requested. However, as tested,
+		 * in order to scale up CNOC clock, instantaneous
+		 * bindwidth (IB) needs to be given a proper value too.
+		 */
+		<4194304 0>, <204800 409600>, /* HS G3 RB L2 */
+		<8388608 0>, <409600 409600>, /* HS G4 RB L2 */
+		<7643136 0>, <307200 0>; /* Max. bandwidth */
+
+		qcom,bus-vector-names = "MIN",
+		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
+		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
+		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
+		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
+		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
+		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
+		"MAX";
+		reset-gpios = <&tlmm 180 GPIO_ACTIVE_LOW>;
+
+		resets = <&gcc GCC_UFS_PHY_BCR>;
+		reset-names = "rst";
+		iommus = <&apps_smmu 0xE0 0x0>;
+		qcom,iommu-dma = "bypass";
+
+		status = "disabled";
+
+		qos0 {
+			mask = <0x0f>;
+			vote = <44>;
+		};
+
+		qos1 {
+			mask = <0xf0>;
+			vote = <44>;
+		};
+	};
+
+	qcom,rmtfs_sharedmem@0 {
+		compatible = "qcom,sharedmem-uio";
+		reg = <0x0 0x280000>;
+		reg-names = "rmtfs";
+		qcom,client-id = <0x00000001>;
+	};
+
+	sdhc2_opp_table: sdhc2-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-100000000 {
+			opp-hz = /bits/ 64 <100000000>;
+			opp-peak-kBps = <1600000 280000>;
+			opp-avg-kBps = <50000 0>;
+		};
+
+		opp-202000000 {
+			opp-hz = /bits/ 64 <202000000>;
+			opp-peak-kBps = <5600000 1500000>;
+			opp-avg-kBps = <104000 0>;
+		};
+	};
+
+	sdhc_2: sdhci@8804000 {
+		compatible = "qcom,sdhci-msm-v5";
+		reg = <0x8804000 0x1000>;
+		reg-names = "hc";
+
+		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hc_irq", "pwr_irq";
+
+		clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+			<&gcc GCC_SDCC2_APPS_CLK>;
+		clock-names = "iface", "core";
+
+		bus-width = <4>;
+		no-sdio;
+		no-mmc;
+		qcom,restore-after-cx-collapse;
+
+		iommus = <&apps_smmu 0x4A0 0x0>;
+		qcom,iommu-dma = "fastmap";
+		dma-coherent;
+
+		interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
+		interconnect-names = "sdhc-ddr","cpu-sdhc";
+		operating-points-v2 = <&sdhc2_opp_table>;
+
+		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+		qcom,dll-hsr-list = <0x0007642C 0xA800 0x10
+					0x2C010800 0x80040868>;
+
+		status = "disabled";
+
+		qos0 {
+			mask = <0x3f>;
+			vote = <44>;
+		};
+
+		qos1 {
+			mask = <0xc0>;
+			vote = <44>;
+		};
+	};
+
 	wdog: qcom,wdt@17c10000 {
 		compatible = "qcom,msm-watchdog";
 		reg = <0x17c10000 0x1000>;
@@ -809,6 +1861,11 @@
 		compatible = "qcom,secure-buffer";
 	};
 
+	mini_dump_mode {
+		compatible = "qcom,minidump";
+		status = "ok";
+	};
+
 	mem_dump {
 		compatible = "qcom,mem-dump";
 		memory-region = <&dump_mem>;
@@ -1149,7 +2206,54 @@
 		};
 	};
 
+	tsens0: tsens@c222000 {
+		compatible = "qcom,tsens24xx";
+		reg = <0xc222000 0x4>,
+			<0xc263000 0x1ff>;
+		reg-names = "tsens_srot_physical",
+				"tsens_tm_physical";
+		interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "tsens-upper-lower", "tsens-critical";
+		tsens-reinit-wa;
+		#thermal-sensor-cells = <1>;
+	};
+
+	tsens1: tsens@c223000 {
+		compatible = "qcom,tsens24xx";
+		reg = <0xc223000 0x4>,
+			<0xc265000 0x1ff>;
+		reg-names = "tsens_srot_physical",
+			"tsens_tm_physical";
+		interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "tsens-upper-lower", "tsens-critical";
+		tsens-reinit-wa;
+		#thermal-sensor-cells = <1>;
+	};
+
+	eud: qcom,msm-eud@88e0000 {
+		compatible = "qcom,msm-eud";
+		interrupt-names = "eud_irq";
+		interrupt-parent = <&pdc>;
+		interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x088E0000 0x2000>,
+			<0x088E2000 0x1000>;
+		reg-names = "eud_base", "eud_mode_mgr2";
+		qcom,secure-eud-en;
+		qcom,eud-clock-vote-req;
+		clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_BCR>;
+		clock-names = "eud_ahb2phy_clk";
+		status = "ok";
+	};
 };
 
+#include "kona-usb.dtsi"
 #include "kona-regulators.dtsi"
+#include "kona-pmic-overlay.dtsi"
+#include "kona-thermal.dtsi"
 #include "kona-pinctrl.dtsi"
+#include "msm-arm-smmu-kona.dtsi"
+#include "kona-dma-heaps.dtsi"
+#include "kona-qupv3.dtsi"
+#include "kona-pcie.dtsi"
diff --git a/qcom/lemans-4pmic-regulators.dtsi b/qcom/lemans-4pmic-regulators.dtsi
index 2da37d95..520d5624 100755
--- a/qcom/lemans-4pmic-regulators.dtsi
+++ b/qcom/lemans-4pmic-regulators.dtsi
@@ -410,9 +410,8 @@
 			qcom,set = <RPMH_REGULATOR_SET_ALL>;
 			regulator-min-microvolt = <2400000>;
 			regulator-max-microvolt = <3300000>;
-			qcom,init-voltage = <2960000>;
 			qcom,init-mode =
-				<RPMH_REGULATOR_MODE_LPM>;
+				<RPMH_REGULATOR_MODE_HPM>;
 		};
 	};
 
diff --git a/qcom/lemans-adp-air.dtsi b/qcom/lemans-adp-air.dtsi
index 689bf563..d14e1d28 100755
--- a/qcom/lemans-adp-air.dtsi
+++ b/qcom/lemans-adp-air.dtsi
@@ -1 +1,5 @@
 #include  "lemans-adp-common.dtsi"
+
+&cdsp1_pas {
+	status = "disabled";
+};
diff --git a/qcom/lemans-adp-common.dtsi b/qcom/lemans-adp-common.dtsi
index 3316447c..12115d7c 100755
--- a/qcom/lemans-adp-common.dtsi
+++ b/qcom/lemans-adp-common.dtsi
@@ -1,4 +1,5 @@
 #include "lemans-pmic-overlay.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. Lemans ADP";
@@ -7,4 +8,127 @@
 };
 
 &soc {
+	/* PWR_CTR1_VDD_PA supply */
+	vreg_conn_pa: vreg_conn_pa {
+		compatible = "regulator-fixed";
+		regulator-name = "vreg_conn_pa";
+		startup-delay-us = <4000>;
+		enable-active-high;
+		gpio = <&pm8775_2_gpios 6 0>;
+	};
+
+};
+
+&pm8775_1_adc {
+	pm8775_1_xo_therm {
+		reg = <PM8775_1_ADC5_GEN3_AMUX1_THM_100K_PU>;
+		label = "pm8775_1_xo_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <700>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm8775_1_ufs0_therm {
+		reg = <PM8775_1_ADC5_GEN3_AMUX5_THM_100K_PU>;
+		label = "pm8775_1_ufs0_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pm8775_1_soc_therm {
+		reg = <PM8775_1_ADC5_GEN3_AMUX6_THM_100K_PU>;
+		label = "pm8775_1_soc_therm";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+};
+
+&pm8775_3_adc {
+	pm8775_3_sdram_therm1 {
+		reg = <PM8775_3_ADC5_GEN3_AMUX6_THM_100K_PU>;
+		label = "pm8775_3_sdram_therm1";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+};
+
+&pcie1 {
+	qcom,boot-option = <0x0>;
+};
+
+&pcie1_rp {
+	nvme_x8 {
+		reg = <0 0 0 0 0>;
+		pci-ids =
+			"8086:0953",
+			"8086:0a54",
+			"8086:0a55",
+			"8086:f1a5",
+			"8086:f1a5",
+			"1c58:0003",
+			"1c58:0023",
+			"1c5c:1327",
+			"1c5f:0540",
+			"144d:a821",
+			"144d:a822",
+			"144d:a808",
+			"1d1d:1f1f",
+			"1d1d:2807",
+			"1d1d:2601",
+			"106b:2001",
+			"106b:2003",
+			"1179:0115",
+			"1179:0116";
+	};
+};
+
+&pm8775_3_gpios {
+	usb201_vbus_boost {
+		usb20_vbus_boost_default: usb20_vbus_boost_default {
+			pins = "gpio3";
+			function = "normal";
+			output-high;
+			power-source = <0>;
+		};
+
+		usb21_vbus_boost_default: usb21_vbus_boost_default {
+			pins = "gpio10";
+			function = "normal";
+			output-high;
+			power-source = <0>;
+		};
+	};
+};
+
+&pm8775_2_gpios {
+	usb22_vbus_boost {
+		usb22_vbus_boost_default: usb22_vbus_boost_default {
+			pins = "gpio9";
+			function = "normal";
+			output-high;
+			power-source = <0>;
+		};
+	};
+};
+
+&usb0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb20_vbus_boost_default>;
+};
+
+&usb1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb21_vbus_boost_default>;
+};
+
+&usb2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb22_vbus_boost_default>;
+};
+
+&ethqos_hw {
+	snps,reset-gpios = <&pm8775_3_gpios 8 GPIO_ACTIVE_HIGH>;
 };
diff --git a/qcom/lemans-adp-star.dtsi b/qcom/lemans-adp-star.dtsi
index 689bf563..d14e1d28 100755
--- a/qcom/lemans-adp-star.dtsi
+++ b/qcom/lemans-adp-star.dtsi
@@ -1 +1,5 @@
 #include  "lemans-adp-common.dtsi"
+
+&cdsp1_pas {
+	status = "disabled";
+};
diff --git a/qcom/lemans-coresight.dtsi b/qcom/lemans-coresight.dtsi
new file mode 100755
index 00000000..0e368640
--- /dev/null
+++ b/qcom/lemans-coresight.dtsi
@@ -0,0 +1,988 @@
+&soc {
+	stm: stm@04002000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb962>;
+		reg = <0x04002000 0x1000>,
+			<0x16280000 0x180000>;
+		reg-names = "stm-base", "stm-stimulus-base";
+
+		atid = <16>;
+		coresight-name = "coresight-stm";
+
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				stm_out_funnel_in0: endpoint {
+					remote-endpoint =
+					<&funnel_in0_in_stm>;
+				};
+			};
+		};
+	};
+
+	tpdm_dcc: tpdm@0x4003000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x4003000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <65>;
+		coresight-name = "coresight-tpdm-dcc";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+		qcom,hw-enable-check;
+
+		out-ports {
+			port {
+				tpdm_dcc_out_tpda_qdss_0: endpoint {
+					remote-endpoint =
+					<&tpda_qdss_0_in_tpdm_dcc>;
+				};
+			};
+		};
+	};
+
+	tpdm_llm_silver: tpdm@068a0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x068a0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <66>;
+		coresight-name = "coresight-tpdm-llm-silver";
+
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_llm_silver_out_tpda_apss_0: endpoint {
+					remote-endpoint =
+					<&tpda_apss_0_in_tpdm_llm_silver>;
+				};
+			};
+		};
+	};
+
+	tpdm_llm_gold: tpdm@068b0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x068b0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <66>;
+		coresight-name = "coresight-tpdm-llm-gold";
+
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_llm_gold_out_tpda_apss_1: endpoint {
+					remote-endpoint =
+					<&tpda_apss_1_in_tpdm_llm_gold>;
+				};
+			};
+		};
+	};
+
+	tpdm_apss_llm: tpdm@068c0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x068c0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <66>;
+		coresight-name = "coresight-tpdm-apss-llm";
+
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_apss_llm_out_tpda_apss_2: endpoint {
+					remote-endpoint =
+					<&tpda_apss_2_in_tpdm_apss_llm>;
+				};
+			};
+		};
+	};
+
+	tpdm_actpm: tpdm@06860000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x06860000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <66>;
+		coresight-name = "coresight-tpdm-actpm";
+
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_apss0_out_tpda_apss_3: endpoint {
+					remote-endpoint =
+					<&tpda_apss_3_in_tpdm_apss0>;
+				};
+			};
+		};
+	};
+
+	tpdm_apss: tpdm@06861000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb968>;
+		reg = <0x06861000 0x1000>;
+		reg-names = "tpdm-base";
+
+		atid = <66>;
+		coresight-name = "coresight-tpdm-apss";
+
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_apps1_out_tpda_apss_4: endpoint {
+					remote-endpoint =
+					<&tpda_apss_4_in_tpdm_apps1>;
+				};
+			};
+		};
+	};
+
+	tpda_apss: tpda@06863000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+
+		reg = <0x06863000 0x1000>;
+		reg-names = "tpda-base";
+
+		qcom,tpda-atid = <66>;
+
+		qcom,dsb-elem-size = <2 32>,
+					<4 32>;
+		qcom,cmb-elem-size = <0 32>,
+				     <1 32>,
+				     <3 64>;
+
+		coresight-name = "coresight-tpda-apss";
+
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tpda_apss_0_in_tpdm_llm_silver: endpoint {
+					remote-endpoint =
+					<&tpdm_llm_silver_out_tpda_apss_0>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				tpda_apss_1_in_tpdm_llm_gold: endpoint {
+					remote-endpoint =
+					<&tpdm_llm_gold_out_tpda_apss_1>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				tpda_apss_3_in_tpdm_apss0: endpoint {
+					remote-endpoint =
+					<&tpdm_apss0_out_tpda_apss_3>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				tpda_apss_2_in_tpdm_apss_llm: endpoint {
+					remote-endpoint =
+					<&tpdm_apss_llm_out_tpda_apss_2>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				tpda_apss_4_in_tpdm_apps1: endpoint {
+					remote-endpoint =
+					<&tpdm_apps1_out_tpda_apss_4>;
+				};
+			};
+
+		};
+
+		out-ports {
+
+			port {
+				tpda_apss_out_funnel_apss: endpoint {
+					remote-endpoint =
+					<&funnel_apss_in_tpda_apss>;
+				};
+			};
+
+		};
+	};
+
+	ete0 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU0>;
+
+		coresight-name = "coresight-ete0";
+		qcom,skip-power-up;
+		atid = <1>;
+		out-ports {
+			port {
+				ete0_out_funnel_ete: endpoint {
+				remote-endpoint = <&funnel_ete_in_ete0>;
+				};
+			};
+		};
+	};
+
+	ete1 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU1>;
+
+		coresight-name = "coresight-ete1";
+		qcom,skip-power-up;
+		atid = <2>;
+		out-ports {
+			port {
+				ete1_out_funnel_ete: endpoint {
+				remote-endpoint = <&funnel_ete_in_ete1>;
+				};
+			};
+		};
+	};
+
+	ete2 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU2>;
+
+		coresight-name = "coresight-ete2";
+		qcom,skip-power-up;
+		atid = <3>;
+		out-ports {
+			port {
+				ete2_out_funnel_ete: endpoint {
+				remote-endpoint = <&funnel_ete_in_ete2>;
+				};
+			};
+		};
+	};
+
+	ete3 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU3>;
+
+		coresight-name = "coresight-ete3";
+		qcom,skip-power-up;
+		atid = <4>;
+		out-ports {
+			port {
+				ete3_out_funnel_ete: endpoint {
+				remote-endpoint = <&funnel_ete_in_ete3>;
+				};
+			};
+		};
+	};
+
+	ete4 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU4>;
+
+		coresight-name = "coresight-ete4";
+		qcom,skip-power-up;
+		atid = <5>;
+		out-ports {
+			port {
+				ete4_out_funnel_ete: endpoint {
+				remote-endpoint = <&funnel_ete_in_ete4>;
+				};
+			};
+		};
+	};
+
+	ete5 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU5>;
+
+		coresight-name = "coresight-ete5";
+		qcom,skip-power-up;
+		atid = <6>;
+		out-ports {
+			port {
+				ete5_out_funnel_ete: endpoint {
+				remote-endpoint = <&funnel_ete_in_ete5>;
+				};
+			};
+		};
+	};
+
+	ete6 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU6>;
+
+		coresight-name = "coresight-ete6";
+		qcom,skip-power-up;
+		atid = <7>;
+		out-ports {
+			port {
+				ete6_out_funnel_ete: endpoint {
+				remote-endpoint = <&funnel_ete_in_ete6>;
+				};
+			};
+		};
+	};
+
+	ete7 {
+		compatible = "arm,embedded-trace-extension";
+		cpu = <&CPU7>;
+
+		coresight-name = "coresight-ete7";
+		qcom,skip-power-up;
+		atid = <8>;
+		out-ports {
+			port {
+				ete7_out_funnel_ete: endpoint {
+				remote-endpoint = <&funnel_ete_in_ete7>;
+				};
+			};
+		};
+	};
+
+	funnel_ete {
+		compatible = "arm,coresight-static-funnel";
+		coresight-name = "coresight-funnel-ete";
+
+		out-ports {
+			port {
+				funnel_ete_out_funnel_apss: endpoint {
+					remote-endpoint =
+					<&funnel_apss_in_funnel_ete>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_ete_in_ete0: endpoint {
+					remote-endpoint =
+					<&ete0_out_funnel_ete>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_ete_in_ete1: endpoint {
+				remote-endpoint =
+					<&ete1_out_funnel_ete>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				funnel_ete_in_ete2: endpoint {
+				remote-endpoint =
+					<&ete2_out_funnel_ete>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				funnel_ete_in_ete3: endpoint {
+				remote-endpoint =
+					<&ete3_out_funnel_ete>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				funnel_ete_in_ete4: endpoint {
+				remote-endpoint =
+					<&ete4_out_funnel_ete>;
+				};
+			};
+
+			port@5 {
+				reg = <5>;
+				funnel_ete_in_ete5: endpoint {
+					remote-endpoint =
+					<&ete5_out_funnel_ete>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				funnel_ete_in_ete6: endpoint {
+					remote-endpoint =
+					<&ete6_out_funnel_ete>;
+				};
+			};
+
+			port@7 {
+				reg = <7>;
+				funnel_ete_in_ete7: endpoint {
+					remote-endpoint =
+					<&ete7_out_funnel_ete>;
+				};
+			};
+		};
+	};
+
+	funnel_apss: funnel@06810000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b908>;
+
+		reg = <0x06810000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-apss";
+
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+
+			port@0 {
+				reg = <0>;
+				funnel_apss_in_funnel_ete: endpoint {
+					remote-endpoint =
+					<&funnel_ete_out_funnel_apss>;
+				};
+			};
+
+
+			port@3 {
+				reg = <3>;
+				funnel_apss_in_tpda_apss: endpoint {
+					remote-endpoint =
+					<&tpda_apss_out_funnel_apss>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_apss_out_funnel_in1: endpoint {
+					remote-endpoint =
+					<&funnel_in1_in_funnel_apss>;
+				};
+			};
+
+		};
+	};
+
+	tpda_qdss: tpda@0x4004000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb969>;
+
+		reg = <0x4004000 0x1000>;
+		reg-names = "tpda-base";
+
+		qcom,tpda-atid = <65>;
+		coresight-name = "coresight-tpda-qdss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tpda_qdss_0_in_tpdm_dcc: endpoint {
+					remote-endpoint =
+					<&tpdm_dcc_out_tpda_qdss_0>;
+				};
+			};
+		};
+
+		out-ports {
+
+			port {
+				tpda_qdss_out_funnel_in0: endpoint {
+					remote-endpoint =
+					<&funnel_in0_in_tpda_qdss>;
+				};
+			};
+		};
+	};
+
+	funnel_in0: funnel@04041000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x04041000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-in0";
+
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@7 {
+				reg = <7>;
+				funnel_in0_in_stm: endpoint {
+					remote-endpoint =
+					<&stm_out_funnel_in0>;
+				};
+			};
+
+			port@6 {
+				reg = <6>;
+				funnel_in0_in_tpda_qdss: endpoint {
+					remote-endpoint =
+					<&tpda_qdss_out_funnel_in0>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_in0_out_funnel_qdss: endpoint {
+					remote-endpoint =
+					<&funnel_qdss_in_funnel_in0>;
+				};
+			};
+
+		};
+	};
+
+	funnel_in1: funnel@04042000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b908>;
+
+		reg = <0x04042000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-in1";
+
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@4 {
+				reg = <4>;
+				funnel_in1_in_funnel_apss: endpoint {
+					remote-endpoint =
+					<&funnel_apss_out_funnel_in1>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_in1_out_funnel_qdss: endpoint {
+					remote-endpoint =
+					<&funnel_qdss_in_funnel_in1>;
+				};
+			};
+
+		};
+	};
+
+	funnel_qdss: funnel@04045000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x04045000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-qdss";
+
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+				funnel_qdss_in_funnel_in1: endpoint {
+					remote-endpoint =
+					<&funnel_in1_out_funnel_qdss>;
+				};
+			};
+
+			port@0 {
+				reg = <0>;
+				funnel_qdss_in_funnel_in0: endpoint {
+					remote-endpoint =
+					<&funnel_in0_out_funnel_qdss>;
+				};
+			};
+
+		};
+
+		out-ports {
+			port {
+				funnel_qdss_out_funnel_aoss: endpoint {
+					remote-endpoint =
+					<&funnel_aoss_in_funnel_qdss>;
+				};
+			};
+
+		};
+	};
+
+
+	funnel_aoss: funnel@04b04000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x04b04000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-aoss";
+
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@7 {
+				reg = <7>;
+				funnel_aoss_in_funnel_qdss: endpoint {
+					remote-endpoint =
+					<&funnel_qdss_out_funnel_aoss>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				funnel_aoss_out_tmc_etf: endpoint {
+					remote-endpoint =
+					<&tmc_etf_in_funnel_aoss>;
+				};
+			};
+		};
+
+	};
+
+	dummy_eud: dummy_sink {
+		compatible = "qcom,coresight-dummy";
+
+		coresight-name = "coresight-eud";
+
+		qcom,dummy-sink;
+		in-ports {
+			port {
+				eud_in_replicator_swao: endpoint {
+					remote-endpoint =
+						<&replicator_swao_out_eud>;
+				};
+			};
+		};
+	};
+
+
+	tmc_etf: tmc@04b05000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb961>;
+		reg = <0x04b05000 0x1000>;
+		reg-names = "tmc-base";
+
+		coresight-name = "coresight-tmc-etf";
+		cti-reset-trig-num = <0>;
+		cti-flush-trig-num = <1>;
+		coresight-csr = <&csr>;
+		arm,default-sink;
+
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				tmc_etf_in_funnel_aoss: endpoint {
+					remote-endpoint =
+					<&funnel_aoss_out_tmc_etf>;
+				};
+			};
+		};
+
+		out-ports {
+			port {
+				tmc_etf_out_replicator_swao: endpoint {
+					remote-endpoint =
+					<&replicator_swao_in_tmc_etf>;
+				};
+			};
+		};
+	};
+
+
+	replicator_swao: replicator@04b06000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb909>;
+		reg = <0x04b06000 0x1000>;
+		reg-names = "replicator-base";
+
+		coresight-name = "coresight-replicator_swao";
+
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				replicator_swao_in_tmc_etf: endpoint {
+					remote-endpoint = <&tmc_etf_out_replicator_swao>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				replicator_swao_out_replicator_qdss: endpoint {
+					remote-endpoint =
+					<&replicator_qdss_in_replicator_swao>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				replicator_swao_out_eud: endpoint {
+					remote-endpoint =
+					  <&eud_in_replicator_swao>;
+				};
+			};
+		};
+	};
+
+	replicator_qdss: replicator@4046000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb909>;
+		reg = <0x04046000 0x1000>;
+		reg-names = "replicator-base";
+
+		coresight-name = "coresight-replicator_qdss";
+
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				replicator_qdss_in_replicator_swao: endpoint {
+					remote-endpoint =
+					<&replicator_swao_out_replicator_qdss>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				replicator_qdss_out_replicator_etr: endpoint {
+					remote-endpoint =
+					<&replicator_etr_in_replicator_qdss>;
+				};
+			};
+		};
+	};
+
+	replicator_etr: replicator@0404E000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb909>;
+		reg = <0x0404E000 0x1000>;
+		reg-names = "replicator-base";
+
+		coresight-name = "coresight-replicator_etr";
+
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		in-ports {
+			port {
+				replicator_etr_in_replicator_qdss: endpoint {
+					remote-endpoint =
+					<&replicator_qdss_out_replicator_etr>;
+				};
+			};
+		};
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				replicator_etr_out_tmc_etr: endpoint {
+					remote-endpoint = <&tmc_etr_in_replicator_etr>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				replicator_etr_out_tmc_etr1: endpoint {
+					remote-endpoint = <&tmc_etr1_in_replicator_etr>;
+				};
+			};
+		};
+	};
+
+
+	csr: csr@04001000 {
+		compatible = "qcom,coresight-csr";
+		reg = <0x04001000 0x1000>;
+		reg-names = "csr-base";
+
+		coresight-name = "coresight-csr";
+		qcom,hwctrl-set-support;
+		qcom,set-byte-cntr-support;
+
+		qcom,blk-size = <1>;
+	};
+
+
+	cti0: cti@078E0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x078E0000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti0";
+
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+	};
+
+
+	swao_csr: csr@04b11000 {
+		compatible = "qcom,coresight-csr";
+		reg = <0x04B11000 0x1000>,
+		      <0x04B110f8 0x50>;
+		reg-names = "csr-base", "msr-base";
+
+		coresight-name = "coresight-swao-csr";
+		qcom,timestamp-support;
+		qcom,msr-support;
+
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		qcom,blk-size = <1>;
+	};
+
+	tmc_etr: tmc@4048000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb961>;
+		reg = <0x4048000 0x1000>,
+			<0x4064000 0x16000>;
+		reg-names = "tmc-base", "bam-base";
+
+		qcom,iommu-dma = "default";
+		iommus = <&apps_smmu 0x04e0 0x40>,
+			<&apps_smmu 0x04a0 0x0>;
+
+		qcom,iommu-dma-addr-pool = <0x0 0xffc00000>;
+
+		coresight-name = "coresight-tmc-etr";
+
+		qcom,mem_support;
+		qcom,sw-usb;
+		dma-coherent;
+		coresight-csr = <&csr>;
+		csr-atid-offset = <0xf8>;
+		csr-irqctrl-offset = <0x6c>;
+		byte-cntr-name = "byte-cntr";
+		byte-cntr-class-name = "coresight-tmc-etr-stream";
+
+		interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "byte-cntr-irq";
+
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+		in-ports {
+			port {
+				tmc_etr_in_replicator_etr: endpoint {
+					remote-endpoint =
+					<&replicator_etr_out_tmc_etr>;
+				};
+			};
+		};
+	};
+
+	tmc_etr1: tmc@404F000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb961>;
+		reg = <0x0404F000 0x1000>;
+		reg-names = "tmc-base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		qcom,mem_support;
+		arm,buffer-size = <0x400000>;
+		coresight-name = "coresight-tmc-etr1";
+		coresight-ctis = <&cti0 &cti0>;
+		cti-reset-trig-num = <0>;
+		cti-flush-trig-num = <3>;
+		coresight-csr = <&csr>;
+		csr-atid-offset = <0x108>;
+		byte-cntr-name = "byte-cntr1";
+		byte-cntr-class-name = "coresight-tmc-etr1-stream";
+		clocks = <&aoss_qmp QDSS_CLK>;
+		clock-names = "apb_pclk";
+
+		qcom,iommu-dma = "default";
+		iommus = <&apps_smmu 0x04c0 0x00>,
+					<&apps_smmu 0x04E0 0x40>,
+					<&apps_smmu 0x04A0 0x40>;
+		qcom,iommu-dma-addr-pool = <0x0 0xffc00000>;
+		interrupts = <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "byte-cntr-irq";
+
+		in-ports {
+			port {
+				tmc_etr1_in_replicator_etr: endpoint {
+					remote-endpoint =
+					<&replicator_etr_out_tmc_etr1>;
+				};
+			};
+		};
+	};
+
+};
diff --git a/qcom/lemans-debug.dtsi b/qcom/lemans-debug.dtsi
index 27e07a2b..30e24f9d 100755
--- a/qcom/lemans-debug.dtsi
+++ b/qcom/lemans-debug.dtsi
@@ -13,6 +13,17 @@
 };
 
 &soc {
+	dcc: dcc_v2@40ff000 {
+		compatible = "qcom,dcc-v2";
+		reg = <0x040ff000 0x1000>,
+			<0x040b8800 0x7000>;
+		reg-names = "dcc-base", "dcc-ram-base";
+		qcom,transaction_timeout = <0>;
+		dcc-ram-offset = <0x0>;
+
+		status = "okay";
+	};
+
 	mem_dump {
 		compatible = "qcom,mem-dump";
 		memory-region = <&dump_mem>;
diff --git a/qcom/lemans-dma-heaps.dtsi b/qcom/lemans-dma-heaps.dtsi
index 87f446c4..75ffb7b7 100755
--- a/qcom/lemans-dma-heaps.dtsi
+++ b/qcom/lemans-dma-heaps.dtsi
@@ -37,10 +37,9 @@
 		};
 
 		qcom,secure_cdsp {
-			qcom,dma-heap-name = "qcom,secure-cdsp";
-			qcom,dma-heap-type = <HEAP_TYPE_SECURE_CARVEOUT>;
+			qcom,dma-heap-name = "qcom,cma-secure-cdsp";
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
 			memory-region = <&cdsp_secure_mem>;
-			qcom,token = <0x20000000>;
 		};
 
 		qcom,sp_hlos {
diff --git a/qcom/lemans-ivi-adas-adp-star-overlay.dts b/qcom/lemans-ivi-adas-adp-star-overlay.dts
new file mode 100755
index 00000000..df1281b1
--- /dev/null
+++ b/qcom/lemans-ivi-adas-adp-star-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "lemans-qam-star.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Lemans IVI ADAS ADP STAR";
+	compatible = "qcom,lemans-ivi-adas", "qcom,lemans", "qcom,adp-star", "qcom,lemans-ivi-adas-adp-star";
+	qcom,msm-id = <534 0x10000>;
+	qcom,board-id = <0x10019 0>;
+};
+
diff --git a/qcom/lemans-ivi-adas-adp-star.dts b/qcom/lemans-ivi-adas-adp-star.dts
new file mode 100755
index 00000000..e52defa2
--- /dev/null
+++ b/qcom/lemans-ivi-adas-adp-star.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "lemans-ivi-adas.dtsi"
+#include "lemans-qam-star.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Lemans IVI ADAS ADP STAR";
+	compatible = "qcom,lemans-ivi-adas", "qcom,lemans", "qcom,adp-star", "qcom,lemans-ivi-adas-adp-star";
+};
+
diff --git a/qcom/lemans-ivi-adas-qam-star-overlay.dts b/qcom/lemans-ivi-adas-qam-star-overlay.dts
new file mode 100755
index 00000000..e68d15fc
--- /dev/null
+++ b/qcom/lemans-ivi-adas-qam-star-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "lemans-qam-star.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Lemans IVI ADAS QAM STAR";
+	compatible = "qcom,lemans-ivi-adas", "qcom,lemans", "qcom,qam-star", "qcom,lemans-ivi-adas-qam-star";
+	qcom,msm-id = <534 0x10000>;
+	qcom,board-id = <0x10025 0>;
+};
+
diff --git a/qcom/lemans-ivi-adas-qam-star.dts b/qcom/lemans-ivi-adas-qam-star.dts
new file mode 100755
index 00000000..24f3f388
--- /dev/null
+++ b/qcom/lemans-ivi-adas-qam-star.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "lemans-ivi-adas.dtsi"
+#include "lemans-qam-star.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Lemans IVI ADAS QAM STAR";
+	compatible = "qcom,lemans-ivi-adas", "qcom,lemans", "qcom,qam-star", "qcom,lemans-ivi-adas-qam-star";
+};
+
diff --git a/qcom/lemans-ivi-adas.dts b/qcom/lemans-ivi-adas.dts
new file mode 100755
index 00000000..9dadb30f
--- /dev/null
+++ b/qcom/lemans-ivi-adas.dts
@@ -0,0 +1,8 @@
+/dts-v1/;
+
+#include "lemans-ivi-adas.dtsi"
+/ {
+	model = "Qualcomm Technologies, Inc. Lemans IVI ADAS SoC";
+	compatible = "qcom,lemans-ivi-adas", "qcom,lemans";
+	qcom,board-id = <0 0>;
+};
diff --git a/qcom/lemans-ivi-adas.dtsi b/qcom/lemans-ivi-adas.dtsi
new file mode 100755
index 00000000..a30d7f15
--- /dev/null
+++ b/qcom/lemans-ivi-adas.dtsi
@@ -0,0 +1,7 @@
+#include "lemans.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. LeMans IVI ADAS SoC";
+	compatible = "qcom,lemans-ivi-adas", "qcom,lemans";
+	qcom,msm-id = <534 0x10000>;
+};
diff --git a/qcom/lemans-pcie.dtsi b/qcom/lemans-pcie.dtsi
index 34cccbd3..f7d1dd23 100755
--- a/qcom/lemans-pcie.dtsi
+++ b/qcom/lemans-pcie.dtsi
@@ -29,11 +29,11 @@
 				"int_d";
 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 0 0xffffffff>;
-		interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
-				0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
-				0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
-				0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
-				0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-map = <0 0 0 0 &intc 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
 
 		perst-gpio = <&tlmm 2 GPIO_ACTIVE_HIGH>;
 		wake-gpio = <&tlmm 0 GPIO_ACTIVE_HIGH>;
@@ -51,7 +51,7 @@
 		vreg-cx-supply = <&VDD_CX_LEVEL>;
 		vreg-mx-supply = <&VDD_MXC_LEVEL>;
 
-		qcom,vreg-1p8-voltage-level = <1200000 1200000 25800>;
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 25800>;
 		qcom,vreg-0p9-voltage-level = <880000 880000 186000>;
 		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
 						RPMH_REGULATOR_LEVEL_NOM 0>;
@@ -349,11 +349,11 @@
 				"int_d";
 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 0 0xffffffff>;
-		interrupt-map = <0 0 0 0 &intc GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH
-				0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH
-				0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
-				0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
-				0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-map = <0 0 0 0 &intc 0 GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc 0 GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 
 		perst-gpio = <&tlmm 4 GPIO_ACTIVE_HIGH>;
 		wake-gpio = <&tlmm 5 GPIO_ACTIVE_HIGH>;
@@ -371,7 +371,7 @@
 		vreg-cx-supply = <&VDD_CX_LEVEL>;
 		vreg-mx-supply = <&VDD_MXC_LEVEL>;
 
-		qcom,vreg-1p8-voltage-level = <1200000 1200000 33300>;
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 33300>;
 		qcom,vreg-0p9-voltage-level = <880000 880000 439000>;
 		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
 						RPMH_REGULATOR_LEVEL_NOM 0>;
diff --git a/qcom/lemans-pinctrl.dtsi b/qcom/lemans-pinctrl.dtsi
index a95e84b6..be937ead 100755
--- a/qcom/lemans-pinctrl.dtsi
+++ b/qcom/lemans-pinctrl.dtsi
@@ -2202,4 +2202,33 @@
 			};
 		};
 	};
+
+	emac {
+		emac_mdc: emac_mdc {
+			mux {
+				pins = "gpio8";
+				function = "emac0_mdc";
+			};
+
+			config {
+				pins = "gpio8";
+				bias-pull-up;
+				drive-strength = <16>;
+			};
+		};
+
+		emac_mdio: emac_mdio {
+			mux {
+					pins = "gpio9";
+					function = "emac0_mdio";
+			};
+
+			config {
+				pins = "gpio9";
+				bias-pull-up;
+				drive-strength = <16>;
+			};
+		};
+	};
+
 };
diff --git a/qcom/lemans-pmic-overlay.dtsi b/qcom/lemans-pmic-overlay.dtsi
index f1cd9b03..f6f853d0 100755
--- a/qcom/lemans-pmic-overlay.dtsi
+++ b/qcom/lemans-pmic-overlay.dtsi
@@ -106,6 +106,22 @@
 	};
 };
 
+&pm8775_1_adc {
+	status = "okay";
+};
+
+&pm8775_2_adc {
+	status = "okay";
+};
+
+&pm8775_3_adc {
+	status = "okay";
+};
+
+&pm8775_4_adc {
+	status = "okay";
+};
+
 &thermal_zones {
 	pm8775_1_temp_alarm: pm8775_1_tz {
 		polling-delay-passive = <100>;
diff --git a/qcom/lemans-qam-star.dtsi b/qcom/lemans-qam-star.dtsi
index 689bf563..d14e1d28 100755
--- a/qcom/lemans-qam-star.dtsi
+++ b/qcom/lemans-qam-star.dtsi
@@ -1 +1,5 @@
 #include  "lemans-adp-common.dtsi"
+
+&cdsp1_pas {
+	status = "disabled";
+};
diff --git a/qcom/lemans-usb.dtsi b/qcom/lemans-usb.dtsi
index 311837de..9aaf5232 100755
--- a/qcom/lemans-usb.dtsi
+++ b/qcom/lemans-usb.dtsi
@@ -11,8 +11,14 @@
 		#size-cells = <1>;
 		ranges;
 
-		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "pwr_event_irq";
+		interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>,
+				<&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
+				<&pdc 12 IRQ_TYPE_LEVEL_HIGH>,
+				<&pdc 15 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+				"ss_phy_irq", "dm_hs_phy_irq";
+		qcom,use-pdc-interrupts;
+
 
 		USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
 		clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
@@ -56,6 +62,7 @@
 			tx-fifo-resize;
 			maximum-speed = "super-speed-plus";
 			dr_mode = "otg";
+			usb-role-switch;
 		};
 	};
 
@@ -222,8 +229,13 @@
 		#size-cells = <1>;
 		ranges;
 
-		interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "pwr_event_irq";
+		interrupts-extended = <&pdc 8 IRQ_TYPE_EDGE_RISING>,
+				<&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+				<&pdc 13 IRQ_TYPE_LEVEL_HIGH>,
+				<&pdc 7 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+				"ss_phy_irq", "dm_hs_phy_irq";
+		qcom,use-pdc-interrupts;
 
 		USB3_GDSC-supply = <&gcc_usb30_sec_gdsc>;
 		clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
@@ -267,6 +279,7 @@
 			tx-fifo-resize;
 			maximum-speed = "super-speed-plus";
 			dr_mode = "otg";
+			usb-role-switch;
 		};
 	};
 
@@ -434,8 +447,12 @@
 		#size-cells = <1>;
 		ranges;
 
-		interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "pwr_event_irq";
+		interrupts-extended = <&pdc 10 IRQ_TYPE_EDGE_RISING>,
+				<&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+				<&pdc 9 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+				"dm_hs_phy_irq";
+		qcom,use-pdc-interrupts;
 
 		USB3_GDSC-supply = <&gcc_usb20_prim_gdsc>;
 		clocks = <&gcc GCC_USB20_MASTER_CLK>,
diff --git a/qcom/lemans-vm-la-overlay.dts b/qcom/lemans-vm-la-overlay.dts
new file mode 100755
index 00000000..24137409
--- /dev/null
+++ b/qcom/lemans-vm-la-overlay.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+/plugin/;
+
+
+/ {
+	model = "Qualcomm Technologies, Inc. Lemans Single LA Guest Virtual Machine";
+	compatible = "qcom,lemans", "qcom,quinvm";
+	qcom,msm-id = <532 0x20000>;
+	qcom,board-id = <0x0 0x1000001>;
+};
diff --git a/qcom/lemans-vm-la.dts b/qcom/lemans-vm-la.dts
new file mode 100755
index 00000000..4beee7f3
--- /dev/null
+++ b/qcom/lemans-vm-la.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "lemans-vm.dtsi"
+#include "lemans-vm-la.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Lemans Single LA Guest Virtual Machine";
+	compatible = "qcom,lemans", "qcom,quinvm";
+	qcom,board-id = <0x0 0x1000001>;
+};
diff --git a/qcom/lemans-vm-la.dtsi b/qcom/lemans-vm-la.dtsi
new file mode 100755
index 00000000..d1fc80fb
--- /dev/null
+++ b/qcom/lemans-vm-la.dtsi
@@ -0,0 +1,40 @@
+&soc {
+};
+
+/ {
+	rename_devices: rename_devices {
+		compatible = "qcom,rename-devices";
+		rename_blk: rename_blk {
+			device-type = "block";
+			actual-dev = "vda", "vdb", "vdc",
+					"vdd", "vde", "vdf",
+					"vdg", "vdh", "vdi",
+					"vdj", "vdk", "vdl",
+					"vdm", "vdn", "vdo",
+					"vdp", "vdq";
+			rename-dev = "super", "userdata", "metadata",
+					"persist", "modem_a","bluetooth_a",
+					"misc", "vbmeta_a", "vbmeta_b",
+					"boot_a", "dtbo_a", "dsp_a",
+					"modem_b", "bluetooth_b", "boot_a",
+					"dtbo_b", "dsp_b";
+		};
+	};
+};
+
+&qcom_rng_ee3 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "ok";
+};
+
+&usb2_phy0 {
+	status = "ok";
+};
+
+&usb_qmp_phy0 {
+	status = "ok";
+};
+
diff --git a/qcom/lemans-vm-lv-overlay.dts b/qcom/lemans-vm-lv-overlay.dts
new file mode 100755
index 00000000..ffa6e29c
--- /dev/null
+++ b/qcom/lemans-vm-lv-overlay.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+/plugin/;
+
+
+/ {
+	model = "Qualcomm Technologies, Inc. LeMans Single Linux Virtual Machine";
+	compatible = "qcom,lemans", "qcom,quinvm";
+	qcom,msm-id = <532 0x20000>;
+	qcom,board-id = <0 0x1000002>;
+};
diff --git a/qcom/lemans-vm-lv.dts b/qcom/lemans-vm-lv.dts
new file mode 100755
index 00000000..c37ce993
--- /dev/null
+++ b/qcom/lemans-vm-lv.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "lemans-vm.dtsi"
+#include "lemans-vm-lv.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. LeMans Single Linux Virtual Machine";
+	compatible = "qcom,lemans", "qcom,quinvm";
+	qcom,board-id = <0 0x1000002>;
+};
diff --git a/qcom/lemans-vm-lv.dtsi b/qcom/lemans-vm-lv.dtsi
new file mode 100755
index 00000000..c7c4f15c
--- /dev/null
+++ b/qcom/lemans-vm-lv.dtsi
@@ -0,0 +1,6 @@
+&soc {
+};
+
+&hab {
+	vmid = <3>;
+};
diff --git a/qcom/lemans-vm-qupv3.dtsi b/qcom/lemans-vm-qupv3.dtsi
new file mode 100755
index 00000000..e6e79dcd
--- /dev/null
+++ b/qcom/lemans-vm-qupv3.dtsi
@@ -0,0 +1,86 @@
+&soc {
+
+	/* QUPv3_1  wrapper  instance */
+	qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0xac0000 0x6000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		iommus = <&apps_smmu 0x443 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		status = "ok";
+
+		qupv3_se11_i2c: i2c@a90000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0xa90000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se11_i2c_active>;
+			pinctrl-1 = <&qupv3_se11_i2c_sleep>;
+			status = "disabled";
+		};
+
+		/* Debug UART Instance */
+		qupv3_se10_2uart: qcom,qup_uart@a8c000 {
+			compatible = "qcom,geni-debug-uart";
+			reg = <0xa8c000 0x4000>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se";
+			clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se10_2uart_active>;
+			pinctrl-1 = <&qupv3_se10_2uart_sleep>;
+			status = "disabled";
+		};
+	};
+
+	/* QUPv3_2  wrapper  instance */
+	qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0x8c0000 0x6000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		iommus = <&apps_smmu 0x5a3  0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		status = "ok";
+
+		/* BT UART Instance */
+		qupv3_se17_4uart: qcom,qup_uart@88c000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0x88c000 0x4000>;
+			reg-names = "se_phys";
+			interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
+					<&tlmm 94 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+			pinctrl-names = "default", "active", "sleep", "shutdown";
+			pinctrl-0 = <&qupv3_se17_default_cts>,
+					<&qupv3_se17_default_rtsrx>, <&qupv3_se17_default_tx>;
+			pinctrl-1 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
+					<&qupv3_se17_tx>;
+			pinctrl-2 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
+					<&qupv3_se17_tx>;
+			pinctrl-3 = <&qupv3_se17_default_cts>,
+					<&qupv3_se17_default_rtsrx>, <&qupv3_se17_default_tx>;
+			qcom,wakeup-byte = <0xFD>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/qcom/lemans-vm-usb.dtsi b/qcom/lemans-vm-usb.dtsi
new file mode 100755
index 00000000..aaf76834
--- /dev/null
+++ b/qcom/lemans-vm-usb.dtsi
@@ -0,0 +1,501 @@
+#include <dt-bindings/phy/qcom,usb3-5nm-qmp-uni.h>
+#include <dt-bindings/clock/qcom,gcc-lemans.h>
+
+&soc {
+	usb0: ssusb@a600000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0xa600000 0x100000>;
+		reg-names = "core_base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pwr_event_irq";
+
+		USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
+		clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+			<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+			<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+			<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+					"utmi_clk", "sleep_clk";
+
+		resets = <&gcc GCC_USB30_PRIM_BCR>;
+		reset-names = "core_reset";
+
+		qcom,core-clk-rate = <200000000>;
+		qcom,core-clk-rate-hs = <66666667>;
+		qcom,core-clk-rate-disconnected = <133333333>;
+		qcom,pm-qos-latency = <2>;
+
+		qcom,host-poweroff-in-pm-suspend;
+
+		status = "disabled";
+
+		dwc3@a600000 {
+			compatible = "snps,dwc3";
+			reg = <0xa600000 0xd93c>;
+			iommus = <&apps_smmu 0x080 0x0>;
+			qcom,iommu-dma = "bypass";
+			interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
+			usb-phy = <&usb2_phy0>, <&usb_qmp_phy0>;
+			snps,disable-clk-gating;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,is-utmi-l1-suspend;
+			snps,usb2-gadget-lpm-disable;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,ssp-u3-u0-quirk;
+			tx-fifo-resize;
+			maximum-speed = "super-speed-plus";
+			dr_mode = "otg";
+			usb-role-switch;
+		};
+	};
+
+	/* Primary USB port related High Speed PHY */
+	usb2_phy0: hsphy@88e4000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x88e4000 0x120>,
+			<0x088e3000 0x4>;
+		reg-names = "hsusb_phy_base",
+			"eud_enable_reg";
+
+		vdd-supply = <&L7A>;
+		vdda18-supply = <&L6C>;
+		vdda33-supply = <&L9A>;
+		qcom,vdd-voltage-level = <0 880000 880000>;
+
+		clocks = <&dummycc RPMH_CXO_CLK>;
+		clock-names = "ref_clk_src";
+
+		resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
+		reset-names = "phy_reset";
+	};
+
+	/* Primary USB port related QMP PHY */
+	usb_qmp_phy0: ssphy@88e8000 {
+		compatible = "qcom,usb-ssphy-qmp-v2";
+		reg = <0x88e8000 0x2000>,
+		    <0x088e828c 0x4>;
+		reg-names = "qmp_phy_base",
+			"pcs_clamp_enable_reg";
+
+		vdd-supply = <&L7A>;
+		qcom,vdd-voltage-level = <0 880000 880000>;
+		qcom,vdd-max-load-uA = <47000>;
+		core-supply = <&L1C>;
+
+		clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+			 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+			 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
+			 <&usb3_phy_wrapper_gcc_usb30_prim_pipe_clk>,
+			 <&dummycc RPMH_CXO_CLK>,
+			 <&gcc GCC_USB_CLKREF_EN>,
+			 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+		clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
+				"pipe_clk_ext_src", "ref_clk_src",
+				"ref_clk", "com_aux_clk";
+
+		resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+				<&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
+		reset-names = "phy_reset", "phy_phy_reset";
+
+		qcom,qmp-phy-reg-offset =
+				<USB3_UNI_PCS_PCS_STATUS1
+				USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
+				USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
+				USB3_UNI_PCS_POWER_DOWN_CONTROL
+				USB3_UNI_PCS_SW_RESET
+				USB3_UNI_PCS_START_CONTROL>;
+
+		qcom,qmp-phy-init-seq =
+				/* <reg_offset, value> */
+				<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL	0x1A
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL	0x11
+				USB3_UNI_QSERDES_COM_HSCLK_SEL	0x01
+				USB3_UNI_QSERDES_COM_DEC_START_MODE0	0x82
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0	0xAB
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0	0xEA
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0	0x02
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0xCA
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x1E
+				USB3_UNI_QSERDES_COM_CP_CTRL_MODE0	0x06
+				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0	0x16
+				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0	0x36
+				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0	0x24
+				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0	0x34
+				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0	0x14
+				USB3_UNI_QSERDES_COM_LOCK_CMP_EN	0x04
+				USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE	0x0A
+				USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1	0x02
+				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1	0x24
+				USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1	0x08
+				USB3_UNI_QSERDES_COM_DEC_START_MODE1	0x82
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1	0xAB
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1	0xEA
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1	0x02
+				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1	0x82
+				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1	0x34
+				USB3_UNI_QSERDES_COM_CP_CTRL_MODE1	0x06
+				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1	0x16
+				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1	0x36
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0xCA
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x1E
+				USB3_UNI_QSERDES_COM_SSC_EN_CENTER	0x01
+				USB3_UNI_QSERDES_COM_SSC_PER1	0x31
+				USB3_UNI_QSERDES_COM_SSC_PER2	0x01
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1	0xDE
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1	0x07
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0	0xDE
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0	0x07
+				USB3_UNI_QSERDES_COM_VCO_TUNE_MAP	0x02
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4	0xDC
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3	0xBD
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2	0xFF
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH	0x7F
+				USB3_UNI_QSERDES_RX_RX_MODE_00_LOW	0xFF
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4	0xA9
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3	0x7B
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2	0xE4
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH	0x24
+				USB3_UNI_QSERDES_RX_RX_MODE_01_LOW	0x64
+				USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS	0x99
+				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1	0x08
+				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2	0x08
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1	0x00
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2	0x04
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN	0x2F
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW	0xFF
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH	0x0F
+				USB3_UNI_QSERDES_RX_UCDR_FO_GAIN	0x0A
+				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1	0x54
+				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2	0x0F
+				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2	0x0F
+				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4	0x0A
+				USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x47
+				USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2	0x80
+				USB3_UNI_QSERDES_RX_SIGDET_CNTRL	0x04
+				USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL	0x0E
+				USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET	0x38
+				USB3_UNI_QSERDES_RX_UCDR_SO_GAIN	0x05
+				USB3_UNI_QSERDES_RX_GM_CAL	0x00
+				USB3_UNI_QSERDES_RX_SIGDET_ENABLES	0x00
+				USB3_UNI_QSERDES_TX_LANE_MODE_1	0xA5
+				USB3_UNI_QSERDES_TX_LANE_MODE_2	0x82
+				USB3_UNI_QSERDES_TX_LANE_MODE_3	0x3F
+				USB3_UNI_QSERDES_TX_LANE_MODE_4	0x3F
+				USB3_UNI_QSERDES_TX_PI_QEC_CTRL	0x21
+				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX	0x10
+				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX	0x0E
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG1	0xC4
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG2	0x89
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG3	0x20
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG6	0x13
+				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L	0xE7
+				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H	0x03
+				USB3_UNI_PCS_RX_SIGDET_LVL	0xAA
+				USB3_UNI_PCS_PCS_TX_RX_CONFIG	0x0C
+				USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2	0x07
+				USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL	0xF8
+				USB3_UNI_PCS_USB3_POWER_STATE_CONFIG1		0x6F
+				USB3_UNI_PCS_CDR_RESET_TIME	0x0A
+				USB3_UNI_PCS_ALIGN_DETECT_CONFIG1	0x88
+				USB3_UNI_PCS_ALIGN_DETECT_CONFIG2	0x13
+				USB3_UNI_PCS_EQ_CONFIG1	0x4B
+				USB3_UNI_PCS_EQ_CONFIG5	0x10
+				USB3_UNI_PCS_REFGEN_REQ_CONFIG1	0x21>;
+
+		status = "disabled";
+	};
+
+	usb1: ssusb@a800000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0xa800000 0x100000>;
+		reg-names = "core_base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pwr_event_irq";
+
+		USB3_GDSC-supply = <&gcc_usb30_sec_gdsc>;
+		clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
+			<&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+			<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+			<&gcc GCC_USB30_SEC_SLEEP_CLK>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+					"utmi_clk", "sleep_clk";
+
+		resets = <&gcc GCC_USB30_SEC_BCR>;
+		reset-names = "core_reset";
+
+		qcom,core-clk-rate = <200000000>;
+		qcom,core-clk-rate-hs = <66666667>;
+		qcom,core-clk-rate-disconnected = <133333333>;
+		qcom,pm-qos-latency = <2>;
+
+		qcom,host-poweroff-in-pm-suspend;
+
+		status = "disabled";
+
+		dwc3@a800000 {
+			compatible = "snps,dwc3";
+			reg = <0xa800000 0xd93c>;
+			interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
+			iommus = <&apps_smmu 0x0A0 0x0>;
+			qcom,iommu-dma = "bypass";
+			usb-phy = <&usb2_phy1>, <&usb_qmp_phy1>;
+			snps,disable-clk-gating;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,ssp-u3-u0-quirk;
+			snps,is-utmi-l1-suspend;
+			snps,usb2-gadget-lpm-disable;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			tx-fifo-resize;
+			maximum-speed = "super-speed-plus";
+			dr_mode = "otg";
+		};
+	};
+
+	/* Secondary USB port related High Speed PHY */
+	usb2_phy1: hsphy@88e6000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x88e6000 0x120>;
+		reg-names = "hsusb_phy_base";
+
+		vdd-supply = <&L7A>;
+		vdda18-supply = <&L6C>;
+		vdda33-supply = <&L9A>;
+		qcom,vdd-voltage-level = <0 880000 880000>;
+
+		clocks = <&dummycc RPMH_CXO_CLK>,
+				<&gcc GCC_USB_CLKREF_EN>;
+		clock-names = "ref_clk_src", "ref_clk";
+
+		resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
+		reset-names = "phy_reset";
+
+		status = "disabled";
+	};
+
+	/* Secondary USB port related QMP PHY */
+	usb_qmp_phy1: ssphy@88ea000 {
+		compatible = "qcom,usb-ssphy-qmp-v2";
+		reg = <0x88ea000 0x2000>,
+		    <0x088ea28c 0x4>;
+		reg-names = "qmp_phy_base",
+			"pcs_clamp_enable_reg";
+
+		vdd-supply = <&L7A>;
+		qcom,vdd-voltage-level = <0 880000 880000>;
+		qcom,vdd-max-load-uA = <47000>;
+		core-supply = <&L1C>;
+
+		clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
+			 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
+			 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK_SRC>,
+			 <&usb3_phy_wrapper_gcc_usb30_sec_pipe_clk>,
+			 <&dummycc RPMH_CXO_CLK>,
+			 <&gcc GCC_USB_CLKREF_EN>,
+			 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
+		clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
+				"pipe_clk_ext_src", "ref_clk_src",
+				"ref_clk", "com_aux_clk";
+
+		resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
+				<&gcc GCC_USB3PHY_PHY_SEC_BCR>;
+		reset-names = "phy_reset", "phy_phy_reset";
+
+		qcom,qmp-phy-reg-offset =
+				<USB3_UNI_PCS_PCS_STATUS1
+				USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
+				USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
+				USB3_UNI_PCS_POWER_DOWN_CONTROL
+				USB3_UNI_PCS_SW_RESET
+				USB3_UNI_PCS_START_CONTROL>;
+
+		qcom,qmp-phy-init-seq =
+				/* <reg_offset, value> */
+				<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL	0x1A
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL	0x11
+				USB3_UNI_QSERDES_COM_HSCLK_SEL	0x01
+				USB3_UNI_QSERDES_COM_DEC_START_MODE0	0x82
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0	0xAB
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0	0xEA
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0	0x02
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0xCA
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x1E
+				USB3_UNI_QSERDES_COM_CP_CTRL_MODE0	0x06
+				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0	0x16
+				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0	0x36
+				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0	0x24
+				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0	0x34
+				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0	0x14
+				USB3_UNI_QSERDES_COM_LOCK_CMP_EN	0x04
+				USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE	0x0A
+				USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1	0x02
+				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1	0x24
+				USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1	0x08
+				USB3_UNI_QSERDES_COM_DEC_START_MODE1	0x82
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1	0xAB
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1	0xEA
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1	0x02
+				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1	0x82
+				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1	0x34
+				USB3_UNI_QSERDES_COM_CP_CTRL_MODE1	0x06
+				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1	0x16
+				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1	0x36
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0xCA
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x1E
+				USB3_UNI_QSERDES_COM_SSC_EN_CENTER	0x01
+				USB3_UNI_QSERDES_COM_SSC_PER1	0x31
+				USB3_UNI_QSERDES_COM_SSC_PER2	0x01
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1	0xDE
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1	0x07
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0	0xDE
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0	0x07
+				USB3_UNI_QSERDES_COM_VCO_TUNE_MAP	0x02
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4	0xDC
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3	0xBD
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2	0xFF
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH	0x7F
+				USB3_UNI_QSERDES_RX_RX_MODE_00_LOW	0xFF
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4	0xA9
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3	0x7B
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2	0xE4
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH	0x24
+				USB3_UNI_QSERDES_RX_RX_MODE_01_LOW	0x64
+				USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS	0x99
+				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1	0x08
+				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2	0x08
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1	0x00
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2	0x04
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN	0x2F
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW	0xFF
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH	0x0F
+				USB3_UNI_QSERDES_RX_UCDR_FO_GAIN	0x0A
+				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1	0x54
+				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2	0x0F
+				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2	0x0F
+				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4	0x0A
+				USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x47
+				USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2	0x80
+				USB3_UNI_QSERDES_RX_SIGDET_CNTRL	0x04
+				USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL	0x0E
+				USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET	0x38
+				USB3_UNI_QSERDES_RX_UCDR_SO_GAIN	0x05
+				USB3_UNI_QSERDES_RX_GM_CAL	0x00
+				USB3_UNI_QSERDES_RX_SIGDET_ENABLES	0x00
+				USB3_UNI_QSERDES_TX_LANE_MODE_1	0xA5
+				USB3_UNI_QSERDES_TX_LANE_MODE_2	0x82
+				USB3_UNI_QSERDES_TX_LANE_MODE_3	0x3F
+				USB3_UNI_QSERDES_TX_LANE_MODE_4	0x3F
+				USB3_UNI_QSERDES_TX_PI_QEC_CTRL	0x21
+				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX	0x10
+				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX	0x0E
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG1	0xC4
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG2	0x89
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG3	0x20
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG6	0x13
+				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L	0xE7
+				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H	0x03
+				USB3_UNI_PCS_RX_SIGDET_LVL	0xAA
+				USB3_UNI_PCS_PCS_TX_RX_CONFIG	0x0C
+				USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2	0x07
+				USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL	0xF8
+				USB3_UNI_PCS_USB3_POWER_STATE_CONFIG1		0x6F
+				USB3_UNI_PCS_CDR_RESET_TIME	0x0A
+				USB3_UNI_PCS_ALIGN_DETECT_CONFIG1	0x88
+				USB3_UNI_PCS_ALIGN_DETECT_CONFIG2	0x13
+				USB3_UNI_PCS_EQ_CONFIG1	0x4B
+				USB3_UNI_PCS_EQ_CONFIG5	0x10
+				USB3_UNI_PCS_REFGEN_REQ_CONFIG1	0x21>;
+
+		status = "disabled";
+	};
+
+	/* Tertiary USB port related controller */
+	usb2: hsusb@a400000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0xa400000 0x100000>;
+		reg-names = "core_base";
+
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "pwr_event_irq";
+
+		USB3_GDSC-supply = <&gcc_usb20_prim_gdsc>;
+		clocks = <&gcc GCC_USB20_MASTER_CLK>,
+			<&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
+			<&gcc GCC_USB20_MOCK_UTMI_CLK>,
+			<&gcc GCC_USB20_SLEEP_CLK>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+					"utmi_clk", "sleep_clk";
+
+		resets = <&gcc GCC_USB20_PRIM_BCR>;
+		reset-names = "core_reset";
+
+		qcom,core-clk-rate = <120000000>;
+
+		qcom,host-poweroff-in-pm-suspend;
+		qcom,default-mode-host;
+
+		status = "disabled";
+
+		dwc3@a400000 {
+			compatible = "snps,dwc3";
+			reg = <0xa400000 0xd800>;
+			iommus = <&apps_smmu 0x020 0x0>;
+			qcom,iommu-dma = "bypass";
+			interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
+			usb-phy = <&usb2_phy2>, <&usb_nop_phy>;
+			snps,disable-clk-gating;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,is-utmi-l1-suspend;
+			snps,usb2-gadget-lpm-disable;
+			tx-fifo-resize;
+			maximum-speed = "high-speed";
+			dr_mode = "host";
+		};
+	};
+
+	/* Tertiary USB port related High Speed PHY */
+	usb2_phy2: hsphy@88e7000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x88e7000 0x120>;
+		reg-names = "hsusb_phy_base";
+
+		vdd-supply = <&L7A>;
+		vdda18-supply = <&L6C>;
+		vdda33-supply = <&L9A>;
+		qcom,vdd-voltage-level = <0 880000 880000>;
+
+		clocks = <&dummycc RPMH_CXO_CLK>,
+				<&gcc GCC_USB_CLKREF_EN>;
+		clock-names = "ref_clk_src", "ref_clk";
+
+		resets = <&gcc GCC_USB3_PHY_TERT_BCR>;
+		reset-names = "phy_reset";
+		status = "disabled";
+	};
+
+	usb_nop_phy: usb_nop_phy {
+		compatible = "usb-nop-xceiv";
+	};
+};
diff --git a/qcom/lemans-vm.dtsi b/qcom/lemans-vm.dtsi
new file mode 100755
index 00000000..8b65cec4
--- /dev/null
+++ b/qcom/lemans-vm.dtsi
@@ -0,0 +1,287 @@
+#include "quin-vm-common.dtsi"
+#include <dt-bindings/clock/qcom,gcc-lemans.h>
+
+/ {
+	model = "Qualcomm Technologies, Inc. Lemans Guest Virtual Machine";
+	qcom,msm-name  = "Lemans";
+	qcom,msm-id = <532 0x20000>;
+
+	aliases {
+		hsuart0 = &qupv3_se17_4uart;
+	};
+};
+
+&firmware {
+	scm {
+		compatible = "qcom,scm";
+	};
+};
+
+&soc {
+
+	apps_smmu: apps-smmu@15000000 {
+		compatible = "qcom,qsmmu-v500";
+		reg = <0x15000000 0x100000>,
+			<0x15182000 0x28>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,skip-init;
+		qcom,use-3-lvl-tables;
+		#global-interrupts = <2>;
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+
+		interrupts =	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	dma_dev@0x0 {
+		compatible = "qcom,iommu-dma";
+		memory-region = <&system_cma>;
+	};
+
+	tlmm: pinctrl@f000000 {
+		compatible = "qcom,lemans-pinctrl";
+		reg = <0xf000000 0x1000000>;
+		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	qcom_rng_ee3: qrng@10d3000 {
+		compatible = "qcom,msm-rng";
+		reg = <0x10d3000 0x1000>;
+		qcom,no-qrng-config;
+		clocks = <&dummycc RPMH_HWKM_CLK>;
+		clock-names = "km_clk_src";
+		status = "disabled";
+	};
+
+	qtee_shmbridge {
+		compatible = "qcom,tee-shared-memory-bridge";
+		/*Boolean property to disable shmbridge*/
+		qcom,disable-shmbridge-support;
+	};
+
+	qcom_qseecom: qseecom@d1800000 {
+		compatible = "qcom,qseecom";
+		reg = <0xd1800000 0x3900000>;
+		reg-names = "secapp-region";
+		memory-region = <&qseecom_mem>;
+		qcom,hlos-num-ce-hw-instances = <1>;
+		qcom,hlos-ce-hw-instance = <0>;
+		qcom,qsee-ce-hw-instance = <0>;
+		qcom,disk-encrypt-pipe-pair = <2>;
+		qcom,no-clock-support;
+		qcom,commonlib-loaded-by-hostvm;
+		qcom,qsee-reentrancy-support = <2>;
+	};
+
+	usb3_phy_wrapper_gcc_usb30_prim_pipe_clk: usb3_phy_wrapper_gcc_usb30_prim_pipe_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <1000>;
+		clock-output-names = "usb3_phy_wrapper_gcc_usb30_prim_pipe_clk";
+		#clock-cells = <0>;
+	};
+
+	usb3_phy_wrapper_gcc_usb30_sec_pipe_clk: usb3_phy_wrapper_gcc_usb30_sec_pipe_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <1000>;
+		clock-output-names = "usb3_phy_wrapper_gcc_usb30_sec_pipe_clk";
+		#clock-cells = <0>;
+	};
+};
+
+&regulator {
+
+	gcc_usb30_prim_gdsc: gcc_usb30_prim_gdsc {
+		regulator-name = "gcc_usb30_prim_gdsc";
+	};
+
+	gcc_pcie_0_gdsc: gcc_pcie_0_gdsc {
+		regulator-name = "gcc_pcie_0_gdsc";
+	};
+
+	gcc_pcie_1_gdsc: gcc_pcie_1_gdsc {
+		regulator-name = "gcc_pcie_1_gdsc";
+	};
+
+	gcc_usb30_sec_gdsc: gcc_usb30_sec_gdsc {
+		regulator-name = "gcc_usb30_sec_gdsc";
+	};
+
+	gcc_usb20_prim_gdsc: gcc_usb20_prim_gdsc {
+		regulator-name = "gcc_usb20_prim_gdsc";
+	};
+
+	L5A: pm8775_a_l5: regulator-pm8775_a-l5 {
+		regulator-name = "ldoa5";
+		regulator-min-microvolt = <870000>;
+		regulator-max-microvolt = <950000>;
+	};
+
+	L7A: pm8775_a_l7: regulator-pm8775_a-l7 {
+		regulator-name = "ldoa7";
+		regulator-min-microvolt = <720000>;
+		regulator-max-microvolt = <950000>;
+		regulator-always-on;
+	};
+
+	L9A: pm8775_a_l9: regulator-pm8775_a-l9 {
+		regulator-name = "ldoa9";
+		regulator-min-microvolt = <2970000>;
+		regulator-max-microvolt = <3544000>;
+	};
+
+	L1C: pm8775_c_l1: regulator-pm8775_c-l1 {
+		regulator-name = "ldoc1";
+		regulator-min-microvolt = <1140000>;
+		regulator-max-microvolt = <1260000>;
+	};
+
+	L6C: pm8775_c_l6: regulator-pm8775_c-l6 {
+		regulator-name = "ldoc6";
+		regulator-min-microvolt = <1620000>;
+		regulator-max-microvolt = <1980000>;
+	};
+};
+
+&scc {
+	status = "disabled";
+};
+
+#include "lemans-pinctrl.dtsi"
+#include "pm8775-vm.dtsi"
+#include "lemans-vm-qupv3.dtsi"
+#include "lemans-vm-usb.dtsi"
diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi
index 69e44b7f..ebdb2df7 100755
--- a/qcom/lemans.dtsi
+++ b/qcom/lemans.dtsi
@@ -29,8 +29,10 @@
 	aliases {
 		serial0 = &qupv3_se10_2uart;
 		ufshc1 = &ufshc_mem; /* Embedded UFS slot */
+		ufshc2 = &ufshc2_mem; /* Embedded 2nd UFS Slot */
 		i2c4 = &qupv3_se11_i2c;
 		spi16 = &qupv3_se16_spi;
+		hsuart0 = &qupv3_se17_4uart;
 	};
 
 	soc: soc { };
@@ -45,6 +47,9 @@
 			device_type = "cpu";
 			compatible = "qcom,kryo";
 			reg = <0x0 0x0>;
+			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
+			power-domains = <&CPU_PD0>;
+			power-domain-names = "psci";
 			enable-method = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			cache-size = <0x20000>;
@@ -68,6 +73,9 @@
 			device_type = "cpu";
 			compatible = "qcom,kryo";
 			reg = <0x0 0x100>;
+			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
+			power-domains = <&CPU_PD1>;
+			power-domain-names = "psci";
 			enable-method = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			cache-size = <0x20000>;
@@ -85,6 +93,9 @@
 			device_type = "cpu";
 			compatible = "qcom,kryo";
 			reg = <0x0 0x200>;
+			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
+			power-domains = <&CPU_PD2>;
+			power-domain-names = "psci";
 			enable-method = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			cache-size = <0x20000>;
@@ -102,6 +113,9 @@
 			device_type = "cpu";
 			compatible = "qcom,kryo";
 			reg = <0x0 0x300>;
+			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
+			power-domains = <&CPU_PD3>;
+			power-domain-names = "psci";
 			enable-method = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			cache-size = <0x20000>;
@@ -119,6 +133,9 @@
 			device_type = "cpu";
 			compatible = "qcom,kryo";
 			reg = <0x0 0x10000>;
+			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
+			power-domains = <&CPU_PD4>;
+			power-domain-names = "psci";
 			enable-method = "psci";
 			cache-size = <0x20000>;
 			cpu-release-addr = <0x0 0x90000000>;
@@ -142,6 +159,9 @@
 			device_type = "cpu";
 			compatible = "qcom,kryo";
 			reg = <0x0 0x10100>;
+			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
+			power-domains = <&CPU_PD5>;
+			power-domain-names = "psci";
 			enable-method = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			cache-size = <0x20000>;
@@ -159,6 +179,9 @@
 			device_type = "cpu";
 			compatible = "qcom,kryo";
 			reg = <0x0 0x10200>;
+			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
+			power-domains = <&CPU_PD6>;
+			power-domain-names = "psci";
 			enable-method = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			cache-size = <0x20000>;
@@ -176,6 +199,9 @@
 			device_type = "cpu";
 			compatible = "qcom,kryo";
 			reg = <0x0 0x10300>;
+			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
+			power-domains = <&CPU_PD7>;
+			power-domain-names = "psci";
 			enable-method = "psci";
 			cpu-release-addr = <0x0 0x90000000>;
 			cache-size = <0x20000>;
@@ -227,6 +253,46 @@
 			};
 		};
 	};
+
+	idle-states {
+		GOLD_OFF: gold-c3 {  /* C3 */
+			compatible = "arm,idle-state";
+			idle-state-name = "pc";
+			entry-latency-us = <549>;
+			exit-latency-us = <901>;
+			min-residency-us = <1774>;
+			arm,psci-suspend-param = <0x40000003>;
+			local-timer-stop;
+		};
+
+		GOLD_RAIL_OFF: gold-c4 {  /* C4 */
+			compatible = "arm,idle-state";
+			idle-state-name = "rail-pc";
+			entry-latency-us = <702>;
+			exit-latency-us = <1061>;
+			min-residency-us = <4488>;
+			arm,psci-suspend-param = <0x40000004>;
+			local-timer-stop;
+		};
+
+		GOLD_CLUSTER_D4: gold-cluster-d4 { /* D4 */
+			compatible = "domain-idle-state";
+			idle-state-name = "pwr-l2-pc";
+			entry-latency-us = <2752>;
+			exit-latency-us = <3048>;
+			min-residency-us = <6118>;
+			arm,psci-suspend-param = <0x41000044>;
+		};
+
+		APSS_OFF: cluster-e3 { /* E3 */
+			compatible = "domain-idle-state";
+			idle-state-name = "llcc-off";
+			entry-latency-us = <3263>;
+			exit-latency-us = <6562>;
+			min-residency-us = <9987>;
+			arm,psci-suspend-param = <0x42000144>;
+		};
+	};
 };
 
 &firmware {
@@ -312,12 +378,12 @@
 		reg = <0x0 0x95c00000 0x0 0x1e00000>;
 	};
 
-	pil_gdsp0_mem: pil_gdsp0_region@97b00000 {
+	rproc_gpdsp0_mem: rproc_gpdsp0_region@97b00000 {
 		no-map;
 		reg = <0x0 0x97b00000 0x0 0x1e00000>;
 	};
 
-	pil_gdsp1_mem: pil_gdsp1_region@99900000 {
+	rproc_gpdsp1_mem: rproc_gpdsp1_region@99900000 {
 		no-map;
 		reg = <0x0 0x99900000 0x0 0x1e00000>;
 	};
@@ -332,7 +398,7 @@
 		reg = <0x0 0x9d600000 0x0 0x2000>;
 	};
 
-	pil_cdsp1_mem: pil_cdsp1_region@9d700000 {
+	rproc_cdsp1_mem: rproc_cdsp1_region@9d700000 {
 		no-map;
 		reg = <0x0 0x9d700000 0x0 0x1e00000>;
 	};
@@ -460,9 +526,80 @@
 	ranges = <0 0 0 0xffffffff>;
 	compatible = "simple-bus";
 
+	qfprom: qfprom@780158 {
+		compatible = "qcom,qfprom";
+		reg = <0x00780158 0x4004>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		read-only;
+		ranges;
+
+		gpu_speed_bin: gpu_speed_bin@4002 {
+			reg = <0x4002 0x2>;
+			bits = <4 8>;
+		};
+	};
+
 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
+
+		CPU_PD0: cpu-pd0 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD0>;
+		};
+
+		CPU_PD1: cpu-pd1 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD0>;
+		};
+
+		CPU_PD2: cpu-pd2 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD0>;
+		};
+
+		CPU_PD3: cpu-pd3 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD0>;
+		};
+
+		CPU_PD4: cpu-pd4 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD1>;
+		};
+
+		CPU_PD5: cpu-pd5 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD1>;
+		};
+
+		CPU_PD6: cpu-pd6 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD1>;
+		};
+
+		CPU_PD7: cpu-pd7 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD1>;
+		};
+
+		CLUSTER_PD0: cluster-pd0 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD2>;
+			domain-idle-states = <&GOLD_CLUSTER_D4>;
+		};
+
+		CLUSTER_PD1: cluster-pd1 {
+			#power-domain-cells = <0>;
+			power-domains = <&CLUSTER_PD2>;
+			domain-idle-states = <&GOLD_CLUSTER_D4>;
+		};
+
+		CLUSTER_PD2: cluster-pd2 {
+			#power-domain-cells = <0>;
+			domain-idle-states = <&APSS_OFF>;
+		};
 	};
 
 	intc: interrupt-controller@17a00000 {
@@ -518,6 +655,7 @@
 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&CLUSTER_PD2>;
 
 		apps_rsc_drv2: drv@2 {
 			qcom,drv-id = <2>;
@@ -655,12 +793,51 @@
 		};
 	};
 
+	cluster-device0 {
+		compatible = "qcom,lpm-cluster-dev";
+		power-domains = <&CLUSTER_PD0>;
+	};
+
+	cluster-device1 {
+		compatible = "qcom,lpm-cluster-dev";
+		power-domains = <&CLUSTER_PD1>;
+	};
+
+	cluster-device2 {
+		compatible = "qcom,lpm-cluster-dev";
+		power-domains = <&CLUSTER_PD2>;
+	};
+
+	sys-pm-vx@c320000 {
+		compatible = "qcom,sys-pm-violators", "qcom,sys-pm-lemans";
+		reg = <0xc320000 0x0400>;
+		mboxes = <&qmp_aop 0>;
+		mbox-names = "aop";
+	};
+
+	soc-sleep-stats@c3f0000 {
+		compatible = "qcom,rpmh-sleep-stats";
+		reg = <0xc3f0000 0x400>;
+		qcom,drv-max = <0x14>;
+		ss-name = "adsp", "cdsp", "apss";
+		mboxes = <&qmp_aop 0>;
+		mbox-names = "aop";
+		ddr-freq-update;
+	};
+
+	subsystem-sleep-stats@c3f0000 {
+		compatible = "qcom,subsystem-sleep-stats";
+		reg = <0xc3f0000 0x400>;
+		ddr-freq-update;
+	};
+
 	tlmm: pinctrl@f000000 {
 		compatible = "qcom,lemans-pinctrl";
 		reg = <0xf000000 0x1000000>;
 		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 		gpio-controller;
 		#gpio-cells = <2>;
+		wakeup-parent = <&pdc>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
 	};
@@ -956,6 +1133,7 @@
 		#interconnect-cells = <1>;
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
+		qcom,skip-qos;
 	};
 
 	system_noc: interconnect@01680000 {
@@ -964,6 +1142,7 @@
 		#interconnect-cells = <1>;
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
+		qcom,skip-qos;
 	};
 
 	aggre1_noc:interconnect@016C0000 {
@@ -972,6 +1151,7 @@
 		#interconnect-cells = <1>;
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
+		qcom,skip-qos;
 		clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
 			<&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>,
 			<&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
@@ -985,6 +1165,7 @@
 		#interconnect-cells = <1>;
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
+		qcom,skip-qos;
 		clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
 			<&rpmhcc RPMH_IPA_CLK>;
 	};
@@ -995,6 +1176,7 @@
 		#interconnect-cells = <1>;
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
+		qcom,skip-qos;
 	};
 
 	gpdsp_anoc: interconnect@01780000 {
@@ -1003,6 +1185,7 @@
 		#interconnect-cells = <1>;
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
+		qcom,skip-qos;
 	};
 
 	mmss_noc: interconnect@017A0000 {
@@ -1011,6 +1194,7 @@
 		#interconnect-cells = <1>;
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
+		qcom,skip-qos;
 	};
 
 	lpass_ag_noc: interconnect@03C40000 {
@@ -1019,6 +1203,7 @@
 		#interconnect-cells = <1>;
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
+		qcom,skip-qos;
 	};
 
 	dc_noc: interconnect@090E0000 {
@@ -1027,6 +1212,7 @@
 		#interconnect-cells = <1>;
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
+		qcom,skip-qos;
 	};
 
 	gem_noc: interconnect@09100000 {
@@ -1036,6 +1222,7 @@
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
 		clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>;
+		qcom,skip-qos;
 	};
 
 	nspa_noc: interconnect@260C0000 {
@@ -1044,6 +1231,7 @@
 		#interconnect-cells = <1>;
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
+		qcom,skip-qos;
 	};
 
 	nspb_noc: interconnect@2A0C0000 {
@@ -1052,6 +1240,7 @@
 		#interconnect-cells = <1>;
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
+		qcom,skip-qos;
 	};
 
 	vendor_hooks: qcom,cpu-vendor-hooks {
@@ -1084,7 +1273,7 @@
 		reg-names = "cx","mx";
 
 		/* Inputs from lpass */
-		interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+		interrupts-extended = <&intc GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
 				<&adsp_smp2p_in 0 0>,
 				<&adsp_smp2p_in 2 0>,
 				<&adsp_smp2p_in 1 0>,
@@ -1150,7 +1339,7 @@
 		reg-names = "cx","mx","nsp0";
 
 		interconnects = <&nspa_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
-		interconnect-names = "crypto_ddr";
+		interconnect-names = "rproc_ddr";
 
 		/* Inputs from turing */
 		interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
@@ -1171,7 +1360,7 @@
 		qcom,smem-states = <&cdsp_smp2p_out 0>;
 		qcom,smem-state-names = "stop";
 
-		glink_cdsp0: glink-edge {
+		glink_cdsp: glink-edge {
 			qcom,remote-pid = <5>;
 			transport = "smem";
 			mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
@@ -1182,8 +1371,8 @@
 				      IPCC_MPROC_SIGNAL_GLINK_QMP
 				      IRQ_TYPE_EDGE_RISING>;
 
-			label = "cdsp0";
-			qcom,glink-label = "cdsp0";
+			label = "cdsp";
+			qcom,glink-label = "cdsp";
 
 			qcom,cdsp0_qrtr {
 				qcom,glink-channels = "IPCRTR";
@@ -1200,6 +1389,188 @@
 		};
 	};
 
+	cdsp1_pas: remoteproc-cdsp1@2a300000 {
+		compatible = "qcom,lemans-cdsp1-pas";
+		reg = <0x2A300000 0x10000>;
+		status = "ok";
+
+		memory-region = <&rproc_cdsp1_mem>;
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		cx-supply = <&VDD_CX_LEVEL>;
+		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		mx-supply = <&VDD_MXC_LEVEL>;
+		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		nsp0-supply = <&VDD_NSP_0_LEVEL>;
+		nsp0-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		reg-names = "cx","mx","nsp0";
+
+		interconnects = <&nspb_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
+		interconnect-names = "rproc_ddr";
+
+		/* Inputs from turing */
+		interrupts-extended = <&intc GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>,
+			<&cdsp1_smp2p_in 0 0>,
+			<&cdsp1_smp2p_in 2 0>,
+			<&cdsp1_smp2p_in 1 0>,
+			<&cdsp1_smp2p_in 3 0>;
+
+		interrupt-names = "wdog",
+			"fatal",
+			"handover",
+			"ready",
+			"stop-ack";
+
+		qcom,qmp = <&aoss_qmp>;
+
+		/* Outputs to turing */
+		qcom,smem-states = <&cdsp1_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		glink_cdsp1: glink-edge {
+			qcom,remote-pid = <12>;
+			transport = "smem";
+			mboxes = <&ipcc_mproc IPCC_CLIENT_NSP1
+				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+			mbox-names = "cdsp1_smem";
+			interrupt-parent = <&ipcc_mproc>;
+			interrupts = <IPCC_CLIENT_NSP1
+				      IPCC_MPROC_SIGNAL_GLINK_QMP
+				      IRQ_TYPE_EDGE_RISING>;
+
+			label = "cdsp1";
+			qcom,glink-label = "cdsp1";
+
+			qcom,cdsp1_qrtr {
+				qcom,glink-channels = "IPCRTR";
+				qcom,intents = <0x800  5
+						0x2000 3
+						0x4400 2>;
+			};
+		};
+
+	};
+
+	gpdsp0_pas: remoteproc-gpdsp0@20c00000 {
+		compatible = "qcom,lemans-gpdsp0-pas";
+		reg = <0x20c00000 0x10000>;
+		status = "ok";
+
+		memory-region = <&rproc_gpdsp0_mem>;
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		cx-supply = <&VDD_CX_LEVEL>;
+		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		mx-supply = <&VDD_MXC_LEVEL>;
+		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		qcom,proxy-reg-names = "cx","mx";
+
+		interconnects = <&gpdsp_anoc MASTER_DSP0 &config_noc SLAVE_CLK_CTL>;
+		interconnect-names = "rproc_ddr";
+
+		interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
+			<&gpdsp0_smp2p_in 0 0>,
+			<&gpdsp0_smp2p_in 2 0>,
+			<&gpdsp0_smp2p_in 1 0>,
+			<&gpdsp0_smp2p_in 3 0>;
+
+		interrupt-names = "wdog",
+			"fatal",
+			"handover",
+			"ready",
+			"stop-ack";
+
+		qcom,qmp = <&aoss_qmp>;
+
+		qcom,smem-states = <&gpdsp0_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		glink_gpdsp0: glink-edge {
+			qcom,remote-pid = <17>;
+			transport = "smem";
+			mboxes = <&ipcc_mproc IPCC_CLIENT_GPDSP0
+				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+			mbox-names = "gpdsp0_smem";
+			interrupt-parent = <&ipcc_mproc>;
+			interrupts = <IPCC_CLIENT_GPDSP0
+				      IPCC_MPROC_SIGNAL_GLINK_QMP
+				      IRQ_TYPE_EDGE_RISING>;
+
+			label = "gpdsp0";
+			qcom,glink-label = "gpdsp0";
+
+			qcom,gpdsp0_qrtr {
+				qcom,glink-channels = "IPCRTR";
+				qcom,intents = <0x800  5
+						0x2000 3
+						0x4400 2>;
+			};
+		};
+	};
+
+	gpdsp1_pas: remoteproc-gpdsp1@21c00000 {
+		compatible = "qcom,lemans-gpdsp1-pas";
+		reg = <0x21c00000 0x10000>;
+		status = "ok";
+
+		memory-region = <&rproc_gpdsp1_mem>;
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+
+		cx-supply = <&VDD_CX_LEVEL>;
+		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		mx-supply = <&VDD_MXC_LEVEL>;
+		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+		qcom,proxy-reg-names = "cx","mx";
+
+		interconnects = <&gpdsp_anoc MASTER_DSP1 &config_noc SLAVE_CLK_CTL>;
+		interconnect-names = "rproc_ddr";
+
+		interrupts-extended = <&intc GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH>,
+			<&gpdsp1_smp2p_in 0 0>,
+			<&gpdsp1_smp2p_in 2 0>,
+			<&gpdsp1_smp2p_in 1 0>,
+			<&gpdsp1_smp2p_in 3 0>;
+
+		interrupt-names = "wdog",
+			"fatal",
+			"handover",
+			"ready",
+			"stop-ack";
+
+		qcom,qmp = <&aoss_qmp>;
+
+		qcom,smem-states = <&gpdsp1_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+
+		glink_gpdsp1: glink-edge {
+			qcom,remote-pid = <18>;
+			transport = "smem";
+			mboxes = <&ipcc_mproc IPCC_CLIENT_GPDSP1
+				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
+			mbox-names = "gpdsp1_smem";
+			interrupt-parent = <&ipcc_mproc>;
+			interrupts = <IPCC_CLIENT_GPDSP1
+				      IPCC_MPROC_SIGNAL_GLINK_QMP
+				      IRQ_TYPE_EDGE_RISING>;
+
+			label = "gpdsp1";
+			qcom,glink-label = "gpdsp1";
+
+			qcom,gpdsp1_qrtr {
+				qcom,glink-channels = "IPCRTR";
+				qcom,intents = <0x800  5
+						0x2000 3
+						0x4400 2>;
+			};
+		};
+	};
+
 	spmi_bus: qcom,spmi@c440000 {
 		compatible = "qcom,spmi-pmic-arb";
 		reg = <0xc440000 0x1100>,
@@ -1351,7 +1722,6 @@
 		iommus = <&apps_smmu 0x100 0x0>;
 		qcom,iommu-dma = "fastmap";
 		dma-coherent;
-		qcom,disable-lpm;
 
 		status = "disabled";
 
@@ -1366,6 +1736,151 @@
 		};
 	};
 
+	ufs2phy_mem: ufsphy2_mem@1da7000 {
+		reg = <0x1da7000 0xe10>;
+		reg-names = "phy_mem";
+		#phy-cells = <0>;
+
+		lanes-per-direction = <2>;
+		clock-names = "ref_clk_src",
+			"ref_clk",
+			"ref_aux_clk";
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_EDP_REF_CLKREF_EN>,
+			<&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
+		resets = <&ufshc2_mem 0>;
+		status = "disabled";
+	};
+
+	ufshc2_mem: ufshc2@1da4000 {
+		compatible = "qcom,ufshc";
+		reg = <0x1da4000 0x3000>;
+		reg-names = "ufs_mem";
+		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+		phys = <&ufs2phy_mem>;
+		phy-names = "ufsphy";
+		#reset-cells = <1>;
+
+		lanes-per-direction = <2>;
+		dev-ref-clk-freq = <0>; /* 19.2 MHz */
+
+		clock-names =
+			"core_clk",
+			"bus_aggr_clk",
+			"iface_clk",
+			"core_clk_unipro",
+			"core_clk_ice",
+			"ref_clk",
+			"tx_lane0_sync_clk",
+			"rx_lane0_sync_clk",
+			"rx_lane1_sync_clk";
+
+		clocks =
+			<&gcc GCC_UFS_CARD_AXI_CLK>,
+			<&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
+			<&gcc GCC_UFS_CARD_AHB_CLK>,
+			<&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
+			<&gcc GCC_UFS_CARD_ICE_CORE_CLK>,
+			<&rpmhcc RPMH_CXO_CLK>,
+			<&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
+			<&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
+			<&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
+
+		freq-table-hz =
+			<75000000 300000000>,
+			<0 0>,
+			<0 0>,
+			<75000000 300000000>,
+			<75000000 300000000>,
+			<0 0>,
+			<0 0>,
+			<0 0>,
+			<0 0>;
+
+		interconnects = <&aggre2_noc MASTER_UFS_CARD &mc_virt SLAVE_EBI1>,
+		      <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_CARD_CFG>;
+		interconnect-names = "ufs-ddr", "cpu-ufs";
+
+		qcom,ufs-bus-bw,name = "ufshc_mem";
+		qcom,ufs-bus-bw,num-cases = <26>;
+		qcom,ufs-bus-bw,num-paths = <2>;
+		qcom,ufs-bus-bw,vectors-KBps =
+		/*
+		 * During HS G3 UFS runs at nominal voltage corner, vote
+		 * higher bandwidth to push other buses in the data path
+		 * to run at nominal to achieve max throughput.
+		 * 4GBps pushes BIMC to run at nominal.
+		 * 200MBps pushes CNOC to run at nominal.
+		 * Vote for half of this bandwidth for HS G3 1-lane.
+		 * For max bandwidth, vote high enough to push the buses
+		 * to run in turbo voltage corner.
+		 */
+		<0 0>, <0 0>,          /* No vote */
+		<922 0>, <1000 0>,     /* PWM G1 */
+		<1844 0>, <1000 0>,    /* PWM G2 */
+		<3688 0>, <1000 0>,    /* PWM G3 */
+		<7376 0>, <1000 0>,    /* PWM G4 */
+		<1844 0>, <1000 0>,    /* PWM G1 L2 */
+		<3688 0>, <1000 0>,    /* PWM G2 L2 */
+		<7376 0>, <1000 0>,    /* PWM G3 L2 */
+		<14752 0>, <1000 0>,   /* PWM G4 L2 */
+		<127796 0>, <1000 0>,  /* HS G1 RA */
+		<255591 0>, <1000 0>,  /* HS G2 RA */
+		<1492582 0>, <102400 0>,  /* HS G3 RA */
+		<2915200 0>, <204800 0>,  /* HS G4 RA */
+		<255591 0>, <1000 0>,  /* HS G1 RA L2 */
+		<511181 0>, <1000 0>,  /* HS G2 RA L2 */
+		<1492582 0>, <204800 0>, /* HS G3 RA L2 */
+		<2915200 0>, <409600 0>, /* HS G4 RA L2 */
+		<149422 0>, <1000 0>,  /* HS G1 RB */
+		<298189 0>, <1000 0>,  /* HS G2 RB */
+		<1492582 0>, <102400 0>,  /* HS G3 RB */
+		<2915200 0>, <204800 0>,  /* HS G4 RB */
+		<298189 0>, <1000 0>,  /* HS G1 RB L2 */
+		<596378 0>, <1000 0>,  /* HS G2 RB L2 */
+		/* As UFS working in HS G3 RB L2 mode, aggregated
+		 * bandwidth (AB) should take care of providing
+		 * optimum throughput requested. However, as tested,
+		 * in order to scale up CNOC clock, instantaneous
+		 * bindwidth (IB) needs to be given a proper value too.
+		 */
+		<1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */
+		<2915200 0>, <409600 409600>, /* HS G4 RB L2 */
+		<7643136 0>, <307200 0>; /* Max. bandwidth */
+
+		qcom,bus-vector-names = "MIN",
+		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
+		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
+		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
+		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
+		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
+		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
+		"MAX";
+
+		reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
+
+		resets = <&gcc GCC_UFS_CARD_BCR>;
+		reset-names = "rst";
+		iommus = <&apps_smmu 0x420 0x0>;
+		qcom,iommu-dma = "fastmap";
+		dma-coherent;
+
+		secondary-storage;
+
+		status = "disabled";
+
+		qos0 {
+			mask = <0xf0>;
+			vote = <44>;
+		};
+
+		qos1 {
+			mask = <0x0f>;
+			vote = <44>;
+		};
+
+	};
+
 	tcsr_mutex_block: syscon@1f40000 {
 		compatible = "syscon";
 		reg = <0x1f40000 0x20000>;
@@ -1435,6 +1950,13 @@
 		hyplog-size-offset = <0x414>;
 	};
 
+	qcom_rng: qrng@10d2000 {
+		compatible = "qcom,msm-rng";
+		reg = <0x010d2000 0x1000>;
+		qcom,no-qrng-config;
+		qcom,no-clock-support;
+	};
+
 	qcom,glinkpkt {
 		compatible = "qcom,glinkpkt";
 
@@ -1490,6 +2012,28 @@
 		};
 	};
 
+	qcom,smp2p-cdsp1@1799000c {
+		compatible = "qcom,smp2p";
+		qcom,smem = <617>, <616>;
+		interrupt-parent = <&ipcc_mproc>;
+		interrupts = <IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P
+			      IRQ_TYPE_EDGE_RISING>;
+		mboxes = <&ipcc_mproc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P>;
+		qcom,local-pid = <0>;
+		qcom,remote-pid = <12>;
+
+		cdsp1_smp2p_out: master-kernel {
+			qcom,entry-name = "master-kernel";
+			#qcom,smem-state-cells = <1>;
+		};
+
+		cdsp1_smp2p_in: slave-kernel {
+			qcom,entry-name = "slave-kernel";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
 	qcom,smp2p-gpdsp0 {
 		compatible = "qcom,smp2p";
 		qcom,smem = <617>, <616>;
@@ -1535,6 +2079,257 @@
 			#interrupt-cells = <2>;
 		};
 	};
+
+	qcom,mpm2-sleep-counter@c221000 {
+		compatible = "qcom,mpm2-sleep-counter";
+		reg = <0xc221000 0x1000>;
+		clock-frequency = <32768>;
+	};
+
+	cpu_pmu: cpu-pmu {
+		compatible = "arm,armv8-pmuv3";
+		qcom,irq-is-percpu;
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	llcc_pmu: llcc-pmu@9095000 {
+		compatible = "qcom,llcc-pmu-ver2";
+		reg = <0x09095000 0x300>;
+		reg-names = "lagg-base";
+	};
+
+	msm_gpu: qcom,kgsl-3d0@3d00000 { };
+
+	qcom,msm-cdsp-loader {
+		compatible = "qcom,cdsp-loader";
+		qcom,proc-img-to-load = "cdsp";
+		qcom,rproc-handle = <&cdsp_pas>;
+	};
+
+	qcom,msm-adsprpc-mem {
+		compatible = "qcom,msm-adsprpc-mem-region";
+		memory-region = <&adsp_mem>;
+	};
+
+	msm_fastrpc: qcom,msm_fastrpc {
+		compatible = "qcom,msm-fastrpc-compute";
+		qcom,adsp-remoteheap-vmid = <22 37>;
+		qcom,fastrpc-adsp-audio-pdr;
+		qcom,rpc-latency-us = <235>;
+		qcom,fastrpc-gids = <2908>;
+		qcom,qos-cores = <0 1 2 3>;
+
+		qcom,msm_fastrpc_compute_cb0_1 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x21C1 0x0000>,
+				 <&apps_smmu 0x2161 0x0000>,
+				 <&apps_smmu 0x2141 0x0000>,
+				 <&apps_smmu 0x21E1 0x0000>,
+				 <&apps_smmu 0x2181 0x0000>,
+				 <&apps_smmu 0x25C1 0x0000>,
+				 <&apps_smmu 0x2561 0x0000>,
+				 <&apps_smmu 0x2541 0x0000>,
+				 <&apps_smmu 0x25E1 0x0000>,
+				 <&apps_smmu 0x2581 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb0_2 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x21C2 0x0000>,
+				 <&apps_smmu 0x2162 0x0000>,
+				 <&apps_smmu 0x2142 0x0000>,
+				 <&apps_smmu 0x21E2 0x0000>,
+				 <&apps_smmu 0x2182 0x0000>,
+				 <&apps_smmu 0x25C2 0x0000>,
+				 <&apps_smmu 0x2562 0x0000>,
+				 <&apps_smmu 0x2542 0x0000>,
+				 <&apps_smmu 0x25E2 0x0000>,
+				 <&apps_smmu 0x2582 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb0_3 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x21C3 0x0000>,
+				 <&apps_smmu 0x2163 0x0000>,
+				 <&apps_smmu 0x2143 0x0000>,
+				 <&apps_smmu 0x21E3 0x0000>,
+				 <&apps_smmu 0x2183 0x0000>,
+				 <&apps_smmu 0x25C3 0x0000>,
+				 <&apps_smmu 0x2563 0x0000>,
+				 <&apps_smmu 0x2543 0x0000>,
+				 <&apps_smmu 0x25E3 0x0000>,
+				 <&apps_smmu 0x2583 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_cb0_4 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "cdsprpc-smd";
+			iommus = <&apps_smmu 0x21C4 0x0000>,
+				 <&apps_smmu 0x2164 0x0000>,
+				 <&apps_smmu 0x2144 0x0000>,
+				 <&apps_smmu 0x21E4 0x0000>,
+				 <&apps_smmu 0x2184 0x0000>,
+				 <&apps_smmu 0x25C4 0x0000>,
+				 <&apps_smmu 0x2564 0x0000>,
+				 <&apps_smmu 0x2544 0x0000>,
+				 <&apps_smmu 0x25E4 0x0000>,
+				 <&apps_smmu 0x2584 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_adsp_cb1 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x3003 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_adsp_cb2 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x3004 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+
+		qcom,msm_fastrpc_compute_adsp_cb3 {
+			compatible = "qcom,msm-fastrpc-compute-cb";
+			label = "adsprpc-smd";
+			iommus = <&apps_smmu 0x3005 0x0000>;
+			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+			qcom,iommu-faults = "stall-disable", "HUPCF";
+			dma-coherent;
+		};
+	};
+
+	mtl_rx_setup: rx-queues-config {
+		snps,rx-queues-to-use = <4>;
+		snps,rx-sched-sp;
+
+		queue0 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x0>;
+			snps,route-up;
+			snps,priority = <0x1>;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x1>;
+			snps,route-ptp;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x2>;
+			snps,route-avcp;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,map-to-dma-channel = <0x3>;
+			snps,priority = <0xC>;
+		};
+	};
+
+	mtl_tx_setup: tx-queues-config {
+		snps,tx-queues-to-use = <4>;
+		snps,tx-sched-sp;
+		queue0 {
+			snps,dcb-algorithm;
+		};
+
+		queue1 {
+			snps,dcb-algorithm;
+		};
+
+		queue2 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3E800>;
+			snps,low_credit = <0xFFC18000>;
+		};
+
+		queue3 {
+			snps,avb-algorithm;
+			snps,send_slope = <0x1000>;
+			snps,idle_slope = <0x1000>;
+			snps,high_credit = <0x3E800>;
+			snps,low_credit = <0xFFC18000>;
+		};
+
+	};
+
+	ethqos_hw: qcom,ethernet@23040000 {
+		compatible = "qcom,stmmac-ethqos", "snps,dwmac-4.20a";
+		reg = <0x23040000 0x10000>,
+				<0x23056000 0x100>,
+				<0x08901000 0xE10>,
+				<0x23056100 0x100>;
+
+		reg-names = "stmmaceth", "rgmii","serdes","reseteth";
+		clocks = <&gcc GCC_EMAC0_AXI_CLK>,
+				<&gcc GCC_EMAC0_SLV_AHB_CLK>,
+				<&gcc GCC_EMAC0_PTP_CLK>,
+				<&gcc GCC_EMAC0_PHY_AUX_CLK>,
+				<&gcc GCC_SGMI_CLKREF_EN>,
+				<&gcc GCC_EMAC0_RGMII_CLK>;
+		clock-names = "stmmaceth", "pclk", "ptp_ref", "phyaux","sgmi_ref","rgmii";
+		snps,ptp-ref-clk-rate = <250000000>;
+		snps,ptp-req-clk-rate = <96000000>;
+		interrupts-extended = <&intc 0 946 4>;
+		qcom,arm-smmu;
+
+		interrupt-names = "macirq";
+
+		snps,tso;
+		snps,pbl = <32>;
+		rx-fifo-depth = <16384>;
+		tx-fifo-depth = <20480>;
+
+		snps,mtl-rx-config = <&mtl_rx_setup>;
+		snps,mtl-tx-config = <&mtl_tx_setup>;
+
+		vreg_emac_phy-supply =  <&pm8775_a_l5>;
+		vreg_rgmii_io_pads-supply = <&pm8775_c_l1>;
+
+		gdsc_emac-supply = <&gcc_emac0_gdsc>;
+
+		phy-mode = "sgmii";
+		snps,reset-delays-us = <0 11000 70000>;
+		pinctrl-names = "dev-emac-mdc",
+				"dev-emac-mdio";
+
+		pinctrl-0 = <&emac_mdc>;
+		pinctrl-1 = <&emac_mdio>;
+
+		snps,ps-speed = <1000>;
+
+		ethqos_emb_smmu: ethqos_emb_smmu {
+			compatible = "qcom,emac-smmu-embedded";
+			iommus = <&apps_smmu 0x120 0xf>;
+			qcom,iommu-dma = "fastmap";
+			qcom,iommu-dma-addr-pool = <0x80000000 0x40000000>;
+		};
+	};
 };
 
 #include "lemans-4pmic-regulators.dtsi"
@@ -1546,6 +2341,7 @@
 #include "lemans-qupv3.dtsi"
 #include "lemans-pcie.dtsi"
 #include "lemans-usb.dtsi"
+#include "lemans-coresight.dtsi"
 
 &cam_cc_titan_top_gdsc {
 	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
@@ -1718,7 +2514,6 @@
 	vdd-hba-fixed-regulator;
 
 	vcc-supply = <&L8A>;
-	vcc-voltage-level = <2504000 2506000>;
 	vcc-max-microamp = <1100000>;
 
 	vccq-supply = <&L4C>;
@@ -1733,6 +2528,37 @@
 	status = "ok";
 };
 
+&ufs2phy_mem {
+	compatible = "qcom,ufs-phy-qmp-v4-waipio";
+
+	vdda-phy-supply = <&L4A>;
+	vdda-pll-supply = <&L1C>;
+	vdda-phy-max-microamp = <137000>;
+	vdda-pll-max-microamp = <18300>;
+
+	status = "ok";
+};
+
+&ufshc2_mem {
+	vdd-hba-supply = <&gcc_ufs_card_gdsc>;
+	vdd-hba-fixed-regulator;
+
+	vcc-supply = <&L8C>;
+	vcc-voltage-level = <2504000 2506000>;
+	vcc-max-microamp = <1100000>;
+
+	vccq-supply = <&L5C>;
+	vccq-max-microamp = <1200000>;
+
+	vccq2-supply = <&S4A>;
+	vccq2-max-microamp = <800000>;
+
+	qcom,vddp-ref-clk-supply = <&L5C>;
+	qcom,vddp-ref-clk-max-microamp = <100>;
+
+	status = "ok";
+};
+
 &qupv3_se10_2uart {
 	status = "ok";
 };
diff --git a/qcom/monaco-coresight.dtsi b/qcom/monaco-coresight.dtsi
index df3db582..a6b8c43c 100755
--- a/qcom/monaco-coresight.dtsi
+++ b/qcom/monaco-coresight.dtsi
@@ -1419,6 +1419,7 @@
 		reg-names = "tmc-base","bam-base";
 
 		coresight-name = "coresight-tmc-etr";
+		qcom,mem_support;
 
 		iommus = <&apps_smmu 0x0180 0>,
 			<&apps_smmu 0x0160 0>;
@@ -1457,7 +1458,7 @@
 
 	cti_cortex_m3: cti@8b30000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8b30000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1469,7 +1470,7 @@
 
 	cti_apss_cti0: cti@98e0000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x98e0000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1481,7 +1482,7 @@
 
 	cti_apss_cti1: cti@98f0000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x98f0000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1493,7 +1494,7 @@
 
 	cti_wcss_cti0: cti@89a4000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x89a4000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1506,7 +1507,7 @@
 
 	cti_wcss_cti1: cti@89a5000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x89a5000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1519,7 +1520,7 @@
 
 	cti_wcss_cti2: cti@89a6000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x89a6000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1532,7 +1533,7 @@
 
 	cti_lpass_lpi: cti@8a21000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8a21000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1545,7 +1546,7 @@
 
 	cti_lpass_q6: cti@8a2b000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8a2b000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1558,7 +1559,7 @@
 
 	cti_mss_q6: cti@8833000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8833000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1570,7 +1571,7 @@
 
 	cti_isdb_gpu: cti@8941000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8941000 0x1000>;
 		reg-names = "cti-base";
 		coresight-name = "coresight-cti-isdb-gpu";
@@ -1582,7 +1583,7 @@
 
 	cti_mapss: cti@8a02000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8a02000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1594,7 +1595,7 @@
 
 	cti_dlct_cti0: cti@8b59000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8b59000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1606,7 +1607,7 @@
 
 	cti_dlct_cti1: cti@8b5a000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8b5a000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1618,7 +1619,7 @@
 
 	cti_dlct_cti2: cti@8b5b000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8b5b000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1630,7 +1631,7 @@
 
 	cti_dlct_cti3: cti@8b5c000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8b5c000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1642,7 +1643,7 @@
 
 	cti0: cti@8010000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8010000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1654,7 +1655,7 @@
 
 	cti1: cti@8011000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8011000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1666,7 +1667,7 @@
 
 	cti2: cti@8012000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8012000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1683,7 +1684,7 @@
 
 	cti3: cti@8013000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8013000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1695,7 +1696,7 @@
 
 	cti4: cti@8014000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8014000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1707,7 +1708,7 @@
 
 	cti5: cti@8015000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8015000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1719,7 +1720,7 @@
 
 	cti6: cti@8016000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8016000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1731,7 +1732,7 @@
 
 	cti7: cti@8017000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8017000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1743,7 +1744,7 @@
 
 	cti8: cti@8018000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8018000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1755,7 +1756,7 @@
 
 	cti9: cti@8019000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x8019000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1767,7 +1768,7 @@
 
 	cti10: cti@801a000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x801a000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1779,7 +1780,7 @@
 
 	cti11: cti@801b000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x801b000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1791,7 +1792,7 @@
 
 	cti12: cti@801c000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x801c000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1803,7 +1804,7 @@
 
 	cti13: cti@801d000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x801d000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1815,7 +1816,7 @@
 
 	cti14: cti@801e000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x801e000 0x1000>;
 		reg-names = "cti-base";
 
@@ -1827,7 +1828,7 @@
 
 	cti15: cti@801f000 {
 		compatible = "arm,primecell";
-		arm,primecell-periphid = <0x000bb966>;
+		arm,primecell-periphid = <0x000bb9a8>;
 		reg = <0x801f000 0x1000>;
 		reg-names = "cti-base";
 
diff --git a/qcom/monaco-idp-v1.dtsi b/qcom/monaco-idp-v1.dtsi
index 46a0a0f2..09e756db 100755
--- a/qcom/monaco-idp-v1.dtsi
+++ b/qcom/monaco-idp-v1.dtsi
@@ -4,14 +4,6 @@
 #include <dt-bindings/clock/qcom,rpmcc.h>
 #include "slate.dtsi"
 
-&soc {
-	bluetooth: bt_wcn3990 {
-		compatible = "qcom,qcc5100";
-
-		status = "ok";
-	};
-};
-
 &pm5100_charger {
 	qcom,remote-fg;
 	#io-channel-cells = <1>;
diff --git a/qcom/monaco-pinctrl.dtsi b/qcom/monaco-pinctrl.dtsi
index aaf4f203..4f8c8891 100755
--- a/qcom/monaco-pinctrl.dtsi
+++ b/qcom/monaco-pinctrl.dtsi
@@ -642,24 +642,37 @@
 				config {
 					pins = "gpio23";
 					drive-strength = <6>;
-					bias-disable;
+					bias-pull-up;
 				};
 			};
 
 			qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
 				mux {
 					pins = "gpio20", "gpio21",
-						"gpio22", "gpio23";
+						"gpio22";
 					function = "gpio";
 				};
 
 				config {
 					pins = "gpio20", "gpio21",
-						"gio22", "gpio23";
+						"gio22";
 					drive-strength = <6>;
 					bias-disable;
 				};
 			};
+
+			qupv3_se4_spi_cs_sleep: qupv3_se4_spi_cs_sleep {
+				mux {
+					pins = "gpio23";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio23";
+					drive-strength = <6>;
+					bias-pull-up;
+				};
+			};
 		};
 
 		qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
diff --git a/qcom/monaco-pmic.dtsi b/qcom/monaco-pmic.dtsi
index dee99a19..5d3277df 100755
--- a/qcom/monaco-pmic.dtsi
+++ b/qcom/monaco-pmic.dtsi
@@ -103,12 +103,10 @@
 };
 
 &thermal_zones {
-	xo-therm-usr {
+	xo-therm {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX1_THM_100K_PU>;
-		wake-capable-sensor;
 		trips {
 			active-config0 {
 				temperature = <125000>;
@@ -118,12 +116,10 @@
 		};
 	};
 
-	pa-therm0-usr {
+	pa-therm0 {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX4_THM_100K_PU>;
-		wake-capable-sensor;
 		trips {
 			active-config0 {
 				temperature = <125000>;
@@ -133,12 +129,10 @@
 		};
 	};
 
-	quiet-therm-usr {
+	quiet-therm {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX5_THM_100K_PU>;
-		wake-capable-sensor;
 		trips {
 			active-config0 {
 				temperature = <125000>;
@@ -148,12 +142,10 @@
 		};
 	};
 
-	sdm-skin-therm-usr {
+	sdm-skin-therm {
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
-		thermal-governor = "user_space";
 		thermal-sensors = <&pm5100_adc PM5100_ADC5_GEN3_AMUX6_THM_100K_PU>;
-		wake-capable-sensor;
 		trips {
 			active-config0 {
 				temperature = <125000>;
@@ -173,6 +165,9 @@
 
 	monaco_batterydata: qcom,battery-data {
 		qcom,batt-id-range-pct = <15>;
+		#include "qbg-battery-profile-alium-860-89032-0000-3600mAh.dtsi"
+		#include "qbg-battery-profile-qrd-zwd-520mAh.dtsi"
+		#include "qbg-battery-profile-305mAh.dtsi"
 	};
 };
 
diff --git a/qcom/monaco-qupv3.dtsi b/qcom/monaco-qupv3.dtsi
index d1d513a0..b9484188 100755
--- a/qcom/monaco-qupv3.dtsi
+++ b/qcom/monaco-qupv3.dtsi
@@ -326,7 +326,7 @@
 			pinctrl-names = "default", "sleep";
 			pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>,
 				<&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>;
-			pinctrl-1 = <&qupv3_se4_spi_sleep>;
+			pinctrl-1 = <&qupv3_se4_spi_sleep>, <&qupv3_se4_spi_cs_sleep> ;
 			dmas = <&gpi_dma0 0 4 1 64 0>,
 				<&gpi_dma0 1 4 1 64 0>;
 			dma-names = "tx", "rx";
diff --git a/qcom/monaco-thermal.dtsi b/qcom/monaco-thermal.dtsi
index ae46ae06..b87f297a 100755
--- a/qcom/monaco-thermal.dtsi
+++ b/qcom/monaco-thermal.dtsi
@@ -286,8 +286,7 @@
 		cooling-maps {
 			mdm0-cx-cdev0 {
 				trip = <&mdm0_cx_mon>;
-				cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
-							THERMAL_MAX_LIMIT>;
+				cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>;
 			};
 
 			mdm0-cx-cdev1 {
@@ -324,8 +323,7 @@
 		cooling-maps {
 			mdm1-cx-cdev0 {
 				trip = <&mdm1_cx_mon>;
-				cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
-							THERMAL_MAX_LIMIT>;
+				cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>;
 			};
 
 			mdm1-cx-cdev1 {
@@ -374,8 +372,7 @@
 
 			gpu-cx-cdev0 {
 				trip = <&gpu_cx_mon>;
-				cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
-							THERMAL_MAX_LIMIT>;
+				cooling-device = <&msm_gpu 3 THERMAL_NO_LIMIT>;
 			};
 
 			gpu-cx-cdev1 {
@@ -443,7 +440,7 @@
 		polling-delay-passive = <0>;
 		polling-delay = <0>;
 		thermal-sensors = <&qmi_sensor
-				(QMI_MODEM_INST_ID)>;
+				(QMI_MODEM_INST_ID+QMI_RF_CAL)>;
 		trips {
 			rf_cal_trip: rf-cal-config {
 				temperature = <2000>;
diff --git a/qcom/monaco-wdp-v1.dtsi b/qcom/monaco-wdp-v1.dtsi
index 6fea5bc4..e90da247 100755
--- a/qcom/monaco-wdp-v1.dtsi
+++ b/qcom/monaco-wdp-v1.dtsi
@@ -1 +1,43 @@
 #include "monaco-idp-v1.dtsi"
+
+
+
+
+
+
+
+
+
+
+&qupv3_se1_i2c {
+	status = "ok";
+
+	tsc@24 {
+		compatible = "parade,pt_i2c_adapter";
+		reg = <0x24>;
+		status = "disabled";
+	};
+
+	raydium_ts@39 {
+		compatible = "raydium,raydium-ts";
+		reg = <0x39>;
+		status = "ok";
+		interrupt-parent = <&tlmm>;
+		interrupts = <13 0x2008>;
+		vdd_ana-supply = <&L29A>;
+		vcc_i2c-supply = <&L21A>;
+		pinctrl-names = "pmx_ts_active","pmx_ts_suspend","pmx_ts_release";
+		pinctrl-0 = <&ts_int_active &ts_reset_active>;
+		pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+		pinctrl-2 = <&ts_release>;
+		raydium,reset-gpio = <&tlmm 12 0x00>;
+		raydium,irq-gpio = <&tlmm 13 0x00>;
+		raydium,num-max-touches = <2>;
+		raydium,soft-reset-delay-ms = <50>;
+		raydium,hard-reset-delay-ms = <100>;
+		raydium,x_max = <320>;
+		raydium,y_max = <360>;
+		raydium,display-coords= <0 0 320 360>;
+	};
+};
+
diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi
index a7b4a2a8..a9ac408c 100755
--- a/qcom/monaco.dtsi
+++ b/qcom/monaco.dtsi
@@ -183,7 +183,7 @@
 	soc: soc { };
 
 	chosen {
-		bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
+		bootargs = "console=ttyMSM0,115200n8 loglevel=6 kpti=off log_buf_len=256K kernel.panic_on_rcu_stall=1 msm_rtb.filter=0x237 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops fw_devlink.strict=1 allow_mismatched_32bit_el0 printk.console_no_auto_verbose=1 irqaffinity=0-2";
 	};
 
 	reserved-memory {
@@ -537,7 +537,7 @@
 		};
 
 		pil@94c {
-			compatible = "qcom,msm-imem-pil";
+			compatible = "qcom,pil-reloc-info";
 			reg = <0x94c 0xc8>;
 		};
 
@@ -556,6 +556,15 @@
 		compatible = "qcom,dload-mode";
 	};
 
+	mini_dump_mode {
+		compatible = "qcom,minidump";
+		status = "ok";
+	};
+
+	vendor_hooks: qcom,cpu-vendor-hooks {
+		compatible = "qcom,cpu-vendor-hooks";
+	};
+
 	qcom,mpm2-slepp-counter@4403000 {
 		compatible = "qcom,mpm2-sleep-counter";
 		reg = <0x4403000 0x1000>;
@@ -623,6 +632,16 @@
 		compatible = "qcom,smcinvoke";
 	};
 
+	qcom_hwkm: hwkm@4440000 {
+		compatible = "qcom,hwkm";
+		reg = <0x4440000 0x9000>;
+		reg-names = "km_master";
+		qcom,enable-hwkm-clk;
+		clock-names = "km_clk_src";
+		clocks = <&rpmcc RPM_SMD_HWKM_CLK>;
+		qcom,op-freq-hz = <75000000>;
+	};
+
 	qcom_tzlog: tz-log@c125720 {
 		compatible = "qcom,tz-log";
 		reg = <0xc125720 0x3000>;
@@ -979,11 +998,11 @@
 		compatible = "qcom,monaco-adsp-pas";
 		reg = <0xab00000 0x00100>;
 
-		cx-supply = <&VDD_LPI_CX_LEVEL>;
+		vdd_lpi_cx-supply = <&VDD_LPI_CX_LEVEL>;
 		reg-names = "vdd_lpi_cx", "vdd_lpi_mx";
-		qcom,vdd_lpi_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
-		mx-supply = <&VDD_LPI_MX_LEVEL>;
-		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+		vdd_lpi_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+		vdd_lpi_mx-supply = <&VDD_LPI_MX_LEVEL>;
+		vdd_lpi_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
 
 		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
 		clock-names = "xo";
@@ -1727,7 +1746,7 @@
 	rpm-sleep-stats@4690000 {
 		compatible = "qcom,rpm-sleep-stats";
 		reg = <0x04690000 0x400>;
-		ss-name = "modem", "adsp", "cdsp", "apss";
+		ss-name = "modem", "adsp", "adsp_island", "cdsp", "apss";
 	};
 
 	qcom,rpm-master-stats@45f0150 {
diff --git a/qcom/msm-arm-smmu-kona.dtsi b/qcom/msm-arm-smmu-kona.dtsi
new file mode 100755
index 00000000..513a697e
--- /dev/null
+++ b/qcom/msm-arm-smmu-kona.dtsi
@@ -0,0 +1,363 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+	kgsl_smmu: kgsl-smmu@3da0000 {
+		compatible = "qcom,qsmmu-v500";
+		reg = <0x3DA0000 0x10000>,
+			<0x3DC2000 0x20>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,use-3-lvl-tables;
+		qcom,no-dynamic-asid;
+		#global-interrupts = <2>;
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		dma-coherent;
+		qcom,regulator-names = "vdd";
+		vdd-supply = <&gpu_cx_gdsc>;
+
+		clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+			 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+			 <&gpucc GPU_CC_AHB_CLK>;
+		clock-names = "gcc_gpu_memnoc_gfx",
+			      "gcc_gpu_snoc_dvm_gfx",
+			      "gpu_cc_ahb";
+
+		interrupts =	<GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
+
+		qcom,actlr =
+			/* All CBs of GFX: +15 deep PF */
+			<0x2 0x400 0x32B>,
+			<0x4 0x400 0x32B>,
+			<0x5 0x400 0x32B>,
+			<0x7 0x400 0x32B>,
+			<0x0 0x401 0x32B>;
+
+		gfx_0_tbu: gfx_0_tbu@3dc5000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x3DC5000 0x1000>,
+				<0x3DC2200 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x0 0x400>;
+			qcom,iova-width = <49>;
+		};
+
+		gfx_1_tbu: gfx_1_tbu@3dc9000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x3DC9000 0x1000>,
+				<0x3DC2208 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x400 0x400>;
+			qcom,iova-width = <49>;
+		};
+	};
+
+	apps_smmu: apps-smmu@15000000 {
+		compatible = "qcom,qsmmu-v500";
+		reg = <0x15000000 0x100000>,
+			<0x15182000 0x20>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,use-3-lvl-tables;
+		#global-interrupts = <2>;
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		dma-coherent;
+		interrupts =	<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
+
+		interconnects = <&system_noc MASTER_GEM_NOC_SNOC
+				 &config_noc SLAVE_IMEM_CFG>;
+		qcom,active-only;
+
+		qcom,actlr =
+			/* For HF-0 TBU +3 deep PF */
+			<0x800 0x3ff 0x103>,
+			/* For HF-1 TBU +3 deep PF */
+			<0xC00 0x3ff 0x103>,
+			/* For SF-0 TBU +3 deep PF */
+			<0x2000 0x3ff 0x103>,
+			/* For SF-1 TBU +3 deep PF */
+			<0x2400 0x3ff 0x103>,
+			/* For NPU +3 deep PF */
+			<0x1081 0x400 0x103>,
+			<0x1082 0x400 0x103>,
+			<0x1085 0x400 0x103>,
+			<0x10a1 0x400 0x103>,
+			<0x10a2 0x400 0x103>,
+			<0x10a5 0x400 0x103>;
+
+		anoc_1_tbu: anoc_1_tbu@15185000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x15185000 0x1000>,
+				<0x15182200 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x0 0x400>;
+			interconnects = <&system_noc MASTER_GEM_NOC_SNOC
+					 &config_noc SLAVE_IMEM_CFG>;
+			qcom,active-only;
+			qcom,iova-width = <36>;
+		};
+
+		anoc_2_tbu: anoc_2_tbu@15189000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x15189000 0x1000>,
+				<0x15182208 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x400 0x400>;
+			interconnects = <&system_noc MASTER_GEM_NOC_SNOC
+					 &config_noc SLAVE_IMEM_CFG>;
+			qcom,active-only;
+			qcom,iova-width = <36>;
+		};
+
+		mnoc_hf_0_tbu: mnoc_hf_0_tbu@1518d000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x1518D000 0x1000>,
+				<0x15182210 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x800 0x400>;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;
+			interconnects = <&mmss_noc MASTER_MDP0
+					 &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
+			qcom,active-only;
+			qcom,iova-width = <32>;
+		};
+
+		mnoc_hf_1_tbu: mnoc_hf_1_tbu@15191000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x15191000 0x1000>,
+				<0x15182218 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0xc00 0x400>;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>;
+			interconnects = <&mmss_noc MASTER_MDP0
+					 &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
+			qcom,active-only;
+			qcom,iova-width = <32>;
+		};
+
+		compute_dsp_1_tbu: compute_dsp_1_tbu@15195000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x15195000 0x1000>,
+				<0x15182220 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1000 0x400>;
+			interconnects = <&compute_noc MASTER_NPU
+					 &compute_noc SLAVE_CDSP_MEM_NOC>;
+			qcom,active-only;
+			qcom,iova-width = <32>;
+		};
+
+		compute_dsp_0_tbu: compute_dsp_0_tbu@15199000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x15199000 0x1000>,
+				<0x15182228 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1400 0x400>;
+			interconnects = <&compute_noc MASTER_NPU
+					 &compute_noc SLAVE_CDSP_MEM_NOC>;
+			qcom,active-only;
+			qcom,iova-width = <32>;
+		};
+
+		adsp_tbu: adsp_tbu@1519d000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x1519D000 0x1000>,
+				<0x15182230 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1800 0x400>;
+			interconnects = <&system_noc MASTER_GEM_NOC_SNOC
+					 &config_noc SLAVE_IMEM_CFG>;
+			qcom,active-only;
+			qcom,iova-width = <32>;
+		};
+
+		anoc_1_pcie_tbu: anoc_1_pcie_tbu@151a1000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151A1000 0x1000>,
+				<0x15182238 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1c00 0x400>;
+			clock-names = "gcc_aggre_noc_pcie_tbu_clk";
+			clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+			interconnects = <&system_noc MASTER_GEM_NOC_SNOC
+					 &config_noc SLAVE_IMEM_CFG>;
+			qcom,active-only;
+			qcom,iova-width = <36>;
+		};
+
+		mnoc_sf_0_tbu: mnoc_sf_0_tbu@151a5000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151A5000 0x1000>,
+				<0x15182240 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x2000 0x400>;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc>;
+			interconnects = <&mmss_noc MASTER_CAMNOC_SF
+					 &mmss_noc SLAVE_MNOC_SF_MEM_NOC>;
+			qcom,active-only;
+			qcom,iova-width = <32>;
+		};
+
+		mnoc_sf_1_tbu: mnoc_sf_1_tbu@151a9000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151A9000 0x1000>,
+				<0x15182248 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x2400 0x400>;
+			qcom,regulator-names = "vdd";
+			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc>;
+			interconnects = <&mmss_noc MASTER_CAMNOC_SF
+					 &mmss_noc SLAVE_MNOC_SF_MEM_NOC>;
+			qcom,active-only;
+			qcom,iova-width = <32>;
+		};
+	};
+
+	dma_dev {
+		compatible = "qcom,iommu-dma";
+		memory-region = <&system_cma>;
+	};
+
+	iommu_test_device {
+		compatible = "qcom,iommu-debug-test";
+
+		kgsl_iommu_test_device {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&kgsl_smmu 0x7 0>;
+			qcom,iommu-dma = "disabled";
+		};
+
+		kgsl_iommu_coherent_test_device {
+			status = "disabled";
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&kgsl_smmu 0x9 0>;
+			qcom,iommu-dma = "disabled";
+			dma-coherent;
+		};
+
+		apps_iommu_test_device {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x21 0>;
+			qcom,iommu-dma = "disabled";
+		};
+
+		apps_iommu_coherent_test_device {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x23 0>;
+			qcom,iommu-dma = "disabled";
+			dma-coherent;
+		};
+	};
+};
diff --git a/qcom/msm-arm-smmu-lemans.dtsi b/qcom/msm-arm-smmu-lemans.dtsi
index 488884d9..9e392354 100755
--- a/qcom/msm-arm-smmu-lemans.dtsi
+++ b/qcom/msm-arm-smmu-lemans.dtsi
@@ -363,6 +363,8 @@
 				<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
 
+		interconnects = <&pcie_anoc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
+
 		pcie_0_tbu: pcie_0_tbu@152f9000 {
 			compatible = "qcom,qsmmuv500-tbu";
 			reg = <0x152F9000 0x1000>,
@@ -383,7 +385,7 @@
 	};
 
 	kgsl_smmu: kgsl-smmu@3da0000 {
-		compatible = "qcom,qsmmu-v500";
+		compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu";
 		reg = <0x3da0000 0x20000>,
 			<0x3dca000 0x28>;
 		reg-names = "base", "tcu-base";
diff --git a/qcom/pm8009.dtsi b/qcom/pm8009.dtsi
new file mode 100755
index 00000000..3e15fdbd
--- /dev/null
+++ b/qcom/pm8009.dtsi
@@ -0,0 +1,51 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+	status = "ok";
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	qcom,pm8009@a {
+		status = "okay";
+		compatible ="qcom,spmi-pmic";
+		reg = <0xa SPMI_USID>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		qcom,revid@100 {
+			status = "okay";
+			compatible = "qcom,qpnp-revid";
+			reg = <0x100 0x100>;
+		};
+
+		qcom,power-on@800 {
+			compatible = "qcom,qpnp-power-on";
+			reg = <0x800 0x100>;
+		};
+
+		pm8009_gpios: pinctrl@c000 {
+			status = "okay";
+			compatible = "qcom,pm8150b-gpio";
+			reg = <0xc000 0x400>;
+			interrupts = <0xa 0xc0 0 IRQ_TYPE_NONE>,
+				     <0xa 0xc1 0 IRQ_TYPE_NONE>,
+				     <0xa 0xc2 0 IRQ_TYPE_NONE>,
+				     <0xa 0xc3 0 IRQ_TYPE_NONE>;
+			interrupt-names = "pm8009_gpio1", "pm8009_gpio2",
+					  "pm8009_gpio3", "pm8009_gpio4";
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};
+
+	qcom,pm8009@b {
+		status = "okay";
+		compatible = "qcom,spmi-pmic";
+		reg = <0xb SPMI_USID>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+	};
+};
diff --git a/qcom/pm8150.dtsi b/qcom/pm8150.dtsi
index 41e60e6d..9ce9c1db 100755
--- a/qcom/pm8150.dtsi
+++ b/qcom/pm8150.dtsi
@@ -7,12 +7,14 @@
 #include <dt-bindings/input/linux-event-codes.h>
 
 &spmi_bus {
+	status = "ok";
 	#address-cells = <2>;
 	#size-cells = <0>;
 	interrupt-controller;
 	#interrupt-cells = <4>;
 
 	pm8150_0: qcom,pm8150@0 {
+		status = "okay";
 		compatible = "qcom,spmi-pmic";
 		reg = <0 SPMI_USID>;
 		#address-cells = <1>;
@@ -70,6 +72,7 @@
 		};
 
 		pm8150_rtc: qcom,pm8150_rtc {
+			status = "okay";
 			compatible = "qcom,pm8941-rtc";
 			reg = <0x6000>, <0x6100>;
 			reg-names = "rtc", "alarm";
@@ -86,6 +89,7 @@
 		};
 
 		pm8150_sdam_2: sdam@b100 {
+			status = "okay";
 			compatible = "qcom,spmi-sdam";
 			reg = <0xb100>;
 			#address-cells = <1>;
@@ -98,6 +102,7 @@
 		};
 
 		pm8150_vadc: vadc@3100 {
+			status = "okay";
 			compatible = "qcom,spmi-adc5";
 			reg = <0x3100>;
 			#address-cells = <1>;
@@ -128,6 +133,7 @@
 		};
 
 		pm8150_adc_tm: adc_tm@3500 {
+			status = "okay";
 			compatible = "qcom,spmi-adc-tm5";
 			reg = <0x3500>;
 			interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
@@ -142,6 +148,7 @@
 	};
 
 	qcom,pm8150@1 {
+		status = "okay";
 		compatible ="qcom,spmi-pmic";
 		reg = <1 SPMI_USID>;
 		#address-cells = <1>;
diff --git a/qcom/pm8150b.dtsi b/qcom/pm8150b.dtsi
new file mode 100755
index 00000000..3bee9948
--- /dev/null
+++ b/qcom/pm8150b.dtsi
@@ -0,0 +1,768 @@
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&spmi_bus {
+	status = "ok";
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	qcom,pm8150b@2 {
+		status = "okay";
+		compatible = "qcom,spmi-pmic";
+		reg = <0x2 SPMI_USID>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		pm8150b_revid: qcom,revid@100 {
+			status = "okay";
+			compatible = "qcom,qpnp-revid";
+			reg = <0x100 0x100>;
+		};
+
+		qcom,power-on@800 {
+			compatible = "qcom,qpnp-power-on";
+			reg = <0x800 0x100>;
+		};
+
+		pm8150b_tz: qcom,temp-alarm@2400 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0x2400 0x100>;
+			interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+			io-channels = <&pm8150b_vadc ADC5_DIE_TEMP>;
+			io-channel-names = "thermal";
+			#thermal-sensor-cells = <0>;
+			qcom,temperature-threshold-set = <1>;
+		};
+
+		pm8150b_clkdiv: clock-controller@6000 {
+			compatible = "qcom,spmi-clkdiv";
+			reg = <0x6000 0x100>;
+			#clock-cells = <1>;
+			qcom,num-clkdivs = <1>;
+			clock-output-names = "pm8150b_div_clk1";
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+		};
+
+		pm8150b_pbs1: qcom,pbs@7200 {
+			status = "okay";
+			compatible = "qcom,qpnp-pbs";
+			reg = <0x7200 0x100>;
+		};
+
+		pm8150b_qnovo: qcom,sdam-qnovo@b000 {
+			status = "okay";
+			compatible = "qcom,qpnp-qnovo5";
+			reg = <0xb000 0x100>;
+			interrupts = <0x2 0xb0 1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "ptrain-done";
+		};
+
+		pm8150b_gpios: pinctrl@c000 {
+			status = "okay";
+			compatible = "qcom,pm8150b-gpio";
+			reg = <0xc000 0xc00>;
+			interrupts = <0x2 0xc0 0x0 IRQ_TYPE_NONE>,
+					<0x2 0xc1 0x0 IRQ_TYPE_NONE>,
+					<0x2 0xc4 0x0 IRQ_TYPE_NONE>,
+					<0x2 0xc5 0x0 IRQ_TYPE_NONE>,
+					<0x2 0xc6 0x0 IRQ_TYPE_NONE>,
+					<0x2 0xc7 0x0 IRQ_TYPE_NONE>,
+					<0x2 0xc8 0x0 IRQ_TYPE_NONE>,
+					<0x2 0xc9 0x0 IRQ_TYPE_NONE>,
+					<0x2 0xcb 0x0 IRQ_TYPE_NONE>;
+			interrupt-names = "pm8150b_gpio1", "pm8150b_gpio2",
+					"pm8150b_gpio5", "pm8150b_gpio6",
+					"pm8150b_gpio7", "pm8150b_gpio8",
+					"pm8150b_gpio9", "pm8150b_gpio10",
+					"pm8150b_gpio12";
+			gpio-controller;
+			#gpio-cells = <2>;
+			qcom,gpios-disallowed = <3 4 11>;
+		};
+
+		pm8150b_charger: qcom,qpnp-smb5 {
+			compatible = "qcom,pm8150-smb5";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#cooling-cells = <2>;
+
+			qcom,pmic-revid = <&pm8150b_revid>;
+
+			qcom,thermal-mitigation
+					= <3000000 1500000 1000000 500000>;
+
+			qcom,chg-term-src = <1>;
+			qcom,charger-temp-max = <800>;
+			qcom,smb-temp-max = <800>;
+			#io-channel-cells = <1>;
+			status = "okay";
+
+			qcom,chgr@1000 {
+				reg = <0x1000>;
+				interrupts =
+					<0x2 0x10 0x0 IRQ_TYPE_EDGE_RISING>,
+					<0x2 0x10 0x1 IRQ_TYPE_EDGE_RISING>,
+					<0x2 0x10 0x2 IRQ_TYPE_EDGE_RISING>,
+					<0x2 0x10 0x3 IRQ_TYPE_EDGE_RISING>,
+					<0x2 0x10 0x4 IRQ_TYPE_EDGE_RISING>,
+					<0x2 0x10 0x6 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x10 0x7 IRQ_TYPE_EDGE_BOTH>;
+
+				interrupt-names = "chgr-error",
+						  "chg-state-change",
+						  "step-chg-state-change",
+						  "step-chg-soc-update-fail",
+						  "step-chg-soc-update-req",
+						  "vph-alarm",
+						  "vph-drop-prechg";
+			};
+
+			qcom,dcdc@1100 {
+				reg = <0x1100>;
+				interrupts =
+					<0x2 0x11 0x0 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x11 0x1 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x11 0x2 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x11 0x4 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x11 0x5 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x11 0x6 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x11 0x7 IRQ_TYPE_EDGE_BOTH>;
+
+				interrupt-names = "otg-fail",
+						  "otg-oc-disable-sw",
+						  "otg-oc-hiccup",
+						  "high-duty-cycle",
+						  "input-current-limiting",
+						  "concurrent-mode-disable",
+						  "switcher-power-ok";
+			};
+
+			qcom,batif@1200 {
+				reg = <0x1200>;
+				interrupts =
+					<0x2 0x12 0x0 IRQ_TYPE_EDGE_RISING>,
+					<0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x12 0x3 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x12 0x4 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x12 0x5 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x12 0x6 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x12 0x7 IRQ_TYPE_EDGE_BOTH>;
+
+				interrupt-names = "bat-temp",
+						  "bat-ov",
+						  "bat-low",
+						  "bat-therm-or-id-missing",
+						  "bat-terminal-missing",
+						  "buck-oc",
+						  "vph-ov";
+			};
+
+			qcom,usb@1300 {
+				reg = <0x1300>;
+				interrupts =
+					<0x2 0x13 0x0 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x13 0x1 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x13 0x2 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x13 0x3 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x13 0x5 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>,
+					<0x2 0x13 0x7 IRQ_TYPE_EDGE_RISING>;
+
+				interrupt-names = "usbin-collapse",
+						  "usbin-vashdn",
+						  "usbin-uv",
+						  "usbin-ov",
+						  "usbin-plugin",
+						  "usbin-revi-change",
+						  "usbin-src-change",
+						  "usbin-icl-change";
+			};
+
+			qcom,dc@1400 {
+				reg = <0x1400 0x100>;
+				interrupts =
+					<0x2 0x14 0x1 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x14 0x2 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x14 0x3 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x14 0x4 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x14 0x5 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x14 0x6 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x14 0x7 IRQ_TYPE_EDGE_BOTH>;
+
+				interrupt-names = "dcin-vashdn",
+						  "dcin-uv",
+						  "dcin-ov",
+						  "dcin-plugin",
+						  "dcin-revi",
+						  "dcin-pon",
+						  "dcin-en";
+			};
+
+			qcom,typec@1500 {
+				reg = <0x1500>;
+				interrupts =
+					<0x2 0x15 0x0 IRQ_TYPE_EDGE_RISING>,
+					<0x2 0x15 0x1 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x15 0x2 IRQ_TYPE_EDGE_RISING>,
+					<0x2 0x15 0x3 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x15 0x4 IRQ_TYPE_EDGE_RISING>,
+					<0x2 0x15 0x5 IRQ_TYPE_EDGE_RISING>,
+					<0x2 0x15 0x6 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x15 0x7 IRQ_TYPE_EDGE_RISING>;
+
+				interrupt-names = "typec-or-rid-detect-change",
+						  "typec-vpd-detect",
+						  "typec-cc-state-change",
+						  "typec-vconn-oc",
+						  "typec-vbus-change",
+						  "typec-attach-detach",
+						  "typec-legacy-cable-detect",
+						  "typec-try-snk-src-detect";
+			};
+
+			qcom,misc@1600 {
+				reg = <0x1600>;
+				interrupts =
+					<0x2 0x16 0x0 IRQ_TYPE_EDGE_RISING>,
+					<0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
+					<0x2 0x16 0x2 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x16 0x3 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x16 0x4 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x16 0x6 IRQ_TYPE_EDGE_BOTH>,
+					<0x2 0x16 0x7 IRQ_TYPE_EDGE_BOTH>;
+
+				interrupt-names = "wdog-snarl",
+						  "wdog-bark",
+						  "aicl-fail",
+						  "aicl-done",
+						  "smb-en",
+						  "temp-change",
+						  "temp-change-smb";
+			};
+		};
+
+		pm8150b_pdphy: qcom,usb-pdphy@1700 {
+			compatible = "qcom,qpnp-pdphy";
+			reg = <0x1700 0x100>;
+			interrupts = <0x2 0x17 0x0 IRQ_TYPE_EDGE_RISING>,
+				     <0x2 0x17 0x1 IRQ_TYPE_EDGE_RISING>,
+				     <0x2 0x17 0x2 IRQ_TYPE_EDGE_RISING>,
+				     <0x2 0x17 0x3 IRQ_TYPE_EDGE_RISING>,
+				     <0x2 0x17 0x4 IRQ_TYPE_EDGE_RISING>,
+				     <0x2 0x17 0x5 IRQ_TYPE_EDGE_RISING>,
+				     <0x2 0x17 0x6 IRQ_TYPE_EDGE_RISING>,
+				     <0x2 0x17 0x7 IRQ_TYPE_EDGE_RISING>;
+
+			interrupt-names = "sig-tx",
+					  "sig-rx",
+					  "msg-tx",
+					  "msg-rx",
+					  "msg-tx-failed",
+					  "msg-tx-discarded",
+					  "msg-rx-discarded",
+					  "fr-swap";
+
+			qcom,default-sink-caps = <5000 3000>, /* 5V @ 3A */
+						 <9000 3000>, /* 9V @ 3A */
+						 <12000 2250>; /* 12V @ 2.25A */
+		};
+
+		pm8150b_bcl: bcl@1d00 {
+			compatible = "qcom,bcl-v5";
+			reg = <0x1d00 0x100>;
+			interrupts = <0x2 0x1d 0x0 IRQ_TYPE_NONE>,
+					<0x2 0x1d 0x1 IRQ_TYPE_NONE>,
+					<0x2 0x1d 0x2 IRQ_TYPE_NONE>;
+			interrupt-names = "bcl-lvl0",
+						"bcl-lvl1",
+						"bcl-lvl2";
+			#thermal-sensor-cells = <1>;
+		};
+
+		bcl_soc:bcl-soc {
+			compatible = "qcom,msm-bcl-soc";
+			#thermal-sensor-cells = <0>;
+		};
+
+		pm8150b_fg: qpnp,fg {
+			compatible = "qcom,fg-gen4";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			qcom,pmic-revid = <&pm8150b_revid>;
+			qcom,pmic-pbs = <&pm8150b_pbs1>;
+			status = "okay";
+
+			qcom,fg-batt-soc@4000 {
+				status = "okay";
+				reg = <0x4000 0x100>;
+				interrupts = <0x2 0x40 0x0 IRQ_TYPE_EDGE_BOTH>,
+					     <0x2 0x40 0x1 IRQ_TYPE_EDGE_BOTH>,
+					     <0x2 0x40 0x2
+							IRQ_TYPE_EDGE_RISING>,
+					     <0x2 0x40 0x3
+							IRQ_TYPE_EDGE_RISING>,
+					     <0x2 0x40 0x4 IRQ_TYPE_EDGE_BOTH>,
+					     <0x2 0x40 0x5
+							IRQ_TYPE_EDGE_RISING>,
+					     <0x2 0x40 0x6 IRQ_TYPE_EDGE_BOTH>,
+					     <0x2 0x40 0x7 IRQ_TYPE_EDGE_BOTH>;
+				interrupt-names = "soc-update",
+						  "soc-ready",
+						  "bsoc-delta",
+						  "msoc-delta",
+						  "msoc-low",
+						  "msoc-empty",
+						  "msoc-high",
+						  "msoc-full";
+			};
+
+			qcom,fg-batt-info@4100 {
+				status = "okay";
+				reg = <0x4100 0x100>;
+				interrupts = <0x2 0x41 0x0 IRQ_TYPE_EDGE_BOTH>,
+					     <0x2 0x41 0x1 IRQ_TYPE_EDGE_BOTH>,
+					     <0x2 0x41 0x3
+							IRQ_TYPE_EDGE_RISING>;
+				interrupt-names = "vbatt-low",
+						  "vbatt-pred-delta",
+						  "esr-delta";
+			};
+
+			qcom,fg-rradc@4200 {
+				status = "okay";
+				reg = <0x4200 0x100>;
+				interrupts = <0x2 0x42 0x0 IRQ_TYPE_EDGE_BOTH>,
+					     <0x2 0x42 0x1 IRQ_TYPE_EDGE_BOTH>,
+					     <0x2 0x42 0x2 IRQ_TYPE_EDGE_BOTH>,
+					     <0x2 0x42 0x3 IRQ_TYPE_EDGE_BOTH>,
+					     <0x2 0x42 0x4 IRQ_TYPE_EDGE_BOTH>;
+				interrupt-names = "batt-missing",
+						  "batt-id",
+						  "batt-temp-delta",
+						  "batt-temp-hot",
+						  "batt-temp-cold";
+			};
+
+			qcom,fg-memif@4300 {
+				status = "okay";
+				reg = <0x4300 0x100>;
+				interrupts = <0x2 0x43 0x0 IRQ_TYPE_EDGE_BOTH>,
+					     <0x2 0x43 0x1 IRQ_TYPE_EDGE_BOTH>,
+					     <0x2 0x43 0x2 IRQ_TYPE_EDGE_BOTH>,
+					     <0x2 0x43 0x3
+							IRQ_TYPE_EDGE_RISING>,
+					     <0x2 0x43 0x4
+							IRQ_TYPE_EDGE_FALLING>;
+				interrupt-names = "ima-rdy",
+						  "ima-xcp",
+						  "dma-xcp",
+						  "dma-grant",
+						  "mem-attn";
+			};
+		};
+
+		pm8150b_vadc: vadc@3100 {
+			status = "okay";
+			compatible = "qcom,spmi-adc5";
+			reg = <0x3100 0x100>, <0x3700 0x100>;
+			reg-names = "adc5-usr-base", "adc5-cal-base";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "eoc-int-en-set";
+			qcom,adc-vdd-reference = <1875>;
+			#io-channel-cells = <1>;
+			io-channel-ranges;
+
+			/* Channel node */
+			ref_gnd@0 {
+				reg = <ADC5_REF_GND>;
+				label = "ref_gnd";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			vref_1p25@1 {
+				reg = <ADC5_1P25VREF>;
+				label = "vref_1p25";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			die_temp@2 {
+				reg = <ADC5_DIE_TEMP>;
+				label = "die_temp";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			chg_temp@9 {
+				reg = <ADC5_CHG_TEMP>;
+				label = "chg_temp";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			bat_id@4b {
+				reg = <ADC5_BAT_ID_100K_PU>;
+				label = "bat_id";
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+			};
+
+			smb1390_therm@e {
+				reg = <ADC5_AMUX_THM2>;
+				label = "smb1390_therm";
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+			};
+
+			smb1355_therm@4e {
+				reg = <ADC5_AMUX_THM2_100K_PU>;
+				label = "smb1355_therm";
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+			};
+
+			usb_in_i_uv@7 {
+				reg = <ADC5_USB_IN_I>;
+				label = "usb_in_i_uv";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			usb_in_v_div_16@8 {
+				reg = <ADC5_USB_IN_V_16>;
+				label = "usb_in_v_div_16";
+				qcom,pre-scaling = <1 16>;
+			};
+
+			chg_sbux@99 {
+				reg = <ADC5_SBUx>;
+				label = "chg_sbux";
+				qcom,pre-scaling = <1 3>;
+			};
+
+			vph_pwr@83 {
+				reg = <ADC5_VPH_PWR>;
+				label = "vph_pwr";
+				qcom,pre-scaling = <1 3>;
+			};
+		};
+
+		pm8150b_adc_tm: adc_tm@3500 {
+			status = "okay";
+			compatible = "qcom,spmi-adc-tm5";
+			reg = <0x3500 0x100>;
+			interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "thr-int-en";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#thermal-sensor-cells = <1>;
+			qcom,pmic-revid = <&pm8150b_revid>;
+		};
+	};
+
+	qcom,pm8150b@3 {
+		status = "okay";
+		compatible ="qcom,spmi-pmic";
+		reg = <0x3 SPMI_USID>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		pm8150b_pwm: qcom,pwms@b100 {
+			status = "okay";
+			compatible = "qcom,pwm-lpg";
+			reg = <0xb100 0x200>;
+			reg-names = "lpg-base";
+			#pwm-cells = <2>;
+			qcom,num-lpg-channels = <2>;
+		};
+
+		pm8150b_hr_led: qcom,leds@d000 {
+			status = "okay";
+			compatible = "qcom,tri-led";
+			reg = <0xd000 0x100>;
+			nvmem-names = "pbs_sdam";
+			nvmem = <&pm8150_sdam_2>;
+			hr_led1 {
+				label = "hr_led1";
+				pwms = <&pm8150b_pwm 0 1000000>;
+				led-sources = <0>;
+			};
+
+			hr_led2 {
+				label = "hr_led2";
+				pwms = <&pm8150b_pwm 1 1000000>;
+				led-sources = <1>;
+			};
+		};
+
+		pm8150b_haptics: qcom,haptics@c000 {
+			status = "okay";
+			compatible = "qcom,haptics";
+			reg = <0xc000 0x100>;
+			interrupts = <0x3 0xc0 0x0 IRQ_TYPE_EDGE_BOTH>,
+				     <0x3 0xc0 0x1 IRQ_TYPE_EDGE_BOTH>;
+			interrupt-names = "hap-sc-irq", "hap-play-irq";
+			qcom,actuator-type = "lra";
+			qcom,vmax-mv = <3600>;
+			qcom,play-rate-us = <6667>;
+			qcom,lra-resonance-sig-shape = "sine";
+			qcom,lra-auto-resonance-mode = "qwd";
+			qcom,lra-allow-variable-play-rate;
+
+			wf_0 {
+				/* CLICK */
+				qcom,effect-id = <0>;
+				qcom,wf-vmax-mv = <3600>;
+				qcom,wf-pattern = [3e 3e 3e 3e 3e 3e 3e 3e];
+				qcom,wf-play-rate-us = <6667>;
+				qcom,wf-brake-pattern = [00 00 00 00];
+				qcom,wf-repeat-count = <1>;
+				qcom,wf-s-repeat-count = <1>;
+				qcom,lra-auto-resonance-disable;
+			};
+
+			wf_1 {
+				/* DOUBLE CLICK */
+				qcom,effect-id = <1>;
+				qcom,wf-vmax-mv = <3600>;
+				qcom,wf-pattern = [3e 3e 3e 3e 3e 3e 3e 3e];
+				qcom,wf-play-rate-us = <6667>;
+				qcom,wf-brake-pattern = [00 00 00 00];
+				qcom,wf-repeat-count = <1>;
+				qcom,wf-s-repeat-count = <1>;
+				qcom,lra-auto-resonance-disable;
+			};
+
+			wf_2 {
+				/* TICK */
+				qcom,effect-id = <2>;
+				qcom,wf-vmax-mv = <3600>;
+				qcom,wf-pattern = [3e 3e 3e 3e 3e 3e 3e 3e];
+				qcom,wf-play-rate-us = <6667>;
+				qcom,wf-brake-pattern = [00 00 00 00];
+				qcom,wf-repeat-count = <1>;
+				qcom,wf-s-repeat-count = <1>;
+				qcom,lra-auto-resonance-disable;
+			};
+
+			wf_3 {
+				/* THUD */
+				qcom,effect-id = <3>;
+				qcom,wf-vmax-mv = <3600>;
+				qcom,wf-pattern = [3e 3e 3e 3e 3e 3e 3e 3e];
+				qcom,wf-play-rate-us = <6667>;
+				qcom,wf-brake-pattern = [00 00 00 00];
+				qcom,wf-repeat-count = <1>;
+				qcom,wf-s-repeat-count = <1>;
+				qcom,lra-auto-resonance-disable;
+			};
+
+			wf_4 {
+				/* POP */
+				qcom,effect-id = <4>;
+				qcom,wf-vmax-mv = <3600>;
+				qcom,wf-pattern = [3e 3e 3e 3e 3e 3e 3e 3e];
+				qcom,wf-play-rate-us = <6667>;
+				qcom,wf-brake-pattern = [00 00 00 00];
+				qcom,wf-repeat-count = <1>;
+				qcom,wf-s-repeat-count = <1>;
+				qcom,lra-auto-resonance-disable;
+			};
+
+			wf_5 {
+				/* HEAVY CLICK */
+				qcom,effect-id = <5>;
+				qcom,wf-vmax-mv = <3600>;
+				qcom,wf-pattern = [3e 3e 3e 3e 3e 3e 3e 3e];
+				qcom,wf-play-rate-us = <6667>;
+				qcom,wf-brake-pattern = [00 00 00 00];
+				qcom,wf-repeat-count = <1>;
+				qcom,wf-s-repeat-count = <1>;
+				qcom,lra-auto-resonance-disable;
+			};
+		};
+	};
+};
+
+&thermal_zones {
+	pm8150b_temp_alarm: pm8150b_tz {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8150b_tz>;
+		wake-capable-sensor;
+
+		trips {
+			pm8150b_trip0: trip0 {
+				temperature = <95000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			pm8150b_trip1: trip1 {
+				temperature = <115000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			trip2 {
+				temperature = <145000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8150b-ibat-lvl0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8150b_bcl 0>;
+		wake-capable-sensor;
+
+		trips {
+			ibat_lvl0:ibat-lvl0 {
+				temperature = <4500>;
+				hysteresis = <200>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8150b-ibat-lvl1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8150b_bcl 1>;
+		wake-capable-sensor;
+
+		trips {
+			ibat_lvl1:ibat-lvl1 {
+				temperature = <5000>;
+				hysteresis = <200>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8150b-vbat-lvl0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "low_limits_cap";
+		thermal-sensors = <&pm8150b_bcl 2>;
+		tracks-low;
+		wake-capable-sensor;
+
+		trips {
+			vbat_lvl0: vbat-lvl0 {
+				temperature = <3000>;
+				hysteresis = <200>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8150b-vbat-lvl1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "low_limits_cap";
+		thermal-sensors = <&pm8150b_bcl 3>;
+		tracks-low;
+		wake-capable-sensor;
+
+		trips {
+			vbat_lvl1:vbat-lvl1 {
+				temperature = <2800>;
+				hysteresis = <200>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8150b-vbat-lvl2 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "low_limits_cap";
+		thermal-sensors = <&pm8150b_bcl 4>;
+		tracks-low;
+		wake-capable-sensor;
+
+		trips {
+			vbat_lvl2:vbat-lvl2 {
+				temperature = <2600>;
+				hysteresis = <200>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8150b-bcl-lvl0 {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8150b_bcl 5>;
+		wake-capable-sensor;
+
+		trips {
+			b_bcl_lvl0: b-bcl-lvl0 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8150b-bcl-lvl1 {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8150b_bcl 6>;
+		wake-capable-sensor;
+
+		trips {
+			b_bcl_lvl1: b-bcl-lvl1 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8150b-bcl-lvl2 {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8150b_bcl 7>;
+		wake-capable-sensor;
+
+		trips {
+			b_bcl_lvl2: b-bcl-lvl2 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+	};
+
+	soc {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "low_limits_cap";
+		thermal-sensors = <&bcl_soc>;
+		tracks-low;
+		wake-capable-sensor;
+
+		trips {
+			soc_trip:soc-trip {
+				temperature = <10>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+		};
+	};
+};
diff --git a/qcom/pm8150l.dtsi b/qcom/pm8150l.dtsi
new file mode 100755
index 00000000..13132be8
--- /dev/null
+++ b/qcom/pm8150l.dtsi
@@ -0,0 +1,596 @@
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&spmi_bus {
+	status = "ok";
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	qcom,pm8150l@4 {
+		status = "okay";
+		compatible = "qcom,spmi-pmic";
+		reg = <0x4 SPMI_USID>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		pm8150l_revid: qcom,revid@100 {
+			status = "okay";
+			compatible = "qcom,qpnp-revid";
+			reg = <0x100 0x100>;
+		};
+
+		qcom,power-on@800 {
+			compatible = "qcom,qpnp-power-on";
+			reg = <0x800 0x100>;
+		};
+
+		pm8150l_tz: qcom,temp-alarm@2400 {
+			compatible = "qcom,spmi-temp-alarm";
+			reg = <0x2400 0x100>;
+			interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+			io-channels = <&pm8150l_vadc ADC5_DIE_TEMP>;
+			io-channel-names = "thermal";
+			#thermal-sensor-cells = <0>;
+			qcom,temperature-threshold-set = <1>;
+		};
+
+		pm8150l_clkdiv: clock-controller@5b00 {
+			compatible = "qcom,spmi-clkdiv";
+			reg = <0x5b00 0x100>;
+			#clock-cells = <1>;
+			qcom,num-clkdivs = <1>;
+			clock-output-names = "pm8150l_div_clk1";
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "xo";
+		};
+
+		pm8150l_gpios: pinctrl@c000 {
+			compatible = "qcom,pm8150l-gpio";
+			reg = <0xc000 0xc00>;
+			interrupts = <0x4 0xc0 0x0 IRQ_TYPE_NONE>,
+					<0x4 0xc2 0x0 IRQ_TYPE_NONE>,
+					<0x4 0xc3 0x0 IRQ_TYPE_NONE>,
+					<0x4 0xc4 0x0 IRQ_TYPE_NONE>,
+					<0x4 0xc5 0x0 IRQ_TYPE_NONE>,
+					<0x4 0xc6 0x0 IRQ_TYPE_NONE>,
+					<0x4 0xc7 0x0 IRQ_TYPE_NONE>,
+					<0x4 0xc9 0x0 IRQ_TYPE_NONE>,
+					<0x4 0xca 0x0 IRQ_TYPE_NONE>;
+			interrupt-names = "pm8150l_gpio1", "pm8150l_gpio3",
+					"pm8150l_gpio4", "pm8150l_gpio5",
+					"pm8150l_gpio6", "pm8150l_gpio7",
+					"pm8150l_gpio8", "pm8150l_gpio10",
+					"pm8150l_gpio11";
+			gpio-controller;
+			#gpio-cells = <2>;
+			qcom,gpios-disallowed = <2 9 12>;
+		};
+
+		pm8150l_vadc: vadc@3100 {
+			status = "okay";
+			compatible = "qcom,spmi-adc5";
+			reg = <0x3100 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "eoc-int-en-set";
+			qcom,adc-vdd-reference = <1875>;
+			#io-channel-cells = <1>;
+			io-channel-ranges;
+
+			/* Channel node */
+			ref_gnd@0 {
+				reg = <ADC5_REF_GND>;
+				label = "ref_gnd";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			vref_1p25@1 {
+				reg = <ADC5_1P25VREF>;
+				label = "vref_1p25";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			die_temp@2 {
+				reg = <ADC5_DIE_TEMP>;
+				label = "die_temp";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			vph_pwr@83 {
+				reg = <ADC5_VPH_PWR>;
+				label = "vph_pwr";
+				qcom,pre-scaling = <1 3>;
+			};
+
+			camera_flash_therm@4d {
+				reg = <ADC5_AMUX_THM1_100K_PU>;
+				label = "camera_flash_therm";
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+			};
+
+			skin_msm_therm@4e {
+				reg = <ADC5_AMUX_THM2_100K_PU>;
+				label = "skin_msm_therm";
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pa_therm2@4f {
+				reg = <ADC5_AMUX_THM3_100K_PU>;
+				label = "pa_therm2";
+				qcom,ratiometric;
+				qcom,hw-settle-time = <200>;
+				qcom,pre-scaling = <1 1>;
+			};
+		};
+
+		pm8150l_bcl: bcl@3d00 {
+			compatible = "qcom,bcl-v5";
+			reg = <0x3d00 0x100>;
+			interrupts = <0x4 0x3d 0x0 IRQ_TYPE_NONE>,
+					<0x4 0x3d 0x1 IRQ_TYPE_NONE>,
+					<0x4 0x3d 0x2 IRQ_TYPE_NONE>;
+			interrupt-names = "bcl-lvl0",
+						"bcl-lvl1",
+						"bcl-lvl2";
+			#thermal-sensor-cells = <1>;
+		};
+
+		pm8150l_adc_tm: adc_tm@3500 {
+			status = "okay";
+			compatible = "qcom,spmi-adc-tm5";
+			reg = <0x3500 0x100>;
+			interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "thr-int-en";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#thermal-sensor-cells = <1>;
+			io-channels = <&pm8150l_vadc ADC5_AMUX_THM1_100K_PU>,
+					<&pm8150l_vadc ADC5_AMUX_THM2_100K_PU>,
+					<&pm8150l_vadc ADC5_AMUX_THM3_100K_PU>;
+		};
+	};
+
+	qcom,pm8150l@5 {
+		status = "okay";
+		compatible ="qcom,spmi-pmic";
+		reg = <0x5 SPMI_USID>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		pm8150l_lcdb: qcom,lcdb@ec00 {
+			compatible = "qcom,qpnp-lcdb-regulator";
+			reg = <0xec00 0x100>;
+			interrupts = <0x5 0xec 0x1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "sc-irq";
+			qcom,pmic-revid = <&pm8150l_revid>;
+			qcom,voltage-step-ramp;
+			status = "okay";
+
+			lcdb_ldo_vreg: ldo {
+				label = "ldo";
+				regulator-name = "lcdb_ldo";
+				regulator-min-microvolt = <4000000>;
+				regulator-max-microvolt = <6000000>;
+			};
+
+			lcdb_ncp_vreg: ncp {
+				label = "ncp";
+				regulator-name = "lcdb_ncp";
+				regulator-min-microvolt = <4000000>;
+				regulator-max-microvolt = <6000000>;
+			};
+
+			lcdb_bst_vreg: bst {
+				label = "bst";
+				regulator-name = "lcdb_bst";
+				regulator-min-microvolt = <4700000>;
+				regulator-max-microvolt = <6275000>;
+			};
+		};
+
+		flash_led: qcom,leds@d300 {
+			compatible = "qcom,qpnp-flash-led-v2";
+			status = "okay";
+			reg = <0xd300 0x100>;
+			label = "flash";
+			interrupts = <0x5 0xd3 0x0 IRQ_TYPE_EDGE_RISING>,
+				     <0x5 0xd3 0x3 IRQ_TYPE_EDGE_RISING>,
+				     <0x5 0xd3 0x4 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "led-fault-irq",
+					  "all-ramp-down-done-irq",
+					  "all-ramp-up-done-irq";
+			qcom,hdrm-auto-mode;
+			qcom,short-circuit-det;
+			qcom,open-circuit-det;
+			qcom,vph-droop-det;
+			qcom,thermal-derate-en;
+			qcom,thermal-derate-current = <200 500 1000>;
+			qcom,isc-delay = <192>;
+			qcom,pmic-revid = <&pm8150l_revid>;
+
+			pm8150l_flash0: qcom,flash_0 {
+				label = "flash";
+				qcom,led-name = "led:flash_0";
+				qcom,max-current = <1500>;
+				qcom,default-led-trigger = "flash0_trigger";
+				qcom,id = <0>;
+				qcom,current-ma = <1000>;
+				qcom,duration-ms = <1280>;
+				qcom,ires-ua = <12500>;
+				qcom,hdrm-voltage-mv = <325>;
+				qcom,hdrm-vol-hi-lo-win-mv = <100>;
+			};
+
+			pm8150l_flash1: qcom,flash_1 {
+				label = "flash";
+				qcom,led-name = "led:flash_1";
+				qcom,max-current = <1500>;
+				qcom,default-led-trigger = "flash1_trigger";
+				qcom,id = <1>;
+				qcom,current-ma = <1000>;
+				qcom,duration-ms = <1280>;
+				qcom,ires-ua = <12500>;
+				qcom,hdrm-voltage-mv = <325>;
+				qcom,hdrm-vol-hi-lo-win-mv = <100>;
+			};
+
+			pm8150l_flash2: qcom,flash_2 {
+				label = "flash";
+				qcom,led-name = "led:flash_2";
+				qcom,max-current = <750>;
+				qcom,default-led-trigger = "flash2_trigger";
+				qcom,id = <2>;
+				qcom,current-ma = <500>;
+				qcom,duration-ms = <1280>;
+				qcom,ires-ua = <12500>;
+				qcom,hdrm-voltage-mv = <325>;
+				qcom,hdrm-vol-hi-lo-win-mv = <100>;
+				status = "disabled";
+			};
+
+			pm8150l_torch0: qcom,torch_0 {
+				label = "torch";
+				qcom,led-name = "led:torch_0";
+				qcom,max-current = <500>;
+				qcom,default-led-trigger = "torch0_trigger";
+				qcom,id = <0>;
+				qcom,current-ma = <300>;
+				qcom,ires-ua = <12500>;
+				qcom,hdrm-voltage-mv = <325>;
+				qcom,hdrm-vol-hi-lo-win-mv = <100>;
+			};
+
+			pm8150l_torch1: qcom,torch_1 {
+				label = "torch";
+				qcom,led-name = "led:torch_1";
+				qcom,max-current = <500>;
+				qcom,default-led-trigger = "torch1_trigger";
+				qcom,id = <1>;
+				qcom,current-ma = <300>;
+				qcom,ires-ua = <12500>;
+				qcom,hdrm-voltage-mv = <325>;
+				qcom,hdrm-vol-hi-lo-win-mv = <100>;
+			};
+
+			pm8150l_torch2: qcom,torch_2 {
+				label = "torch";
+				qcom,led-name = "led:torch_2";
+				qcom,max-current = <500>;
+				qcom,default-led-trigger = "torch2_trigger";
+				qcom,id = <2>;
+				qcom,current-ma = <300>;
+				qcom,ires-ua = <12500>;
+				qcom,hdrm-voltage-mv = <325>;
+				qcom,hdrm-vol-hi-lo-win-mv = <100>;
+				status = "disabled";
+			};
+
+			pm8150l_switch0: qcom,led_switch_0 {
+				label = "switch";
+				qcom,led-name = "led:switch_0";
+				qcom,led-mask = <1>; /* Channel 1 */
+				qcom,default-led-trigger = "switch0_trigger";
+			};
+
+			pm8150l_switch1: qcom,led_switch_1 {
+				label = "switch";
+				qcom,led-name = "led:switch_1";
+				qcom,led-mask = <2>; /* Channel 2 */
+				qcom,default-led-trigger = "switch1_trigger";
+			};
+
+			pm8150l_switch2: qcom,led_switch_2 {
+				label = "switch";
+				qcom,led-name = "led:switch_2";
+				qcom,led-mask = <3>; /* Channels 1 and 2 */
+				qcom,default-led-trigger = "switch2_trigger";
+			};
+
+			pm8150l_switch3: qcom,led_switch_3 {
+				label = "switch";
+				qcom,led-name = "led:switch_3";
+				qcom,led-mask = <4>; /* Channel 3 */
+				qcom,default-led-trigger = "switch3_trigger";
+			};
+		};
+
+		pm8150l_wled: qcom,wled@d800 {
+			compatible = "qcom,pm8150l-wled";
+			reg = <0xd800 0x100>, <0xd900 0x100>;
+			reg-names = "wled-ctrl-base", "wled-sink-base";
+			label = "backlight";
+			interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
+				     <0x5 0xd8 0x4 IRQ_TYPE_EDGE_BOTH>,
+				     <0x5 0xd8 0x5 IRQ_TYPE_EDGE_BOTH>;
+			interrupt-names = "ovp-irq", "pre-flash-irq",
+					  "flash-irq";
+			qcom,pmic-revid = <&pm8150l_revid>;
+			qcom,auto-calibration;
+			status = "okay";
+
+			wled_flash: qcom,wled-flash {
+				label = "flash";
+				qcom,default-led-trigger = "wled_flash";
+			};
+
+			wled_torch: qcom,wled-torch {
+				label = "torch";
+				qcom,default-led-trigger = "wled_torch";
+				qcom,wled-torch-timer = <1200>;
+			};
+
+			wled_switch: qcom,wled-switch {
+				label = "switch";
+				qcom,default-led-trigger = "wled_switch";
+			};
+		};
+
+		pm8150l_lpg: qcom,pwms@b100 {
+			status = "okay";
+			compatible = "qcom,pwm-lpg";
+			reg = <0xb100 0x300>, <0xb000 0x100>;
+			reg-names = "lpg-base", "lut-base";
+			#pwm-cells = <2>;
+			qcom,num-lpg-channels = <3>;
+			qcom,lut-patterns = <0 10 20 30 40 50 60 70 80 90 100
+						90 80 70 60 50 40 30 20 10 0>;
+			lpg1 {
+				qcom,lpg-chan-id = <1>;
+				qcom,ramp-step-ms = <100>;
+				qcom,ramp-pause-hi-count = <2>;
+				qcom,ramp-pause-lo-count = <2>;
+				qcom,ramp-low-index = <0>;
+				qcom,ramp-high-index = <20>;
+				qcom,ramp-from-low-to-high;
+				qcom,ramp-pattern-repeat;
+			};
+
+			lpg2 {
+				qcom,lpg-chan-id = <2>;
+				qcom,ramp-step-ms = <100>;
+				qcom,ramp-pause-hi-count = <2>;
+				qcom,ramp-pause-lo-count = <2>;
+				qcom,ramp-low-index = <0>;
+				qcom,ramp-high-index = <20>;
+				qcom,ramp-from-low-to-high;
+				qcom,ramp-pattern-repeat;
+			};
+
+			lpg3 {
+				qcom,lpg-chan-id = <3>;
+				qcom,ramp-step-ms = <100>;
+				qcom,ramp-pause-hi-count = <2>;
+				qcom,ramp-pause-lo-count = <2>;
+				qcom,ramp-low-index = <0>;
+				qcom,ramp-high-index = <20>;
+				qcom,ramp-from-low-to-high;
+				qcom,ramp-pattern-repeat;
+			};
+		};
+
+		pm8150l_pwm: qcom,pwms@bc00 {
+			compatible = "qcom,pwm-lpg";
+			reg = <0xbc00 0x200>;
+			reg-names = "lpg-base";
+			#pwm-cells = <2>;
+			qcom,num-lpg-channels = <2>;
+		};
+
+		pm8150l_rgb_led: qcom,leds@d000 {
+			status = "okay";
+			compatible = "qcom,tri-led";
+			reg = <0xd000 0x100>;
+			red {
+				label = "red";
+				pwms = <&pm8150l_lpg 0 1000000>;
+				led-sources = <0>;
+				linux,default-trigger = "timer";
+			};
+
+			green {
+				label = "green";
+				pwms = <&pm8150l_lpg 1 1000000>;
+				led-sources = <1>;
+				linux,default-trigger = "timer";
+			};
+
+			blue {
+				label = "blue";
+				pwms = <&pm8150l_lpg 2 1000000>;
+				led-sources = <2>;
+				linux,default-trigger = "timer";
+			};
+		};
+
+		pm8150a_amoled: qcom,amoled {
+			compatible = "qcom,qpnp-amoled-regulator";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "okay";
+
+			oledb_vreg: oledb@e000 {
+				reg = <0xe000 0x100>;
+				reg-names = "oledb_base";
+				regulator-name = "oledb";
+				regulator-min-microvolt = <4925000>;
+				regulator-max-microvolt = <8100000>;
+				qcom,swire-control;
+			};
+
+			ab_vreg: ab@de00 {
+				reg = <0xde00 0x100>;
+				reg-names = "ab_base";
+				regulator-name = "ab";
+				regulator-min-microvolt = <4600000>;
+				regulator-max-microvolt = <6100000>;
+				qcom,swire-control;
+			};
+
+			ibb_vreg: ibb@dc00 {
+				reg = <0xdc00 0x100>;
+				reg-names = "ibb_base";
+				regulator-name = "ibb";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <5400000>;
+				qcom,swire-control;
+			};
+		};
+	};
+};
+
+&thermal_zones {
+	pm8150l_temp_alarm: pm8150l_tz {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8150l_tz>;
+		wake-capable-sensor;
+
+		trips {
+			trip0 {
+				temperature = <95000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			trip1 {
+				temperature = <115000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+
+			trip2 {
+				temperature = <145000>;
+				hysteresis = <0>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8150l-vph-lvl0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "low_limits_cap";
+		thermal-sensors = <&pm8150l_bcl 2>;
+		tracks-low;
+		wake-capable-sensor;
+
+		trips {
+			vph_lvl0: vph-lvl0 {
+				temperature = <3000>;
+				hysteresis = <200>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8150l-vph-lvl1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "low_limits_cap";
+		thermal-sensors = <&pm8150l_bcl 3>;
+		tracks-low;
+		wake-capable-sensor;
+
+		trips {
+			vph_lvl1:vph-lvl1 {
+				temperature = <2750>;
+				hysteresis = <200>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8150l-vph-lvl2 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "low_limits_cap";
+		thermal-sensors = <&pm8150l_bcl 4>;
+		tracks-low;
+		wake-capable-sensor;
+
+		trips {
+			vph_lvl2:vph-lvl2 {
+				temperature = <2500>;
+				hysteresis = <200>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8150l-bcl-lvl0 {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8150l_bcl 5>;
+		wake-capable-sensor;
+
+		trips {
+			l_bcl_lvl0: l-bcl-lvl0 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8150l-bcl-lvl1 {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8150l_bcl 6>;
+		wake-capable-sensor;
+
+		trips {
+			l_bcl_lvl1: l-bcl-lvl1 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+	};
+
+	pm8150l-bcl-lvl2 {
+		polling-delay-passive = <100>;
+		polling-delay = <0>;
+		thermal-governor = "step_wise";
+		thermal-sensors = <&pm8150l_bcl 7>;
+		wake-capable-sensor;
+
+		trips {
+			l_bcl_lvl2: l-bcl-lvl2 {
+				temperature = <1>;
+				hysteresis = <1>;
+				type = "passive";
+			};
+		};
+	};
+};
diff --git a/qcom/pm8195-vm.dtsi b/qcom/pm8195-vm.dtsi
new file mode 100755
index 00000000..4a38d67d
--- /dev/null
+++ b/qcom/pm8195-vm.dtsi
@@ -0,0 +1,58 @@
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/qcom,qpnp-power-on.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+	#address-cells = <2>;
+	#size-cells = <0>;
+	interrupt-controller;
+	#interrupt-cells = <4>;
+
+	qcom,pm8195@0 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8195_1_rtc: qcom,pm8195_1_rtc {
+			compatible = "qcom,pm8941-rtc";
+			reg = <0x6000>, <0x6100>;
+			reg-names = "rtc", "alarm";
+			interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+		};
+
+		pm8195_1_gpios: pinctrl@c000 {
+			compatible = "qcom,pm8150-gpio";
+			reg = <0xc000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+	};
+};
+
+/* PMIC GPIO pin control configurations */
+&pm8195_1_gpios {
+	storage_sd_detect {
+		storage_cd_default: storage_cd_default {
+			pins = "gpio4";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+			power-source = <0>;
+		};
+	};
+
+	key_vol_up {
+		key_vol_up_default: key_vol_up_default {
+			pins = "gpio6";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+			power-source = <1>;
+		};
+	};
+};
diff --git a/qcom/pm8775-vm.dtsi b/qcom/pm8775-vm.dtsi
new file mode 100755
index 00000000..65ae17db
--- /dev/null
+++ b/qcom/pm8775-vm.dtsi
@@ -0,0 +1,77 @@
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+
+	qcom,pm8775@0 {
+		compatible = "qcom,spmi-pmic";
+		reg = <0 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8775_1_gpios: pinctrl@8800 {
+			compatible = "qcom,pm8775-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pm8775_1_rtc: qcom,pm8775_1_rtc {
+			compatible = "qcom,pmk8350-rtc";
+			reg = <0x6100>, <0x6200>;
+			reg-names = "rtc", "alarm";
+			interrupts = <0x0 0x62 0x1 IRQ_TYPE_NONE>;
+			disable-alarm-wakeup;
+		};
+	};
+
+	qcom,pm8775@2 {
+		compatible = "qcom,spmi-pmic";
+		reg = <2 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8775_2_gpios: pinctrl@8800 {
+			compatible = "qcom,pm8775-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	qcom,pm8775@4 {
+		compatible = "qcom,spmi-pmic";
+		reg = <4 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8775_3_gpios: pinctrl@8800 {
+			compatible = "qcom,pm8775-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+
+	qcom,pm8775@6 {
+		compatible = "qcom,spmi-pmic";
+		reg = <6 SPMI_USID>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pm8775_4_gpios: pinctrl@8800 {
+			compatible = "qcom,pm8775-gpio";
+			reg = <0x8800>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+	};
+};
+
diff --git a/qcom/pm8775.dtsi b/qcom/pm8775.dtsi
index 32b34cfe..766ac923 100755
--- a/qcom/pm8775.dtsi
+++ b/qcom/pm8775.dtsi
@@ -3,6 +3,7 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pm8775.h>
 
 
 &spmi_bus {
@@ -21,9 +22,47 @@
 			compatible = "qcom,spmi-temp-alarm";
 			reg = <0xa00>;
 			interrupts = <0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			io-channels = <&pm8775_1_adc PM8775_1_ADC5_GEN3_DIE_TEMP>;
+			io-channel-names = "thermal";
 			#thermal-sensor-cells = <0>;
 		};
 
+		pm8775_1_adc: vadc@8000 {
+			compatible = "qcom,spmi-adc5-gen3";
+			reg = <0x8000>;
+			reg-names = "adc5-gen3-base";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "adc-sdam0";
+			#io-channel-cells = <1>;
+			status = "disabled";
+
+			pm8775_1_ref_gnd {
+				reg = <PM8775_1_ADC5_GEN3_OFFSET_REF>;
+				label = "pm8775_1_ref_gnd";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm8775_1_vref_1p25 {
+				reg = <PM8775_1_ADC5_GEN3_1P25VREF>;
+				label = "pm8775_1_vref_1p25";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm8775_1_die_temp {
+				reg = <PM8775_1_ADC5_GEN3_DIE_TEMP>;
+				label = "pm8775_1_die_temp";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm8775_1_vph_pwr {
+				reg = <PM8775_1_ADC5_GEN3_VPH_PWR>;
+				label = "pm8775_1_vph_pwr";
+				qcom,pre-scaling = <1 3>;
+			};
+		};
+
 		pon_pbs@800 {
 			compatible = "qcom,qpnp-power-on";
 			reg = <0x800>;
@@ -109,9 +148,47 @@
 			compatible = "qcom,spmi-temp-alarm";
 			reg = <0xa00>;
 			interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			io-channels = <&pm8775_2_adc PM8775_2_ADC5_GEN3_DIE_TEMP>;
+			io-channel-names = "thermal";
 			#thermal-sensor-cells = <0>;
 		};
 
+		pm8775_2_adc: vadc@8000 {
+			compatible = "qcom,spmi-adc5-gen3";
+			reg = <0x8000>;
+			reg-names = "adc5-gen3-base";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0x2 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "adc-sdam0";
+			#io-channel-cells = <1>;
+			status = "disabled";
+
+			pm8775_2_ref_gnd {
+				reg = <PM8775_2_ADC5_GEN3_OFFSET_REF>;
+				label = "pm8775_2_ref_gnd";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm8775_2_vref_1p25 {
+				reg = <PM8775_2_ADC5_GEN3_1P25VREF>;
+				label = "pm8775_2_vref_1p25";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm8775_2_die_temp {
+				reg = <PM8775_2_ADC5_GEN3_DIE_TEMP>;
+				label = "pm8775_2_die_temp";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm8775_2_vph_pwr {
+				reg = <PM8775_2_ADC5_GEN3_VPH_PWR>;
+				label = "pm8775_2_vph_pwr";
+				qcom,pre-scaling = <1 3>;
+			};
+		};
+
 		pon_pbs@800 {
 			compatible = "qcom,qpnp-power-on";
 			reg = <0x800>;
@@ -155,9 +232,47 @@
 			compatible = "qcom,spmi-temp-alarm";
 			reg = <0xa00>;
 			interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			io-channels = <&pm8775_3_adc PM8775_3_ADC5_GEN3_DIE_TEMP>;
+			io-channel-names = "thermal";
 			#thermal-sensor-cells = <0>;
 		};
 
+		pm8775_3_adc: vadc@8000 {
+			compatible = "qcom,spmi-adc5-gen3";
+			reg = <0x8000>;
+			reg-names = "adc5-gen3-base";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0x4 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "adc-sdam0";
+			#io-channel-cells = <1>;
+			status = "disabled";
+
+			pm8775_3_ref_gnd {
+				reg = <PM8775_3_ADC5_GEN3_OFFSET_REF>;
+				label = "pm8775_3_ref_gnd";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm8775_3_vref_1p25 {
+				reg = <PM8775_3_ADC5_GEN3_1P25VREF>;
+				label = "pm8775_3_vref_1p25";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm8775_3_die_temp {
+				reg = <PM8775_3_ADC5_GEN3_DIE_TEMP>;
+				label = "pm8775_3_die_temp";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm8775_3_vph_pwr {
+				reg = <PM8775_3_ADC5_GEN3_VPH_PWR>;
+				label = "pm8775_3_vph_pwr";
+				qcom,pre-scaling = <1 3>;
+			};
+		};
+
 		pon_pbs@800 {
 			compatible = "qcom,qpnp-power-on";
 			reg = <0x800>;
@@ -201,9 +316,47 @@
 			compatible = "qcom,spmi-temp-alarm";
 			reg = <0xa00>;
 			interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+			io-channels = <&pm8775_4_adc PM8775_4_ADC5_GEN3_DIE_TEMP>;
+			io-channel-names = "thermal";
 			#thermal-sensor-cells = <0>;
 		};
 
+		pm8775_4_adc: vadc@8000 {
+			compatible = "qcom,spmi-adc5-gen3";
+			reg = <0x8000>;
+			reg-names = "adc5-gen3-base";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0x6 0x80 0x1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "adc-sdam0";
+			#io-channel-cells = <1>;
+			status = "disabled";
+
+			pm8775_4_ref_gnd {
+				reg = <PM8775_4_ADC5_GEN3_OFFSET_REF>;
+				label = "pm8775_4_ref_gnd";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm8775_4_vref_1p25 {
+				reg = <PM8775_4_ADC5_GEN3_1P25VREF>;
+				label = "pm8775_4_vref_1p25";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm8775_4_die_temp {
+				reg = <PM8775_4_ADC5_GEN3_DIE_TEMP>;
+				label = "pm8775_4_die_temp";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pm8775_4_vph_pwr {
+				reg = <PM8775_4_ADC5_GEN3_VPH_PWR>;
+				label = "pm8775_4_vph_pwr";
+				qcom,pre-scaling = <1 3>;
+			};
+		};
+
 		pon_pbs@800 {
 			compatible = "qcom,qpnp-power-on";
 			reg = <0x800>;
diff --git a/qcom/pmx35.dtsi b/qcom/pmx35.dtsi
index 4ec5ef1f..f8fc7081 100755
--- a/qcom/pmx35.dtsi
+++ b/qcom/pmx35.dtsi
@@ -1,5 +1,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/input/input.h>
 #include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-adc5-gen3-pmx35.h>
 
 &spmi_bus {
 	#address-cells = <2>;
@@ -71,5 +73,42 @@
 			reg-names = "rtc", "alarm";
 			interrupts = <0x0 0x65 0x1 IRQ_TYPE_NONE>;
 		};
+
+		pmx35_sdam_2: sdam@7100 {
+			compatible = "qcom,spmi-sdam";
+			reg = <0x7100>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
+		pmx35_vadc: qcom,pmx35_vadc {
+			compatible = "qcom,spmi-adc5-gen3";
+			reg = <0x7700>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <0x0 0x76 0x1 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "adc-sdam0";
+			#io-channel-cells = <1>;
+			#thermal-sensor-cells = <1>;
+			status = "disabled";
+
+			pmx35_ref_gnd {
+				reg = <PMX35_ADC5_GEN3_OFFSET_REF>;
+				label = "pmx35_ref_gnd";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pmx35_vref_1p25 {
+				reg = <PMX35_ADC5_GEN3_1P25VREF>;
+				label = "pmx35_vref_1p25";
+				qcom,pre-scaling = <1 1>;
+			};
+
+			pmx35_die_temp {
+				reg = <PMX35_ADC5_GEN3_DIE_TEMP>;
+				label = "pmx35_die_temp";
+				qcom,pre-scaling = <1 1>;
+			};
+		};
 	};
 };
diff --git a/qcom/qbg-battery-profile-305mAh.dtsi b/qcom/qbg-battery-profile-305mAh.dtsi
new file mode 100755
index 00000000..ab5846ac
--- /dev/null
+++ b/qcom/qbg-battery-profile-305mAh.dtsi
@@ -0,0 +1,661 @@
+qcom,qbg-305mAh-averaged {
+	qcom,battery-type = "305MAH_AVERAGED";
+	qcom,batt-id-kohm = <10>;
+	qcom,capacity = <306>;
+	qcom,max-voltage-uv = <4400000>;
+	qcom,fastchg-current-ma = <305>;
+	qcom,checksum = <4291097>; /*@5, 0.005V, 4% */
+	qcom,soh-range = <0 100>;
+	/*Nominal_Impedance in 10nohm @ SOC 50% 25C* 0:fresh cell, 1: aged cell*/
+	qcom,battery-impedance = <95906000 191812000>;
+	/*Nominal_Capacity in mAh. 0: fresh cell, 1:aged cell*/
+	qcom,battery-capacity = <290 229>;
+	/*SOC delta (in percent) dropped from EOC SOC to enable recharge*/
+	qcom,recharge-soc-delta =<5>;
+	/*vfloat delta (in mV) dropped from regular vfloat in recharge*/
+	qcom,recharge-vflt-delta =<50>;
+	/*termination current (in mA) in recharge*/
+	qcom,recharge-iterm-ma = <6>;
+
+	qcom,jeita-fcc-ranges = <0  150 300000
+				151 420 300000
+				421 450 300000>;
+
+	qcom,jeita-fv-ranges = <0  150 4350000
+				151 420 4400000
+				421 450 4350000>;
+
+	qcom,jeita-soft-fcc-ua = <156000 200000>;
+	qcom,jeita-soft-fv-uv = <4350000 4350000>;
+
+	/* COOL = 15 DegC, WARM = 45 DegC */
+	qcom,jeita-soft-thresholds = <0x084E 0x02F5>;
+	/* COLD = 0 DegC, HOT = 45.1 DegC */
+	qcom,jeita-hard-thresholds = <0x0E46 0x02F2>;
+	/* COOL = 18 DegC, WARM = 44 DegC*/
+	qcom,jeita-soft-hys-thresholds = <0x0775 0x030E>;
+
+	qcom,bp-c-table-0 {
+		qcom,temperature = <25>;
+		qcom,soc = <    0    39    58    78    97>,
+			<  136   195   292   429   605>,
+			<  703   820  1230  1660  2089>,
+			< 2519  2949  3378  3808  4238>,
+			< 4668  5097  5527  5957  6386>,
+			< 6679  7011  7441  7793  8046>,
+			< 8476  8906  9335  9765 10000>;
+		qcom,ocv = <30000 31624 32313 32890 33333>,
+			<33923 34535 35328 36111 36802>,
+			<36976 37009 37107 37404 37703>,
+			<37930 38068 38190 38327 38495>,
+			<38696 38937 39240 39626 40124>,
+			<40429 40749 41160 41525 41800>,
+			<42271 42754 43237 43691 43888>;
+	};
+
+	qcom,bp-c-table-1 {
+		qcom,temperature = <(-20)>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 33162 43935 47433 43683 43715 55044>,
+			<43661 53533 33154 43966 47535 43707 43717 53512>,
+			<43664 54313 33152 43605 47154 43711 43736 53256>,
+			<43748 10827 33152 43587 47238 43699 43743 54029>,
+			<43723 10257 33152 43640 47977 43703 43730 53790>,
+			<43554 12213 33164 43532 48042 43663 43732 56388>,
+			<43625 11560 33206 43730 47803 43655 43567 56850>,
+			<43918  8255 32859 43724 42418 43678 43559 55529>,
+			<43783  9997 33173 43744 42220 43753 43583 56047>,
+			<43255 15048 33252 43672 42915 43765 43581 50963>,
+			<43029 14912 33276 43648 42942 43712 43576 50743>,
+			<43422 15280 33244 43698 43005 43534 43579 49501>,
+			<44644 15111 33212 43659 42051 43576 43570 50814>,
+			<44246 14406 33270 43675 48101 43712 43577 50428>,
+			<41603 16039 33087 43666 47963 43760 43570 50947>,
+			<41853 15987 33222 43759 47130 43751 43577 50697>,
+			<41263 16376 33173 43718 47602 43670 43579 49503>,
+			<42904 16145 33183 43559 48866 43674 43579 50856>,
+			<42058 15543 33257 43313 47326 43664 43994 51104>,
+			<47652 15573 33214 42336 41919 43716 45031 50181>,
+			<47254 15760 32774 47854 41975 43719 44905 50334>,
+			<47427 12947 32811 42307 41914 43719 44978 50721>,
+			<48957 13263 32831 42199 41777 43719 43504 49549>,
+			<48623 12326 32865 42222 41119 43718 43129 49576>,
+			<45656 12574 33192 42352 41210 43713 43476 49464>,
+			<45245 13834 32976 47687 41196 43713 44793 49501>,
+			<45513 14161 32968 47714 41132 43718 43331 49435>,
+			<47035 13682 32986 47768 41794 43738 43116 49621>,
+			<46299  3001 32780 47692 41445 43728 43037 50616>,
+			<46532  2216 32855 48003 42610 43743 43021 55738>,
+			<35766  2306 33037 47884 48090 43713 43202 55029>,
+			<34912  4057 33124 47963 48182 43713 43196 11457>,
+			<36573  3528 34768 41839 36598 43753 43935 15406>,
+			<35983  1015 34644 43082 33289 43655 43549  2911>,
+			<36282   225 34228 43555 35807 43657 43740 13762>;
+	};
+
+	qcom,bp-c-table-2 {
+		qcom,temperature = <(-10)>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 33162 43935 47433 43683 43715 55044>,
+			<43661 53533 33154 43966 47535 43707 43717 53512>,
+			<43664 54313 33152 43605 47154 43711 43736 53256>,
+			<43748 10827 33152 43587 47238 43699 43743 54029>,
+			<43723 10257 33152 43640 47977 43703 43730 53790>,
+			<43554 12213 33164 43532 48042 43663 43732 56388>,
+			<43625 11560 33206 43730 47803 43655 43567 56850>,
+			<43918  8255 32859 43724 42418 43678 43559 55529>,
+			<43783  9997 33173 43744 42220 43753 43583 56047>,
+			<43255 15048 33252 43672 42915 43765 43581 50963>,
+			<43029 14912 33276 43648 42942 43712 43576 50743>,
+			<43422 15280 33244 43698 43005 43534 43579 49501>,
+			<44644 15111 33212 43659 42051 43576 43570 50814>,
+			<44246 14406 33270 43675 48101 43712 43577 50428>,
+			<41603 16039 33087 43666 47963 43760 43570 50947>,
+			<41853 15987 33222 43759 47130 43751 43577 50697>,
+			<41263 16376 33173 43718 47602 43670 43579 49503>,
+			<42904 16145 33183 43559 48866 43674 43579 50856>,
+			<42058 15543 33257 43313 47326 43664 43994 51104>,
+			<47652 15573 33214 42336 41919 43716 45031 50181>,
+			<47254 15760 32774 47854 41975 43719 44905 50334>,
+			<47427 12947 32811 42307 41914 43719 44978 50721>,
+			<48957 13263 32831 42199 41777 43719 43504 49549>,
+			<48623 12326 32865 42222 41119 43718 43129 49576>,
+			<45656 12574 33192 42352 41210 43713 43476 49464>,
+			<45245 13834 32976 47687 41196 43713 44793 49501>,
+			<45513 14161 32968 47714 41132 43718 43331 49435>,
+			<47035 13682 32986 47768 41794 43738 43116 49621>,
+			<46299  3001 32780 47692 41445 43728 43037 50616>,
+			<46532  2216 32855 48003 42610 43743 43021 55738>,
+			<35766  2306 33037 47884 48090 43713 43202 55029>,
+			<34912  4057 33124 47963 48182 43713 43196 11457>,
+			<36573  3528 34768 41839 36598 43753 43935 15406>,
+			<35983  1015 34644 43082 33289 43655 43549  2911>,
+			<36282   225 34228 43555 35807 43657 43740 13762>;
+	};
+
+	qcom,bp-c-table-3 {
+		qcom,temperature = <0>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 33162 43935 47433 43683 43715 55044>,
+			<43661 53533 33154 43966 47535 43707 43717 53512>,
+			<43664 54313 33152 43605 47154 43711 43736 53256>,
+			<43748 10827 33152 43587 47238 43699 43743 54029>,
+			<43723 10257 33152 43640 47977 43703 43730 53790>,
+			<43554 12213 33164 43532 48042 43663 43732 56388>,
+			<43625 11560 33206 43730 47803 43655 43567 56850>,
+			<43918  8255 32859 43724 42418 43678 43559 55529>,
+			<43783  9997 33173 43744 42220 43753 43583 56047>,
+			<43255 15048 33252 43672 42915 43765 43581 50963>,
+			<43029 14912 33276 43648 42942 43712 43576 50743>,
+			<43422 15280 33244 43698 43005 43534 43579 49501>,
+			<44644 15111 33212 43659 42051 43576 43570 50814>,
+			<44246 14406 33270 43675 48101 43712 43577 50428>,
+			<41603 16039 33087 43666 47963 43760 43570 50947>,
+			<41853 15987 33222 43759 47130 43751 43577 50697>,
+			<41263 16376 33173 43718 47602 43670 43579 49503>,
+			<42904 16145 33183 43559 48866 43674 43579 50856>,
+			<42058 15543 33257 43313 47326 43664 43994 51104>,
+			<47652 15573 33214 42336 41919 43716 45031 50181>,
+			<47254 15760 32774 47854 41975 43719 44905 50334>,
+			<47427 12947 32811 42307 41914 43719 44978 50721>,
+			<48957 13263 32831 42199 41777 43719 43504 49549>,
+			<48623 12326 32865 42222 41119 43718 43129 49576>,
+			<45656 12574 33192 42352 41210 43713 43476 49464>,
+			<45245 13834 32976 47687 41196 43713 44793 49501>,
+			<45513 14161 32968 47714 41132 43718 43331 49435>,
+			<47035 13682 32986 47768 41794 43738 43116 49621>,
+			<46299  3001 32780 47692 41445 43728 43037 50616>,
+			<46532  2216 32855 48003 42610 43743 43021 55738>,
+			<35766  2306 33037 47884 48090 43713 43202 55029>,
+			<34912  4057 33124 47963 48182 43713 43196 11457>,
+			<36573  3528 34768 41839 36598 43753 43935 15406>,
+			<35983  1015 34644 43082 33289 43655 43549  2911>,
+			<36282   225 34228 43555 35807 43657 43740 13762>;
+	};
+
+	qcom,bp-c-table-4 {
+		qcom,temperature = <10>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 35713 43533 42854 43686 43740 58470>,
+			<43661 53556 35433 43557 42989 43699 43734 59267>,
+			<43664 54518 35387 43563 42926 43662 43562 59135>,
+			<43748 10753 35528 43736 42603 43672 43561 57641>,
+			<43723 10460 35485 43721 42539 43753 43567 57373>,
+			<43554 11897 46404 43756 42659 43718 43553 58261>,
+			<43625 11665 46340 43661 41428 43538 43579 60704>,
+			<43918  8447 46434 43711 41387 43982 43571 60589>,
+			<43783 10183 46336 43694 41015 43442 43531 61136>,
+			<43255 14983 46394 43688 41822 44783 43522 59466>,
+			<43029 14959 46578 43688 41738 44688 43575 60224>,
+			<43422 14916 46572 43688 41841 44668 43569 60206>,
+			<44644 15297 46473 43154 41827 43968 43898 59625>,
+			<44246 14545 46519 41863 44885 43565 44059 61155>,
+			<41603 14603 46465 41969 44264 43555 44443 59728>,
+			<41853 15908 46160 41731 44193 43564 44152 59493>,
+			<41263 16302 46146 41855 44208 43566 44248 60287>,
+			<42904 16321 46147 41128 44185 43560 44175 60369>,
+			<42058 16244 46195 41167 44231 43733 44196 60193>,
+			<47652 15553 46086 40980 44460 43732 44897 60252>,
+			<47254 15805 46122 41038 41679 43732 44945 59515>,
+			<47427 15733 46090 41394 40998 43733 44919 60971>,
+			<48957 12885 46209 41392 41024 43729 44372 61171>,
+			<48623 12311 46929 41005 44104 43732 44202 38362>,
+			<45656 13978 46956 40966 44239 43562 44805 38105>,
+			<45245 14211 46877 41087 44138 43562 44908 37920>,
+			<45513 13328 46951 41832 44210 43563 43332 38848>,
+			<47035  2810 46915 41197 44171 43733 44773 38140>,
+			<46299  2877 46940 41060 44251 43735 44757 38162>,
+			<46532  2102 46967 41028 44132 43734 44699 60127>,
+			<35766  3788 46899 41229 44332 43728 44696 59634>,
+			<34912  3220 46902 42649 41815 43731 43281 60675>,
+			<36573   648 46929 42683 47850 43729 43008 63899>,
+			<35983   852 46174 41925 48379 43729 43882 63418>,
+			<36282    91 35476 44681 48555 43767 43633 63337>;
+	};
+
+	qcom,bp-c-table-5 {
+		qcom,temperature = <25>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 47424 44718 44638 43713 43932 32945>,
+			<43661 53538 48772 44779 44557 43738 43859 33766>,
+			<43664 54419 48879 44799 44754 43736 43239 33357>,
+			<43748 10960 48893 44745 44780 43743 43058 33321>,
+			<43723 10399 48841 44742 44734 43730 43123 33420>,
+			<43554 11817 48837 44760 43283 43733 43414 36316>,
+			<43625 11341 48837 44739 43460 43565 43472 35895>,
+			<43918  8362 48820 43351 43306 43579 43101 36612>,
+			<43783 10149 47437 44558 43115 43569 44623 36431>,
+			<43255  9576 47361 44796 43126 43534 44740 36530>,
+			<43029 15066 47384 44779 43219 43530 44973 35269>,
+			<43422 14907 47362 44791 43040 43575 45000 35300>,
+			<44644 14937 47581 44976 44675 43572 44817 36477>,
+			<44246 14518 47607 44832 44646 43575 44139 36825>,
+			<41603 14829 47612 44851 44981 43572 44427 36804>,
+			<41853 16000 47591 44205 45009 43571 44316 36727>,
+			<41263 15902 47491 44160 45030 43581 41713 36840>,
+			<42904 16260 47534 44170 44974 43580 44315 36600>,
+			<42058 16157 47218 44180 44627 43577 44433 35157>,
+			<47652 15605 47200 44244 44964 43557 44078 36539>,
+			<47254 15746 47208 44152 44842 43559 44834 36406>,
+			<47427 12979 47130 44475 44094 43559 44649 36707>,
+			<48957 13282 47165 44477 44383 43578 44742 35937>,
+			<48623 12384 47311 44075 41502 43576 44177 36037>,
+			<45656 13846 47311 44871 44570 43582 45041 35617>,
+			<45245 14151 47307 44871 44732 43582 45041 35757>,
+			<45513 13703 47346 44887 43346 43582 45009 35411>,
+			<47035  2658 47334 44223 44770 43583 44928 35778>,
+			<46299  2207 47252 44214 44592 43583 44597 35653>,
+			<46532  2530 47263 44173 44660 43582 44756 35019>,
+			<35766  4021 47258 44247 45002 43582 44552 35223>,
+			<34912  3496 47294 44145 44204 43582 44556 36572>,
+			<36573   591 47320 44427 41595 43577 43373 33328>,
+			<35983     1 47539 44668 42550 43557 43855 34343>,
+			<36282   474 48838 44588 41374 43731 43829 34533>;
+	};
+
+	qcom,bp-c-table-6 {
+		qcom,temperature = <40>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 42133 43465 43515 43567 43802 48586>,
+			<43661 53744 42121 43460 43454 43553 43412 48219>,
+			<43664 55132 42175 43482 43103 43556 44718 48145>,
+			<43748 10895 42157 43480 43135 43579 44651 48173>,
+			<43723 11109 42835 43483 43036 43582 45019 48382>,
+			<43554 11961 42826 43463 43222 43571 44088 48990>,
+			<43625 11485 42863 43464 43157 43530 44543 49119>,
+			<43918  9018 42756 43395 43194 43522 44238 48736>,
+			<43783  9743 42793 43101 43187 43527 45015 48840>,
+			<43255  9712 42945 43106 43190 43548 44988 47445>,
+			<43029 15030 42959 43052 43868 43542 44978 47404>,
+			<43422 15083 42993 43063 43842 43551 44818 47400>,
+			<44644 14899 42987 43429 43500 43549 44559 49054>,
+			<44246 15214 42905 43400 43517 43550 44858 49031>,
+			<41603 14415 42891 43470 43319 43536 44101 48933>,
+			<41853 14691 42919 43309 43271 43546 44465 48897>,
+			<41263 16065 42587 43476 43270 43547 44430 49115>,
+			<42904 15940 42619 43313 43465 43524 44328 49077>,
+			<42058 16174 42503 43282 43508 43522 44154 49083>,
+			<47652 15504 42537 43328 43475 43529 44913 49043>,
+			<47254 15804 42712 44723 43377 43528 44652 48924>,
+			<47427 12938 42697 44686 44753 43529 43356 48381>,
+			<48957 13252 42721 44711 44636 43533 43314 48188>,
+			<48623 12731 42730 43320 44638 43526 43323 48981>,
+			<45656 13916 42629 43496 43009 43533 44948 47599>,
+			<45245 13475 42637 43415 43008 43520 44963 47506>,
+			<45513 13801 42637 43412 43026 43521 44561 47593>,
+			<47035  2655 42628 43490 43448 43520 44769 47365>,
+			<46299  2267 42629 43492 43471 43526 43329 48828>,
+			<46532  2349 42653 43472 43320 43524 44685 48683>,
+			<35766  4035 42723 43361 43332 43525 44756 49145>,
+			<34912  3576 42751 43382 44583 43525 44730 48304>,
+			<36573   902 42695 44672 44941 43544 44769 48514>,
+			<35983   114 42608 43313 41563 43526 43115 45139>,
+			<36282   265 42141 43253 44158 43539 43805 45990>;
+	};
+
+	qcom,bp-c-table-7 {
+		qcom,temperature = <50>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 41227 43112 43026 43569 43403 47305>,
+			<43661 53643 41253 43118 43069 43573 44718 47282>,
+			<43664 55052 41260 43112 43052 43531 44591 47961>,
+			<43748 54633 41431 43028 43228 43528 44963 47994>,
+			<43723 11214 41438 43024 43212 43534 44833 47879>,
+			<43554 10499 41423 43013 43245 43522 44252 48070>,
+			<43625 11454 41464 43016 43189 43526 44539 48063>,
+			<43918  9115 41365 43047 43842 43544 44300 47627>,
+			<43783  9955 41355 43217 43878 43551 44289 47845>,
+			<43255  9634 41377 43213 43781 43627 44387 42320>,
+			<43029  9585 41387 43196 43824 43616 44109 42287>,
+			<43422 15021 41055 43860 43825 43619 44105 42434>,
+			<44644 15092 41029 43230 43025 43631 44641 47702>,
+			<44246 15150 41034 43200 43033 43625 44918 47734>,
+			<41603 14337 41086 43203 43089 43616 44202 48056>,
+			<41853 14628 41064 43218 43402 43627 44887 48025>,
+			<41263 16022 40975 43209 43396 43625 44811 48045>,
+			<42904 15995 41005 43042 43027 43536 44082 47625>,
+			<42058 16346 41176 43022 43119 43551 44900 47636>,
+			<47652 15492 41162 43114 43434 43524 44571 48033>,
+			<47254 15803 41188 43105 43481 43524 43279 47915>,
+			<47427 12943 41108 43121 43378 43546 43519 47937>,
+			<48957 13265 41093 43122 43333 43545 43501 47966>,
+			<48623 12682 41097 43219 43300 43538 43458 48045>,
+			<45656 13904 41138 43190 43157 43541 44746 42470>,
+			<45245 13484 41150 43187 43232 43624 44726 42491>,
+			<45513 13806 41145 43166 43254 43627 44768 42451>,
+			<47035  2647 41139 43225 43044 43626 44548 42323>,
+			<46299  2257 41096 43055 43125 43540 44738 47861>,
+			<46532  2367 41102 43042 43407 43541 44686 47621>,
+			<35766  4054 41088 43060 43320 43543 43359 48021>,
+			<34912  3528 41112 43108 43329 43537 44681 47997>,
+			<36573   914 41108 43094 44581 43626 44686 47213>,
+			<35983   117 40995 43438 44225 43624 43457 48705>,
+			<36282   263 41340 43829 44176 43645 43807 48659>;
+	};
+
+	qcom,bp-d-table-0 {
+		qcom,temperature = <25>;
+		qcom,soc = <    0    39    58    78    97>,
+			<  136   195   292   429   605>,
+			<  703   820  1230  1660  2089>,
+			< 2519  2949  3378  3808  4238>,
+			< 4668  5097  5527  5957  6386>,
+			< 6679  7011  7441  7793  8046>,
+			< 8476  8906  9335  9765 10000>;
+		qcom,ocv = <31073 31787 32126 32450 32757>,
+			<33307 33966 34776 35568 36347>,
+			<36629 36779 36885 37084 37355>,
+			<37558 37757 37937 38107 38291>,
+			<38507 38759 39063 39479 39993>,
+			<40313 40635 41062 41430 41705>,
+			<42182 42666 43143 43619 43880>;
+	};
+
+	qcom,bp-d-table-1 {
+		qcom,temperature = <(-20)>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 53660 64259 21845 21845 43689 43705 21845>,
+			<43661 55283 63747 21845 21845 43688 43685 21845>,
+			<43664 54516 65027 21845 21845 43691 43707 21845>,
+			<43748 54781 65312 21845 21845 43691 43711 21845>,
+			<43723 10979 64671 21845 21845 43690 43697 21845>,
+			<43554 10413 64559 21845 21845 43690 43650 21845>,
+			<43625 11995 65471 21845 21845 43690 43768 21845>,
+			<43918 11772 65193 21845 21845 43690 43556 21845>,
+			<43783  9046 63525 21845 12654 43690 43541 21845>,
+			<43255  9875 64334 21845 62536 43690 43642 21845>,
+			<43029 10122 64245 21845 64090 43690 43632 21845>,
+			<43422 10052 58432 21845 61360 43690 43646 21845>,
+			<44644  9577 58479 21845 60678 43690 43941 21845>,
+			<44246 14944 58905 21845 37937 43690 43613 21845>,
+			<41603 15156 57646 21845 38947 43690 43936 21845>,
+			<41853 14584 57594 30648 33702 43691 43917 21845>,
+			<41263 14427 60725 27562 36567 43691 43908 21845>,
+			<42904 14628 60593  3502 35555 43691 44003 21845>,
+			<42058 16013 60942  9504 46887 43691 44024 21845>,
+			<47652 15979 59707 54774 45349 43691 44020 21845>,
+			<47254 16375 59901 55359 45899 43691 43992 21845>,
+			<47427 16213 59745 52773 45785 43691 43987 21845>,
+			<48957 15390 59604 61929 48535 43691 43813 21845>,
+			<48623 15678 59596 61556 48189 43691 43885 21845>,
+			<45656 12909 60290 61479 48571 43691 43146 21845>,
+			<45245 13157 59995 61550 45702 43691 43256 21845>,
+			<45513 12699 59988 63155 45060 43691 43042 21845>,
+			<47035 14233 60017 52167 46878 43691 43300 21845>,
+			<46299 13643 60023 49709 33362 43691 44591 21845>,
+			<46532  3038 59973 49605 33792 43691 44671 21845>,
+			<35766  2091 60209 49630 33206 43691 43171 21845>,
+			<34912  3638 60014 53309 35892 43691 43236 21845>,
+			<36573  3469 59923  8750 35237 43691 43149 21845>,
+			<35983   186 60411 14552 35339 43691 43993 21845>,
+			<36282   379 60263 15528 46403 43691 43599 21845>;
+	};
+
+	qcom,bp-d-table-2 {
+		qcom,temperature = <(-10)>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 54802 38511 21845 21845 43708 43690 21845>,
+			<43661 54507 38770 21845 21845 43685 43706 21845>,
+			<43664 54697 38133 21845 21845 43681 43700 21845>,
+			<43748 54638 38012 21845 21845 43682 43674 21845>,
+			<43723 10798 38302 21845 21845 43694 43759 21845>,
+			<43554 11093 38352 21845 21845 43690 43741 21845>,
+			<43625 11926 38099 21845 26496 43690 43594 21845>,
+			<43918 11742 38511 17769 63508 43690 43826 21845>,
+			<43783  8197 36957  6979 33067 43690 43253 21845>,
+			<43255 10134 37434 11872 46839 43691 43115 21845>,
+			<43029  9351 40418 55369 45818 43691 43080 21845>,
+			<43422  9308 40097 53114 48256 43691 43116 21845>,
+			<44644 15047 40617 51903 45701 43691 43232 21845>,
+			<44246 15336 39176 63993 47360 43691 43165 21845>,
+			<41603 15195 39341 57419 47910 43691 43195 21845>,
+			<41853 14393 40628 60164 47721 43691 43851 21845>,
+			<41263 14745 39321 38593 47752 43688 43865 21845>,
+			<42904 14701 39386 40090 47661 43688 43880 21678>,
+			<42058 16115 40618 39879 47661 43688 43805 23876>,
+			<47652 15943 39269 34621 47760 43688 43797 22748>,
+			<47254 16163 39392 32897 47752 43688 43880 17639>,
+			<47427 15509 39233 33481 47846 43688 43883 17982>,
+			<48957 15770 40653 33286 42310 43688 43143 17979>,
+			<48623 13013 39191 33379 47966 43688 43066 18219>,
+			<45656 13140 39385 33336 48818 43688 43220 17499>,
+			<45245 12787 39380 32865 48374 43688 43413 22649>,
+			<45513 14314 39185 39738 45069 43688 44835 22280>,
+			<47035 13569 39340 39696 36710 43688 43349 21845>,
+			<46299  2657 39328 38978 36513 43688 43041 21845>,
+			<46532  2853 39348 40563 35809 43688 43194 21845>,
+			<35766  2519 39310 38436 46217 43688 43221 21845>,
+			<34912  3883 38978 61153 46097 43688 43206 21845>,
+			<36573  3351 39018 58953 46669 43688 43165 21845>,
+			<35983   149 38922 64705 48475 43691 43892 21845>,
+			<36282   278 38920 61786 48986 43691 43803 21845>;
+	};
+
+	qcom,bp-d-table-3 {
+		qcom,temperature = <0>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 53322 33863 21845 21845 43708 43690 21845>,
+			<43661 55283 34269 21845 21845 43685 43690 21845>,
+			<43664 54316 34256 21845 21845 43686 43673 21845>,
+			<43748 54543 34294 21845 21845 43682 43730 21845>,
+			<43723 10782 34189 21845 21845 43695 43540 21845>,
+			<43554 10290 33841  6719 19581 43691 44006 21845>,
+			<43625 11898 34689 56657 63547 43691 43165 21845>,
+			<43918 11526 32845 61446 35202 43691 43513 21845>,
+			<43783  8312 33572 38179 48098 43691 43379 21594>,
+			<43255 10006 33686 40556 42268 43691 44774 17106>,
+			<43029  9219 33700 39137 42289 43691 43343 20084>,
+			<43422  9717 33316 34286 42425 43691 43404 19116>,
+			<44644 15062 36217 39155 42200 43691 43256 19098>,
+			<44246 15246 36132 33160 41293 43691 43188 30752>,
+			<41603 15172 33415 36549 41325 43688 43232 27956>,
+			<41853 14444 36216 46143 42557 43688 43050  5309>,
+			<41263 14786 33442 45669 42558 43688 43236  7830>,
+			<42904 14683 36160 48664 42559 43688 43197  1950>,
+			<42058 16088 36183 47657 42931 43689 43881   701>,
+			<47652 15953 33454 42987 42970 43689 43791  2362>,
+			<47254 16138 36198 42505 42912 43689 43881 13587>,
+			<47427 15403 36193 42244 42639 43689 43226 14166>,
+			<48957 15645 33414 47258 42212 43694 43127 13661>,
+			<48623 13232 33411 48814 47742 43694 43123  2532>,
+			<45656 12343 33436 48939 47339 43692 43131  3977>,
+			<45245 14050 33522 48174 48368 43701 43319   311>,
+			<45513 13314 33323 48604 46167 43721 44868  4246>,
+			<47035 13695 36319 48194 46605 43774 43038  7383>,
+			<46299  2962 36155 46822 48393 43750 43361  4642>,
+			<46532  2301 36101 46419 49096 43756 44559  4387>,
+			<35766  3748 36350 46384 48252 43678 43504  5425>,
+			<34912  3246 36279 35769 48415 43675 43440 28174>,
+			<36573   672 36322 36309 48558 43699 43048 24705>,
+			<35983   237 36172 39178 48677 43690 43998 31375>,
+			<36282   309 33509 37768 47195 43690 43585 31013>;
+	};
+
+	qcom,bp-d-table-4 {
+		qcom,temperature = <10>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 53271 35077 22500 21845 43664 43690 21845>,
+			<43661 55175 34854 31526 21845 43674 43690 21845>,
+			<43664 54513 35674  7356 21974 43651 43690 21845>,
+			<43748 54741 35833 13192 30774 43659 43549 21845>,
+			<43723 10812 35350 55025  3927 43699 43826 21845>,
+			<43554 10300 46360 57507 64861 43681 43395 21845>,
+			<43625 11863 46177 36167 35314 43689 44670 26318>,
+			<43918 11622 46227 46964 48874 43689 44183    81>,
+			<43783  8301 46261 48620 42875 43689 44663 12523>,
+			<43255 10014 46935 48002 42614 43689 43488 10129>,
+			<43029  9339 46959 47988 42924 43694 43290  8490>,
+			<43422  9513 46873 42332 42530 43694 43123  8719>,
+			<44644 15085 46992 42601 41093 43694 43235 11942>,
+			<44246 15272 47011 42578 41498 43693 43084 56599>,
+			<41603 14504 46976 41110 41773 43709 43434 50432>,
+			<41853 14414 47078 41145 44352 43743 44210 50116>,
+			<41263 14810 47081 41943 44097 43734 45020 51453>,
+			<42904 14709 47050 41679 44258 43563 44716 61813>,
+			<42058 16074 47007 41703 44806 43560 44710 64931>,
+			<47652 16266 47030 41560 44198 43560 44912 64648>,
+			<47254 15540 47094 41735 41641 43561 44444 64959>,
+			<47427 15805 47101 41149 41538 43554 44211 64920>,
+			<48957 13036 46985 41384 41127 43560 44825 62142>,
+			<48623 13062 47037 42658 41218 43734 45033 61588>,
+			<45656 12751 47060 42824 42219 43741 44812 62670>,
+			<45245 13944 47059 41996 47951 43743 45024 51312>,
+			<45513 13374 47012 42380 48566 43736 43300 52568>,
+			<47035  2737 46709 47294 47275 43721 43488 52316>,
+			<46299  3028 46710 47279 48111 43773 43420 52578>,
+			<46532  2104 46708 47987 48038 43769 43416 50102>,
+			<35766  3800 47020 47296 47747 43775 43298 49554>,
+			<34912  3273 47018 47150 47850 43768 43463 51026>,
+			<36573   767 46689 47245 42096 43751 43415 50437>,
+			<35983   245 46837 48031 41435 43757 43095 55964>,
+			<36282   289 46721 47688 41007 43753 43133 50459>;
+	};
+
+	qcom,bp-d-table-5 {
+		qcom,temperature = <25>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 54219 48371 21845 21845 43690 43690 21845>,
+			<43661 54913 49007 21845 21845 43690 43690 21845>,
+			<43664 55252 49112 29304 21845 43709 43577 21845>,
+			<43748 54376 49035 14095 21845 43667 43187 21845>,
+			<43723 54623 48767 52307   206 43773 43306 21845>,
+			<43554 10417 48846 46060 34294 43562 44814 56827>,
+			<43625 11780 48798 41983 47583 43561 44156 58008>,
+			<43918 11634 48775 44406 42177 43741 44292 60060>,
+			<43783  8282 47486 44470 41913 43729 44378 37438>,
+			<43255 10065 47457 44045 44442 43565 44323 39292>,
+			<43029  9663 47397 44133 44300 43552 44125 39294>,
+			<43422  9473 47413 44057 44266 43554 44902 39755>,
+			<44644 15039 47405 45020 44676 43567 44643 34664>,
+			<44246 14966 47593 44942 44777 43577 44610 32807>,
+			<41603 15169 47563 44934 44714 43569 44915 33463>,
+			<41853 14364 47196 44965 43367 43530 44240 36070>,
+			<41263 14807 47547 45004 44663 43573 44377 36281>,
+			<42904 16027 47521 45021 44816 43529 44536 36227>,
+			<42058 15985 47531 45012 44861 43528 44256 35896>,
+			<47652 16185 47223 44836 44985 43530 44198 36654>,
+			<47254 15553 47208 44813 44649 43572 44186 36449>,
+			<47427 15821 47215 44816 44547 43569 44283 36566>,
+			<48957 12861 47116 44925 44985 43570 44198 36429>,
+			<48623 12445 47104 44071 44510 43581 44894 36162>,
+			<45656 13971 47315 44434 41441 43580 44690 34454>,
+			<45245 14291 47301 44332 41440 43577 43519 34545>,
+			<45513 13329 47322 44393 41915 43554 43076 32803>,
+			<47035  2764 47302 44387 44525 43560 43320 33769>,
+			<46299  2940 47308 44296 44042 43563 44707 33307>,
+			<46532  2115 47307 44504 44239 43563 44773 33501>,
+			<35766  3692 47301 44425 44179 43564 44569 33511>,
+			<34912  3072 47308 44128 44275 43555 44553 33335>,
+			<36573   557 47142 44248 44167 43556 44760 33295>,
+			<35983   201 47174 44214 44810 43582 44682 33493>,
+			<36282   450 47543 44888 45049 43581 43347 33510>;
+	};
+
+	qcom,bp-d-table-6 {
+		qcom,temperature = <40>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 53902 42383 33702 40084 43665 43923 53967>,
+			<43661 53736 42104 46522 34491 43737 43111 51998>,
+			<43664 54804 41999 45870 36264 43552 43312 65357>,
+			<43748 54412 42195 48804 34951 43572 44746 57387>,
+			<43723 54736 42235 42413 46864 43524 44978 60067>,
+			<43554 11108 42174 44291 48176 43624 44264 39592>,
+			<43625 11982 42846 44962 48039 43539 44425 35956>,
+			<43918 11739 42877 44683 42986 43582 41645 35605>,
+			<43783  8392 42815 43388 41558 43577 41494 46618>,
+			<43255 10133 42998 43291 44765 43528 41582 48436>,
+			<43029  9255 42983 43387 44704 43522 41611 48531>,
+			<43422  9677 42985 43342 43274 43522 44819 48255>,
+			<44644  9595 42892 43448 43245 43526 44856 48889>,
+			<44246 14889 42580 43435 43220 43537 44925 48820>,
+			<41603 15161 42597 43078 43065 43539 44202 47462>,
+			<41853 14528 42502 43126 43128 43539 44182 47466>,
+			<41263 14821 42507 43454 43363 43626 44203 48748>,
+			<42904 16004 42540 43516 44658 43627 44805 48298>,
+			<42058 15943 42715 43491 44561 43626 44624 49001>,
+			<47652 16141 42738 43402 43356 43543 44603 48640>,
+			<47254 15569 42653 43455 43498 43551 44556 47459>,
+			<47427 15839 42638 43400 43079 43524 44959 47559>,
+			<48957 12811 42685 43405 43454 43524 45035 47399>,
+			<48623 12432 42680 43295 44608 43547 44954 48979>,
+			<45656 13956 42687 44775 44102 43525 43423 45666>,
+			<45245 14287 42672 44598 44093 43520 43101 45599>,
+			<45513 13322 42676 44665 44576 43575 43479 48209>,
+			<47035  2789 42632 44678 43358 43580 43488 49000>,
+			<46299  2923 42624 43346 43479 43581 43321 49037>,
+			<46532  2169 42654 43380 43414 43571 43329 48754>,
+			<35766  3588 42746 43317 43439 43574 44688 48861>,
+			<34912  3130 42739 43511 43091 43531 44744 48874>,
+			<36573   710 42691 43516 43085 43533 44658 48875>,
+			<35983   146 42536 43505 43109 43525 44807 48839>,
+			<36282   390 42533 43470 43114 43545 44199 48653>;
+	};
+
+	qcom,bp-d-table-7 {
+		qcom,temperature = <50>;
+		qcom,nrows = <35>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 53934 41328 47651 35472 43932 43196 60132>,
+			<43661 53365 41244 42846 46743 43953 43491 37497>,
+			<43664 55019 41231 42697 45215 43943 43343 40560>,
+			<43748 55101 41278 40981 45727 43946 44756 39496>,
+			<43723 54389 41257 41911 48354 43614 44987 34720>,
+			<43554 11165 41423 44189 47224 43639 44211 35992>,
+			<43625 11944 41448 43351 42398 43626 44419 46439>,
+			<43918 11651 41395 43422 42669 43530 41659 45354>,
+			<43783  8320 41054 43083 41872 43529 41489 45735>,
+			<43255  9819 41060 43115 44692 43524 41570 47211>,
+			<43029  9361 40983 43107 43398 43544 41477 47872>,
+			<43422  9631 40985 43452 43428 43525 44063 47991>,
+			<44644  9482 41010 43160 43851 43541 45010 42279>,
+			<44246 15096 41173 43185 43149 43622 44632 42296>,
+			<41603 15299 41160 43239 43258 43646 44074 42341>,
+			<41853 14485 41197 43149 43221 43623 44891 42346>,
+			<41263 14734 41118 43166 43452 43621 45028 47847>,
+			<42904 16052 41102 43237 44787 43647 44764 47921>,
+			<42058 15936 41146 43158 44773 43644 43360 48091>,
+			<47652 16142 41812 43162 43509 43643 43390 47818>,
+			<47254 15575 41819 43258 43023 43622 44665 42269>,
+			<47427 15824 41807 43263 43263 43628 44839 42443>,
+			<48957 12802 41840 43210 43051 43626 44839 42297>,
+			<48623 12437 41851 43116 44697 43541 44622 47879>,
+			<45656 13954 41850 43477 44990 43536 43518 47556>,
+			<45245 14326 41850 43275 44668 43545 43395 47609>,
+			<45513 13374 41854 43278 43511 43523 43373 47951>,
+			<47035  2796 41841 43314 43221 43523 44984 48063>,
+			<46299  2834 41800 43394 43223 43535 44789 47662>,
+			<46532  2144 41795 43119 43051 43529 43365 47770>,
+			<35766  3599 41811 43058 43153 43524 44783 42340>,
+			<34912  3106 41135 43253 43136 43545 44751 42285>,
+			<36573   715 41150 43161 43137 43542 44755 42441>,
+			<35983   130 41090 43199 43158 43616 44591 42441>,
+			<36282   434 41112 43172 43237 43642 44591 42452>;
+	};
+};
diff --git a/qcom/qbg-battery-profile-alium-860-89032-0000-3600mAh.dtsi b/qcom/qbg-battery-profile-alium-860-89032-0000-3600mAh.dtsi
new file mode 100755
index 00000000..8e4974d1
--- /dev/null
+++ b/qcom/qbg-battery-profile-alium-860-89032-0000-3600mAh.dtsi
@@ -0,0 +1,552 @@
+qcom,qbg-battery-profile-alium-860-89032-0000-3600mAh {
+	qcom,battery-type = "ALIUM_860_89032_0000_3600MAH";
+	qcom,batt-id-kohm = <107>;
+	qcom,capacity = <3588>;
+	qcom,max-voltage-uv = <4350000>;
+	qcom,fastchg-current-ma = <3600>;
+	qcom,checksum = <4563678>; /*@5, 0.005V, 10% */
+	qcom,soh-range = <0 100>;
+	/* Nominal_Capacity in mAh. 0: fresh cell, 1:aged cell */
+	qcom,battery-capacity = <3408 2691>;
+	/* SOC delta (in percent) dropped from EOC SOC to enable recharge */
+	qcom,recharge-soc-delta =<5>;
+	/* vfloat delta (in mV) dropped from regular vfloat in recharge */
+	qcom,recharge-vflt-delta =<50>;
+	/* termination current (in mA) in recharge */
+	qcom,recharge-iterm-ma = <300>;
+	qcom,bp-c-table-0 {
+		qcom,temperature = <25>;
+		qcom,soc = <    0    19    39    58    78>,
+			<   97   136   214   312   449>,
+			<  605   722  1093  1640  2617>,
+			< 3886  5019  5683  6210  6621>,
+			< 7031  7343  7519  7871  8027>,
+			< 8554  9101  9628 10000>;
+		qcom,ocv = <30000 30863 31659 32364 32956>,
+			<33410 34016 34824 35559 36295>,
+			<36867 37001 37083 37388 37894>,
+			<38164 38590 38975 39497 39791>,
+			<40073 40586 40837 41110 41228>,
+			<41772 42360 42953 43365>;
+	};
+
+	qcom,bp-c-table-1 {
+		qcom,temperature = <(-20)>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 44160 43965 44002 43601 41390 42954>,
+			<43705 53789 44184 43942 44013 43604 41068 42903>,
+			<43661 53585 44179 43946 44012 43945 41181 42931>,
+			<43664 54350 44180 43614 44015 43949 41137 42589>,
+			<43748 11251 44267 43587 44014 43943 41746 42623>,
+			<43723 10728 44270 43639 44009 43961 41976 42526>,
+			<43554 12062 44268 43629 44010 43957 41534 42717>,
+			<43644  8826 44271 43523 43933 43920 44406 42687>,
+			<43922  8449 44185 43570 43907 43976 41611 41327>,
+			<43883  9254 44179 43730 43919 43808 44367 41425>,
+			<43255 14867 44167 43672 44001 44025 45053 41445>,
+			<43128 15244 44168 43672 44029 44024 45048 41451>,
+			<44783 15158 44173 43774 44013 43988 44048 41467>,
+			<44226 14421 44161 43540 44013 43793 41113 41326>,
+			<41107 15967 44173 43625 43776 43793 41789 41295>,
+			<42372 15526 44884 43584 43856 43898 41322 41282>,
+			<47409 15831 44867 43908 43900 43066 47981 41317>,
+			<48281 12906 44874 44012 43875 43131 48704 41247>,
+			<45800 13155 44916 43995 43899 43076 48598 41287>,
+			<45943 12500 44865 43789 43856 43091 45767 42694>,
+			<45533 12745 44884 43866 43224 43448 45801 42993>,
+			<46597 13859 44193 43189 43133 43499 45732 42112>,
+			<47093 14086 44221 43184 43128 43496 48592 42215>,
+			<46101  2729 44165 43176 43029 43392 48814 42199>,
+			<46577  2616 44188 43179 43085 43392 47122 42001>,
+			<35776  2202 44260 43180 43334 43496 42250 42316>,
+			<35111  3788 44259 43191 44671 43496 42897 48054>,
+			<36662  3128 44267 43146 44800 43421 41436 47272>,
+			<36282   748 44268 43594 44960 41594 44901 47858>;
+	};
+
+	qcom,bp-c-table-2 {
+		qcom,temperature = <(-10)>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 44160 43965 44002 43601 41390 42954>,
+			<43705 53789 44184 43942 44013 43604 41068 42903>,
+			<43661 53585 44179 43946 44012 43945 41181 42931>,
+			<43664 54350 44180 43614 44015 43949 41137 42589>,
+			<43748 11251 44267 43587 44014 43943 41746 42623>,
+			<43723 10728 44270 43639 44009 43961 41976 42526>,
+			<43554 12062 44268 43629 44010 43957 41534 42717>,
+			<43644  8826 44271 43523 43933 43920 44406 42687>,
+			<43922  8449 44185 43570 43907 43976 41611 41327>,
+			<43883  9254 44179 43730 43919 43808 44367 41425>,
+			<43255 14867 44167 43672 44001 44025 45053 41445>,
+			<43128 15244 44168 43672 44029 44024 45048 41451>,
+			<44783 15158 44173 43774 44013 43988 44048 41467>,
+			<44226 14421 44161 43540 44013 43793 41113 41326>,
+			<41107 15967 44173 43625 43776 43793 41789 41295>,
+			<42372 15526 44884 43584 43856 43898 41322 41282>,
+			<47409 15831 44867 43908 43900 43066 47981 41317>,
+			<48281 12906 44874 44012 43875 43131 48704 41247>,
+			<45800 13155 44916 43995 43899 43076 48598 41287>,
+			<45943 12500 44865 43789 43856 43091 45767 42694>,
+			<45533 12745 44884 43866 43224 43448 45801 42993>,
+			<46597 13859 44193 43189 43133 43499 45732 42112>,
+			<47093 14086 44221 43184 43128 43496 48592 42215>,
+			<46101  2729 44165 43176 43029 43392 48814 42199>,
+			<46577  2616 44188 43179 43085 43392 47122 42001>,
+			<35776  2202 44260 43180 43334 43496 42250 42316>,
+			<35111  3788 44259 43191 44671 43496 42897 48054>,
+			<36662  3128 44267 43146 44800 43421 41436 47272>,
+			<36282   748 44268 43594 44960 41594 44901 47858>;
+	};
+
+	qcom,bp-c-table-3 {
+		qcom,temperature = <0>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 44160 43965 44002 43601 41390 42954>,
+			<43705 53789 44184 43942 44013 43604 41068 42903>,
+			<43661 53585 44179 43946 44012 43945 41181 42931>,
+			<43664 54350 44180 43614 44015 43949 41137 42589>,
+			<43748 11251 44267 43587 44014 43943 41746 42623>,
+			<43723 10728 44270 43639 44009 43961 41976 42526>,
+			<43554 12062 44268 43629 44010 43957 41534 42717>,
+			<43644  8826 44271 43523 43933 43920 44406 42687>,
+			<43922  8449 44185 43570 43907 43976 41611 41327>,
+			<43883  9254 44179 43730 43919 43808 44367 41425>,
+			<43255 14867 44167 43672 44001 44025 45053 41445>,
+			<43128 15244 44168 43672 44029 44024 45048 41451>,
+			<44783 15158 44173 43774 44013 43988 44048 41467>,
+			<44226 14421 44161 43540 44013 43793 41113 41326>,
+			<41107 15967 44173 43625 43776 43793 41789 41295>,
+			<42372 15526 44884 43584 43856 43898 41322 41282>,
+			<47409 15831 44867 43908 43900 43066 47981 41317>,
+			<48281 12906 44874 44012 43875 43131 48704 41247>,
+			<45800 13155 44916 43995 43899 43076 48598 41287>,
+			<45943 12500 44865 43789 43856 43091 45767 42694>,
+			<45533 12745 44884 43866 43224 43448 45801 42993>,
+			<46597 13859 44193 43189 43133 43499 45732 42112>,
+			<47093 14086 44221 43184 43128 43496 48592 42215>,
+			<46101  2729 44165 43176 43029 43392 48814 42199>,
+			<46577  2616 44188 43179 43085 43392 47122 42001>,
+			<35776  2202 44260 43180 43334 43496 42250 42316>,
+			<35111  3788 44259 43191 44671 43496 42897 48054>,
+			<36662  3128 44267 43146 44800 43421 41436 47272>,
+			<36282   748 44268 43594 44960 41594 44901 47858>;
+	};
+
+	qcom,bp-c-table-4 {
+		qcom,temperature = <10>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 45033 43737 43603 43866 41563 41506>,
+			<43705 53766 44949 43738 43615 43178 41536 41690>,
+			<43661 53577 44945 43718 43611 43194 41551 41715>,
+			<43664 54292 44957 43715 43591 43147 41544 41705>,
+			<43748 11150 44953 43724 43587 43160 41547 41607>,
+			<43723 10326 44933 43721 43599 43246 41545 41661>,
+			<43554 12232 44930 43764 43636 43202 41536 44378>,
+			<43644  8751 44982 43774 43641 43036 41903 44295>,
+			<43922  8649 44987 43750 43619 43445 41931 44506>,
+			<43883  9454 44972 43751 43542 43300 41165 44527>,
+			<43255 15062 44630 43675 43626 43382 41676 44476>,
+			<43128 14925 44628 43679 43624 44718 41718 44452>,
+			<44783 15341 44627 43769 43549 43379 41249 44470>,
+			<44226 14371 44627 43637 43736 44651 37910 44528>,
+			<41107 15906 44613 43608 43735 44644 60857 44534>,
+			<42372 16330 44671 43960 43543 44544 57836 44350>,
+			<47409 15371 44642 43907 43608 44553 57110 44399>,
+			<48281 12899 44650 43963 43583 44742 57671 44522>,
+			<45800 12525 44571 43615 43579 44729 36578 44455>,
+			<45943 12714 44546 43958 43523 43379 36745 44437>,
+			<45533 13989 44546 44029 43592 43367 33164 44314>,
+			<46597 14183 44546 44013 43587 43369 36861 44292>,
+			<47093 13706 44550 43911 43595 43295 45396 44349>,
+			<46101  2616 44574 44008 43586 43268 45463 44309>,
+			<46577  2653 44562 44016 43607 43290 46905 44379>,
+			<35776  2120 44573 44021 44000 43285 45839 41703>,
+			<35111  4019 44651 44023 43872 43336 48949 41545>,
+			<36662  3523 44564 43604 43218 44073 42138 41879>,
+			<36282   937 44666 43576 43065 43488 41623 41555>;
+	};
+
+	qcom,bp-c-table-5 {
+		qcom,temperature = <25>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 43332 43718 43763 43378 46676 44985>,
+			<43705 53797 43329 43712 43763 44712 46710 44963>,
+			<43661 53505 43341 43725 43762 44672 46649 44629>,
+			<43664 54470 43342 43726 43773 44792 46721 44636>,
+			<43748 10774 43339 43720 43773 44755 45338 44614>,
+			<43723 10280 43380 43722 43772 44597 45443 44617>,
+			<43554 11850 43378 43761 43775 44623 45199 44665>,
+			<43644  8866 43367 43774 43769 45042 46057 44573>,
+			<43922  8269 43368 43770 43770 44818 46020 44554>,
+			<43883 10093 43283 43769 43746 44874 46300 44581>,
+			<43255 15017 43289 43749 43755 44267 35516 44753>,
+			<43128 14883 43288 43668 43748 44088 48866 44766>,
+			<44783 14961 43291 43763 43757 44915 36601 44589>,
+			<44226 14502 43268 43733 43770 44193 64491 44571>,
+			<41107 16044 43276 43565 43766 44884 63795 44561>,
+			<42372 16318 43312 43571 43720 44857 63606 44643>,
+			<47409 15380 43301 43577 43582 45042 33472 44609>,
+			<48281 12949 43298 43570 43545 44804 61244 44962>,
+			<45800 12515 43307 43558 43724 44812 58642 44599>,
+			<45943 12741 43472 43562 43722 44959 35952 44579>,
+			<45533 13859 43474 43533 43735 45034 39071 44647>,
+			<46597 13344 43472 43561 43728 44966 35574 44546>,
+			<47093 13615 43478 43743 43741 44634 45953 44594>,
+			<46101  2620 43473 43576 43740 44978 35216 44575>,
+			<46577  2982 43473 43568 43740 44935 35895 44567>,
+			<35776  2438 43475 43531 43560 44929 36356 44645>,
+			<35111  4050 43474 43532 43547 44954 35561 44975>,
+			<36662  3427 43473 43582 43603 45036 45867 44945>,
+			<36282   975 43472 43723 43960 44931 42369 44980>;
+	};
+
+	qcom,bp-c-table-6 {
+		qcom,temperature = <40>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 43505 43765 43675 44739 58612 44734>,
+			<43705 53966 43507 43767 43672 44606 58146 44709>,
+			<43661 53746 43517 43761 43672 44650 61420 44704>,
+			<43664 55133 43519 43763 43672 44615 60222 44716>,
+			<43748 10886 43513 43773 43673 44976 38086 44715>,
+			<43723 11080 43515 43775 43673 45039 37222 43351>,
+			<43554 11924 43495 43771 43673 44862 37542 43358>,
+			<43644 11736 43490 43751 43673 44202 40166 43341>,
+			<43922  8444 43497 43744 43674 44258 38461 43382>,
+			<43883 10129 43413 43756 43674 44094 38631 43384>,
+			<43255  9512 43414 43755 43648 44120 60617 43368>,
+			<43128 14976 43409 43666 43662 44472 40898 43289>,
+			<44783 15069 43408 43758 43678 44051 60003 43364>,
+			<44226 15113 43411 43750 43750 44093 59439 43332>,
+			<41107 14650 43420 43774 43770 44224 65165 43346>,
+			<42372 15936 43397 43763 43748 44800 38880 43357>,
+			<47409 15366 43394 43713 43721 44903 39733 44726>,
+			<48281 12945 43406 43721 43557 44205 40872 44688>,
+			<45800 12433 43402 43761 43714 44270 60945 44713>,
+			<45943 12572 43446 43774 43753 44908 40456 43385>,
+			<45533 13949 43440 43727 43723 44854 40753 44715>,
+			<46597 13367 43440 43749 43771 44922 35253 43377>,
+			<47093 13773 43441 43748 43750 44923 34973 43389>,
+			<46101  2603 43440 43764 43769 44811 34575 43334>,
+			<46577  2981 43443 43722 43775 44852 33813 43354>,
+			<35776  2543 43452 43720 43767 44850 33075 43346>,
+			<35111  3848 43455 43715 43730 44802 33637 44721>,
+			<36662  3422 43454 43765 43530 44914 34945 44700>,
+			<36282   808 43449 43712 43765 44073 36789 43345>;
+	};
+
+	qcom,bp-c-table-7 {
+		qcom,temperature = <50>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 43415 43760 43651 44707 65307 43336>,
+			<43705 53993 43409 43762 43648 44776 63897 43381>,
+			<43661 53693 43408 43772 43649 44759 64131 43377>,
+			<43664 55092 43410 43769 43654 44560 58990 43378>,
+			<43748 54635 43421 43771 43654 44637 58265 43390>,
+			<43723 11226 43420 43749 43655 44953 61196 43387>,
+			<43554 10599 43417 43745 43653 44810 38392 43361>,
+			<43644 11680 43397 43759 43674 44167 36864 43370>,
+			<43922  9049 43398 43755 43674 44072 38762 43293>,
+			<43883  9841 43395 43668 43652 44132 60565 43268>,
+			<43255  9603 43405 43666 43651 44505 64189 43317>,
+			<43128  9539 43404 43654 43701 44304 38320 43299>,
+			<44783 14995 43404 43676 43678 44532 37230 43267>,
+			<44226 15345 43404 43671 43745 44471 59557 43373>,
+			<41107 14817 43401 43754 43749 44115 57646 43366>,
+			<42372 15972 43447 43745 43759 44219 61314 43360>,
+			<47409 15366 43452 43774 43764 44823 32791 43328>,
+			<48281 13038 43451 43772 43733 44214 39831 44718>,
+			<45800 12516 43428 43756 43760 44284 37974 43367>,
+			<45943 12665 43425 43759 43668 44209 38319 43270>,
+			<45533 14270 43427 43748 43769 44874 38717 43360>,
+			<46597 13355 43427 43744 43753 44871 37475 43294>,
+			<47093 13725 43427 43745 43755 44864 36926 43294>,
+			<46101  2768 43437 43770 43744 44870 36983 43370>,
+			<46577  2994 43436 43770 43750 44874 37629 43368>,
+			<35776  2559 43438 43774 43775 44905 40470 43364>,
+			<35111  3858 43435 43773 43739 44822 33978 43329>,
+			<36662   687 43093 43748 43582 44877 36384 44712>,
+			<36282   813 43088 43768 43723 44316 35572 43367>;
+	};
+
+	qcom,bp-d-table-0 {
+		qcom,temperature = <25>;
+		qcom,soc = <    0    19    39    58    78>,
+			<   97   136   214   312   449>,
+			<  605   722  1093  1640  2617>,
+			< 3886  5019  5683  6210  6621>,
+			< 7031  7343  7519  7871  8027>,
+			< 8554  9101  9628 10000>;
+		qcom,ocv = <28020 29554 30909 31906 32434>,
+			<32777 33252 34082 34943 35817>,
+			<36507 36768 36886 37109 37543>,
+			<37954 38397 38781 39283 39670>,
+			<39927 40519 40770 40989 41101>,
+			<41666 42257 42876 43360>;
+	};
+
+	qcom,bp-d-table-1 {
+		qcom,temperature = <(-20)>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 55845 41409 21845 21845 43694 43705 21845>,
+			<43705 57283 41409 21845 21845 43695 43649 21845>,
+			<43661 53814 41409 21845 21845 43692 43774 21845>,
+			<43664 53319 41409 21845 21845 43692 43553 21845>,
+			<43748 54810 41423 21845 21845 43693 43641 21845>,
+			<43723 54402 41459 21845 21845 43692 43908 21845>,
+			<43554 10764 41360   386 63661 43692 43862 21845>,
+			<43644 11815 41045 55488 35741 43693 43379 30577>,
+			<43922 11521 40982 63723 47555 43692 44886  2459>,
+			<43883  8395 40961 40248 41338 43693 41911 56339>,
+			<43255  9955 41091 36084 44402 43682 42515 62276>,
+			<43128 10223 41131 35399 44101 43683 42773 64460>,
+			<44783  9704 41823 46673 41699 43683 42089 59385>,
+			<44226 14850 41143 48413 44295 43683 41448 60636>,
+			<41107 14470 41122 47597 44870 43683 41937 38251>,
+			<42372 14606 41812 42195 44615 43680 41542 37878>,
+			<47409 15985 41854 41448 44604 43680 41607 40513>,
+			<48281 16148 41794 41828 44585 43681 41726 38979>,
+			<45800 15381 41806 41905 44594 43686 41969 39793>,
+			<45943 15731 41798 41478 44633 43686 41207 39887>,
+			<45533 13236 41801 41648 44856 43687 41125 39843>,
+			<46597 12457 41803 44366 44825 43684 41587 39528>,
+			<47093 12368 41847 44357 44282 43684 41945 39914>,
+			<46101 13694 41835 41903 42479 43707 48631 37286>,
+			<46577  2623 41749 41916 47842 43707 45706 38580>,
+			<35776  2973 41829 41705 42094 43684 44421 36912>,
+			<35111  2462 41744 42345 41789 43705 41209 38706>,
+			<36662  3291 41803 47453 41798 43680 44262 61324>,
+			<36282   824 41130 49041 41026 43690 43690 57741>;
+	};
+
+	qcom,bp-d-table-2 {
+		qcom,temperature = <(-10)>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 50529 41780 21845 21845 43695 43710 21845>,
+			<43705 56941 41780 21845 21845 43686 43649 21845>,
+			<43661 53781 41780 21845 21845 43707 43726 21845>,
+			<43664 53705 41786 21845 21845 43705 43639 21845>,
+			<43748 55191 41926 21845 21845 43705 43783 21845>,
+			<43723 54284 41887 26259 21845 43706 43084 21845>,
+			<43554 10827 41570 57991 33374 43683 44899 13506>,
+			<43644 11872 41693 34887 41483 43693 41148 58785>,
+			<43922  8945 41723 45501 44208 43683 42555 59581>,
+			<43883  8511 41617 48394 44812 43683 42113 38905>,
+			<43255 10081 41616 48662 45012 43683 47757 37739>,
+			<43128  9325 41620 47175 45045 43683 47861 40400>,
+			<44783 14980 41610 47875 44222 43680 42894 40088>,
+			<44226 15283 41655 42088 44658 43680 41019 39731>,
+			<41107 14547 41612 40973 43366 43681 41203 33074>,
+			<42372 14666 41636 44169 43504 43685 41934 36413>,
+			<47409 15952 41614 44693 43437 43711 41572 35331>,
+			<48281 15535 41661 43367 43452 43703 40975 46479>,
+			<45800 15822 41647 43281 43387 43661 42933 46164>,
+			<45943 12863 41660 43314 44773 43673 42509 46146>,
+			<45533 13183 41609 43470 44759 43714 41320 46141>,
+			<46597 12703 41656 44685 44644 43848 46238 46364>,
+			<47093 14042 41634 44693 44831 43198 35723 35713>,
+			<46101  2988 44380 43499 47654 43534 47325 32959>,
+			<46577  3026 44383 43403 47882 43724 42882 32895>,
+			<35776  2975 41639 43307 41368 43771 44987 36726>,
+			<35111  3791 41637 41594 44489 43612 47500 33289>,
+			<36662  3194 44373 44431 44116 43624 43080 33297>,
+			<36282   806 44381 43232 41661 43649 43690 33325>;
+	};
+
+	qcom,bp-d-table-3 {
+		qcom,temperature = <0>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 50372 44353 21845 21845 43695 43710 21845>,
+			<43705 57283 44353 21845 21845 43706 43651 21845>,
+			<43661 54080 44352 21845 21845 43710 43767 21845>,
+			<43664 54960 44390 21845 21845 43705 43833 21845>,
+			<43748 55060 44326 20286 21845 43706 43351 21845>,
+			<43723 54697 44523  8575 21845 43687 44153 21845>,
+			<43554 11163 44149 45557 41969 43683 40987 59942>,
+			<43644 12268 44132 48903 44256 43683 41247 40065>,
+			<43922  8812 44055 47152 44840 43683 42691 39684>,
+			<43883  9907 44055 42216 44970 43680 42793 33116>,
+			<43255  9257 44086 41051 44639 43686 42381 36297>,
+			<43128  9715 44088 41774 44651 43687 42165 36436>,
+			<44783 14980 44069 41632 44713 43685 41084 34994>,
+			<44226 15283 44072 44620 43468 43699 41436 45364>,
+			<41107 14462 44078 43247 43096 43761 41254 48684>,
+			<42372 14663 44241 44008 43855 43946 41385 47752>,
+			<47409 16281 44235 43946 43899 43992 41413 41992>,
+			<48281 15459 44275 43985 43177 43085 48564 42109>,
+			<45800 13044 44278 43898 43217 43307 45390 42432>,
+			<45943 13097 44233 43841 43056 43487 45412 42281>,
+			<45533 12396 44287 43863 43054 43412 47092 42489>,
+			<46597 13455 44268 43144 41636 43507 46025 48762>,
+			<47093 13798 44267 43246 41974 43510 48267 48266>,
+			<46101 13662 44267 43124 44571 43041 42674 47342>,
+			<46577  2789 44264 43076 43384 43200 41381 48070>,
+			<35776  2249 44256 43229 43274 43134 47578 48041>,
+			<35111  3588 44256 43228 43437 43013 47562 47678>,
+			<36662  3472 44265 43198 43011 43114 47227 47750>,
+			<36282   980 44181 43897 43040 43100 47147 42319>;
+	};
+
+	qcom,bp-d-table-4 {
+		qcom,temperature = <10>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 51163 44874 51317 21845 43695 43708 21845>,
+			<43705 55613 44874 64906 21845 43698 43636 21845>,
+			<43661 53829 44874 57837 21845 43679 43162 21845>,
+			<43664 54785 44874 60052 56852 43762 43376 29256>,
+			<43748 54323 44912 40533 38120 43555 44277 11699>,
+			<43723 54611 44911 35962 35922 43634 41066 62404>,
+			<43554 11097 44833 41332 41454 43823 48856 35640>,
+			<43644 12252 45045 43397 44689 43875 48244 47349>,
+			<43922  8820 45050 43053 43496 43850 48900 42268>,
+			<43883  9961 45035 43182 43056 43167 48201 42964>,
+			<43255  9333 44954 43886 43063 43045 48146 42504>,
+			<43128  9578 44955 43805 43041 43011 48180 42750>,
+			<44783 14999 44936 44013 43879 43149 47866 41069>,
+			<44226 15256 44939 43960 43990 43433 48721 41832>,
+			<41107 14462 44986 43549 43913 43510 47298 41530>,
+			<42372 16045 44973 43540 43590 44761 45578 41651>,
+			<47409 16231 44639 43630 43606 44546 48572 44353>,
+			<48281 15843 44638 43643 43966 44595 45772 44379>,
+			<45800 12823 44608 43607 44029 44757 46718 41724>,
+			<45943 13124 44608 43958 43795 44746 46866 41596>,
+			<45533 12766 44623 43926 43210 44698 46792 41787>,
+			<46597 13469 44656 43800 43394 43368 47963 41080>,
+			<47093 13805 44669 43879 43500 43321 42473 41376>,
+			<46101  2737 44662 43970 43868 43458 47973 41931>,
+			<46577  2594 44663 44024 43779 43471 47119 41903>,
+			<35776  2079 44656 44013 43987 43460 47382 41598>,
+			<35111  3666 44618 43936 44031 43298 47241 41518>,
+			<36662  3521 44662 43605 44015 43385 48696 41682>,
+			<36282   990 44665 43913 44000 44710 45581 41527>;
+	};
+
+	qcom,bp-d-table-5 {
+		qcom,temperature = <25>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 51166 44775 47124 21845 43693 43709 21845>,
+			<43705 55768 44775 42052 21845 43629 44600 21845>,
+			<43661 53783 44775 41259 21845 43987 41550 21845>,
+			<43664 54792 44775 41501 61566 43196 42926 50758>,
+			<43748 54296 44769 44058 42233 43056 48033 45433>,
+			<43723 10915 44689 44659 41117 43444 48945 48852>,
+			<43554 11086 44717 43849 45025 44716 46210 41271>,
+			<43644 12168 43343 43548 43241 44764 35739 44523>,
+			<43922  8917 43382 43569 44012 44547 35662 44210>,
+			<43883  8515 43365 43554 43593 44988 35035 44838>,
+			<43255  9265 43372 43741 43644 45034 46786 45047>,
+			<43128  9482 43374 43566 43602 45013 46325 44832>,
+			<44783 15036 43371 43767 43558 45011 48146 44634>,
+			<44226 14943 43287 43774 43732 44830 48165 44644>,
+			<41107 14349 43282 43772 43738 44804 45963 44562>,
+			<42372 16104 43271 43737 43582 44926 36856 44609>,
+			<47409 16215 43316 43774 43564 44894 48867 44547>,
+			<48281 15831 43325 43762 43580 44861 48983 44569>,
+			<45800 13273 43320 43572 43912 45050 47025 44833>,
+			<45943 12380 43322 43549 43835 44981 45972 44217>,
+			<45533 12637 43303 43534 43950 44554 48740 45022>,
+			<46597 13549 43308 43538 43604 44773 48921 45008>,
+			<47093 13800 43311 43542 43602 44779 49021 45008>,
+			<46101  2743 43311 43552 43628 44746 47348 44985>,
+			<46577  2599 43311 43733 43551 44739 47972 44638>,
+			<35776  2152 43310 43730 43575 44582 48877 44666>,
+			<35111  4027 43310 43772 43529 44971 42101 44568>,
+			<36662  3542 43308 43769 43568 45054 42333 44546>,
+			<36282   970 43309 43761 43553 45012 47510 44568>;
+	};
+
+	qcom,bp-d-table-6 {
+		qcom,temperature = <40>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 51194 43317 43723 21845 43904 43699 21845>,
+			<43705 55597 43317 43433 21845 43858 44606 21845>,
+			<43661 53857 43317 44608 21845 43009 41891 21845>,
+			<43664 54971 43317 44840 43003 43402 42967 48409>,
+			<43748 55122 43325 44623 41934 43470 47118 48114>,
+			<43723 54745 43308 43277 44139 43275 45814 42567>,
+			<43554 11017 43466 43944 43384 44707 35608 41661>,
+			<43644 12196 43515 43725 43983 44640 35080 45034>,
+			<43922  8933 43495 43764 43549 45017 35968 44591>,
+			<43883  8451 43501 43750 43562 44206 35810 44702>,
+			<43255  9457 43502 43745 43576 44228 46407 44779>,
+			<43128  9716 43497 43768 43647 44266 46648 44576>,
+			<44783  9572 43496 43753 43773 44229 36065 43345>,
+			<44226 14901 43498 43752 43775 44067 33852 43359>,
+			<41107 14564 43415 43754 43746 44071 39629 43337>,
+			<42372 16023 43423 43754 43735 44087 35414 44730>,
+			<47409 15530 43393 43752 43762 44272 35657 43337>,
+			<48281 15656 43404 43747 43764 44882 35074 43334>,
+			<45800 13269 43400 43721 43618 44855 46400 44762>,
+			<45943 12730 43402 43717 43614 44840 45218 44545>,
+			<45533 14004 43445 43764 43573 44629 45722 44777>,
+			<46597 13474 43446 43725 43533 44665 45641 44793>,
+			<47093 13389 43441 43715 43522 44645 45991 44796>,
+			<46101 13640 43443 43768 43735 44980 48200 44709>,
+			<46577  2762 43442 43750 43738 44948 48336 43345>,
+			<35776  2098 43452 43750 43722 44838 45237 43340>,
+			<35111  3676 43454 43746 43760 44803 45373 43379>,
+			<36662  3569 43454 43747 43774 44828 46449 43384>,
+			<36282   900 43454 43744 43768 44830 35264 43385>;
+	};
+
+	qcom,bp-d-table-7 {
+		qcom,temperature = <50>;
+		qcom,nrows = <29>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 51120 43482 43723 21845 43917 43696 21845>,
+			<43705 55378 43482 43228 21845 43244 44765 21845>,
+			<43661 56668 43482 43346 24109 43423 41585 21159>,
+			<43664 53659 43482 44743 41335 43294 42982 48852>,
+			<43748 55195 43456 43333 41722 43382 47309 42416>,
+			<43723 54370 43511 43098 44877 43356 45742 41469>,
+			<43554 11136 43496 43641 43414 44726 35620 44432>,
+			<43644 11793 43410 43766 43926 44646 36626 44613>,
+			<43922 11605 43423 43775 43532 44855 33761 44773>,
+			<43883  8703 43419 43758 43743 44170 35271 44717>,
+			<43255  9378 43396 43668 43561 44090 46107 44705>,
+			<43128  9610 43399 43747 43635 44034 46844 44742>,
+			<44783  9529 43399 43666 43775 44116 36331 43385>,
+			<44226 15093 43393 43676 43762 44430 39369 43384>,
+			<41107 14501 43395 43674 43745 44433 39567 43287>,
+			<42372 16024 43403 43672 43743 44489 46412 43337>,
+			<47409 16209 43442 43676 43770 44142 36065 43282>,
+			<48281 15829 43448 43667 43774 44283 36585 43286>,
+			<45800 13278 43431 43744 43535 44800 46795 44727>,
+			<45943 12724 43425 43774 43631 44998 45964 44768>,
+			<45533 14071 43424 43748 43565 44993 45928 44718>,
+			<46597 14205 43426 43768 43552 44982 45526 44707>,
+			<47093 13363 43436 43768 43552 44961 45429 44707>,
+			<46101 13675 43438 43752 43724 45001 45164 43384>,
+			<46577  2810 43438 43754 43767 45009 45137 43374>,
+			<35776  2093 43432 43755 43771 44814 35455 43292>,
+			<35111  3651 43435 43752 43745 44851 36039 43269>,
+			<36662  3552 43093 43667 43751 44276 35743 43279>,
+			<36282   954 43092 43674 43771 44148 48769 43318>;
+	};
+};
diff --git a/qcom/qbg-battery-profile-qrd-zwd-520mAh.dtsi b/qcom/qbg-battery-profile-qrd-zwd-520mAh.dtsi
new file mode 100755
index 00000000..3661ca66
--- /dev/null
+++ b/qcom/qbg-battery-profile-qrd-zwd-520mAh.dtsi
@@ -0,0 +1,637 @@
+qcom,qbg-battery-profile-qrd-zwd-520mAh {
+	qcom,battery-type = "QRD_ZWD_520MAH";
+	qcom,batt-id-kohm = <33>;
+	qcom,capacity = <503>;
+	qcom,battery-beta = <4250>;
+	qcom,battery-therm-kohm = <100>;
+	qcom,max-voltage-uv = <4350000>;
+	qcom,fastchg-current-ma = <1040>;
+	qcom,checksum = <4295719>; /*@5, 0.005V, 4% */
+	qcom,soh-range = <0 100>;
+	/* Nominal_Impedance in 10nohm @ SOC 50% 25C* 0:fresh cell, 1: aged cell */
+	qcom,battery-impedance = <63931000 127862000>;
+	/* Nominal_Capacity in mAh. 0: fresh cell, 1:aged cell */
+	qcom,battery-capacity = <477 377>;
+	/* SOC delta (in percent) dropped from EOC SOC to enable recharge */
+	qcom,recharge-soc-delta =<5>;
+	/* vfloat delta (in mV) dropped from regular vfloat in recharge */
+	qcom,recharge-vflt-delta =<50>;
+	/* Termination current (in mA) in recharge */
+	qcom,recharge-iterm-ma = <10>;
+
+	qcom,jeita-fcc-ranges = <0 150 156000
+				151 435 1040000
+				436 445 800000
+				446 450 650000>;
+
+	qcom,jeita-fv-ranges = <0 150 4300000
+				151 435 4350000
+				436 445 4350000
+				446 450 4350000>;
+
+	/* COOL = 15 DegC, WARM = 45 DegC */
+	qcom,jeita-soft-thresholds = <0x27c1 0x128c>;
+	/* COLD = 0 DegC, HOT = 45.1 DegC */
+	qcom,jeita-hard-thresholds = <0x3257 0x127e>;
+	/* COOL = 18 DegC, WARM = 44 DegC*/
+	qcom,jeita-soft-hys-thresholds = <0x256e 0x131c>;
+	qcom,step-jeita-hysteresis = <5 5>;
+	qcom,jeita-soft-fcc-ua = <156000 520000>;
+	qcom,jeita-soft-fv-uv = <4300000 4300000>;
+
+	qcom,bp-c-table-0 {
+		qcom,temperature = <25>;
+		qcom,soc = <    0    39    78    97   136>,
+			<  195   292   410   585   722>,
+			<  917  1347  1777  2207  2636>,
+			< 3066  3496  3925  4355  4785>,
+			< 5214  5644  6074  6503  6933>,
+			< 7363  7714  7968  8398  8828>,
+			< 9257  9687 10000>;
+		qcom,ocv = <30000 31558 32793 33239 33837>,
+			<34450 35224 35898 36621 36960>,
+			<37035 37138 37388 37663 37892>,
+			<38079 38213 38351 38505 38683>,
+			<38898 39150 39436 39808 40303>,
+			<40790 41083 41316 41735 42171>,
+			<42614 43061 43361>;
+	};
+
+	qcom,bp-c-table-1 {
+		qcom,temperature = <(-20)>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 46249 43823 42806 43710 43528 63481>,
+			<43661 53696 46923 43968 42940 43711 43581 61818>,
+			<43748 10968 46957 44004 42559 43708 43578 61693>,
+			<43723 10488 46871 44011 42748 43709 43559 62219>,
+			<43554 11874 46853 43917 41291 43698 43554 62183>,
+			<43625 11653 46863 43944 41443 43697 43567 64560>,
+			<43918  8326 46959 43625 41011 43659 43555 65029>,
+			<43824  9826 46947 43521 41801 43663 43571 63926>,
+			<43235  9533 46877 43554 41474 43654 43523 64121>,
+			<43128 14970 46226 43714 41666 43679 43530 58694>,
+			<43327 15254 46921 43738 41551 43673 43535 64158>,
+			<45033 15227 46855 43560 41806 43652 43548 64432>,
+			<44123 14462 46153 43581 40975 43649 43625 64304>,
+			<41525 14716 46966 43582 41354 43649 43539 64323>,
+			<41190 15933 46306 43631 42710 43662 43617 64313>,
+			<41296 16266 46933 43136 42601 43656 43916 64487>,
+			<42754 16162 46939 44544 42664 43654 43869 64483>,
+			<42495 16192 46875 44079 41436 43664 43097 64508>,
+			<48041 15555 46710 44477 41240 43669 43267 64440>,
+			<47131 15449 46679 44333 42738 43759 44588 64440>,
+			<48884 15669 46610 44354 42532 43768 45005 64069>,
+			<48294 13014 46812 41619 42535 43764 44263 64146>,
+			<48400 13256 46819 41505 42501 43714 44490 58677>,
+			<46029 12514 46783 41890 42767 43719 44399 64505>,
+			<45503 12744 46805 41837 42275 43716 44515 64740>,
+			<46697 14216 46900 41082 47831 43717 44236 62641>,
+			<46216 13396 46370 41282 47713 43738 44835 52442>,
+			<46474 13648 46400 42707 47876 43739 44653 49493>,
+			<35428  3037 35486 42605 47434 43736 43307 57045>,
+			<35030  2476 35739 42498 48155 43716 43009 55120>,
+			<36483  3592 35625 42702 45888 43770 43194  8928>,
+			<36733  3273 35768 44271 46636 43710 43939  9217>,
+			<36282  3381 35760 43042 45296 43680 43580 14429>;
+	};
+
+	qcom,bp-c-table-2 {
+		qcom,temperature = <(-10)>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 46249 43823 42806 43710 43528 63481>,
+			<43661 53696 46923 43968 42940 43711 43581 61818>,
+			<43748 10968 46957 44004 42559 43708 43578 61693>,
+			<43723 10488 46871 44011 42748 43709 43559 62219>,
+			<43554 11874 46853 43917 41291 43698 43554 62183>,
+			<43625 11653 46863 43944 41443 43697 43567 64560>,
+			<43918  8326 46959 43625 41011 43659 43555 65029>,
+			<43824  9826 46947 43521 41801 43663 43571 63926>,
+			<43235  9533 46877 43554 41474 43654 43523 64121>,
+			<43128 14970 46226 43714 41666 43679 43530 58694>,
+			<43327 15254 46921 43738 41551 43673 43535 64158>,
+			<45033 15227 46855 43560 41806 43652 43548 64432>,
+			<44123 14462 46153 43581 40975 43649 43625 64304>,
+			<41525 14716 46966 43582 41354 43649 43539 64323>,
+			<41190 15933 46306 43631 42710 43662 43617 64313>,
+			<41296 16266 46933 43136 42601 43656 43916 64487>,
+			<42754 16162 46939 44544 42664 43654 43869 64483>,
+			<42495 16192 46875 44079 41436 43664 43097 64508>,
+			<48041 15555 46710 44477 41240 43669 43267 64440>,
+			<47131 15449 46679 44333 42738 43759 44588 64440>,
+			<48884 15669 46610 44354 42532 43768 45005 64069>,
+			<48294 13014 46812 41619 42535 43764 44263 64146>,
+			<48400 13256 46819 41505 42501 43714 44490 58677>,
+			<46029 12514 46783 41890 42767 43719 44399 64505>,
+			<45503 12744 46805 41837 42275 43716 44515 64740>,
+			<46697 14216 46900 41082 47831 43717 44236 62641>,
+			<46216 13396 46370 41282 47713 43738 44835 52442>,
+			<46474 13648 46400 42707 47876 43739 44653 49493>,
+			<35428  3037 35486 42605 47434 43736 43307 57045>,
+			<35030  2476 35739 42498 48155 43716 43009 55120>,
+			<36483  3592 35625 42702 45888 43770 43194  8928>,
+			<36733  3273 35768 44271 46636 43710 43939  9217>,
+			<36282  3381 35760 43042 45296 43680 43580 14429>;
+	};
+
+	qcom,bp-c-table-3 {
+		qcom,temperature = <0>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 46249 43823 42806 43710 43528 63481>,
+			<43661 53696 46923 43968 42940 43711 43581 61818>,
+			<43748 10968 46957 44004 42559 43708 43578 61693>,
+			<43723 10488 46871 44011 42748 43709 43559 62219>,
+			<43554 11874 46853 43917 41291 43698 43554 62183>,
+			<43625 11653 46863 43944 41443 43697 43567 64560>,
+			<43918  8326 46959 43625 41011 43659 43555 65029>,
+			<43824  9826 46947 43521 41801 43663 43571 63926>,
+			<43235  9533 46877 43554 41474 43654 43523 64121>,
+			<43128 14970 46226 43714 41666 43679 43530 58694>,
+			<43327 15254 46921 43738 41551 43673 43535 64158>,
+			<45033 15227 46855 43560 41806 43652 43548 64432>,
+			<44123 14462 46153 43581 40975 43649 43625 64304>,
+			<41525 14716 46966 43582 41354 43649 43539 64323>,
+			<41190 15933 46306 43631 42710 43662 43617 64313>,
+			<41296 16266 46933 43136 42601 43656 43916 64487>,
+			<42754 16162 46939 44544 42664 43654 43869 64483>,
+			<42495 16192 46875 44079 41436 43664 43097 64508>,
+			<48041 15555 46710 44477 41240 43669 43267 64440>,
+			<47131 15449 46679 44333 42738 43759 44588 64440>,
+			<48884 15669 46610 44354 42532 43768 45005 64069>,
+			<48294 13014 46812 41619 42535 43764 44263 64146>,
+			<48400 13256 46819 41505 42501 43714 44490 58677>,
+			<46029 12514 46783 41890 42767 43719 44399 64505>,
+			<45503 12744 46805 41837 42275 43716 44515 64740>,
+			<46697 14216 46900 41082 47831 43717 44236 62641>,
+			<46216 13396 46370 41282 47713 43738 44835 52442>,
+			<46474 13648 46400 42707 47876 43739 44653 49493>,
+			<35428  3037 35486 42605 47434 43736 43307 57045>,
+			<35030  2476 35739 42498 48155 43716 43009 55120>,
+			<36483  3592 35625 42702 45888 43770 43194  8928>,
+			<36733  3273 35768 44271 46636 43710 43939  9217>,
+			<36282  3381 35760 43042 45296 43680 43580 14429>;
+	};
+
+	qcom,bp-c-table-4 {
+		qcom,temperature = <10>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 48492 43621 41539 43657 43521 38680>,
+			<43661 53705 48409 43543 41519 43661 43523 38594>,
+			<43748 10994 48432 43522 41614 43654 43523 37248>,
+			<43723 10371 48422 43572 44383 43653 43523 36920>,
+			<43554 11813 48600 43555 44340 43679 43521 37855>,
+			<43625 11358 48638 43739 44442 43671 43525 37551>,
+			<43918  9053 48528 43762 44062 43744 43536 40160>,
+			<43824  9776 48590 43757 44286 43773 43625 40543>,
+			<43235  9692 48237 43703 44906 43520 43618 39212>,
+			<43128 14873 48213 43705 44843 43596 43541 39122>,
+			<43327 15266 48178 43707 44876 43911 43542 38973>,
+			<45033 15166 48573 43674 44039 43732 43636 39343>,
+			<44123 14390 48234 43753 44459 43720 43602 39340>,
+			<41525 14606 48515 43763 44451 43774 43936 38950>,
+			<41190 16087 48131 43771 44478 43761 43612 39798>,
+			<41296 15966 48129 44766 43333 43555 44865 39146>,
+			<42754 16372 48178 44808 43303 43582 41716 39147>,
+			<42495 16254 48344 44894 43386 43583 41778 39041>,
+			<48041 15566 48382 44265 44719 43583 41024 39092>,
+			<47131 15794 48318 44066 44684 43580 42738 39083>,
+			<48884 12972 48292 44094 43348 43576 41408 39879>,
+			<48294 13237 48266 44091 43386 43559 41929 39494>,
+			<48400 12522 48311 44046 43378 43555 44358 39453>,
+			<46029 12786 48903 44452 44697 43552 44308 39499>,
+			<45503 13879 48958 44482 44557 43556 44354 39883>,
+			<46697 13316 49105 44033 44632 43555 44547 39743>,
+			<46216  2730 48904 44122 44809 43555 44729 39403>,
+			<46474  2683 48987 44530 44243 43552 43348 40812>,
+			<35428  2303 48309 44319 44307 43553 43282 37756>,
+			<35030  2373 48257 44365 41878 43556 43272 38299>,
+			<36483  3847 48266 44614 42982 43730 43221 61356>,
+			<36733  3536 48302 43756 47846 43753 43598 57367>,
+			<36282   513 48308 43769 42998 43667 43547 58712>;
+	};
+
+	qcom,bp-c-table-5 {
+		qcom,temperature = <25>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 42192 43128 43244 43727 44594 46360>,
+			<43661 53740 42033 43027 43242 43719 44790 46504>,
+			<43748 10931 41985 43070 43163 43740 44676 46328>,
+			<43723 11133 41988 43050 43138 43728 44727 46934>,
+			<43554 11911 41989 43250 43196 43561 44713 47092>,
+			<43625 11320 41985 43136 43182 43559 43355 46603>,
+			<43918  9010 42202 43181 43858 43583 44711 45381>,
+			<43824  9872 42114 43199 43881 43575 44634 45547>,
+			<43235  9639 42864 43196 43827 43523 44916 45105>,
+			<43128 15050 42825 43815 43886 43551 43517 45891>,
+			<43327 14849 42844 43778 43903 43551 43504 45943>,
+			<45033 15288 42816 43063 43843 43527 41833 45265>,
+			<44123 14502 42850 43111 43167 43545 41290 45112>,
+			<41525 14773 42853 43072 43137 43543 42860 45186>,
+			<41190 16046 42779 43076 43156 43537 42902 45950>,
+			<41296 15893 42815 43110 43178 43550 41191 45652>,
+			<42754 16367 42968 43125 43180 43525 41810 45630>,
+			<42495 16229 42959 43103 43144 43520 41560 45766>,
+			<48041 15555 43002 43395 43259 43527 41895 45778>,
+			<47131 15793 42935 43463 43063 43538 41747 45679>,
+			<48884 15704 42923 43307 43405 43540 41763 45959>,
+			<48294 12868 42892 43307 43384 43628 41141 45835>,
+			<48400 12454 42939 43297 44789 43622 42133 45224>,
+			<46029 12586 42567 43298 43271 43642 42378 46003>,
+			<45503 14277 42584 43496 43204 43629 41437 48443>,
+			<46697 13820 42930 43089 43138 43547 44463 48615>,
+			<46216  2769 42890 43425 43222 43524 44241 48463>,
+			<46474  3022 42926 43392 43044 43547 44041 45697>,
+			<35428  2477 42573 43487 43008 43538 44505 45590>,
+			<35030  3601 42568 43271 43443 43551 44455 45926>,
+			<36483  3292 42565 43362 44582 43627 44872 46658>,
+			<36733   671 42898 43497 44078 43540 44672 35344>,
+			<36282   971 42578 43043 44115 43553 43059 35054>;
+	};
+
+	qcom,bp-c-table-6 {
+		qcom,temperature = <40>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 41793 43858 43922 43542 41226 47804>,
+			<43661 53646 41849 43895 43930 43631 41458 42348>,
+			<43748 54642 41747 43796 43906 43620 40993 42461>,
+			<43723 11042 41734 43781 43919 43641 41120 42491>,
+			<43554 10616 41791 43832 43956 43633 41890 42400>,
+			<43625 11416 41940 43993 43964 43599 41663 42014>,
+			<43918  9116 41951 44017 43943 43611 44291 42227>,
+			<43824  8574 41958 44022 43950 43615 41695 42114>,
+			<43235  9230 41880 44012 43939 43605 44373 42827>,
+			<43128  9555 41884 44008 43598 43947 41001 42763>,
+			<43327 15085 41880 44001 43634 43608 41407 42966>,
+			<45033 14863 41869 43822 43832 43615 41081 42215>,
+			<44123 15106 41899 43815 43801 43614 41253 42212>,
+			<41525 14441 41554 43786 43803 43609 42813 42115>,
+			<41190 14605 41567 43777 43885 43589 42861 42162>,
+			<41296 16114 41590 43795 43899 43590 42201 42152>,
+			<42754 16299 41494 43800 43823 43587 42961 42975>,
+			<42495 16179 41527 43799 43822 43596 42643 43003>,
+			<48041 15598 41517 43884 43824 43595 41122 43000>,
+			<47131 15776 41683 43854 43887 43633 41771 42960>,
+			<48884 15706 41669 43177 43169 43634 41964 42879>,
+			<48294 13225 41675 43179 43218 43647 44345 42118>,
+			<48400 12521 41721 43171 43082 43647 44405 42023>,
+			<46029 12654 41717 43176 43129 43636 42633 42183>,
+			<45503 14091 41718 43879 43781 43599 41290 42936>,
+			<46697 13810 41717 43792 44028 43596 41818 42502>,
+			<46216  2570 41674 43793 43995 43596 41893 42610>,
+			<46474  2866 41675 43883 43811 43587 41495 42924>,
+			<35428  2531 41664 43898 43794 43597 41723 42952>,
+			<35030  4014 41680 43842 43866 43593 41672 42872>,
+			<36483  3181 41512 43179 43251 43595 44369 42022>,
+			<36733   553 41478 43856 43305 43586 44882 47752>,
+			<36282   769 41691 43829 43494 43964 43315 42352>;
+	};
+
+	qcom,bp-c-table-7 {
+		qcom,temperature = <50>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57242 44354 44009 43908 43585 44092 41271>,
+			<43661 53331 44404 44014 43956 43611 44352 41434>,
+			<43748 54567 44411 44014 43936 43613 41958 41455>,
+			<43723 11167 44384 44009 43947 43600 41821 41370>,
+			<43554 10705 44311 44011 43588 43946 41357 41376>,
+			<43625 12145 44293 43926 43633 43949 42720 41075>,
+			<43918  8778 44303 43909 43623 43963 42544 41012>,
+			<43824  8491 44325 43906 43630 43966 42591 41177>,
+			<43235  9466 44504 43966 43616 43915 41225 41187>,
+			<43128  9497 44484 43610 43617 43930 41179 41144>,
+			<43327 15011 44535 43606 43550 43912 41989 41808>,
+			<45033 15053 44537 43955 43970 43913 41787 40978>,
+			<44123 15300 44513 43952 43974 43913 41169 40975>,
+			<41525 14372 44443 43913 43971 43913 42660 41017>,
+			<41190 14810 44467 43930 43811 43958 42710 41012>,
+			<41296 16010 44454 43921 43801 43964 42581 40978>,
+			<42754 15991 44120 43926 44000 43961 42210 41095>,
+			<42495 16340 44149 44013 44011 43939 42949 41149>,
+			<48041 15515 44140 44025 44027 43950 41275 41099>,
+			<47131 15787 44057 43983 43999 43605 41137 41196>,
+			<48884 15704 44044 43985 43780 43606 41552 40993>,
+			<48294 13216 44086 43810 43179 43600 44381 41032>,
+			<48400 12541 44095 43998 43233 43606 44468 41400>,
+			<46029 12623 44091 43983 43165 43607 41877 41033>,
+			<45503 14102 44094 43926 43932 43938 40990 41754>,
+			<46697 13762 44082 43917 43936 43942 41929 41950>,
+			<46216  2585 44081 43928 43959 43938 41957 41785>,
+			<46474  2817 44042 44001 43904 43948 40992 41832>,
+			<35428  2548 44033 44031 44024 43948 41100 41133>,
+			<35030  4021 44063 44031 43810 43950 41580 41191>,
+			<36483  3150 44143 43976 43892 43945 41648 41056>,
+			<36733   561 44152 43986 43218 43950 44124 41273>,
+			<36282   791 44033 43971 43227 44003 44622 41470>;
+	};
+
+	qcom,bp-d-table-0 {
+		qcom,temperature = <25>;
+		qcom,soc = <    0    39    78    97   136>,
+			<  195   292   410   585   722>,
+			<  917  1347  1777  2207  2636>,
+			< 3066  3496  3925  4355  4785>,
+			< 5214  5644  6074  6503  6933>,
+			< 7363  7714  7968  8398  8828>,
+			< 9257  9687 10000>;
+		qcom,ocv = <30573 31378 32148 32511 33171>,
+			<33946 34784 35511 36281 36628>,
+			<36800 36904 37089 37320 37504>,
+			<37676 37863 38059 38243 38435>,
+			<38653 38912 39204 39552 40019>,
+			<40572 40908 41136 41558 42004>,
+			<42457 42948 43345>;
+	};
+
+	qcom,bp-d-table-1 {
+		qcom,temperature = <(-20)>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 54254 59705 21845 21845 43691 43699 21845>,
+			<43661 53723 59506 21845 21845 43691 43705 21845>,
+			<43748 55249 60243 21845 21845 43691 43697 21845>,
+			<43723 54488 60202 21845 21845 43691 43662 21845>,
+			<43554 10900 59939 21845 21845 43690 43670 21845>,
+			<43625 10291 38323 21845 21845 43690 43738 21845>,
+			<43918 12097 38553 21845 10225 43690 43604 21845>,
+			<43824  8758 37091 21845 58409 43690 43998 21845>,
+			<43235  8578 37390 21845 36992 43690 43864 21845>,
+			<43128  9920 40220 21845 40738 43691 43191 21845>,
+			<43327 10090 40216 21845 40568 43691 43229 21845>,
+			<45033  9514 40151 24910 33285 43691 43017 21845>,
+			<44123 14884 40581  3528 35824 43691 43200 21845>,
+			<41525 15304 40648 12876 47073 43691 43232 21845>,
+			<41190 14500 39183 14356 45543 43691 43146 21845>,
+			<41296 14345 40480  9894 45193 43691 43862 21845>,
+			<42754 14750 40936 11355 46008 43691 43871 21845>,
+			<42495 14702 40544 10366 45750 43691 43862 21845>,
+			<48041 16122 40638 55123 48428 43691 43841 21845>,
+			<47131 15947 40911 54106 48220 43691 43889 21845>,
+			<48884 16340 40499 56417 48328 43691 43901 21845>,
+			<48294 15491 40593 55745 48308 43691 43875 21845>,
+			<48400 15450 40879 56134 48972 43691 43872 21845>,
+			<46029 15694 40788 56203 48974 43691 43899 21845>,
+			<45503 13236 40660 56235 48334 43691 43178 21845>,
+			<46697 12293 40931 55627 48468 43691 43256 21845>,
+			<46216 13989 40843 56529 45879 43691 43249 21845>,
+			<46474 14306 40874 54079 45366 43691 43230 21845>,
+			<35428  2786 40929 12141 36437 43691 44553 21845>,
+			<35030  2209 40450  9760 36155 43691 43205 21845>,
+			<36483  3734 40551 12780 36661 43691 43842 21845>,
+			<36733  3481 40093  7190 46961 43691 43842 21845>,
+			<36282   886 40262 24682 48397 43691 43863 21845>;
+	};
+
+	qcom,bp-d-table-2 {
+		qcom,temperature = <(-10)>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 56785 40870 21845 21845 43689 43690 21845>,
+			<43661 53639 39288 21845 21845 43688 43686 21845>,
+			<43748 54465 39134 21845 21845 43691 43727 21845>,
+			<43723 54631 39702 21845 21845 43691 43574 21845>,
+			<43554 10411 39582 21845  4257 43690 43914 21845>,
+			<43625 11819 34602 26974 37269 43691 43260 21845>,
+			<43918 11530 33620  8320 45420 43691 43280 21845>,
+			<43824  8344 33308 54068 49087 43691 43355 21845>,
+			<43235  9830 33695 55743 48755 43691 44747 21845>,
+			<43128  9379 33734 56293 48564 43691 44772 21845>,
+			<43327  9601 33715 56096 45294 43691 44729 21845>,
+			<45033 15095 33664 52620 48552 43691 43130 21845>,
+			<44123 15247 33717 62952 47594 43691 43213 21845>,
+			<41525 15201 33336 62243 47621 43691 43240 21845>,
+			<41190 14543 33335 63815 42243 43691 43144 21845>,
+			<41296 14419 33311 58803 42064 43691 43185 21845>,
+			<42754 14624 33362 57662 42043 43691 43147 21845>,
+			<42495 16063 33675 60766 42235 43691 43196 21505>,
+			<48041 15880 33737 61161 42833 43688 43188 20700>,
+			<47131 16280 33401 60355 42849 43688 43175 23937>,
+			<48884 16255 33570 38384 42753 43688 43192 24481>,
+			<48294 15419 33384 38819 42855 43688 43169 22640>,
+			<48400 15659 33339 38632 42216 43688 43164 22529>,
+			<46029 12829 33334 38633 42487 43688 43059 24261>,
+			<45503 12420 33690 38502 47968 43691 43015 23934>,
+			<46697 12667 33618 38362 47447 43691 43046 22349>,
+			<46216 13552 33788 60619 46526 43691 44565 21845>,
+			<46474 13641 33355 57366 36553 43691 44914 21845>,
+			<35428  2987 32907 58944 34908 43691 43213 21845>,
+			<35030  2069 33751 64791 35577 43691 43239 21845>,
+			<36483  3701 33677 52525 46855 43691 43136 21845>,
+			<36733  3549 33573 53471 45549 43691 43876 21845>,
+			<36282   878 33000  9066 45827 43691 43835 21845>;
+	};
+
+	qcom,bp-d-table-3 {
+		qcom,temperature = <0>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 53448 36742 21845 21845 43690 43690 21845>,
+			<43661 54856 36530 21845 18713 43690 43690 21845>,
+			<43748 54767 34937 23067  3610 43691 43554 21845>,
+			<43723 10959 34951 25029 10706 43691 43985 21845>,
+			<43554 10449 35409  8904 60678 43691 43411 21845>,
+			<43625 12199 46459 62192 46757 43691 44555 21845>,
+			<43918  8894 46468 64077 48883 43691 44620 21078>,
+			<43824  8223 46377 57543 47704 43691 44640 17971>,
+			<43235 10190 46102 59746 42343 43691 44974 19234>,
+			<43128  9229 46556 61372 47241 43691 44572 20215>,
+			<43327  9483 46343 60865 47384 43691 43339 19467>,
+			<45033 15059 46362 38238 42785 43691 43042 32143>,
+			<44123 15241 46544 37732 41001 43691 43261 26154>,
+			<41525 15206 46554 40612 41849 43688 43153 28185>,
+			<41190 14383 46108 33863 41821 43688 43218  5277>,
+			<41296 14727 46482 32977 41091 43688 43222  5027>,
+			<42754 14698 46588 35951 41140 43688 43223  7898>,
+			<42495 16108 46536 35289 41796 43688 43222  6792>,
+			<48041 15977 46520 35522 41801 43688 43153  1776>,
+			<47131 16356 46513 46216 41762 43688 43258   607>,
+			<48884 16196 46519 46735 41763 43688 43237  3111>,
+			<48294 15382 46515 45445 41849 43688 43045  3941>,
+			<48400 15712 46495 45262 41449 43688 43111  3214>,
+			<46029 13234 46487 45243 42826 43688 43128   716>,
+			<45503 12291 46511 46761 47791 43688 43106  1589>,
+			<46697 14209 46504 35167 45822 43688 44270  4509>,
+			<46216 13729 46190 36856 35348 43688 44977 27890>,
+			<46474  2738 46092 36017 35282 43688 43314 24610>,
+			<35428  3050 46498 32977 46316 43688 43191 26253>,
+			<35030  2490 46149 39096 46970 43688 43138 32343>,
+			<36483  3978 46198 38556 45388 43688 43187 29988>,
+			<36733  3375 46157 57970 48224 43691 43888 17212>,
+			<36282   822 46464 63920 48776 43691 43786 23160>;
+	};
+
+	qcom,bp-d-table-4 {
+		qcom,temperature = <10>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 54128 46077  2519 53838 43688 43690 21845>,
+			<43661 54827 45661  8656 51542 43688 43659 21845>,
+			<43748 54691 45761 51143 57682 43688 43790 21845>,
+			<43723 10896 45706 62699 60085 43688 43200 21845>,
+			<43554 10432 48439 59762 33229 43688 43386 17457>,
+			<43625 12193 48610 39799 45453 43691 44630 27786>,
+			<43918 11607 48220 33115 47354 43688 45029  7998>,
+			<43824  8219 48338 36051 42020 43688 45017   820>,
+			<43235 10028 48140 35776 42995 43688 44832  2762>,
+			<43128  9339 48346 35267 42247 43688 44637  4029>,
+			<43327  9521 48367 36552 42842 43688 43477  3804>,
+			<45033 15077 48967 46812 44318 43688 43063 14644>,
+			<44123 15273 48338 49001 44468 43688 43034  9139>,
+			<41525 15178 48273 47709 44290 43689 43120 11219>,
+			<41190 14388 48373 42987 44406 43689 43128 53367>,
+			<41296 14742 48383 40999 44363 43694 43026 57248>,
+			<42754 14697 48348 41702 44388 43694 43055 50523>,
+			<42495 16110 48142 44095 44399 43695 43205 49438>,
+			<48041 15980 48255 44550 41606 43693 43144 52530>,
+			<47131 16368 48355 43408 41587 43683 43872 52912>,
+			<48884 15542 48187 43352 41510 43682 43045 51259>,
+			<48294 15780 48325 44789 41939 43682 43076 51254>,
+			<48400 12954 48352 44948 41229 43682 43425 51479>,
+			<46029 13266 48322 44308 42578 43682 43492 52384>,
+			<45503 12374 48284 41831 42146 43687 43402 49761>,
+			<46697 13498 48178 42588 46614 43733 44203 54838>,
+			<46216 13800 48329 42966 46744 43775 43387 54941>,
+			<46474  2729 48285 42844 45212 43670 43205 53550>,
+			<35428  2916 48256 48838 47420 43727 44660 54569>,
+			<35030  2517 48289 47421 48782 43749 43323 10389>,
+			<36483  4085 48284 48957 47386 43663 43219 12185>,
+			<36733  3391 48244 47001 48104 43690 43140  8708>,
+			<36282   990 48639 35657 42431 43690 43025  8667>;
+	};
+
+	qcom,bp-d-table-5 {
+		qcom,temperature = <25>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 56775 47640 35996 39236 43753 43690 15573>,
+			<43661 53304 47855 46557 32848 43765 43956 10253>,
+			<43748 55102 42338 48239 35801 43717 43017 50882>,
+			<43723 54357 42273 47345 46711 43742 43471 52003>,
+			<43554 11065 42380 40989 48763 43730 44648 58416>,
+			<43625 11824 42054 44925 42771 43737 44207 38198>,
+			<43918 11594 42428 44545 41542 43773 44063 40239>,
+			<43824  8221 42202 44731 44083 43721 44439 39102>,
+			<43235 10003 42183 43277 44233 43743 44478 33808>,
+			<43128  9662 42129 43374 41662 43730 44883 39673>,
+			<43327  9578 42226 43484 44208 43740 45006 34565>,
+			<45033 14978 42226 43019 43088 43735 45012 36333>,
+			<44123 14923 42170 43049 43121 43558 44921 36769>,
+			<41525 15202 42123 43224 43130 43570 44816 35310>,
+			<41190 14378 42841 43218 43011 43530 44193 35657>,
+			<41296 14726 42146 43054 43118 43529 44287 35416>,
+			<42754 14669 42166 43020 43468 43533 44124 35454>,
+			<42495 15873 42841 43124 43356 43527 44401 35396>,
+			<48041 16329 42829 43083 43335 43551 44464 35490>,
+			<47131 15497 42853 43118 43270 43525 44880 46492>,
+			<48884 15447 42848 43024 43485 43522 45041 46126>,
+			<48294 12970 42862 43101 43301 43527 44284 46095>,
+			<48400 13198 42857 43405 43329 43524 44089 46571>,
+			<46029 12330 42856 43512 44619 43527 44882 35379>,
+			<45503 14073 42782 44689 44327 43542 44079 36491>,
+			<46697 13526 42846 44961 41473 43545 44550 35942>,
+			<46216 13670 42845 44615 44499 43522 44966 36674>,
+			<46474  2586 42841 44651 44273 43531 45043 36792>,
+			<35428  2300 42861 44791 44854 43572 45026 36397>,
+			<35030  3774 42160 44688 45053 43530 44922 36380>,
+			<36483  3955 42148 43389 44615 43574 45012 36574>,
+			<36733  3438 42949 43093 44689 43553 43286 35272>,
+			<36282  1019 42507 43231 43269 43733 43145 34830>;
+	};
+
+	qcom,bp-d-table-6 {
+		qcom,temperature = <40>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57067 47769 21845 21845 43570 43690 21845>,
+			<43661 53839 42899 21845 21845 43644 43838 21845>,
+			<43748 54856 41403 57454 21845 43606 43454 21845>,
+			<43723 54317 40998 41129 33239 43946 43373 61234>,
+			<43554 11148 41209 43367 48002 43589 44984 35138>,
+			<43625 11967 41096 43226 42945 43616 44095 46219>,
+			<43918 11669 41823 43180 41874 43630 44389 45999>,
+			<43824  9048 41749 43892 44933 43623 41690 48833>,
+			<43235 10144 41778 43804 43114 43639 41908 48100>,
+			<43128  9239 41728 43795 43479 43585 44107 47948>,
+			<43327  9505 41786 43786 43075 43610 44180 48058>,
+			<45033  9588 41940 44027 43821 43584 44327 42070>,
+			<44123 14885 41933 44026 43834 43602 41639 42001>,
+			<41525 15317 41875 44030 43834 43605 41520 42196>,
+			<41190 14575 41879 44019 43836 43614 41513 42216>,
+			<41296 14783 41864 43968 43847 43614 41689 42201>,
+			<42754 14674 41889 43817 43105 43602 41503 42374>,
+			<42495 15995 41890 43823 43409 43612 44307 42451>,
+			<48041 16184 41556 43813 43130 43608 44329 42054>,
+			<47131 15612 41592 43988 43161 43588 44038 42160>,
+			<48884 15773 41598 43818 43849 43610 44100 42856>,
+			<48294 12956 41574 43808 43896 43591 44422 42776>,
+			<48400 13303 41572 43838 43849 43596 44124 42875>,
+			<46029 12397 41597 43781 43223 43639 44268 41991>,
+			<45503 13834 41547 43150 43379 43623 44279 47665>,
+			<46697 13355 41564 43145 43321 43541 44616 47660>,
+			<46216 13681 41554 43144 43101 43630 44815 47798>,
+			<46474  2660 41556 43191 43064 43618 44186 42256>,
+			<35428  2264 41918 43880 43248 43619 44661 42488>,
+			<35030  3712 41869 43886 43162 43620 44830 42465>,
+			<36483  3907 41881 43801 43197 43647 44866 42472>,
+			<36733  3347 41872 43818 43171 43594 44930 42372>,
+			<36282   944 41885 44031 43171 43596 43325 42378>;
+	};
+
+	qcom,bp-d-table-7 {
+		qcom,temperature = <50>;
+		qcom,nrows = <33>;
+		qcom,ncols = <8>;
+		qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>;
+		qcom,data = <43690 57019 42570 21845 21845 43613 43729 21845>,
+			<43661 54005 41159 21845 21845 43920 43900 21845>,
+			<43748 54927 41473 57872 21845 44026 43406 21845>,
+			<43723 55061 41705 41932 32907 44003 43374 38047>,
+			<43554 10947 41614 43393 42000 43959 44637 45330>,
+			<43625 10704 41632 43799 41407 43597 44241 48273>,
+			<43918 11389 44403 43980 41956 43586 44360 47477>,
+			<43824  9173 44387 44014 44603 43588 41701 42007>,
+			<43235  9780 44299 43934 43147 43949 41947 41303>,
+			<43128  9417 44322 43907 43177 43955 44502 41232>,
+			<43327  9720 44501 43956 43144 43953 44166 41238>,
+			<45033  9472 44484 43947 43928 43912 41837 40992>,
+			<44123 15101 44531 43615 44006 43905 41916 41180>,
+			<41525 15332 44437 43608 43971 43918 41522 41159>,
+			<41190 14512 44420 43600 43977 43959 41978 41189>,
+			<41296 14427 44467 43951 43812 43912 41863 41157>,
+			<42754 14659 44449 43954 43238 43919 41492 41355>,
+			<42495 15986 44118 43956 43134 43912 44352 41264>,
+			<48041 16191 44096 43963 43243 43959 44112 41026>,
+			<47131 15604 44106 43967 43880 43919 44325 41161>,
+			<48884 15850 44147 43954 43992 43959 41631 41121>,
+			<48294 13034 44156 43913 44028 43961 41858 41808>,
+			<48400 13261 44156 43907 43978 43938 41536 41120>,
+			<46029 12410 44157 43927 43903 43600 44288 40960>,
+			<45503 13834 44108 43989 43081 43590 44239 42684>,
+			<46697 13527 44103 43835 43070 43584 44220 41293>,
+			<46216 13691 44120 43968 43145 43586 44824 41459>,
+			<46474  2667 44124 44007 43901 43586 44832 41052>,
+			<35428  2241 44449 44003 43832 43591 44094 40982>,
+			<35030  3723 44465 43924 43973 43614 44524 41013>,
+			<36483  3956 44425 43931 44016 43603 44395 40995>,
+			<36733  3342 44416 43915 44027 43607 41651 41183>,
+			<36282   605 44420 43953 44028 43605 44380 41153>;
+	};
+};
diff --git a/qcom/qrb5165-iot.dts b/qcom/qrb5165-iot.dts
new file mode 100755
index 00000000..040b5018
--- /dev/null
+++ b/qcom/qrb5165-iot.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "qrb5165-iot.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. kona-iot RB5 Platform";
+	compatible = "qcom,kona-iot";
+	qcom,board-id = <0 0>;
+};
diff --git a/qcom/qrb5165-iot.dtsi b/qcom/qrb5165-iot.dtsi
new file mode 100755
index 00000000..d6cdd304
--- /dev/null
+++ b/qcom/qrb5165-iot.dtsi
@@ -0,0 +1,7 @@
+ #include "kona.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. kona-iot RB5 Platform";
+	compatible = "qcom,kona-iot";
+	qcom,msm-id = <455 0x0>;
+};
diff --git a/qcom/qrb5165n-iot.dts b/qcom/qrb5165n-iot.dts
new file mode 100755
index 00000000..0831447c
--- /dev/null
+++ b/qcom/qrb5165n-iot.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "qrb5165n-iot.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. kona-iot RB5 NON POP Platform";
+	compatible = "qcom,kona-iot";
+	qcom,board-id = <0 0>;
+};
diff --git a/qcom/qrb5165n-iot.dtsi b/qcom/qrb5165n-iot.dtsi
new file mode 100755
index 00000000..e0637eb1
--- /dev/null
+++ b/qcom/qrb5165n-iot.dtsi
@@ -0,0 +1,7 @@
+ #include "qrb5165-iot.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. kona-iot RB5 NON POP Platform";
+	compatible = "qcom,kona-iot";
+	qcom,msm-id = <496 0x0>;
+};
diff --git a/qcom/quin-vm-common.dtsi b/qcom/quin-vm-common.dtsi
index 18282678..2c736a90 100755
--- a/qcom/quin-vm-common.dtsi
+++ b/qcom/quin-vm-common.dtsi
@@ -14,7 +14,7 @@
 	};
 
 	chosen {
-		bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 cgroup.memory=nokmem,nosocket";
+		bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 cgroup.memory=nokmem,nosocket kpti=0 qcom_dma_heaps.enable_bitstream_contig_heap=y arm64.nopauth kasan=off";
 	};
 
 	soc: soc { };
@@ -55,6 +55,14 @@
 		};
 	};
 
+	vdevs {
+		compatible = "simple-bus";
+		virtio_input_keyboard@1c150000 {
+			compatible = "virtio,mmio";
+			wakeup-source;
+		};
+	};
+
 	firmware: firmware {
 		android {
 			compatible = "android,firmware";
@@ -127,10 +135,14 @@
 		interrupt-controller;
 	};
 
-	regulator: virtio_regulator@1c700000 {
+	virtio_regulator@1c700000 {
 		compatible = "virtio,mmio";
 		reg = <0x1c700000 0x1000>;
 		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+
+		regulator: virtio_regulator_device {
+			compatible = "virtio,device31";
+		};
 	};
 
 	qcom_dma_heaps: qcom,dma-heaps {
@@ -282,5 +294,18 @@
 			compatible = "virtio,device33";
 		};
 	};
-};
 
+	qcom,secure-buffer {
+		compatible = "qcom,secure-buffer";
+	};
+
+	qcom,mem-buf {
+		compatible = "qcom,mem-buf";
+		qcom,mem-buf-capabilities = "supplier";
+		qcom,vmid = <3>;
+	};
+
+	qcom,mem-buf-msgq {
+		compatible = "qcom,mem-buf-msgq";
+	};
+};
diff --git a/qcom/sa410m-pcie.dtsi b/qcom/sa410m-pcie.dtsi
index b5268ced..b76172a5 100755
--- a/qcom/sa410m-pcie.dtsi
+++ b/qcom/sa410m-pcie.dtsi
@@ -5,6 +5,9 @@
 		compatible = "qcom,pci-msm";
 		cell-index = <0>;
 
+		#address-cells = <3>;
+		#size-cells = <2>;
+
 		reg = <0x05020000 0x3000>,
 			<0x05026000 0x1000>,
 			<0x18000000 0xf20>,
@@ -15,8 +18,6 @@
 
 		reg-names = "parf", "phy", "dm_core", "elbi", "iatu",
 						"conf", "mhi";
-		#adddress-cells = <3>;
-		#size-cells = <2>;
 
 		ranges = <0x01000000 0x0 0x18200000 0x18200000 0x0 0x100000>,
 			<0x02000000 0x0 0x18300000 0x18300000 0x0 0x27d00000>;
@@ -160,7 +161,7 @@
 		qcom,phy-power-down-offset = <0x804>;
 		qcom,core-preset = <0x77777777>;
 
-		qcom,boot-option = <0x0>;
+		qcom,boot-option = <0x1>;
 
 		linux,pci-domain = <0>;
 
diff --git a/qcom/sa410m.dtsi b/qcom/sa410m.dtsi
index c8d0e1c4..3665afc9 100755
--- a/qcom/sa410m.dtsi
+++ b/qcom/sa410m.dtsi
@@ -562,6 +562,55 @@
 		#reset-cells = <1>;
 	};
 
+	qcom_cedev: qcedev@1b20000 {
+		compatible = "qcom,qcedev";
+		reg = <0x1b20000 0x20000>,
+			<0x1b04000 0x24000>;
+		reg-names = "crypto-base","crypto-bam-base";
+		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,bam-pipe-pair = <2>;
+		qcom,ce-hw-instance = <0>;
+		qcom,ce-device = <0>;
+		qcom,ce-hw-shared;
+		qcom,bam-ee = <0>;
+		qcom,smmu-s1-enable;
+		qcom,no-clock-support;
+		interconnect-names = "data_path";
+		interconnects = <&sys_noc MASTER_CRYPTO_CORE0 &bimc_noc SLAVE_EBI_CH0>;
+		iommus = <&apps_smmu 0x0084 0x0011>,
+				<&apps_smmu 0x0092 0x00>,
+				<&apps_smmu 0x0086 0x0011>;
+		qcom,iommu-dma = "atomic";
+		dma-coherent;
+
+		qcom_cedev_ns_cb {
+			compatible = "qcom,qcedev,context-bank";
+			label = "ns_context";
+			iommus = <&apps_smmu 0x0086 0x0011>,
+				<&apps_smmu 0x0092 0x00>,
+				<&apps_smmu 0x0098 0x0001>;
+			dma-coherent;
+		};
+
+		qcom_cedev_s_cb {
+			compatible = "qcom,qcedev,context-bank";
+			label = "secure_context";
+			iommus = <&apps_smmu 0x093 0x000>,
+				 <&apps_smmu 0x09c 0x001>,
+				 <&apps_smmu 0x09d 0x001>,
+				 <&apps_smmu 0x09E 0x000>;
+			qcom,iommu-vmid = <0x9>;
+			qcom,secure-context-bank;
+		};
+	};
+
+	qcom_rng: qrng@4453000 {
+		compatible = "qcom,msm-rng";
+		reg = <0x4453000 0x1000>;
+		qcom,no-qrng-config;
+		qcom,no-clock-support;
+	};
+
 	mccc_debug: syscon@447d200 {
 		compatible = "syscon";
 		reg = <0x0447d200 0x100>;
diff --git a/qcom/sa8155-pmic-overlay.dtsi b/qcom/sa8155-pmic-overlay.dtsi
index a34b4c43..5d8ab9f3 100755
--- a/qcom/sa8155-pmic-overlay.dtsi
+++ b/qcom/sa8155-pmic-overlay.dtsi
@@ -226,6 +226,94 @@ pm8150_1_adc_tm: &pm8150_adc_tm {
 			};
 		};
 
+		cooling-maps {
+			trip0_cpu0 {
+				trip = <&pm8150_2_trip0>;
+				cooling-device =
+					<&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT >;
+			};
+
+			trip0_cpu1 {
+				trip = <&pm8150_2_trip0>;
+				cooling-device = <&cpu1_pause 1 1>;
+			};
+
+			trip0_cpu2 {
+				trip = <&pm8150_2_trip0>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+
+			trip0_cpu3 {
+				trip = <&pm8150_2_trip0>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+
+			trip0_cpu4 {
+				trip = <&pm8150_2_trip0>;
+				cooling-device = <&cpu4_pause 1 1>;
+			};
+
+			trip0_cpu5 {
+				trip = <&pm8150_2_trip0>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+
+			trip0_cpu6 {
+				trip = <&pm8150_2_trip0>;
+				cooling-device = <&cpu6_pause 1 1>;
+			};
+
+			trip0_cpu7 {
+				trip = <&pm8150_2_trip0>;
+				cooling-device = <&cpu7_pause 1 1>;
+			};
+		};
+	};
+
+	pm8150_tz {
+		cooling-maps {
+			trip0_cpu0 {
+				trip = <&pm8150_trip0>;
+				cooling-device =
+					<&CPU0 THERMAL_NO_LIMIT
+						THERMAL_NO_LIMIT>;
+			};
+
+			trip0_cpu1 {
+				trip = <&pm8150_trip0>;
+				cooling-device = <&cpu1_pause 1 1>;
+			};
+
+			trip0_cpu2 {
+				trip = <&pm8150_trip0>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+
+			trip0_cpu3 {
+				trip = <&pm8150_trip0>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+
+			trip0_cpu4 {
+				trip = <&pm8150_trip0>;
+				cooling-device = <&cpu4_pause 1 1>;
+			};
+
+			trip0_cpu5 {
+				trip = <&pm8150_trip0>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+
+			trip0_cpu6 {
+				trip = <&pm8150_trip0>;
+				cooling-device = <&cpu6_pause 1 1>;
+			};
+
+			trip0_cpu7 {
+				trip = <&pm8150_trip0>;
+				cooling-device = <&cpu7_pause 1 1>;
+			};
+		};
 	};
 
 	xo-therm {
diff --git a/qcom/sa8155-vm-la.dtsi b/qcom/sa8155-vm-la.dtsi
index feb10fe9..6132aa88 100755
--- a/qcom/sa8155-vm-la.dtsi
+++ b/qcom/sa8155-vm-la.dtsi
@@ -18,25 +18,114 @@
 };
 
 &soc {
-};
 
-&usb0 {
-	status = "ok";
-};
+	hsi2s: qcom,hsi2s@172c0000 {
+		compatible = "qcom,sa8155-hsi2s", "qcom,hsi2s";
+		number-of-interfaces = <3>;
+		reg = <0x172c0000 0x28000>,
+		      <0x17080000 0xe000>;
+		reg-names = "lpa_if", "lpass_tcsr";
+		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+		number-of-rate-detectors = <2>;
+		rate-detector-interfaces = <0 1>;
+		iommus = <&apps_smmu 0x1B5C 0x1>,
+			 <&apps_smmu 0x1B5E 0x0>;
+		qcom,iommu-dma-addr-pool = <0x0 0xFFFFFFFF>;
 
-&usb2_phy0 {
-	status = "ok";
-};
+		sdr0: qcom,hs0_i2s {
+			compatible = "qcom,hsi2s-interface";
+			minor-number = <0>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&hs1_i2s_mclk_active &hs1_i2s_sck_active
+				     &hs1_i2s_ws_active &hs1_i2s_data0_active
+				     &hs1_i2s_data1_active>;
+			pinctrl-1 = <&hs1_i2s_mclk_sleep &hs1_i2s_sck_sleep
+				     &hs1_i2s_ws_sleep &hs1_i2s_data0_sleep
+				     &hs1_i2s_data1_sleep>;
+			bit-clock-hz = <12288000>;
+			data-buffer-ms = <10>;
+			bit-depth = <32>;
+			spkr-channel-count = <2>;
+			mic-channel-count = <2>;
+			pcm-rate = <2>;
+			pcm-sync-src = <0>;
+			aux-mode = <0>;
+			rpcm-width = <1>;
+			tpcm-width = <1>;
+			enable-tdm = <1>;
+			tdm-rate = <32>;
+			tdm-rpcm-width = <16>;
+			tdm-tpcm-width = <16>;
+			tdm-sync-delay = <2>;
+			tdm-inv-sync = <0>;
+			pcm-lane-config = <1>;
+		};
 
-&usb1 {
-	status = "ok";
+		sdr1: qcom,hs1_i2s {
+			compatible = "qcom,hsi2s-interface";
+			minor-number = <1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&hs2_i2s_mclk_active &hs2_i2s_sck_active
+				     &hs2_i2s_ws_active &hs2_i2s_data0_active
+				     &hs2_i2s_data1_active>;
+			pinctrl-1 = <&hs2_i2s_mclk_sleep &hs2_i2s_sck_sleep
+				     &hs2_i2s_ws_sleep &hs2_i2s_data0_sleep
+				     &hs2_i2s_data1_sleep>;
+			bit-clock-hz = <12288000>;
+			data-buffer-ms = <10>;
+			bit-depth = <32>;
+			spkr-channel-count = <2>;
+			mic-channel-count = <2>;
+			pcm-rate = <2>;
+			pcm-sync-src = <0>;
+			aux-mode = <0>;
+			rpcm-width = <1>;
+			tpcm-width = <1>;
+			enable-tdm = <1>;
+			tdm-rate = <32>;
+			tdm-rpcm-width = <16>;
+			tdm-tpcm-width = <16>;
+			tdm-sync-delay = <2>;
+			tdm-inv-sync = <0>;
+			pcm-lane-config = <1>;
+		};
+
+		sdr2: qcom,hs2_i2s {
+			compatible = "qcom,hsi2s-interface";
+			minor-number = <2>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&hs3_i2s_mclk_active &hs3_i2s_sck_active
+				     &hs3_i2s_ws_active &hs3_i2s_data0_active
+				     &hs3_i2s_data1_active>;
+			pinctrl-1 = <&hs3_i2s_mclk_sleep &hs3_i2s_sck_sleep
+				     &hs3_i2s_ws_sleep &hs3_i2s_data0_sleep
+				     &hs3_i2s_data1_sleep>;
+			bit-clock-hz = <12288000>;
+			data-buffer-ms = <10>;
+			bit-depth = <32>;
+			spkr-channel-count = <2>;
+			mic-channel-count = <2>;
+			pcm-rate = <2>;
+			pcm-sync-src = <0>;
+			aux-mode = <0>;
+			rpcm-width = <1>;
+			tpcm-width = <1>;
+			enable-tdm = <1>;
+			tdm-rate = <32>;
+			tdm-rpcm-width = <16>;
+			tdm-tpcm-width = <16>;
+			tdm-sync-delay = <2>;
+			tdm-inv-sync = <0>;
+			pcm-lane-config = <1>;
+		};
+	};
 };
 
-&usb2_phy1 {
+&usb0 {
 	status = "ok";
 };
 
-&usb_qmp_phy {
+&usb2_phy0 {
 	status = "ok";
 };
 
@@ -52,11 +141,11 @@
 					"vdm", "vdn", "vdo",
 					"vdp", "vdq";
 			rename-dev = "super", "userdata", "metadata",
-					"persist", "modem_a", "modem_b",
-					"bluetooth_a", "bluetooth_b",
+					"persist", "modem_a","bluetooth_a",
 					"misc", "vbmeta_a", "vbmeta_b",
-					"boot_a", "boot_b", "dtbo_a",
-					"dtbo_b", "dsp_a", "dsp_b";
+					"boot_a", "dtbo_a","dsp_a",
+					"modem_b", "bluetooth_b", "boot_b",
+					"dtbo_b", "dsp_b";
 		};
 	};
 };
diff --git a/qcom/sa8155-vm.dtsi b/qcom/sa8155-vm.dtsi
index 6646a79d..da1a0546 100755
--- a/qcom/sa8155-vm.dtsi
+++ b/qcom/sa8155-vm.dtsi
@@ -305,92 +305,88 @@
 };
 
 &regulator {
-	virt_regulator {
-		compatible = "virtio,device31";
-
-		usb30_prim_gdsc: usb30_prim_gdsc {
-			regulator-name = "usb30_prim_gdsc";
-		};
+	usb30_prim_gdsc: usb30_prim_gdsc {
+		regulator-name = "usb30_prim_gdsc";
+	};
 
-		usb30_sec_gdsc: usb30_sec_gdsc {
-			regulator-name = "usb30_sec_gdsc";
-		};
+	usb30_sec_gdsc: usb30_sec_gdsc {
+		regulator-name = "usb30_sec_gdsc";
+	};
 
-		pcie_0_gdsc: pcie_0_gdsc {
-			regulator-name = "pcie_0_gdsc";
-		};
+	pcie_0_gdsc: pcie_0_gdsc {
+		regulator-name = "pcie_0_gdsc";
+	};
 
-		pcie_1_gdsc: pcie_1_gdsc {
-			regulator-name = "pcie_1_gdsc";
-		};
+	pcie_1_gdsc: pcie_1_gdsc {
+		regulator-name = "pcie_1_gdsc";
+	};
 
-		L2A: pm8150_1_l2: regulator-pm8150-1-l2 {
-			regulator-name = "ldoa2";
-			regulator-min-microvolt = <3072000>;
-			regulator-max-microvolt = <3072000>;
-		};
+	L2A: pm8150_1_l2: regulator-pm8150-1-l2 {
+		regulator-name = "ldoa2";
+		regulator-min-microvolt = <3072000>;
+		regulator-max-microvolt = <3072000>;
+	};
 
-		L5A: pm8150_1_l5: regulator-pm8150-1-l5 {
-			regulator-name = "ldoa5";
-			regulator-min-microvolt = <880000>;
-			regulator-max-microvolt = <880000>;
-		};
+	L5A: pm8150_1_l5: regulator-pm8150-1-l5 {
+		regulator-name = "ldoa5";
+		regulator-min-microvolt = <880000>;
+		regulator-max-microvolt = <880000>;
+	};
 
-		L12A: pm8150_1_l12: regulator-pm8150-1-l12 {
-			regulator-name = "ldoa12";
-			regulator-min-microvolt = <1800000>;
-			regulator-max-microvolt = <1800000>;
-		};
+	L12A: pm8150_1_l12: regulator-pm8150-1-l12 {
+		regulator-name = "ldoa12";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
 
-		L17A: pm8150_1_l17: regulator-pm8150-1-l17 {
-			regulator-name = "ldoa17";
-			regulator-min-microvolt = <2704000>;
-			regulator-max-microvolt = <2960000>;
-		};
+	L17A: pm8150_1_l17: regulator-pm8150-1-l17 {
+		regulator-name = "ldoa17";
+		regulator-min-microvolt = <2704000>;
+		regulator-max-microvolt = <2960000>;
+	};
 
-		L8C: pm8150_2_l8: regulator-pm8150-2-l8 {
-			regulator-name = "ldoc8";
-			regulator-min-microvolt = <1200000>;
-			regulator-max-microvolt = <1200000>;
-			regulator-allow-set-load;
-		};
+	L8C: pm8150_2_l8: regulator-pm8150-2-l8 {
+		regulator-name = "ldoc8";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-allow-set-load;
+	};
 
-		L13C: pm8150_2_l13: regulator-pm8150-2-l13 {
-			regulator-name = "ldoc13";
-			regulator-min-microvolt = <1800000>;
-			regulator-max-microvolt = <2960000>;
-		};
+	L13C: pm8150_2_l13: regulator-pm8150-2-l13 {
+		regulator-name = "ldoc13";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <2960000>;
+	};
 
-		L15C: pm8150_2_l15: regulator-pm8150-2-l15 {
-			regulator-name = "ldoc15";
-			regulator-min-microvolt = <1800000>;
-			regulator-max-microvolt = <1904000>;
-		};
+	L15C: pm8150_2_l15: regulator-pm8150-2-l15 {
+		regulator-name = "ldoc15";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1904000>;
+	};
 
-		L18C: pm8150_2_l18: regulator-pm8150-2-l18 {
-			regulator-name = "ldoc18";
-			regulator-min-microvolt = <880000>;
-			regulator-max-microvolt = <880000>;
-			regulator-allow-set-load;
-		};
+	L18C: pm8150_2_l18: regulator-pm8150-2-l18 {
+		regulator-name = "ldoc18";
+		regulator-min-microvolt = <880000>;
+		regulator-max-microvolt = <880000>;
+		regulator-allow-set-load;
+	};
 
-		S6A: pm8150_1_s6: regulator-pm8150-1-s6 {
-			regulator-name = "smpa6";
-			regulator-min-microvolt = <600000>;
-			regulator-max-microvolt = <1352000>;
-		};
+	S6A: pm8150_1_s6: regulator-pm8150-1-s6 {
+		regulator-name = "smpa6";
+		regulator-min-microvolt = <600000>;
+		regulator-max-microvolt = <1352000>;
+	};
 
-		S4C: pm8150_2_s4: regulator-pm8150-2-s4 {
-			regulator-name = "smpc4";
-			regulator-min-microvolt = <800000>;
-			regulator-max-microvolt = <1400000>;
-		};
+	S4C: pm8150_2_s4: regulator-pm8150-2-s4 {
+		regulator-name = "smpc4";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1400000>;
+	};
 
-		S5C: pm8150_2_s5: regulator-pm8150-2-s5 {
-			regulator-name = "smpc5";
-			regulator-min-microvolt = <1824000>;
-			regulator-max-microvolt = <2040000>;
-		};
+	S5C: pm8150_2_s5: regulator-pm8150-2-s5 {
+		regulator-name = "smpc5";
+		regulator-min-microvolt = <1824000>;
+		regulator-max-microvolt = <2040000>;
 	};
 };
 
diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi
index 5ce5c715..e3a034d5 100755
--- a/qcom/sa8155.dtsi
+++ b/qcom/sa8155.dtsi
@@ -395,6 +395,31 @@ hsi2s: qcom,hsi2s {
 		status = "disabled";
 	};
 
+	ddr {
+		polling-delay-passive = <10>;
+		polling-delay = <0>;
+		thermal-sensors = <&tsens1 3>;
+		trips {
+			thermal-engine-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			thermal-hal-config {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			reset-mon-cfg {
+				temperature = <118000>;
+				hysteresis = <5000>;
+				type = "passive";
+			};
+		};
+	};
+
 	npu {
 		trips {
 			reset-mon-cfg {
diff --git a/qcom/sa8195-pmic.dtsi b/qcom/sa8195-pmic.dtsi
index 7567a662..42ca99f4 100755
--- a/qcom/sa8195-pmic.dtsi
+++ b/qcom/sa8195-pmic.dtsi
@@ -97,6 +97,50 @@
 				type = "critical";
 			};
 		};
+
+		cooling-maps {
+			trip0_cpu0 {
+				trip = <&pm8195_1_trip0>;
+				cooling-device =
+					<&CPU0 THERMAL_NO_LIMIT
+						THERMAL_NO_LIMIT>;
+			};
+
+			trip0_cpu1 {
+				trip = <&pm8195_1_trip0>;
+				cooling-device = <&cpu1_pause 1 1>;
+			};
+
+			trip0_cpu2 {
+				trip = <&pm8195_1_trip0>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+
+			trip0_cpu3 {
+				trip = <&pm8195_1_trip0>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+
+			trip0_cpu4 {
+				trip = <&pm8195_1_trip0>;
+				cooling-device = <&cpu4_pause 1 1>;
+			};
+
+			trip0_cpu5 {
+				trip = <&pm8195_1_trip0>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+
+			trip0_cpu6 {
+				trip = <&pm8195_1_trip0>;
+				cooling-device = <&cpu6_pause 1 1>;
+			};
+
+			trip0_cpu7 {
+				trip = <&pm8195_1_trip0>;
+				cooling-device = <&cpu7_pause 1 1>;
+			};
+		};
 	};
 
 	pm8195_2_temp_alarm: pm8195_2_tz {
@@ -124,6 +168,50 @@
 				type = "critical";
 			};
 		};
+
+		cooling-maps {
+			trip0_cpu0 {
+				trip = <&pm8195_2_trip0>;
+				cooling-device =
+					<&CPU0 THERMAL_NO_LIMIT
+						THERMAL_NO_LIMIT>;
+			};
+
+			trip0_cpu1 {
+				trip = <&pm8195_2_trip0>;
+				cooling-device = <&cpu1_pause 1 1>;
+			};
+
+			trip0_cpu2 {
+				trip = <&pm8195_2_trip0>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+
+			trip0_cpu3 {
+				trip = <&pm8195_2_trip0>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+
+			trip0_cpu4 {
+				trip = <&pm8195_2_trip0>;
+				cooling-device = <&cpu4_pause 1 1>;
+			};
+
+			trip0_cpu5 {
+				trip = <&pm8195_2_trip0>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+
+			trip0_cpu6 {
+				trip = <&pm8195_2_trip0>;
+				cooling-device = <&cpu6_pause 1 1>;
+			};
+
+			trip0_cpu7 {
+				trip = <&pm8195_2_trip0>;
+				cooling-device = <&cpu7_pause 1 1>;
+			};
+		};
 	};
 
 	pm8195_3_temp_alarm: pm8195_3_tz {
@@ -151,6 +239,50 @@
 				type = "critical";
 			};
 		};
+
+		cooling-maps {
+			trip0_cpu0 {
+				trip = <&pm8195_3_trip0>;
+				cooling-device =
+					<&CPU0 THERMAL_NO_LIMIT
+						THERMAL_NO_LIMIT>;
+			};
+
+			trip0_cpu1 {
+				trip = <&pm8195_3_trip0>;
+				cooling-device = <&cpu1_pause 1 1>;
+			};
+
+			trip0_cpu2 {
+				trip = <&pm8195_3_trip0>;
+				cooling-device = <&cpu2_pause 1 1>;
+			};
+
+			trip0_cpu3 {
+				trip = <&pm8195_3_trip0>;
+				cooling-device = <&cpu3_pause 1 1>;
+			};
+
+			trip0_cpu4 {
+				trip = <&pm8195_3_trip0>;
+				cooling-device = <&cpu4_pause 1 1>;
+			};
+
+			trip0_cpu5 {
+				trip = <&pm8195_3_trip0>;
+				cooling-device = <&cpu5_pause 1 1>;
+			};
+
+			trip0_cpu6 {
+				trip = <&pm8195_3_trip0>;
+				cooling-device = <&cpu6_pause 1 1>;
+			};
+
+			trip0_cpu7 {
+				trip = <&pm8195_3_trip0>;
+				cooling-device = <&cpu7_pause 1 1>;
+			};
+		};
 	};
 };
 
diff --git a/qcom/sa8195-thermal.dtsi b/qcom/sa8195-thermal.dtsi
index c6eaba1d..c708ed82 100755
--- a/qcom/sa8195-thermal.dtsi
+++ b/qcom/sa8195-thermal.dtsi
@@ -224,6 +224,14 @@
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			gpu_cdev {
+				trip = <&gpuss0_trip0>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	gpuss-1 {
@@ -255,6 +263,14 @@
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			gpu1_cdev {
+				trip = <&gpuss1_trip0>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	gpuss-2 {
@@ -286,6 +302,14 @@
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			gpu2_cdev {
+				trip = <&gpuss2_trip0>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	gpuss-3 {
@@ -317,6 +341,14 @@
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			gpu3_cdev {
+				trip = <&gpuss3_trip0>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	cpu-0-0 {
diff --git a/qcom/sa8195-vm-la-overlay.dts b/qcom/sa8195-vm-la-overlay.dts
index ab8fc5f4..decf47e1 100755
--- a/qcom/sa8195-vm-la-overlay.dts
+++ b/qcom/sa8195-vm-la-overlay.dts
@@ -1,8 +1,6 @@
 /dts-v1/;
 /plugin/;
 
-#include "sa8195-vm.dtsi"
-#include "sa8195-vm-la.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. SA8195 Single LA Virtual Machine";
diff --git a/qcom/sa8195-vm-la.dtsi b/qcom/sa8195-vm-la.dtsi
index 17f1e228..2eea62b1 100755
--- a/qcom/sa8195-vm-la.dtsi
+++ b/qcom/sa8195-vm-la.dtsi
@@ -1,2 +1,62 @@
+&reserved_memory {
+	secure_display_memory: secure_display_region {
+		compatible = "shared-dma-pool";
+		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+		reusable;
+		alignment = <0x0 0x400000>;
+		size = <0x0 0x0a000000>;
+	};
+};
+
+&qcom_dma_heaps {
+	qcom,display {
+		qcom,dma-heap-name = "qcom,display";
+		qcom,dma-heap-type = <HEAP_TYPE_CMA>;
+		qcom,max-align = <9>;
+		memory-region = <&secure_display_memory>;
+	};
+};
+
 &soc {
 };
+
+/ {
+	rename_devices: rename_devices {
+		compatible = "qcom,rename-devices";
+		rename_blk: rename_blk {
+			device-type = "block";
+			actual-dev = "vda", "vdb", "vdc",
+					"vdd", "vde", "vdf",
+					"vdg", "vdh", "vdi",
+					"vdj", "vdk", "vdl",
+					"vdm", "vdn", "vdo",
+					"vdp", "vdq";
+			rename-dev = "super", "userdata", "metadata",
+					"persist", "modem_a","bluetooth_a",
+					"misc", "vbmeta_a", "vbmeta_b",
+					"boot_a", "dtbo_a","dsp_a",
+					"modem_b", "bluetooth_b", "boot_b",
+					"dtbo_b", "dsp_b";
+		};
+	};
+};
+
+&usb0 {
+	status = "ok";
+};
+
+&usb2_phy0 {
+	status = "ok";
+};
+
+&qupv3_se17_4uart {
+	status = "ok";
+};
+
+&pcie0_msi {
+	status = "ok";
+};
+
+&pcie0 {
+	status = "ok";
+};
diff --git a/qcom/sa8195-vm-pcie.dtsi b/qcom/sa8195-vm-pcie.dtsi
new file mode 100755
index 00000000..bd3cce24
--- /dev/null
+++ b/qcom/sa8195-vm-pcie.dtsi
@@ -0,0 +1,1320 @@
+
+&soc {
+	pcie0: qcom,pcie@1c00000 {
+		compatible = "qcom,pci-msm";
+		cell-index = <0>;
+
+		reg = <0x1c00000 0x4000>,
+			<0x1c06000 0x1000>,
+			<0x60000000 0xf1d>,
+			<0x60000f20 0xa8>,
+			<0x60001000 0x1000>,
+			<0x60100000 0x100000>,
+			<0x60200000 0x100000>,
+			<0x60300000 0x3d00000>;
+
+		reg-names = "parf", "phy", "dm_core", "elbi",
+				"iatu", "conf", "io", "bars";
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
+			<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
+		interrupt-parent = <&pcie0>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = < 0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+
+		qcom,phy-sequence = <0x0840 0x03 0x0
+				0x0094 0x08 0x0
+				0x0154 0x34 0x0
+				0x016c 0x08 0x0
+				0x0058 0x0f 0x0
+				0x00a4 0x42 0x0
+				0x0110 0x24 0x0
+				0x011c 0x03 0x0
+				0x0118 0xb4 0x0
+				0x010c 0x02 0x0
+				0x01bc 0x11 0x0
+				0x00bc 0x82 0x0
+				0x00d4 0x03 0x0
+				0x00d0 0x55 0x0
+				0x00cc 0x55 0x0
+				0x00b0 0x1a 0x0
+				0x00ac 0x0a 0x0
+				0x00c4 0x68 0x0
+				0x00e0 0x02 0x0
+				0x00dc 0xaa 0x0
+				0x00d8 0xab 0x0
+				0x00b8 0x34 0x0
+				0x00b4 0x14 0x0
+				0x0158 0x01 0x0
+				0x0074 0x06 0x0
+				0x007c 0x16 0x0
+				0x0084 0x36 0x0
+				0x0078 0x06 0x0
+				0x0080 0x16 0x0
+				0x0088 0x36 0x0
+				0x01b0 0x1e 0x0
+				0x01ac 0xb9 0x0
+				0x01b8 0x18 0x0
+				0x01b4 0x94 0x0
+				0x0050 0x07 0x0
+				0x0010 0x00 0x0
+				0x001c 0x31 0x0
+				0x0020 0x01 0x0
+				0x0024 0xde 0x0
+				0x0028 0x07 0x0
+				0x0030 0x4c 0x0
+				0x0034 0x06 0x0
+				0x029c 0x12 0x0
+				0x0284 0x35 0x0
+				0x023c 0x11 0x0
+				0x051c 0x03 0x0
+				0x0518 0x1c 0x0
+				0x0524 0x1e 0x0
+				0x04e8 0x00 0x0
+				0x04ec 0x0e 0x0
+				0x04f0 0x4a 0x0
+				0x04f4 0x0f 0x0
+				0x05b4 0x04 0x0
+				0x0434 0x7f 0x0
+				0x0444 0x70 0x0
+				0x0510 0x17 0x0
+				0x04d4 0x54 0x0
+				0x04d8 0x07 0x0
+				0x0598 0xd4 0x0
+				0x059c 0x54 0x0
+				0x05a0 0xdb 0x0
+				0x05a4 0x3b 0x0
+				0x05a8 0x31 0x0
+				0x0584 0x24 0x0
+				0x0588 0xe4 0x0
+				0x058c 0xec 0x0
+				0x0590 0x3b 0x0
+				0x0594 0x36 0x0
+				0x0570 0xff 0x0
+				0x0574 0xff 0x0
+				0x0578 0xff 0x0
+				0x057c 0x7f 0x0
+				0x0580 0x66 0x0
+				0x04fc 0x00 0x0
+				0x04f8 0xc0 0x0
+				0x0460 0x30 0x0
+				0x0464 0xc0 0x0
+				0x05bc 0x0c 0x0
+				0x04dc 0x0d 0x0
+				0x0408 0x0c 0x0
+				0x0414 0x03 0x0
+				0x09a4 0x01 0x0
+				0x0c90 0x00 0x0
+				0x0c40 0x01 0x0
+				0x0c48 0x01 0x0
+				0x0c50 0x00 0x0
+				0x0cbc 0x00 0x0
+				0x0ce0 0x58 0x0
+				0x0048 0x90 0x0
+				0x0c1c 0xc1 0x0
+				0x0988 0x88 0x0
+				0x0998 0x0b 0x0
+				0x08dc 0x0d 0x0
+				0x09ec 0x01 0x0
+				0x0800 0x00 0x0
+				0x0844 0x03 0x0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie0_clkreq_default
+			&pcie0_perst_default
+			&pcie0_wake_default>;
+
+		perst-gpio = <&tlmm 35 0>;
+		wake-gpio = <&tlmm 37 0>;
+
+		gdsc-core-vdd-supply = <&pcie_0_gdsc>;
+		vreg-1p2-supply = <&pm8195_1_l9>;
+		vreg-0p9-supply = <&pm8195_3_l5>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 24000>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 24000>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+
+		msi-parent = <&pcie0_msi>;
+
+		qcom,no-l0s-supported;
+		qcom,no-l1-supported;
+		qcom,no-l1ss-supported;
+		qcom,no-aux-clk-sync;
+
+		qcom,ep-latency = <10>;
+
+		qcom,slv-addr-space-size = <0x4000000>;
+
+		qcom,phy-status-offset = <0x814>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0x840>;
+
+		qcom,boot-option = <0x1>;
+
+		linux,pci-domain = <0>;
+
+		qcom,pcie-phy-ver = <2110>;
+		qcom,use-19p2mhz-aux-clk;
+
+		qcom,smmu-sid-base = <0x1d80>;
+
+		iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
+			<0x100 &apps_smmu 0x1d81 0x1>,
+			<0x200 &apps_smmu 0x1d82 0x1>,
+			<0x300 &apps_smmu 0x1d83 0x1>,
+			<0x400 &apps_smmu 0x1d84 0x1>,
+			<0x500 &apps_smmu 0x1d85 0x1>,
+			<0x600 &apps_smmu 0x1d86 0x1>,
+			<0x700 &apps_smmu 0x1d87 0x1>,
+			<0x800 &apps_smmu 0x1d88 0x1>,
+			<0x900 &apps_smmu 0x1d89 0x1>,
+			<0xa00 &apps_smmu 0x1d8a 0x1>,
+			<0xb00 &apps_smmu 0x1d8b 0x1>,
+			<0xc00 &apps_smmu 0x1d8c 0x1>,
+			<0xd00 &apps_smmu 0x1d8d 0x1>,
+			<0xe00 &apps_smmu 0x1d8e 0x1>,
+			<0xf00 &apps_smmu 0x1d8f 0x1>;
+
+		clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+			<&dummycc RPMH_CXO_CLK>,
+			<&gcc GCC_PCIE_0_AUX_CLK>,
+			<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_0_CLKREF_CLK>,
+			<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+			<&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
+			<&gcc GCC_PCIE_PHY_AUX_CLK>;
+
+		clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
+				"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
+				"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
+				"pcie_ldo", "pcie_0_slv_q2a_axi_clk",
+				"pcie_tbu_clk", "pcie_phy_refgen_clk",
+				"pcie_phy_aux_clk";
+
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <100000000>, <0>;
+
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>,
+						 <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_0_BCR>,
+			<&gcc GCC_PCIE_0_PHY_BCR>;
+
+		reset-names = "pcie_0_core_reset",
+				"pcie_0_phy_reset";
+
+		status = "disabled";
+
+		pcie_rc0: pcie_rc0 {
+			#address-cells = <5>;
+			#size-cells = <0>;
+			reg = <0 0 0 0 0>;
+			pci-ids = "17cb:0109";
+		};
+	};
+
+	pcie0_msi: qcom,pcie0_msi@17a00040 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0x17a00040 0x0>;
+		interrupts = <GIC_SPI 864 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 865 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 866 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 867 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 868 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 869 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 870 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 871 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 872 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 873 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 874 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 875 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 876 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 877 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 878 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 879 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 880 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 881 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 882 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 883 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 884 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 885 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 886 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 887 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 888 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 889 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 890 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 891 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 892 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 893 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 894 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 895 IRQ_TYPE_EDGE_RISING>;
+		status = "disabled";
+	};
+
+	pcie1: qcom,pcie@1c10000 {
+		compatible = "qcom,pci-msm";
+		cell-index = <1>;
+
+		reg = <0x1c10000 0x3000>,
+			<0x01c16000 0x2000>,
+			<0x68000000 0xf1d>,
+			<0x68000f20 0xa8>,
+			<0x68001000 0x1000>,
+			<0x68100000 0x100000>,
+			<0x68200000 0x100000>,
+			<0x68300000 0x3d00000>,
+			<0x01fec004 0x4>;
+
+		reg-names = "parf", "phy", "dm_core", "elbi",
+				"iatu", "conf", "io", "bars", "tcsr";
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x68200000 0x68200000 0x0 0x100000>,
+			<0x02000000 0x0 0x68300000 0x68300000 0x0 0x3d00000>;
+		interrupt-parent = <&pcie1>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>;
+
+		qcom,tcsr = <0x0 0x0>;
+		qcom,phy-sequence = <0x0a40 0x03 0x0
+				0x0010 0x00 0x0
+				0x001c 0x31 0x0
+				0x0020 0x01 0x0
+				0x0024 0xde 0x0
+				0x0028 0x07 0x0
+				0x0030 0x4c 0x0
+				0x0034 0x06 0x0
+				0x0048 0x90 0x0
+				0x0058 0x0f 0x0
+				0x0074 0x06 0x0
+				0x0078 0x06 0x0
+				0x007c 0x16 0x0
+				0x0080 0x16 0x0
+				0x0084 0x36 0x0
+				0x0088 0x36 0x0
+				0x0094 0x08 0x0
+				0x00a4 0x42 0x0
+				0x00ac 0x0a 0x0
+				0x00b0 0x1a 0x0
+				0x00b4 0x14 0x0
+				0x00b8 0x34 0x0
+				0x00bc 0x82 0x0
+				0x00c4 0x68 0x0
+				0x00cc 0x55 0x0
+				0x00d0 0x55 0x0
+				0x00d4 0x03 0x0
+				0x00d8 0xab 0x0
+				0x00dc 0xaa 0x0
+				0x00e0 0x02 0x0
+				0x010c 0x02 0x0
+				0x0110 0x24 0x0
+				0x0118 0xb4 0x0
+				0x011c 0x03 0x0
+				0x0154 0x34 0x0
+				0x0158 0x01 0x0
+				0x016c 0x08 0x0
+				0x01ac 0xb9 0x0
+				0x01b0 0x1e 0x0
+				0x01b4 0x94 0x0
+				0x01b8 0x18 0x0
+				0x01bc 0x11 0x0
+				0x023c 0x11 0x0
+				0x0284 0x35 0x0
+				0x029c 0x12 0x0
+				0x0304 0x02 0x0
+				0x0408 0x0c 0x0
+				0x0414 0x03 0x0
+				0x0434 0x7f 0x0
+				0x0444 0x70 0x0
+				0x0460 0x30 0x0
+				0x0464 0x00 0x0
+				0x04d4 0x54 0x0
+				0x04d8 0x07 0x0
+				0x04dc 0x0d 0x0
+				0x04e8 0x00 0x0
+				0x04ec 0x0e 0x0
+				0x04f0 0x4a 0x0
+				0x04f4 0x0f 0x0
+				0x04f8 0xc0 0x0
+				0x04fc 0x00 0x0
+				0x0510 0x17 0x0
+				0x0518 0x1c 0x0
+				0x051c 0x03 0x0
+				0x0524 0x1e 0x0
+				0x0570 0xff 0x0
+				0x0574 0xff 0x0
+				0x0578 0xff 0x0
+				0x057c 0x7f 0x0
+				0x0580 0x66 0x0
+				0x0584 0x24 0x0
+				0x0588 0xe4 0x0
+				0x058c 0xec 0x0
+				0x0590 0x3b 0x0
+				0x0594 0x36 0x0
+				0x0598 0xd4 0x0
+				0x059c 0x54 0x0
+				0x05a0 0xdb 0x0
+				0x05a4 0x3b 0x0
+				0x05a8 0x31 0x0
+				0x05bc 0x0c 0x0
+				0x063c 0x11 0x0
+				0x0684 0x35 0x0
+				0x069c 0x12 0x0
+				0x0704 0x20 0x0
+				0x0808 0x0c 0x0
+				0x0814 0x03 0x0
+				0x0834 0x7f 0x0
+				0x0844 0x70 0x0
+				0x0860 0x30 0x0
+				0x0864 0x00 0x0
+				0x08d4 0x54 0x0
+				0x08d8 0x07 0x0
+				0x08dc 0x0d 0x0
+				0x08e8 0x00 0x0
+				0x08ec 0x0e 0x0
+				0x08f0 0x4a 0x0
+				0x08f4 0x0f 0x0
+				0x08f8 0xc0 0x0
+				0x08fc 0x00 0x0
+				0x0910 0x17 0x0
+				0x0918 0x1c 0x0
+				0x091c 0x03 0x0
+				0x0924 0x1e 0x0
+				0x0970 0xff 0x0
+				0x0974 0xff 0x0
+				0x0978 0xff 0x0
+				0x097c 0x7f 0x0
+				0x0980 0x66 0x0
+				0x0984 0x24 0x0
+				0x0988 0xe4 0x0
+				0x098c 0xec 0x0
+				0x0990 0x3b 0x0
+				0x0994 0x36 0x0
+				0x0998 0xd4 0x0
+				0x099c 0x54 0x0
+				0x09a0 0xdb 0x0
+				0x09a4 0x3b 0x0
+				0x09a8 0x31 0x0
+				0x09bc 0x0c 0x0
+				0x0adc 0x05 0x0
+				0x0b88 0x88 0x0
+				0x0b98 0x0b 0x0
+				0x0ba4 0x01 0x0
+				0x0bec 0x01 0x0
+				0x0e0c 0x0d 0x0
+				0x0e14 0x07 0x0
+				0x0e1c 0xc1 0x0
+				0x0e40 0x01 0x0
+				0x0e48 0x01 0x0
+				0x0e90 0x00 0x0
+				0x0ebc 0x00 0x0
+				0x0ee0 0x58 0x0
+				0x0eb4 0x33 0x0
+				0x0a00 0x00 0x0
+				0x0a44 0x03 0x0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie1_clkreq_default
+			&pcie1_perst_default
+			&pcie1_wake_default>;
+
+		perst-gpio = <&tlmm 175 0>;
+		wake-gpio = <&tlmm 177 0>;
+
+		gdsc-core-vdd-supply = <&pcie_1_gdsc>;
+		vreg-1p2-supply = <&pm8195_1_l9>;
+		vreg-0p9-supply = <&pm8195_3_l5>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 24000>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 24000>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+
+		msi-parent = <&pcie1_msi>;
+
+		qcom,no-l0s-supported;
+
+		qcom,ep-latency = <10>;
+
+		qcom,slv-addr-space-size = <0x4000000>;
+
+		qcom,phy-status-offset = <0xa14>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0xa40>;
+
+		qcom,boot-option = <0x1>;
+
+		linux,pci-domain = <1>;
+
+		qcom,pcie-phy-ver = <2113>;
+		qcom,use-19p2mhz-aux-clk;
+
+		qcom,smmu-sid-base = <0x1c80>;
+
+		iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+			<0x100 &apps_smmu 0x1c81 0x1>,
+			<0x200 &apps_smmu 0x1c82 0x1>,
+			<0x300 &apps_smmu 0x1c83 0x1>,
+			<0x400 &apps_smmu 0x1c84 0x1>,
+			<0x500 &apps_smmu 0x1c85 0x1>,
+			<0x600 &apps_smmu 0x1c86 0x1>,
+			<0x700 &apps_smmu 0x1c87 0x1>,
+			<0x800 &apps_smmu 0x1c88 0x1>,
+			<0x900 &apps_smmu 0x1c89 0x1>,
+			<0xa00 &apps_smmu 0x1c8a 0x1>,
+			<0xb00 &apps_smmu 0x1c8b 0x1>,
+			<0xc00 &apps_smmu 0x1c8c 0x1>,
+			<0xd00 &apps_smmu 0x1c8d 0x1>,
+			<0xe00 &apps_smmu 0x1c8e 0x1>,
+			<0xf00 &apps_smmu 0x1c8f 0x1>;
+
+		clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
+			<&dummycc RPMH_CXO_CLK>,
+			<&gcc GCC_PCIE_1_AUX_CLK>,
+			<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_1_CLKREF_CLK>,
+			<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+			<&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
+			<&gcc GCC_PCIE_PHY_AUX_CLK>;
+
+		clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
+				"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
+				"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
+				"pcie_ldo", "pcie_1_slv_q2a_axi_clk",
+				"pcie_tbu_clk", "pcie_phy_refgen_clk",
+				"pcie_phy_aux_clk";
+
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <100000000>, <0>;
+
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>,
+						 <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_1_BCR>,
+			<&gcc GCC_PCIE_1_PHY_BCR>;
+
+		reset-names = "pcie_1_core_reset",
+				"pcie_1_phy_reset";
+
+		status = "disabled";
+
+		pcie_rc1: pcie_rc1 {
+			#address-cells = <5>;
+			#size-cells = <0>;
+			reg = <0 0 0 0 0>;
+			pci-ids = "17cb:0109";
+		};
+	};
+
+	pcie1_msi: qcom,pcie1_msi@17a00040 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0x17a00040 0x0>;
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 896 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 897 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 898 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 899 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 900 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 901 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 902 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 903 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 904 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 905 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 906 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 907 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 908 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 909 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 910 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 911 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 912 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 913 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 914 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 915 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 916 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 917 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 918 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 919 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 920 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 921 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 922 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 923 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 924 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 925 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 926 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 927 IRQ_TYPE_EDGE_RISING>;
+	};
+
+	pcie2: qcom,pcie@1c18000 {
+		compatible = "qcom,pci-msm";
+		cell-index = <2>;
+
+		reg = <0x1c18000 0x3000>,
+			<0x01c1c000 0x2000>,
+			<0x70000000 0xf1d>,
+			<0x70000f20 0xa8>,
+			<0x70001000 0x1000>,
+			<0x70100000 0x100000>,
+			<0x70200000 0x100000>,
+			<0x70300000 0x3d00000>,
+			<0x01fec004 0x4>;
+
+		reg-names = "parf", "phy", "dm_core", "elbi",
+				"iatu", "conf", "io", "bars", "tcsr";
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x70200000 0x70200000 0x0 0x100000>,
+			<0x02000000 0x0 0x70300000 0x70300000 0x0 0x3d00000>;
+		interrupt-parent = <&pcie2>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>;
+
+		qcom,tcsr = <0x0 0x0>;
+		qcom,phy-sequence = <0x0a40 0x03 0x0
+				0x0010 0x00 0x0
+				0x001c 0x31 0x0
+				0x0020 0x01 0x0
+				0x0024 0xde 0x0
+				0x0028 0x07 0x0
+				0x0030 0x4c 0x0
+				0x0034 0x06 0x0
+				0x0048 0x90 0x0
+				0x0058 0x0f 0x0
+				0x0074 0x06 0x0
+				0x0078 0x06 0x0
+				0x007c 0x16 0x0
+				0x0080 0x16 0x0
+				0x0084 0x36 0x0
+				0x0088 0x36 0x0
+				0x0094 0x08 0x0
+				0x00a4 0x42 0x0
+				0x00ac 0x0a 0x0
+				0x00b0 0x1a 0x0
+				0x00b4 0x14 0x0
+				0x00b8 0x34 0x0
+				0x00bc 0x82 0x0
+				0x00c4 0x68 0x0
+				0x00cc 0x55 0x0
+				0x00d0 0x55 0x0
+				0x00d4 0x03 0x0
+				0x00d8 0xab 0x0
+				0x00dc 0xaa 0x0
+				0x00e0 0x02 0x0
+				0x010c 0x02 0x0
+				0x0110 0x24 0x0
+				0x0118 0xb4 0x0
+				0x011c 0x03 0x0
+				0x0154 0x34 0x0
+				0x0158 0x01 0x0
+				0x016c 0x08 0x0
+				0x01ac 0xb9 0x0
+				0x01b0 0x1e 0x0
+				0x01b4 0x94 0x0
+				0x01b8 0x18 0x0
+				0x01bc 0x11 0x0
+				0x023c 0x11 0x0
+				0x0284 0x35 0x0
+				0x029c 0x12 0x0
+				0x0304 0x02 0x0
+				0x0408 0x0c 0x0
+				0x0414 0x03 0x0
+				0x0434 0x7f 0x0
+				0x0444 0x70 0x0
+				0x0460 0x30 0x0
+				0x0464 0x00 0x0
+				0x04d4 0x54 0x0
+				0x04d8 0x07 0x0
+				0x04dc 0x0d 0x0
+				0x04e8 0x00 0x0
+				0x04ec 0x0e 0x0
+				0x04f0 0x4a 0x0
+				0x04f4 0x0f 0x0
+				0x04f8 0xc0 0x0
+				0x04fc 0x00 0x0
+				0x0510 0x17 0x0
+				0x0518 0x1c 0x0
+				0x051c 0x03 0x0
+				0x0524 0x1e 0x0
+				0x0570 0xff 0x0
+				0x0574 0xff 0x0
+				0x0578 0xff 0x0
+				0x057c 0x7f 0x0
+				0x0580 0x66 0x0
+				0x0584 0x24 0x0
+				0x0588 0xe4 0x0
+				0x058c 0xec 0x0
+				0x0590 0x3b 0x0
+				0x0594 0x36 0x0
+				0x0598 0xd4 0x0
+				0x059c 0x54 0x0
+				0x05a0 0xdb 0x0
+				0x05a4 0x3b 0x0
+				0x05a8 0x31 0x0
+				0x05bc 0x0c 0x0
+				0x063c 0x11 0x0
+				0x0684 0x35 0x0
+				0x069c 0x12 0x0
+				0x0704 0x20 0x0
+				0x0808 0x0c 0x0
+				0x0814 0x03 0x0
+				0x0834 0x7f 0x0
+				0x0844 0x70 0x0
+				0x0860 0x30 0x0
+				0x0864 0x00 0x0
+				0x08d4 0x54 0x0
+				0x08d8 0x07 0x0
+				0x08dc 0x0d 0x0
+				0x08e8 0x00 0x0
+				0x08ec 0x0e 0x0
+				0x08f0 0x4a 0x0
+				0x08f4 0x0f 0x0
+				0x08f8 0xc0 0x0
+				0x08fc 0x00 0x0
+				0x0910 0x17 0x0
+				0x0918 0x1c 0x0
+				0x091c 0x03 0x0
+				0x0924 0x1e 0x0
+				0x0970 0xff 0x0
+				0x0974 0xff 0x0
+				0x0978 0xff 0x0
+				0x097c 0x7f 0x0
+				0x0980 0x66 0x0
+				0x0984 0x24 0x0
+				0x0988 0xe4 0x0
+				0x098c 0xec 0x0
+				0x0990 0x3b 0x0
+				0x0994 0x36 0x0
+				0x0998 0xd4 0x0
+				0x099c 0x54 0x0
+				0x09a0 0xdb 0x0
+				0x09a4 0x3b 0x0
+				0x09a8 0x31 0x0
+				0x09bc 0x0c 0x0
+				0x0adc 0x05 0x0
+				0x0b88 0x88 0x0
+				0x0b98 0x0b 0x0
+				0x0ba4 0x01 0x0
+				0x0bec 0x01 0x0
+				0x0e0c 0x0d 0x0
+				0x0e14 0x07 0x0
+				0x0e1c 0xc1 0x0
+				0x0e40 0x01 0x0
+				0x0e48 0x01 0x0
+				0x0e90 0x00 0x0
+				0x0ebc 0x00 0x0
+				0x0ee0 0x58 0x0
+				0x0eb4 0x33 0x0
+				0x0a00 0x00 0x0
+				0x0a44 0x03 0x0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie2_clkreq_default
+			&pcie2_perst_default
+			&pcie2_wake_default>;
+
+		perst-gpio = <&tlmm 102 0>;
+		wake-gpio = <&tlmm 104 0>;
+
+		gdsc-core-vdd-supply = <&pcie_2_gdsc>;
+		vreg-1p2-supply = <&pm8195_1_l9>;
+		vreg-0p9-supply = <&pm8195_3_l5>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 24000>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 24000>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+
+		msi-parent = <&pcie2_msi>;
+
+		qcom,no-l0s-supported;
+
+		qcom,ep-latency = <10>;
+
+		qcom,slv-addr-space-size = <0x4000000>;
+
+		qcom,phy-status-offset = <0xa14>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0xa40>;
+
+		qcom,boot-option = <0x1>;
+
+		linux,pci-domain = <2>;
+
+		qcom,pcie-phy-ver = <2105>;
+		qcom,use-19p2mhz-aux-clk;
+
+		qcom,smmu-sid-base = <0x1d00>;
+
+		iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
+			<0x100 &apps_smmu 0x1d01 0x1>,
+			<0x200 &apps_smmu 0x1d02 0x1>,
+			<0x300 &apps_smmu 0x1d03 0x1>,
+			<0x400 &apps_smmu 0x1d04 0x1>,
+			<0x500 &apps_smmu 0x1d05 0x1>,
+			<0x600 &apps_smmu 0x1d06 0x1>,
+			<0x700 &apps_smmu 0x1d07 0x1>,
+			<0x800 &apps_smmu 0x1d08 0x1>,
+			<0x900 &apps_smmu 0x1d09 0x1>,
+			<0xa00 &apps_smmu 0x1d0a 0x1>,
+			<0xb00 &apps_smmu 0x1d0b 0x1>,
+			<0xc00 &apps_smmu 0x1d0c 0x1>,
+			<0xd00 &apps_smmu 0x1d0d 0x1>,
+			<0xe00 &apps_smmu 0x1d0e 0x1>,
+			<0xf00 &apps_smmu 0x1d0f 0x1>;
+
+		clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
+			<&dummycc RPMH_CXO_CLK>,
+			<&gcc GCC_PCIE_2_AUX_CLK>,
+			<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_2_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_2_CLKREF_CLK>,
+			<&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+			<&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
+			<&gcc GCC_PCIE_PHY_AUX_CLK>;
+
+		clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
+				"pcie_2_aux_clk", "pcie_2_cfg_ahb_clk",
+				"pcie_2_mstr_axi_clk", "pcie_2_slv_axi_clk",
+				"pcie_ldo", "pcie_2_slv_q2a_axi_clk",
+				"pcie_tbu_clk", "pcie_phy_refgen_clk",
+				"pcie_phy_aux_clk";
+
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <100000000>, <0>;
+
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>,
+						 <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_2_BCR>,
+			<&gcc GCC_PCIE_2_PHY_BCR>;
+
+		reset-names = "pcie_2_core_reset",
+				"pcie_2_phy_reset";
+
+		status = "disabled";
+
+		pcie_rc2: pcie_rc2 {
+			reg = <0 0 0 0 0>;
+			pci-ids = "17cb:0109";
+			#address-cells = <5>;
+			#size-cells = <0>;
+		};
+	};
+
+	pcie2_msi: qcom,pcie2_msi@17a00040 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0x17a00040 0x0>;
+		interrupts = <GIC_SPI 832 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 833 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 834 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 835 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 836 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 837 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 838 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 839 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 840 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 841 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 842 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 843 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 844 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 845 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 846 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 847 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 848 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 849 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 850 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 851 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 852 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 853 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 854 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 856 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 857 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 858 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 859 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 860 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 861 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 862 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 863 IRQ_TYPE_EDGE_RISING>;
+		status = "disabled";
+	};
+
+	pcie3: qcom,pcie@1c08000 {
+		compatible = "qcom,pci-msm";
+		cell-index = <3>;
+
+		reg = <0x1c08000 0x3000>,
+			<0x1c0c000 0x4000>,
+			<0x40000000 0xf1d>,
+			<0x40000f20 0xa8>,
+			<0x40001000 0x1000>,
+			<0x40100000 0x100000>,
+			<0x40200000 0x100000>,
+			<0x40300000 0x1fd00000> ;
+
+		reg-names = "parf", "phy", "dm_core", "elbi",
+				"iatu", "conf", "io", "bars";
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
+			<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
+		interrupt-parent = <&pcie3>;
+		interrupts = <0 1 2 3 4>;
+		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+				"int_d";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0xffffffff>;
+		interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
+				0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
+
+		qcom,phy-sequence = <0x0a40 0x03 0x0
+				0x0010 0x00 0x0
+				0x001c 0x31 0x0
+				0x0020 0x01 0x0
+				0x0024 0xde 0x0
+				0x0028 0x07 0x0
+				0x0030 0x4c 0x0
+				0x0034 0x06 0x0
+				0x0048 0x90 0x0
+				0x0044 0x1c 0x0
+				0x0058 0x0f 0x0
+				0x0074 0x06 0x0
+				0x0078 0x06 0x0
+				0x007c 0x16 0x0
+				0x0080 0x16 0x0
+				0x0084 0x36 0x0
+				0x0088 0x36 0x0
+				0x0094 0x08 0x0
+				0x00a4 0x42 0x0
+				0x00ac 0x0a 0x0
+				0x00b0 0x1a 0x0
+				0x00b4 0x14 0x0
+				0x00b8 0x34 0x0
+				0x00bc 0x82 0x0
+				0x00c4 0x68 0x0
+				0x00cc 0x55 0x0
+				0x00d0 0x55 0x0
+				0x00d4 0x03 0x0
+				0x00d8 0xab 0x0
+				0x00dc 0xaa 0x0
+				0x00e0 0x02 0x0
+				0x010c 0x02 0x0
+				0x0110 0x24 0x0
+				0x0118 0xb4 0x0
+				0x011c 0x03 0x0
+				0x0154 0x34 0x0
+				0x0158 0x01 0x0
+				0x016c 0x08 0x0
+				0x01ac 0xb9 0x0
+				0x01b0 0x1e 0x0
+				0x01b4 0x94 0x0
+				0x01b8 0x18 0x0
+				0x01bc 0x11 0x0
+				0x0284 0x35 0x0
+				0x023c 0x11 0x0
+				0x029c 0x12 0x0
+				0x0408 0x0c 0x0
+				0x0414 0x03 0x0
+				0x0434 0x7f 0x0
+				0x0444 0x70 0x0
+				0x0460 0x30 0x0
+				0x0464 0x00 0x0
+				0x04d4 0x54 0x0
+				0x04d8 0x07 0x0
+				0x04dc 0x0d 0x0
+				0x04e8 0x00 0x0
+				0x04ec 0x0e 0x0
+				0x04f0 0x4a 0x0
+				0x04f4 0x0f 0x0
+				0x04f8 0xc0 0x0
+				0x04fc 0x00 0x0
+				0x0510 0x17 0x0
+				0x0518 0x1c 0x0
+				0x051c 0x03 0x0
+				0x0524 0x1e 0x0
+				0x0570 0xff 0x0
+				0x0574 0xff 0x0
+				0x0578 0xff 0x0
+				0x057c 0x7f 0x0
+				0x0580 0x66 0x0
+				0x0584 0x24 0x0
+				0x0588 0xe4 0x0
+				0x058c 0xec 0x0
+				0x0590 0x3b 0x0
+				0x0594 0x36 0x0
+				0x0598 0xd4 0x0
+				0x059c 0x54 0x0
+				0x05a0 0xdb 0x0
+				0x05a4 0x3b 0x0
+				0x05a8 0x31 0x0
+				0x05bc 0x0c 0x0
+				0x0684 0x35 0x0
+				0x063c 0x11 0x0
+				0x069c 0x12 0x0
+				0x0808 0x0c 0x0
+				0x0814 0x03 0x0
+				0x0834 0x7f 0x0
+				0x0844 0x70 0x0
+				0x0860 0x30 0x0
+				0x0864 0x00 0x0
+				0x08d4 0x54 0x0
+				0x08d8 0x07 0x0
+				0x08dc 0x0d 0x0
+				0x08e8 0x00 0x0
+				0x08ec 0x0e 0x0
+				0x08f0 0x4a 0x0
+				0x08f4 0x0f 0x0
+				0x08f8 0xc0 0x0
+				0x08fc 0x00 0x0
+				0x0910 0x17 0x0
+				0x0918 0x1c 0x0
+				0x091c 0x03 0x0
+				0x0924 0x1e 0x0
+				0x0970 0xff 0x0
+				0x0974 0xff 0x0
+				0x0978 0xff 0x0
+				0x097c 0x7f 0x0
+				0x0980 0x66 0x0
+				0x0984 0x24 0x0
+				0x0988 0xe4 0x0
+				0x098c 0xec 0x0
+				0x0990 0x3b 0x0
+				0x0994 0x36 0x0
+				0x0998 0xd4 0x0
+				0x099c 0x54 0x0
+				0x09a0 0xdb 0x0
+				0x09a4 0x3b 0x0
+				0x09a8 0x31 0x0
+				0x09bc 0x0c 0x0
+				0x0adc 0x05 0x0
+				0x0b88 0x88 0x0
+				0x0b98 0x0b 0x0
+				0x0ba4 0x01 0x0
+				0x0bec 0x01 0x0
+				0x0e0c 0x0d 0x0
+				0x0e14 0x07 0x0
+				0x0e1c 0xc1 0x0
+				0x0e40 0x01 0x0
+				0x0e48 0x01 0x0
+				0x0e90 0x00 0x0
+				0x0ebc 0x00 0x0
+				0x0ee0 0x58 0x0
+				0x0eb4 0x33 0x0
+				0x2a40 0x03 0x0
+				0x2010 0x00 0x0
+				0x201c 0x31 0x0
+				0x2020 0x01 0x0
+				0x2024 0xde 0x0
+				0x2028 0x07 0x0
+				0x2030 0x4c 0x0
+				0x2034 0x06 0x0
+				0x2048 0x90 0x0
+				0x2044 0x1c 0x0
+				0x2058 0x0f 0x0
+				0x2074 0x06 0x0
+				0x2078 0x06 0x0
+				0x207c 0x16 0x0
+				0x2080 0x16 0x0
+				0x2084 0x36 0x0
+				0x2088 0x36 0x0
+				0x2094 0x08 0x0
+				0x20a4 0x42 0x0
+				0x20ac 0x0a 0x0
+				0x20b0 0x1a 0x0
+				0x20b4 0x14 0x0
+				0x20b8 0x34 0x0
+				0x20bc 0x82 0x0
+				0x20c4 0x68 0x0
+				0x20cc 0x55 0x0
+				0x20d0 0x55 0x0
+				0x20d4 0x03 0x0
+				0x20d8 0xab 0x0
+				0x20dc 0xaa 0x0
+				0x20e0 0x02 0x0
+				0x210c 0x02 0x0
+				0x2110 0x24 0x0
+				0x2118 0xb4 0x0
+				0x211c 0x03 0x0
+				0x2154 0x34 0x0
+				0x2158 0x01 0x0
+				0x216c 0x08 0x0
+				0x21ac 0xb9 0x0
+				0x21b0 0x1e 0x0
+				0x21b4 0x94 0x0
+				0x21b8 0x18 0x0
+				0x21bc 0x11 0x0
+				0x2284 0x35 0x0
+				0x223c 0x11 0x0
+				0x229c 0x12 0x0
+				0x2408 0x0c 0x0
+				0x2414 0x03 0x0
+				0x2434 0x7f 0x0
+				0x2444 0x70 0x0
+				0x2460 0x30 0x0
+				0x2464 0x00 0x0
+				0x24d4 0x54 0x0
+				0x24d8 0x07 0x0
+				0x24dc 0x0d 0x0
+				0x24e8 0x00 0x0
+				0x24ec 0x0e 0x0
+				0x24f0 0x4a 0x0
+				0x24f4 0x0f 0x0
+				0x24f8 0xc0 0x0
+				0x24fc 0x00 0x0
+				0x2510 0x17 0x0
+				0x2518 0x1c 0x0
+				0x251c 0x03 0x0
+				0x2524 0x1e 0x0
+				0x2570 0xff 0x0
+				0x2574 0xff 0x0
+				0x2578 0xff 0x0
+				0x257c 0x7f 0x0
+				0x2580 0x66 0x0
+				0x2584 0x24 0x0
+				0x2588 0xe4 0x0
+				0x258c 0xec 0x0
+				0x2590 0x3b 0x0
+				0x2594 0x36 0x0
+				0x2598 0xd4 0x0
+				0x259c 0x54 0x0
+				0x25a0 0xdb 0x0
+				0x25a4 0x3b 0x0
+				0x25a8 0x31 0x0
+				0x25bc 0x0c 0x0
+				0x2684 0x35 0x0
+				0x263c 0x11 0x0
+				0x269c 0x12 0x0
+				0x2808 0x0c 0x0
+				0x2814 0x03 0x0
+				0x2834 0x7f 0x0
+				0x2844 0x70 0x0
+				0x2860 0x30 0x0
+				0x2864 0x00 0x0
+				0x28d4 0x54 0x0
+				0x28d8 0x07 0x0
+				0x28dc 0x0d 0x0
+				0x28e8 0x00 0x0
+				0x28ec 0x0e 0x0
+				0x28f0 0x4a 0x0
+				0x28f4 0x0f 0x0
+				0x28f8 0xc0 0x0
+				0x28fc 0x00 0x0
+				0x2910 0x17 0x0
+				0x2918 0x1c 0x0
+				0x291c 0x03 0x0
+				0x2924 0x1e 0x0
+				0x2970 0xff 0x0
+				0x2974 0xff 0x0
+				0x2978 0xff 0x0
+				0x297c 0x7f 0x0
+				0x2980 0x66 0x0
+				0x2984 0x24 0x0
+				0x2988 0xe4 0x0
+				0x298c 0xec 0x0
+				0x2990 0x3b 0x0
+				0x2994 0x36 0x0
+				0x2998 0xd4 0x0
+				0x299c 0x54 0x0
+				0x29a0 0xdb 0x0
+				0x29a4 0x3b 0x0
+				0x29a8 0x31 0x0
+				0x29bc 0x0c 0x0
+				0x2adc 0x05 0x0
+				0x2b88 0x88 0x0
+				0x2b98 0x0b 0x0
+				0x2ba4 0x01 0x0
+				0x2bec 0x01 0x0
+				0x2e0c 0x0d 0x0
+				0x2e14 0x07 0x0
+				0x2e1c 0xc1 0x0
+				0x2e40 0x01 0x0
+				0x2e48 0x01 0x0
+				0x2e90 0x00 0x0
+				0x2ebc 0x00 0x0
+				0x2ee0 0x58 0x0
+				0x2eb4 0x33 0x0
+				0x0a00 0x00 0x0
+				0x0a44 0x03 0x0>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie3_clkreq_default
+			&pcie3_perst_default
+			&pcie3_wake_default>;
+
+		perst-gpio = <&tlmm 178 0>;
+		wake-gpio = <&tlmm 56 0>;
+
+		gdsc-core-vdd-supply = <&pcie_3_gdsc>;
+		vreg-1p2-supply = <&pm8195_1_l9>;
+		vreg-0p9-supply = <&pm8195_3_l5>;
+		vreg-cx-supply = <&VDD_CX_LEVEL>;
+
+		qcom,vreg-1p2-voltage-level = <1200000 1200000 24000>;
+		qcom,vreg-0p9-voltage-level = <880000 880000 24000>;
+		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+						RPMH_REGULATOR_LEVEL_NOM 0>;
+
+		msi-parent = <&pcie3_msi>;
+
+		qcom,no-l0s-supported;
+
+		qcom,ep-latency = <10>;
+
+		qcom,slv-addr-space-size = <0x20000000>;
+
+		qcom,phy-status-offset = <0xa14>;
+		qcom,phy-status-bit = <6>;
+		qcom,phy-power-down-offset = <0xa40>;
+
+		qcom,boot-option = <0x1>;
+
+		linux,pci-domain = <3>;
+
+		qcom,pcie-phy-ver = <2105>;
+		qcom,use-19p2mhz-aux-clk;
+
+		qcom,smmu-sid-base = <0x1e00>;
+
+		iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
+			<0x100 &apps_smmu 0x1e01 0x1>,
+			<0x200 &apps_smmu 0x1e02 0x1>,
+			<0x300 &apps_smmu 0x1e03 0x1>,
+			<0x400 &apps_smmu 0x1e04 0x1>,
+			<0x500 &apps_smmu 0x1e05 0x1>,
+			<0x600 &apps_smmu 0x1e06 0x1>,
+			<0x700 &apps_smmu 0x1e07 0x1>,
+			<0x800 &apps_smmu 0x1e08 0x1>,
+			<0x900 &apps_smmu 0x1e09 0x1>,
+			<0xa00 &apps_smmu 0x1e0a 0x1>,
+			<0xb00 &apps_smmu 0x1e0b 0x1>,
+			<0xc00 &apps_smmu 0x1e0c 0x1>,
+			<0xd00 &apps_smmu 0x1e0d 0x1>,
+			<0xe00 &apps_smmu 0x1e0e 0x1>,
+			<0xf00 &apps_smmu 0x1e0f 0x1>;
+
+		clocks = <&gcc GCC_PCIE_3_PIPE_CLK>,
+			<&dummycc RPMH_CXO_CLK>,
+			<&gcc GCC_PCIE_3_AUX_CLK>,
+			<&gcc GCC_PCIE_3_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
+			<&gcc GCC_PCIE_3_SLV_AXI_CLK>,
+			<&gcc GCC_PCIE_3_CLKREF_CLK>,
+			<&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
+			<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+			<&gcc GCC_PCIE3_PHY_REFGEN_CLK>,
+			<&gcc GCC_PCIE_PHY_AUX_CLK>;
+
+		clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
+				"pcie_3_aux_clk", "pcie_3_cfg_ahb_clk",
+				"pcie_3_mstr_axi_clk", "pcie_3_slv_axi_clk",
+				"pcie_ldo", "pcie_3_slv_q2a_axi_clk",
+				"pcie_tbu_clk", "pcie_phy_refgen_clk",
+				"pcie_phy_aux_clk";
+
+		clock-frequency = <0>, <0>, <19200000>, <0>, <0>,
+					<0>, <0>, <0>, <0>, <100000000>, <0>;
+
+		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>,
+						 <0>, <0>, <0>, <0>;
+
+		resets = <&gcc GCC_PCIE_3_BCR>,
+			<&gcc GCC_PCIE_3_PHY_BCR>;
+
+		reset-names = "pcie_3_core_reset",
+				"pcie_3_phy_reset";
+
+		status = "disabled";
+
+		pcie_rc3: pcie_rc3 {
+			reg = <0 0 0 0 0>;
+			pci-ids = "17cb:0109";
+		};
+	};
+
+	pcie3_msi: qcom,pcie3_msi@17a00040 {
+		compatible = "qcom,pci-msi";
+		msi-controller;
+		reg = <0x17a00040 0x0>;
+		interrupts = <GIC_SPI 800 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 801 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 802 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 803 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 804 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 805 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 806 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 807 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 808 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 809 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 810 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 811 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 812 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 813 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 814 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 815 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 816 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 817 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 818 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 819 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 820 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 821 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 822 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 823 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 824 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 825 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 826 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 827 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 828 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 829 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 830 IRQ_TYPE_EDGE_RISING>,
+			<GIC_SPI 831 IRQ_TYPE_EDGE_RISING>;
+		status = "disabled";
+	};
+};
+
diff --git a/qcom/sa8195-vm-qupv3.dtsi b/qcom/sa8195-vm-qupv3.dtsi
new file mode 100755
index 00000000..4f1f384c
--- /dev/null
+++ b/qcom/sa8195-vm-qupv3.dtsi
@@ -0,0 +1,62 @@
+&soc {
+	/* QUPv3 SE Instances
+	 * Qup0 0: SE 0
+	 * Qup0 1: SE 1
+	 * Qup0 2: SE 2
+	 * Qup0 3: SE 3
+	 * Qup0 4: SE 4
+	 * Qup0 5: SE 5
+	 * Qup0 6: SE 6
+	 * Qup0 7: SE 7
+	 * Qup1 0: SE 8
+	 * Qup1 1: SE 9
+	 * Qup1 2: SE 10
+	 * Qup1 3: SE 11
+	 * Qup1 4: SE 12
+	 * Qup1 5: SE 13
+	 * Qup2 0: SE 14
+	 * Qup2 1: SE 15
+	 * Qup2 2: SE 16
+	 * Qup2 3: SE 17
+	 * Qup2 4: SE 18
+	 * Qup2 5: SE 19
+	 */
+
+	/* QUPv3_2  wrapper  instance */
+	qupv3_2: qcom,qupv3_2_geni_se@cc0000 {
+		compatible = "qcom,geni-se-qup";
+		reg = <0xcc0000 0x6000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		clock-names = "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		iommus = <&apps_smmu 0x7a3  0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		status = "ok";
+
+		/* HS UART Instance */
+		qupv3_se17_4uart: qcom,qup_uart@c8c000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0xc8c000 0x4000>;
+			reg-names = "se_phys";
+			interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
+					<&tlmm 46 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+			pinctrl-names = "default", "active", "sleep", "shutdown";
+			pinctrl-0 = <&qupv3_se17_default_ctsrtsrx>,
+						<&qupv3_se17_default_tx>;
+			pinctrl-1 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
+			<&qupv3_se17_tx>;
+			pinctrl-2 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
+			<&qupv3_se17_tx>;
+			pinctrl-3 = <&qupv3_se17_default_ctsrtsrx>,<&qupv3_se17_default_tx>;
+			qcom,wakeup-byte = <0xFD>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/qcom/sa8195-vm-usb.dtsi b/qcom/sa8195-vm-usb.dtsi
new file mode 100755
index 00000000..8bd6b9e9
--- /dev/null
+++ b/qcom/sa8195-vm-usb.dtsi
@@ -0,0 +1,167 @@
+#include <dt-bindings/phy/qcom,sm8150-qmp-usb3.h>
+
+&soc {
+	/* Primary USB port related controller */
+	usb0: ssusb@a600000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0x0a600000 0x100000>;
+		reg-names = "core_base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
+				<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+				<&pdc 8 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+				"dm_hs_phy_irq";
+		qcom,use-pdc-interrupts;
+
+		USB3_GDSC-supply = <&usb30_prim_gdsc>;
+		clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+			<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+			<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+			<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+			<&dummycc RPMH_CXO_CLK>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+					"utmi_clk", "sleep_clk", "xo";
+
+		resets = <&gcc GCC_USB30_PRIM_BCR>;
+		reset-names = "core_reset";
+
+		qcom,core-clk-rate = <200000000>;
+		qcom,core-clk-rate-hs = <66666667>;
+		qcom,host-poweroff-in-pm-suspend;
+
+		status = "disabled";
+		dwc3@a600000 {
+			compatible = "snps,dwc3";
+			reg = <0x0a600000 0xcd00>;
+			iommus = <&apps_smmu 0x140 0x0>;
+			qcom,iommu-dma = "atomic";
+			qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
+			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+			usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
+			snps,disable-clk-gating;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,is-utmi-l1-suspend;
+			snps,usb2-gadget-lpm-disable;
+			tx-fifo-resize;
+			maximum-speed = "high-speed";
+			dr_mode = "otg";
+			usb-role-switch;
+		};
+	};
+
+	/* Primary USB port related High Speed PHY */
+	usb2_phy0: hsphy@88e2000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x88e2000 0x110>,
+			<0x007801f8 0x4>;
+		reg-names = "hsusb_phy_base",
+			"phy_rcal_reg";
+
+		vdd-supply = <&L5E>;
+		vdda18-supply = <&L12A>;
+		vdda33-supply = <&L16E>;
+		qcom,vdd-voltage-level = <0 880000 880000>;
+
+		clocks = <&dummycc RPMH_CXO_CLK>;
+		clock-names = "ref_clk_src";
+
+		resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+		reset-names = "phy_reset";
+		qcom,param-override-seq = <0x43 0x70>;
+		qcom,rcal-mask = <0x1e00000>;
+
+		status = "disabled";
+	};
+
+	usb_nop_phy: usb_nop_phy {
+		compatible = "usb-nop-xceiv";
+	};
+
+	/* Secondary USB port related controller */
+	usb1: ssusb@a800000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0x0a800000 0x100000>;
+		reg-names = "core_base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		interrupts-extended = <&pdc 11 IRQ_TYPE_EDGE_RISING>,
+				<&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+				<&pdc 10 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+				"dm_hs_phy_irq";
+		qcom,use-pdc-interrupts;
+
+		qcom,default-mode-host;
+		qcom,host-poweroff-in-pm-suspend;
+
+		USB3_GDSC-supply = <&usb30_sec_gdsc>;
+		clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
+			<&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+			<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+			<&gcc GCC_USB30_SEC_SLEEP_CLK>,
+			<&dummycc RPMH_CXO_CLK>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+					"utmi_clk", "sleep_clk", "xo";
+
+		resets = <&gcc GCC_USB30_SEC_BCR>;
+		reset-names = "core_reset";
+
+		qcom,core-clk-rate = <200000000>;
+		qcom,core-clk-rate-hs = <66666667>;
+
+		status = "disabled";
+		dwc3@a800000 {
+			compatible = "snps,dwc3";
+			reg = <0x0a800000 0xcd00>;
+			iommus = <&apps_smmu 0x160 0x0>;
+			qcom,iommu-dma = "atomic";
+			qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
+			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			usb-phy = <&usb2_phy1>, <&usb_nop_phy>;
+			snps,disable-clk-gating;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,is-utmi-l1-suspend;
+			snps,usb2-gadget-lpm-disable;
+			tx-fifo-resize;
+			maximum-speed = "high-speed";
+			dr_mode = "otg";
+			usb-role-switch;
+		};
+	};
+
+	/* Secondary USB port related High Speed PHY */
+	usb2_phy1: hsphy@88e3000 {
+		compatible = "qcom,usb-hsphy-snps-femto";
+		reg = <0x88e3000 0x110>,
+			<0x007801f8 0x4>;
+		reg-names = "hsusb_phy_base",
+			"phy_rcal_reg";
+
+		vdd-supply = <&L5E>;
+		vdda18-supply = <&L12A>;
+		vdda33-supply = <&L16E>;
+		qcom,vdd-voltage-level = <0 880000 880000>;
+
+		clocks = <&dummycc RPMH_CXO_CLK>;
+		clock-names = "ref_clk_src";
+
+		resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+		reset-names = "phy_reset";
+		qcom,param-override-seq = <0x43 0x70>;
+		qcom,rcal-mask = <0x1e00000>;
+
+		status = "disabled";
+	};
+};
diff --git a/qcom/sa8195-vm.dtsi b/qcom/sa8195-vm.dtsi
index 98ccd3f9..69853b52 100755
--- a/qcom/sa8195-vm.dtsi
+++ b/qcom/sa8195-vm.dtsi
@@ -1,7 +1,413 @@
+#include <dt-bindings/clock/qcom,gcc-sc8180x.h>
 #include "quin-vm-common.dtsi"
+#include "pm8195-vm.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. SA8195 Virtual Machine";
 	qcom,msm-name = "SA8195P";
 	qcom,msm-id = <405 0x20000>;
+	aliases {
+		hsuart0 = &qupv3_se17_4uart;
+	};
+};
+
+&soc {
+	/* Rome 3.3V supply */
+	vreg_wlan: vreg_wlan {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "vreg_wlan";
+	};
+
+	/* PWR_CTR2_VDD_1P8 supply */
+	vreg_conn_1p8: vreg_conn_1p8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vreg_conn_1p8";
+		pinctrl-names = "default";
+		pinctrl-0 = <&conn_power_1p8_active>;
+		startup-delay-us = <4000>;
+		enable-active-high;
+		gpio = <&tlmm 173 0>;
+	};
+
+	/* PWR_CTR1_VDD_PA supply */
+	vreg_conn_pa: vreg_conn_pa {
+		compatible = "regulator-fixed";
+		regulator-name = "vreg_conn_pa";
+		pinctrl-names = "default";
+		pinctrl-0 = <&conn_power_pa_active>;
+		startup-delay-us = <4000>;
+		enable-active-high;
+		gpio = <&tlmm 174 0>;
+	};
+
+	apps_smmu: apps-smmu@15000000 {
+		compatible = "qcom,qsmmu-v500";
+		reg = <0x15000000 0x100000>,
+			<0x15182000 0x20>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,skip-init;
+		qcom,use-3-lvl-tables;
+		qcom,handoff-smrs = <0xffff 0x0>;
+		qcom,multi-match-handoff-smr;
+		#global-interrupts = <1>;
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		interrupts =	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	dma_dev@0x0 {
+		compatible = "qcom,iommu-dma";
+		memory-region = <&system_cma>;
+	};
+
+	qtee_shmbridge {
+		compatible = "qcom,tee-shared-memory-bridge";
+	};
+
+	qcom_qseecom: qseecom@87a00000 {
+		compatible = "qcom,qseecom";
+		reg = <0x87a00000 0x2100000>;
+		reg-names = "secapp-region";
+		memory-region = <&qseecom_mem>;
+		qcom,hlos-num-ce-hw-instances = <1>;
+		qcom,hlos-ce-hw-instance = <0>;
+		qcom,qsee-ce-hw-instance = <0>;
+		qcom,disk-encrypt-pipe-pair = <2>;
+		qcom,no-clock-support;
+		qcom,qsee-reentrancy-support = <2>;
+	};
+
+	qcom_rng: qrng@793000 {
+		compatible = "qcom,msm-rng";
+		reg = <0x793000 0x1000>;
+		qcom,no-qrng-config;
+		clocks = <&gcc GCC_PRNG_AHB_CLK>;
+		clock-names = "km_clk_src";
+	};
+
+	pdc: interrupt-controller@b220000 {
+		compatible = "qcom,pdc";
+		reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
+		qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&intc>;
+		interrupt-controller;
+	};
+
+	VDD_CX_LEVEL:
+	S3E_LEVEL: pm8195_3_s3_level: regulator-pm8195-3-s3-level {
+		compatible = "qcom,stub-regulator";
+		regulator-name = "pm8195_3_s3_level";
+		regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+		regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+	};
+};
+
+&firmware {
+	scm {
+		compatible = "qcom,scm";
+	};
+};
+
+#include "sdmshrike-pinctrl.dtsi"
+#include "sa8195-vm-qupv3.dtsi"
+#include "sa8195-vm-usb.dtsi"
+#include "sa8195-vm-pcie.dtsi"
+
+&tlmm {
+	/delete-property/ wakeup-parent;
+};
+
+&regulator {
+	usb30_prim_gdsc: usb30_prim_gdsc {
+		regulator-name = "usb30_prim_gdsc";
+	};
+
+	usb30_sec_gdsc: usb30_sec_gdsc {
+		regulator-name = "usb30_sec_gdsc";
+	};
+
+	usb30_mp_gdsc: qcom,gdsc@1a6004 {
+		regulator-name = "usb30_mp_gdsc";
+	};
+
+	ufs_card_2_gdsc: ufs_card_2_gdsc {
+		regulator-name = "ufs_card_2_gdsc";
+	};
+
+	pcie_0_gdsc: pcie_0_gdsc {
+		regulator-name = "pcie_0_gdsc";
+	};
+
+	pcie_1_gdsc: pcie_1_gdsc {
+		regulator-name = "pcie_1_gdsc";
+	};
+
+	pcie_2_gdsc: pcie_2_gdsc {
+		regulator-name = "pcie_2_gdsc";
+	};
+
+	pcie_3_gdsc: pcie_3_gdsc {
+		regulator-name = "pcie_3_gdsc";
+	};
+
+	L2A: pm8195_1_l2: regulator-pm8195-1-l2 {
+		regulator-name = "ldoa2";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	L9A: pm8195_1_l9: regulator-pm8195-1-l9 {
+		regulator-name = "ldoa9";
+		regulator-min-microvolt = <1150000>;
+		regulator-max-microvolt = <1250000>;
+		regulator-allow-set-load;
+	};
+
+	L10A: pm8195_1_l10: regulator-pm8195-1-l10 {
+		regulator-name = "ldoa10";
+		regulator-min-microvolt = <2700000>;
+		regulator-max-microvolt = <3544000>;
+	};
+
+	L12A: pm8195_1_l12: regulator-pm8195-1-l12 {
+		regulator-name = "ldoa12";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1890000>;
+	};
+
+	L7C: pm8195_2_l7: regulator-pm8195-2-l7 {
+		regulator-name = "ldoc7";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <2040000>;
+	};
+
+	L5E: pm8195_3_l5: regulator-pm8195-3-l5 {
+		regulator-name = "ldoe5";
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <920000>;
+		regulator-allow-set-load;
+	};
+
+	L9E: pm8195_3_l9: regulator-pm8195-3-l9 {
+		regulator-name = "ldoe9";
+		regulator-min-microvolt = <830000>;
+		regulator-max-microvolt = <920000>;
+	};
+
+	L16E: pm8195_3_l16: regulator-pm8195-3-l16 {
+		regulator-name = "ldoe16";
+		regulator-min-microvolt = <2921000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	S2A: pm8195_1_s2: regulator-pm8195-1-s2 {
+		regulator-name = "smpa2";
+		regulator-min-microvolt = <1179000>;
+		regulator-max-microvolt = <1379000>;
+	};
+
+	S5A: pm8195_1_s5: regulator-pm8195-1-s5 {
+		regulator-name = "smpa5";
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <1000000>;
+	};
+
+	S5C: pm8195_2_s5: regulator-pm8195-2-s5 {
+		regulator-name = "smpc5";
+		regulator-min-microvolt = <1713000>;
+		regulator-max-microvolt = <2040000>;
+	};
+};
+
+&soc {
+	tcsr_compute_signal_glb: syscon@0x1fd8000 {
+		compatible = "syscon";
+		reg = <0x1fd8000 0x1000>;
+	};
+
+	tcsr_compute_signal_sender0: syscon@0x1fd9000 {
+		compatible = "syscon";
+		reg = <0x1fd9000 0x1000>;
+	};
+
+	tcsr_compute_signal_sender1: syscon@0x1fdd000 {
+		compatible = "syscon";
+		reg = <0x1fdd000 0x1000>;
+	};
+
+	tcsr_compute_signal_receiver0: syscon@0x1fdb000 {
+		compatible = "syscon";
+		reg = <0x1fdb000 0x1000>;
+	};
+
+	tcsr_compute_signal_receiver1: syscon@0x1fdf000 {
+		compatible = "syscon";
+		reg = <0x1fdf000 0x1000>;
+	};
+
+	hgsl_tcsr_sender0: hgsl_tcsr_sender0 {
+		compatible = "qcom,hgsl-tcsr-sender";
+		syscon = <&tcsr_compute_signal_sender0>;
+		syscon-glb = <&tcsr_compute_signal_glb>;
+	};
+
+	hgsl_tcsr_sender1: hgsl_tcsr_sender1 {
+		compatible = "qcom,hgsl-tcsr-sender";
+		syscon = <&tcsr_compute_signal_sender1>;
+		syscon-glb = <&tcsr_compute_signal_glb>;
+	};
+
+	hgsl_tcsr_receiver0: hgsl_tcsr_receiver0 {
+		compatible = "qcom,hgsl-tcsr-receiver";
+		syscon = <&tcsr_compute_signal_receiver0>;
+		interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	hgsl_tcsr_receiver1: hgsl_tcsr_receiver1 {
+		compatible = "qcom,hgsl-tcsr-receiver";
+		syscon = <&tcsr_compute_signal_receiver1>;
+		interrupts = <0 239 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	msm_gpu_hyp: qcom,hgsl@0x2c00000 {
+		compatible = "qcom,hgsl";
+		reg = <0x2c00000 0x8>, <0x2c8f000 0x4>;
+		reg-names = "hgsl_reg_hwinf", "hgsl_reg_gmucx";
+
+		qcom,glb-db-senders = <&hgsl_tcsr_sender0
+					&hgsl_tcsr_sender1>;
+		qcom,glb-db-receivers = <&hgsl_tcsr_receiver0
+					&hgsl_tcsr_receiver1>;
+	};
 };
diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi
index fb46d767..89b1509d 100755
--- a/qcom/sa8195p.dtsi
+++ b/qcom/sa8195p.dtsi
@@ -171,7 +171,6 @@
 	vcc-max-microamp = <750000>;
 	vccq-max-microamp = <750000>;
 	vccq2-max-microamp = <750000>;
-	qcom,disable-lpm;
 
 	qcom,vddp-ref-clk-supply = <&pm8195_2_l5>;
 	qcom,vddp-ref-clk-max-microamp = <100>;
diff --git a/qcom/sdmshrike-dma-heaps.dtsi b/qcom/sdmshrike-dma-heaps.dtsi
index a8e48717..e873e73a 100755
--- a/qcom/sdmshrike-dma-heaps.dtsi
+++ b/qcom/sdmshrike-dma-heaps.dtsi
@@ -24,8 +24,9 @@
 
 		qcom,qseecom {
 			qcom,dma-heap-name = "qcom,qseecom";
-			qcom,dma-heap-type = <HEAP_TYPE_CARVEOUT>;
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
 			memory-region = <&qseecom_mem>;
+			qcom,uncached-heap;
 		};
 
 		qcom,qseecom_ta {
diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi
index 59710463..3180dd22 100755
--- a/qcom/sdmshrike.dtsi
+++ b/qcom/sdmshrike.dtsi
@@ -403,11 +403,6 @@
 			reg = <0x0 0x8b700000 0x0 0x500000>;
 		};
 
-		pil_wlan_fw_mem: pil_wlan_fw_region@8bc00000 {
-			no-map;
-			reg = <0x0 0x8bc00000 0x0 0x180000>;
-		};
-
 		pil_npu_mem: pil_npu_region@8bd80000 {
 			no-map;
 			reg = <0x0 0x8bd80000 0x0 0x80000>;
@@ -1449,7 +1444,7 @@
 		memory-region = <&rproc_adsp_mem>;
 
 		/* Inputs from ssc */
-		interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+		interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 					<&adsp_smp2p_in 0 0>,
 					<&adsp_smp2p_in 2 0>,
 					<&adsp_smp2p_in 1 0>,
@@ -1783,6 +1778,7 @@
 
 	qtee_shmbridge {
 		compatible = "qcom,tee-shared-memory-bridge";
+		qcom,disable-shmbridge-support;
 	};
 
 	qcom_qseecom: qseecom@87900000 {
@@ -1802,6 +1798,49 @@
 		qcom,qsee-reentrancy-support = <2>;
 	};
 
+	qcom_cedev: qcedev@1de0000 {
+		compatible = "qcom,qcedev";
+		reg = <0x1de0000 0x20000>,
+			<0x1dc4000 0x28000>;
+		reg-names = "crypto-base","crypto-bam-base";
+		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,bam-pipe-pair = <2>;
+		qcom,ce-hw-instance = <0>;
+		qcom,ce-device = <0>;
+		qcom,ce-hw-shared;
+		qcom,bam-ee = <0>;
+		qcom,smmu-s1-enable;
+		qcom,no-clock-support;
+		interconnect-names = "data_path";
+		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
+		iommus = <&apps_smmu 0x0512 0x0000>,
+			<&apps_smmu 0x051C 0x0005>,
+			<&apps_smmu 0x051D 0x0005>,
+			<&apps_smmu 0x051F 0x0000>;
+		qcom,iommu-dma = "atomic";
+		dma-coherent;
+
+		qcom_cedev_ns_cb {
+			compatible = "qcom,qcedev,context-bank";
+			label = "ns_context";
+			iommus = <&apps_smmu 0x0504 0x0013>,
+				<&apps_smmu 0x0508 0x0001>,
+				<&apps_smmu 0x0514 0x0013>,
+				<&apps_smmu 0x0518 0x0005>;
+			dma-coherent;
+		};
+
+		qcom_cedev_s_cb {
+			compatible = "qcom,qcedev,context-bank";
+			label = "secure_context";
+			iommus = <&apps_smmu 0x0513 0x0000>,
+				<&apps_smmu 0x051E 0x0000>;
+			qcom,iommu-vmid = <0x9>;
+			qcom,secure-context-bank;
+			dma-coherent;
+		};
+	};
+
 	qcom_rng: qrng@793000 {
 		compatible = "qcom,msm-rng";
 		reg = <0x793000 0x1000>;
@@ -1970,6 +2009,8 @@
 			dma-coherent;
 		};
 	};
+
+	msm_gpu: qcom,kgsl-3d0@2c00000 { };
 };
 
 &firmware {
diff --git a/qcom/sdxbaagha-pcie.dtsi b/qcom/sdxbaagha-pcie.dtsi
index b50fea61..d39e9848 100755
--- a/qcom/sdxbaagha-pcie.dtsi
+++ b/qcom/sdxbaagha-pcie.dtsi
@@ -47,7 +47,7 @@
 			&pcie0_perst_default
 			&pcie0_wake_default>;
 
-		gdsc-vdd-supply = <&gcc_pcie_gdsc>;
+		gdsc-core-vdd-supply = <&gcc_pcie_gdsc>;
 
 		vreg-1p2-supply = <&L14A>;
 		vreg-0p9-supply = <&L3A>;
@@ -70,7 +70,7 @@
 				100000000>;
 
 		interconnect-names = "icc_path";
-		//interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
+		interconnects = <&pcie_anoc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
 
 		clocks = <&gcc GCC_PCIE_PIPE_CLK>,
 			<&rpmhcc RPMH_CXO_CLK>,
@@ -106,7 +106,8 @@
 		iommu-map = <0x0 &apps_smmu 0x0400 0x1>,
 			<0x100 &apps_smmu 0x0401 0x1>;
 
-		qcom,target-link-speed = <1>;
+		qcom,target-link-speed = <2>;
+		qcom,boot-option = <0x1>;
 		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
 		qcom,tpwr-on-scale = <1>;
 		qcom,tpwr-on-value = <9>;
diff --git a/qcom/sdxbaagha-pinctrl.dtsi b/qcom/sdxbaagha-pinctrl.dtsi
index 2b9c9bb2..670aeac4 100755
--- a/qcom/sdxbaagha-pinctrl.dtsi
+++ b/qcom/sdxbaagha-pinctrl.dtsi
@@ -19,7 +19,7 @@
 
 				config {
 					pins = "gpio8";
-					drive-strength= <2>;
+					drive-strength = <2>;
 					bias-disable;
 				};
 			};
@@ -32,7 +32,7 @@
 
 				config {
 					pins = "gpio9";
-					drive-strength= <2>;
+					drive-strength = <2>;
 					bias-disable;
 				};
 			};
@@ -51,6 +51,374 @@
 			};
 		};
 
+		qupv3_se0_2uart_pins: qupv3_se0_2uart_pins {
+			qupv3_se0_2uart_tx_active: qupv3_se0_2uart_tx_active {
+				mux {
+					pins = "gpio48";
+					function = "qup0_se0_l2";
+				};
+
+				config {
+					pins = "gpio48";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se0_2uart_rx_active: qupv3_se0_2uart_rx_active {
+				mux {
+					pins = "gpio49";
+					function = "qup0_se0_l3";
+				};
+
+				config {
+					pins = "gpio49";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se0_2uart_sleep: qupv3_se0_2uart_sleep {
+				mux {
+					pins = "gpio48", "gpio49";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio48", "gpio49";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+		};
+
+		qupv3_se1_4uart_pins: qupv3_se1_4uart_pins {
+			qupv3_se1_default_cts: qupv3_se1_default_cts {
+				mux {
+					pins = "gpio65";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio65";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se1_default_rts: qupv3_se1_default_rts {
+				mux {
+					pins = "gpio66";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio66";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+
+			qupv3_se1_default_tx: qupv3_se1_default_tx {
+				mux {
+					pins = "gpio63";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio63";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qupv3_se1_default_rx: qupv3_se1_default_rx {
+				mux {
+					pins = "gpio64";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio64";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+
+			qupv3_se1_cts: qupv3_se1_cts {
+				mux {
+					pins = "gpio65";
+					function = "qup0_se1_l0";
+				};
+
+				config {
+					pins = "gpio65";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se1_rts: qupv3_se1_rts {
+				mux {
+					pins = "gpio66";
+					function = "qup0_se1_l1";
+				};
+
+				config {
+					pins = "gpio66";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+
+			qupv3_se1_tx: qupv3_se1_tx {
+				mux {
+					pins = "gpio63";
+					function = "qup0_se1_l2";
+				};
+
+				config {
+					pins = "gpio63";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qupv3_se1_rx: qupv3_se1_rx {
+				mux {
+					pins = "gpio64";
+					function = "qup0_se1_l3";
+				};
+
+				config {
+					pins = "gpio64";
+					drive-strength = <2>;
+					bias-disable;
+				};
+			};
+		};
+
+		qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
+			qupv3_se2_i2c_sda_active: qupv3_se2_i2c_sda_active {
+				mux {
+					pins = "gpio5";
+					function = "qup0_se2_l0";
+				};
+
+				config {
+					pins = "gpio5";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qupv3_se2_i2c_scl_active: qupv3_se2_i2c_scl_active {
+				mux {
+					pins = "gpio4";
+					function = "qup0_se2_l1";
+				};
+
+				config {
+					pins = "gpio4";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
+				mux {
+					pins = "gpio5", "gpio4";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio5", "gpio4";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+		};
+
+		qupv3_se2_spi_pins: qupv3_se2_spi_pins {
+			qupv3_se2_spi_miso_active: qupv3_se2_spi_miso_active {
+				mux {
+					pins = "gpio5";
+					function = "qup0_se2_l0";
+				};
+
+				config {
+					pins = "gpio5";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se2_spi_mosi_active: qupv3_se2_spi_mosi_active {
+				mux {
+					pins = "gpio4";
+					function = "qup0_se2_l1";
+				};
+
+				config {
+					pins = "gpio4";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se2_spi_clk_active: qupv3_se2_spi_clk_active {
+				mux {
+					pins = "gpio7";
+					function = "qup0_se2_l2";
+				};
+
+				config {
+					pins = "gpio7";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se2_spi_cs_active: qupv3_se2_spi_cs_active {
+				mux {
+					pins = "gpio6";
+					function = "qup0_se2_l3";
+				};
+
+				config {
+					pins = "gpio6";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
+				mux {
+					pins = "gpio5", "gpio4",
+						"gpio7", "gpio6";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio5", "gpio4",
+						"gpio7", "gpio6";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+		};
+
+		qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
+			qupv3_se4_i2c_sda_active: qupv3_se4_i2c_sda_active {
+				mux {
+					pins = "gpio10";
+					function = "qup0_se4_l0";
+				};
+
+				config {
+					pins = "gpio10";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qupv3_se4_i2c_scl_active: qupv3_se4_i2c_scl_active {
+				mux {
+					pins = "gpio11";
+					function = "qup0_se4_l1";
+				};
+
+				config {
+					pins = "gpio11";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
+			};
+
+			qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
+				mux {
+					pins = "gpio10", "gpio11";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio10", "gpio11";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+		};
+
+		qupv3_se4_spi_pins: qupv3_se4_spi_pins {
+			qupv3_se4_spi_miso_active: qupv3_se4_spi_miso_active {
+				mux {
+					pins = "gpio10";
+					function = "qup0_se4_l0";
+				};
+
+				config {
+					pins = "gpio10";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se4_spi_mosi_active: qupv3_se4_spi_mosi_active {
+				mux {
+					pins = "gpio11";
+					function = "qup0_se4_l1";
+				};
+
+				config {
+					pins = "gpio11";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se4_spi_clk_active: qupv3_se4_spi_clk_active {
+				mux {
+					pins = "gpio80";
+					function = "qup0_se4_l2";
+				};
+
+				config {
+					pins = "gpio80";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se4_spi_cs_active: qupv3_se4_spi_cs_active {
+				mux {
+					pins = "gpio81";
+					function = "qup0_se4_l3";
+				};
+
+				config {
+					pins = "gpio81";
+					drive-strength = <6>;
+					bias-disable;
+				};
+			};
+
+			qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
+				mux {
+					pins = "gpio10", "gpio11",
+						"gpio80", "gpio81";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio10", "gpio11",
+						"gpio80", "gpio81";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+		};
+
+
 		pcie_ep {
 			pcie_ep_clkreq_default: pcie_ep_clkreq_default {
 				mux {
@@ -92,59 +460,59 @@
 				};
 			};
 		};
-	};
-pcie0 {
-		pcie0_perst_default: pcie0_perst_default {
-			mux {
-				pins = "gpio57";
-				function = "gpio";
-			};
 
-			config {
-				pins = "gpio57";
-				drive-strength = <2>;
-				bias-pull-down;
-			};
-		};
+		pcie0 {
+			pcie0_perst_default: pcie0_perst_default {
+				mux {
+					pins = "gpio57";
+					function = "gpio";
+				};
 
-		pcie0_clkreq_default: pcie0_clkreq_default {
-			mux {
-				pins = "gpio56";
-				function = "pcie0_clkreq_n";
+				config {
+					pins = "gpio57";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
 			};
 
-			config {
-				pins = "gpio56";
-				drive-strength = <2>;
-				bias-pull-up;
-			};
-		};
+			pcie0_clkreq_default: pcie0_clkreq_default {
+				mux {
+					pins = "gpio56";
+					function = "pcie0_clkreq_n";
+				};
 
-		pcie0_wake_default: pcie0_wake_default {
-			mux {
-				pins = "gpio53";
-				function = "gpio";
+				config {
+					pins = "gpio56";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
 			};
 
-			config {
-				pins = "gpio53";
-				drive-strength = <2>;
-				bias-pull-up;
-			};
-		};
+			pcie0_wake_default: pcie0_wake_default {
+				mux {
+					pins = "gpio53";
+					function = "gpio";
+				};
 
-		pcie0_clkreq_sleep: pcie0_clkreq_sleep {
-			mux {
-				pins = "gpio56";
-				function = "gpio";
+				config {
+					pins = "gpio53";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
 			};
 
-			config {
-				pins = "gpio56";
-				drive-strength = <2>;
-				bias-pull-up;
+			pcie0_clkreq_sleep: pcie0_clkreq_sleep {
+				mux {
+					pins = "gpio56";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio56";
+					drive-strength = <2>;
+					bias-pull-up;
+				};
 			};
 		};
 	};
-
 };
diff --git a/qcom/sdxbaagha-pmic-overlay.dtsi b/qcom/sdxbaagha-pmic-overlay.dtsi
new file mode 100755
index 00000000..1a54923c
--- /dev/null
+++ b/qcom/sdxbaagha-pmic-overlay.dtsi
@@ -0,0 +1,196 @@
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include "pmx35.dtsi"
+
+&pmx35_gpios {
+	smb_int {
+		smb_int_default: smb_int_default {
+			pins = "gpio7";
+			function = "normal";
+			input-enable;
+			bias-pull-up;
+			qcom,pull-up-strength = <PMIC_GPIO_PULL_UP_30>;
+			power-source = <0>;
+		};
+	};
+
+	batt_id {
+		batt_id_default: batt_id_default {
+			pins = "gpio6";
+			bias-high-impedance;
+		};
+	};
+};
+
+&qupv3_se4_i2c {
+	smb23x-lbc@24 {
+		compatible = "qcom,smb231-lbc";
+		reg = <0x24>;
+		interrupt-parent = <&pmx35_gpios>;
+		interrupts = <&pmx35_gpios 7 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&smb_int_default>;
+		#io-channel-cells = <1>;
+		io-channels = <&pmx35_vadc PMX35_ADC5_GEN3_AMUX3_GPIO6_100K_PU>;
+		io-channel-names = "batt-id";
+
+		qcom,bms-psy-name = "bms";
+		qcom,float-voltage-mv = <4350>;
+		qcom,charging-timeout = <360>;
+		qcom,recharge-thresh-mv = <150>;
+		qcom,iterm-ma = <50>;
+		qcom,fastchg-ma = <1000>;
+		qcom,hot-bat-decidegc = <450>;
+		qcom,warm-bat-decidegc = <400>;
+		qcom,cool-bat-decidegc = <50>;
+		qcom,cold-bat-decidegc = <(0)>;
+		qcom,soft-temp-vfloat-comp-mv = <200>;
+		qcom,soft-temp-current-comp-ma = <400>;
+		qcom,chg-inhibit-disabled;
+		qcom,apsd-disabled;
+		qcom,thermal-mitigation = <1500 900 500 100>;
+	};
+};
+
+&soc {
+	pmic-pon-log {
+		compatible = "qcom,pmic-pon-log";
+		nvmem = <&pmx35_sdam_2>;
+		nvmem-names = "pon_log";
+	};
+};
+
+&pmx35_vbus_detect {
+	status = "okay";
+};
+
+&pmx35_vadc {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&batt_id_default>;
+	pmx35_batt_id {
+		reg = <PMX35_ADC5_GEN3_AMUX3_GPIO6_100K_PU>;
+		label = "batt_id";
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_GEN3_BATT_ID_100K>;
+	};
+
+	pmx35_quiet_therm {
+		reg = <PMX35_ADC5_GEN3_AMUX_THM2_100K_PU>;
+		label = "pmx35_quiet_therm";
+		qcom,ratiometric;
+		qcom,adc-tm-type = <1>;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pmx35_xo_therm {
+		reg = <PMX35_ADC5_GEN3_AMUX_THM5_100K_PU>;
+		label = "pmx35_xo_therm";
+		qcom,ratiometric;
+		qcom,adc-tm-type = <1>;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	pa-therm1 {
+		reg = <PMX35_ADC5_GEN3_AMUX_THM1_100K_PU>;
+		label = "pmx35_pa_therm1";
+		qcom,ratiometric;
+		qcom,adc-tm-type = <1>;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+	mdm-skin-therm {
+		reg = <PMX35_ADC5_GEN3_AMUX_THM3_100K_PU>;
+		label = "mdm-skin-therm";
+		qcom,ratiometric;
+		qcom,adc-tm-type = <1>;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+	};
+
+};
+
+&thermal_zones {
+	sys-therm-0 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmx35_vadc PMX35_ADC5_GEN3_AMUX_THM1_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sys-therm-1 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmx35_vadc PMX35_ADC5_GEN3_AMUX_THM3_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sys-therm-2 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-sensors = <&pmx35_vadc PMX35_ADC5_GEN3_AMUX_THM5_100K_PU>;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+
+	sys-therm-3 {
+		polling-delay-passive = <0>;
+		polling-delay = <0>;
+		thermal-governor = "user_space";
+		thermal-sensors = <&pmx35_vadc PMX35_ADC5_GEN3_AMUX_THM2_100K_PU>;
+		wake-capable-sensor;
+		trips {
+			active-config0 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+
+			active-config1 {
+				temperature = <125000>;
+				hysteresis = <1000>;
+				type = "passive";
+			};
+		};
+	};
+};
diff --git a/qcom/sdxbaagha-qupv3.dtsi b/qcom/sdxbaagha-qupv3.dtsi
index 8a77bfff..945ad02e 100755
--- a/qcom/sdxbaagha-qupv3.dtsi
+++ b/qcom/sdxbaagha-qupv3.dtsi
@@ -1,4 +1,33 @@
 &soc {
+	/* QUPv3 SE Instances
+	 * Qup0 0: SE 0
+	 * Qup0 1: SE 1
+	 * Qup0 2: SE 2
+	 * Qup0 3: SE 3
+	 * Qup0 4: SE 4
+	 */
+
+	/* GPI Instance */
+	gpi_dma0: qcom,gpi-dma@900000  {
+		compatible = "qcom,gpi-dma";
+		#dma-cells = <5>;
+		reg = <0x900000  0x60000>;
+		reg-names = "gpi-top";
+		iommus = <&apps_smmu 0x156 0x0>;
+		qcom,max-num-gpii = <5>;
+		interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,gpii-mask = <0xf>;
+		qcom,ev-factor = <2>;
+		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+		qcom,gpi-ee-offset = <0x10000>;
+		dma-coherent;
+		status = "ok";
+	};
+
 	/* QUPv3_0 wrapper instance */
 	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
 		compatible = "qcom,geni-se-qup";
@@ -9,7 +38,7 @@
 		clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 		/*
-		 * iommus = <&apps_smmu 0xa3 0x0>;
+		 * iommus = <&apps_smmu 0x143 0x0>;
 		 * qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
 		 * qcom,iommu-geometry = <0x40000000 0x10000000>;
 		 * qcom,iommu-dma = "fastmap";
@@ -18,7 +47,7 @@
 		ranges;
 		status = "ok";
 
-		/*PORed Debug UART Instance */
+		 /* PORed Debug UART Instance */
 		qupv3_se3_2uart: qcom,qup_uart@98c000 {
 			compatible = "qcom,geni-debug-uart";
 			reg = <0x98c000 0x4000>;
@@ -29,14 +58,167 @@
 			/*
 			 * interconnect-names = "qup-core", "qup-config", "qup-memory";
 			 * interconnects =
-			 * <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
-			 * <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
-			 * <&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
+			 * <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			 * <&mem_noc MASTER_APPSS_PROC &cnoc_main SLAVE_QUP_0>,
+			 * <&aggre_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
 			 */
 			pinctrl-names = "default", "sleep";
 			pinctrl-0 = <&qupv3_se3_2uart_tx_active>, <&qupv3_se3_2uart_rx_active>;
 			pinctrl-1 = <&qupv3_se3_2uart_sleep>;
 			status = "disabled";
 		};
+
+		/* IPC HS UART Instance */
+		qupv3_se0_2uart: qcom,qup_uart@980000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0x980000 0x4000>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+			/*
+			 * interconnect-names = "qup-core", "qup-config", "qup-memory";
+			 * interconnects =
+			 * <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			 * <&mem_noc MASTER_APPSS_PROC &cnoc_main SLAVE_QUP_0>,
+			 * <&aggre_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+			 */
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se0_2uart_tx_active>, <&qupv3_se0_2uart_rx_active>;
+			pinctrl-1 = <&qupv3_se0_2uart_sleep>;
+			status = "disabled";
+		};
+
+		/* BT HCI UART Instance */
+		qupv3_se1_4uart: qcom,qup_uart@984000 {
+			compatible = "qcom,msm-geni-serial-hs";
+			reg = <0x984000 0x4000>;
+			reg-names = "se_phys";
+			interrupts-extended = <&intc GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+					<&tlmm 64 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+			/*
+			 * interconnect-names = "qup-core", "qup-config", "qup-memory";
+			 * interconnects =
+			 * <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			 * <&mem_noc MASTER_APPSS_PROC &cnoc_main SLAVE_QUP_0>,
+			 * <&aggre_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+			 */
+			pinctrl-names = "default", "active", "sleep", "shutdown";
+			pinctrl-0 = <&qupv3_se1_default_cts>, <&qupv3_se1_default_rts>,
+			<&qupv3_se1_default_tx>, <&qupv3_se1_default_rx>;
+			pinctrl-1 = <&qupv3_se1_cts>, <&qupv3_se1_rts>,
+			<&qupv3_se1_tx>, <&qupv3_se1_rx>;
+			pinctrl-2 = <&qupv3_se1_cts>, <&qupv3_se1_rts>,
+			<&qupv3_se1_tx>, <&qupv3_se1_default_rx>;
+			pinctrl-3 = <&qupv3_se1_default_cts>, <&qupv3_se1_default_rts>,
+			<&qupv3_se1_default_tx>, <&qupv3_se1_default_rx>;
+			qcom,wakeup-byte = <0xFD>;
+			status = "disabled";
+		};
+
+		qupv3_se2_i2c: i2c@988000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x988000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+			/*
+			 * interconnect-names = "qup-core", "qup-config", "qup-memory";
+			 * interconnects =
+			 * <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			 * <&mem_noc MASTER_APPSS_PROC &cnoc_main SLAVE_QUP_0>,
+			 * <&aggre_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+			 */
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se2_i2c_sleep>;
+			dmas = <&gpi_dma0 0 2 3 64 0>,
+				<&gpi_dma0 1 2 3 64 0>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		qupv3_se2_spi: spi@988000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x988000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+			/*
+			 * interconnect-names = "qup-core", "qup-config", "qup-memory";
+			 * interconnects =
+			 * <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			 * <&mem_noc MASTER_APPSS_PROC &cnoc_main SLAVE_QUP_0>,
+			 * <&aggre_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+			 */
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>,
+				<&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se2_spi_sleep>;
+			dmas = <&gpi_dma0 0 2 1 64 0>,
+				<&gpi_dma0 1 2 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
+
+		qupv3_se4_i2c: i2c@990000 {
+			compatible = "qcom,i2c-geni";
+			reg = <0x990000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+			/*
+			 * interconnect-names = "qup-core", "qup-config", "qup-memory";
+			 * interconnects =
+			 * <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			 * <&mem_noc MASTER_APPSS_PROC &cnoc_main SLAVE_QUP_0>,
+			 * <&aggre_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+			 */
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>;
+			pinctrl-1 = <&qupv3_se4_i2c_sleep>;
+			dmas = <&gpi_dma0 0 4 3 64 0>,
+				<&gpi_dma0 1 4 3 64 0>;
+			dma-names = "tx", "rx";
+			qcom,shared;
+			status = "disabled";
+		};
+
+		qupv3_se4_spi: spi@990000 {
+			compatible = "qcom,spi-geni";
+			reg = <0x990000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+			/*
+			 * interconnect-names = "qup-core", "qup-config", "qup-memory";
+			 * interconnects =
+			 * <&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+			 * <&mem_noc MASTER_APPSS_PROC &cnoc_main SLAVE_QUP_0>,
+			 * <&aggre_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+			 */
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>,
+				<&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>;
+			pinctrl-1 = <&qupv3_se4_spi_sleep>;
+			dmas = <&gpi_dma0 0 4 1 64 0>,
+				<&gpi_dma0 1 4 1 64 0>;
+			dma-names = "tx", "rx";
+			spi-max-frequency = <50000000>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/qcom/sdxbaagha-regulators.dtsi b/qcom/sdxbaagha-regulators.dtsi
index 3671dbe3..4d38a328 100755
--- a/qcom/sdxbaagha-regulators.dtsi
+++ b/qcom/sdxbaagha-regulators.dtsi
@@ -1,6 +1,6 @@
 #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
 
-&apps_rsc_drv1 {
+&apps_rsc_drv2 {
 	rpmh-regulator-cxlvl {
 		compatible = "qcom,rpmh-arc-regulator";
 		qcom,resource-name = "cx.lvl";
@@ -35,6 +35,7 @@
 			qcom,init-voltage-level =
 				<RPMH_REGULATOR_LEVEL_RETENTION>;
 		};
+	};
 
 	rpmh-regulator-mxlvl {
 		compatible = "qcom,rpmh-arc-regulator";
diff --git a/qcom/sdxbaagha-rumi.dtsi b/qcom/sdxbaagha-rumi.dtsi
index e3f70810..d4750a43 100755
--- a/qcom/sdxbaagha-rumi.dtsi
+++ b/qcom/sdxbaagha-rumi.dtsi
@@ -1,6 +1,6 @@
 &soc {
 	pcie0: qcom,pcie@1bf0000 {
-		status = "disabled";
+		status = "ok";
 		reg = <0x01bf0000 0x4000>,
 			<0x01bf6000 0x2000>,
 			<0x48000000 0xf1d>,
diff --git a/qcom/sdxbaagha.dtsi b/qcom/sdxbaagha.dtsi
index 8128cc80..becc6be6 100755
--- a/qcom/sdxbaagha.dtsi
+++ b/qcom/sdxbaagha.dtsi
@@ -4,8 +4,10 @@
 #include <dt-bindings/soc/qcom,ipcc.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
 #include <dt-bindings/interconnect/qcom,sdxbaagha.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/spmi/spmi.h>
 
 / {
 	#address-cells = <1>;
@@ -18,6 +20,8 @@
 
 	aliases {
 		serial0 = &qupv3_se3_2uart;
+		serial1 = &qupv3_se0_2uart; /* MDM SAP UART Instance */
+		hsuart0 = &qupv3_se1_4uart; /* HST BT HCI UART Instance */
 	};
 
 	chosen {
@@ -149,7 +153,6 @@
 	soc: soc { };
 };
 
-#include "sdxbaagha-stub-regulator.dtsi"
 
 &soc {
 	#address-cells = <1>;
@@ -247,23 +250,29 @@
 		label = "apps_rsc";
 		compatible = "qcom,rpmh-rsc";
 		reg = <0x17040000 0x10000>,
-		      <0x17050000 0x10000>;
-		reg-names = "drv-0", "drv-1";
-		qcom,drv-count = <2>;
+		      <0x17050000 0x10000>,
+		      <0x17060000 0x10000>;
+		reg-names = "drv-0", "drv-1", "drv-2";
+		qcom,drv-count = <3>;
 		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* dummy */
 			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 
-		apps_rsc_drv1: drv@1 {
-			qcom,drv-id = <1>;
+		apps_rsc_drv2: drv@2 {
+			qcom,drv-id = <2>;
 			qcom,tcs-offset = <0xd00>;
 			channel@0 {
 				qcom,tcs-config = <ACTIVE_TCS    2>,
-						  <SLEEP_TCS     1>,
-						  <WAKE_TCS      1>,
+						  <SLEEP_TCS     3>,
+						  <WAKE_TCS      3>,
 						  <CONTROL_TCS   0>,
 						  <FAST_PATH_TCS 0>;
 			};
 
+			apps_bcm_voter: bcm_voter {
+				compatible = "qcom,bcm-voter";
+			};
+
 			rpmhcc: clock-controller {
 				compatible = "qcom,sdxbaagha-rpmh-clk";
 				#clock-cells = <1>;
@@ -497,51 +506,74 @@
 		#mbox-cells = <2>;
 	};
 
-	mc_virt: interconnect@0 {
+	clk_virt: interconnect@0 {
+		compatible = "qcom,sdxbaagha-clk_virt";
+		#interconnect-cells = <1>;
+		qcom,skip-qos;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	mc_virt: interconnect@1 {
 		compatible = "qcom,sdxbaagha-mc_virt";
 		#interconnect-cells = <1>;
-		qcom,stub;
 		qcom,skip-qos;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
 	};
 
 	aggre_noc: interconnect@1640000 {
 		reg = <0x1640000 0x33400>;
 		compatible = "qcom,sdxbaagha-aggre_noc";
 		#interconnect-cells = <1>;
-		qcom,stub;
 		qcom,skip-qos;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
 	};
 
 	cnoc_main: interconnect@1580000 {
 		reg = <0x01580000 0x19200>;
 		compatible = "qcom,sdxbaagha-cnoc_main";
 		#interconnect-cells = <1>;
-		qcom,stub;
 		qcom,skip-qos;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
 	};
 
-	dc_noc_dch: interconnect@190E0000 {
+	dc_noc: interconnect@190E0000 {
 		reg = <0x190E0000 0x5080>;
-		compatible = "qcom,sdxbaagha-dc_noc_dch";
+		compatible = "qcom,sdxbaagha-dc_noc";
 		#interconnect-cells = <1>;
-		qcom,stub;
 		qcom,skip-qos;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
 	};
 
 	mem_noc: interconnect@19100000 {
 		reg = <0x19100000 0x2D080>;
 		compatible = "qcom,sdxbaagha-mem_noc";
 		#interconnect-cells = <1>;
-		qcom,stub;
 		qcom,skip-qos;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
 	};
 
-	snoc: interconnect@15C0000 {
+	pcie_anoc: interconnect@16C0000 {
+		reg = <0x16C0000 0x16400>;
+		compatible = "qcom,sdxbaagha-pcie_anoc";
+		#interconnect-cells = <1>;
+		qcom,skip-qos;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
+	};
+
+	system_noc: interconnect@15C0000 {
 		reg = <0x15C0000 0x14080>;
-		compatible = "qcom,sdxbaagha-snoc";
+		compatible = "qcom,sdxbaagha-system_noc";
 		#interconnect-cells = <1>;
-		qcom,stub;
 		qcom,skip-qos;
+		qcom,bcm-voter-names = "hlos";
+		qcom,bcm-voters = <&apps_bcm_voter>;
 	};
 
 	qcom,sps {
@@ -613,7 +645,7 @@
 		reset-names = "pcie_core_reset", "pcie_phy_reset";
 
 		interconnect-names = "icc_path";
-		interconnects = <&aggre_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
+		interconnects = <&pcie_anoc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
 
 		qcom,pcie-vendor-id = /bits/ 16 <0x17cb>;
 		qcom,pcie-device-id = /bits/ 16 <0x011a>;
@@ -624,6 +656,7 @@
 		qcom,pcie-mhi-a7-irq;
 		qcom,phy-status-reg2 = <0x214>;
 		qcom,mhi-soc-reset-offset = <0xb001b8>;
+		qcom,pcie-cesta-clkreq-offset = <0x30b8>;
 		qcom,aoss-rst-clr;
 		qcom,aux-clk = <0x13>;
 		qcom,phy-init = <0x0240 0x01 0x0
@@ -719,6 +752,49 @@
 		compatible = "qcom,msm-mhi-dev-net";
 		status = "disabled";
 	};
+
+	spmi_bus: qcom,spmi@c42d000 {
+		compatible = "qcom,spmi-pmic-arb";
+		reg = <0xc42d000 0x4000>,
+		      <0xc400000 0x3000>,
+		      <0xc500000 0x400000>,
+		      <0xc440000 0x80000>,
+		      <0xc4c0000 0x10000>;
+		reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
+		interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "periph_irq";
+		interrupt-controller;
+		#interrupt-cells = <4>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		cell-index = <0>;
+		qcom,channel = <0>;
+		qcom,ee = <0>;
+		qcom,bus-id = <0>;
+	};
+
+	spmi_debug_bus: qcom,spmi-debug@24b14000 {
+		compatible = "qcom,spmi-pmic-arb-debug";
+		reg = <0x24b14000 0x60>, <0x221c8784 0x4>;
+		reg-names = "core", "fuse";
+		clocks = <&aoss_qmp>;
+		clock-names = "core_clk";
+		qcom,fuse-enable-bit = <18>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		depends-on-supply = <&spmi_bus>;
+
+		qcom,pmx35-debug@0 {
+			compatible = "qcom,spmi-pmic";
+			reg = <0 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+	};
+
+	thermal_zones: thermal-zones {
+	};
 };
 
 #include "sdxbaagha-pinctrl.dtsi"
@@ -727,6 +803,8 @@
 #include "sdxbaagha-pcie.dtsi"
 #include "sdxbaagha-qupv3.dtsi"
 #include "sdxbaagha-usb.dtsi"
+#include "sdxbaagha-pmic-overlay.dtsi"
+#include "sdxbaagha-regulators.dtsi"
 
 &qupv3_se3_2uart {
 	status = "ok";
diff --git a/qcom/sdxpinn.dtsi b/qcom/sdxpinn.dtsi
index d534ebd9..47139301 100755
--- a/qcom/sdxpinn.dtsi
+++ b/qcom/sdxpinn.dtsi
@@ -349,6 +349,41 @@
 		hwlocks = <&tcsr_mutex 3>;
 	};
 
+	qcom_cedev: qcedev@1de0000 {
+		compatible = "qcom,qcedev";
+		reg = <0x1de0000 0x20000>,
+			<0x1dc4000 0x28000>;
+		reg-names = "crypto-base","crypto-bam-base";
+		interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,bam-pipe-pair = <2>;
+		qcom,ce-hw-instance = <0>;
+		qcom,ce-device = <0>;
+		qcom,ce-hw-shared;
+		qcom,bam-ee = <0>;
+		qcom,smmu-s1-enable;
+		qcom,no-clock-support;
+		interconnect-names = "data_path";
+		interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
+		iommus = <&apps_smmu 0x0020 0x0>,
+			<&apps_smmu 0x0021 0x0>;
+		qcom,iommu-dma = "atomic";
+		dma-coherent;
+
+		qcom_cedev_ns_cb {
+			compatible = "qcom,qcedev,context-bank";
+			label = "ns_context";
+			iommus = <&apps_smmu 0x0021 0x0>;
+			dma-coherent;
+		};
+	};
+
+	qcom_rng: qrng@10c3000 {
+		compatible = "qcom,msm-rng";
+		reg = <0x10c3000 0x1000>;
+		qcom,no-qrng-config;
+		qcom,no-clock-support;
+	};
+
 	qcom,smp2p-modem {
 		compatible = "qcom,smp2p";
 		qcom,smem = <435>, <428>;
@@ -486,7 +521,7 @@
 	pdc: interrupt-controller@b220000 {
 		compatible = "qcom,sdxpinn-pdc", "qcom,pdc";
 		reg = <0xb220000 0x30000>, <0x174000f0 0x64>;
-		qcom,pdc-ranges = <0 147 52>, <52 558 91>;
+		qcom,pdc-ranges = <0 147 52>, <52 266 32>, <84 500 59>;
 		#interrupt-cells = <2>;
 		interrupt-parent = <&intc>;
 		interrupt-controller;
diff --git a/qcom/slate.dtsi b/qcom/slate.dtsi
index a5869c0d..11f9f7a2 100755
--- a/qcom/slate.dtsi
+++ b/qcom/slate.dtsi
@@ -26,10 +26,31 @@
 		qcom,rproc-handle = <&aon_pas>;
 	};
 
-	qcom,glink-slatecom-xprt-slate {
+	glink_slatecom:qcom,glink-slatecom-xprt-slate {
 		compatible = "qcom,glink-slatecom-xprt";
 		label = "slate";
 
+		qcom,glink-slate-events-bridge {
+			qcom,glink-channels = "slate-event";
+			qcom,intents = <0x0181 1>;
+		};
+
+		qcom,glink-slatecom-ctrl {
+			qcom,glink-channels = "slate-ctrl";
+			qcom,intents = <0x0C 1>;
+		};
+
+		qcom,glink-slate-ux-ctl {
+			qcom,glink-channels = "slate-ux-ctl";
+			qcom,intents = <0x0C 1>;
+		};
+
+		qcom,glink-slate-rsb {
+			qcom,glink-channels = "slate-rsb-ctl";
+			qcom,intents = <0x0C 1>;
+		};
+
+
 		qcom,glinkpkt-slate-ssc-hal {
 			qcom,glink-channels = "ssc_hal";
 			qcom,intents = <0x2710 2
@@ -144,4 +165,32 @@
 					0x3E8  2>;
 		};
 	};
+
+	qcom,slatecom-rpmsg {
+		compatible = "qcom,slatecom-rpmsg";
+		qcom,glink-channels = "slate-ctrl";
+		qcom,glinkpkt-edge = "slate";
+		intents = <0x200 20>;
+	};
+
+	qcom,slate-events-bridge {
+		compatible = "qcom,slate-events-bridge";
+	};
+
+	qcom,slate-events-bridge-rpmsg {
+		compatible = "qcom,slate-events-bridge-rpmsg";
+		qcom,glink-channels = "slate-event";
+		qcom,glinkpkt-edge = "slate";
+	};
+
+	qcom,slate-rsb {
+		compatible = "qcom,slate-rsb";
+	};
+
+	qcom,slatersb-rpmsg {
+		compatible = "qcom,slatersb-rpmsg";
+		qcom,glink-channels = "slate-rsb-ctl";
+		qcom,glinkpkt-edge = "slate";
+		intents = <0x200 1>;
+	};
 };
diff --git a/qcom/sm8150-coresight.dtsi b/qcom/sm8150-coresight.dtsi
new file mode 100755
index 00000000..ce155c64
--- /dev/null
+++ b/qcom/sm8150-coresight.dtsi
@@ -0,0 +1,2726 @@
+&soc {
+
+	replicator_qdss: replicator@6046000 {
+		compatible = "arm,coresight-dynamic-replicator",
+						"arm,primecell";
+
+		reg = <0x6046000 0x1000>;
+		reg-names = "replicator-base";
+
+		coresight-name = "coresight-replicator-qdss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				replicator0_out_tmc_etr: endpoint {
+					remote-endpoint=
+						<&tmc_etr_in_replicator0>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				replicator0_out_replicator1_in: endpoint {
+					remote-endpoint=
+					<&replicator1_in_replicator0_out>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				replicator0_in_tmc_etf: endpoint {
+					remote-endpoint=
+						<&tmc_etf_out_replicator0>;
+				};
+			};
+		};
+	};
+
+	replicator_qdss1: replicator@604a000 {
+		compatible = "arm,coresight-dynamic-replicator",
+						"arm,primecell";
+
+		reg = <0x604a000 0x1000>;
+		reg-names = "replicator-base";
+
+		coresight-name = "coresight-replicator-qdss1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				replicator1_out_funnel_swao: endpoint {
+					remote-endpoint=
+					<&funnel_swao_in_replicator1_out>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				replicator1_in_replicator0_out: endpoint {
+					remote-endpoint=
+					<&replicator0_out_replicator1_in>;
+				};
+			};
+		};
+	};
+
+	replicator_swao: replicator@6b0a000 {
+		compatible = "arm,coresight-dynamic-replicator",
+						"arm,primecell";
+
+		reg = <0x6b0a000 0x1000>;
+		reg-names = "replicator-base";
+
+		coresight-name = "coresight-replicator-swao";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* Always have EUD before funnel leading to ETR. If both
+			 * sink are active we need to give preference to EUD
+			 * over ETR
+			 */
+
+			port@1 {
+				reg = <1>;
+				replicator_swao_out_eud: endpoint {
+					remote-endpoint =
+					  <&eud_in_replicator_swao>;
+				};
+			};
+
+			port@0 {
+				reg = <0>;
+				replicator_swao_out_funnel_in1: endpoint {
+					remote-endpoint =
+					<&funnel_in1_in_replicator_swao>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				replicator_swao_in_tmc_etf_swao: endpoint {
+					remote-endpoint =
+					  <&tmc_etf_swao_out_replicator_swao>;
+				};
+			};
+		};
+	};
+
+	tmc_etf_swao: tmc@6b09000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb961>;
+
+		reg = <0x6b09000 0x1000>;
+		reg-names = "tmc-base";
+
+		coresight-name = "coresight-tmc-etf-swao";
+		coresight-csr = <&csr>;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tmc_etf_swao_out_replicator_swao: endpoint {
+					remote-endpoint=
+					  <&replicator_swao_in_tmc_etf_swao>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				tmc_etf_swao_in_funnel_swao: endpoint {
+					remote-endpoint=
+					  <&funnel_swao_out_tmc_etf_swao>;
+				};
+			};
+		};
+
+	};
+
+	funnel_swao:funnel@0x6b08000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6b08000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-swao";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				funnel_swao_out_tmc_etf_swao: endpoint {
+					remote-endpoint =
+						<&tmc_etf_swao_in_funnel_swao>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <5>;
+				funnel_swao_in_ssc_etm0: endpoint {
+					remote-endpoint=
+						<&ssc_etm0_out_funnel_swao>;
+				};
+			};
+
+			port@1 {
+				reg = <6>;
+				funnel_swao_in_replicator1_out: endpoint {
+					remote-endpoint=
+						<&replicator1_out_funnel_swao>;
+				};
+			};
+
+			port@2 {
+				reg = <7>;
+				funnel_swao_in_tpda_swao: endpoint {
+					remote-endpoint=
+						<&tpda_swao_out_funnel_swao>;
+				};
+			};
+		};
+	};
+
+	tpda_swao: tpda@6b01000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b969>;
+		reg = <0x6b01000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-swao";
+
+		qcom,tpda-atid = <71>;
+		qcom,dsb-elem-size = <1 32>;
+		qcom,cmb-elem-size = <0 64>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				reg = <0>;
+				tpda_swao_out_funnel_swao: endpoint {
+					remote-endpoint =
+						<&funnel_swao_in_tpda_swao>;
+				};
+
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tpda_swao_in_tpdm_swao0: endpoint {
+					remote-endpoint =
+						<&tpdm_swao0_out_tpda_swao>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				tpda_swao_in_tpdm_swao1: endpoint {
+					remote-endpoint =
+						<&tpdm_swao1_out_tpda_swao>;
+				};
+
+			};
+		};
+	};
+
+	tpdm_swao0: tpdm@6b02000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+
+		reg = <0x6b02000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-swao-0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_swao0_out_tpda_swao: endpoint {
+				remote-endpoint = <&tpda_swao_in_tpdm_swao0>;
+				};
+			};
+		};
+	};
+
+	tpdm_swao1: tpdm@6b03000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x6b03000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name="coresight-tpdm-swao-1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,msr-fix-req;
+
+		out-ports {
+			port {
+				tpdm_swao1_out_tpda_swao: endpoint {
+					remote-endpoint = <&tpda_swao_in_tpdm_swao1>;
+				};
+			};
+		};
+	};
+
+	tmc_etr: tmc@6048000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb961>;
+		reg = <0x6048000 0x1000>,
+		      <0x6064000 0x15000>;
+		reg-names = "tmc-base", "bam-base";
+
+		qcom,iommu-dma = "default";
+		iommus = <&apps_smmu 0x05e0 0>,
+			<&apps_smmu 0x04a0 0>;
+		qcom,iommu-dma-addr-pool = <0x0 0xffc00000>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		arm,buffer-size = <0x400000>;
+		coresight-name = "coresight-tmc-etr";
+		coresight-ctis = <&cti0 &cti0>;
+		cti-reset-trig-num = <0>;
+		cti-flush-trig-num = <3>;
+		coresight-csr = <&csr>;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "byte-cntr-irq";
+
+		in-ports {
+			port {
+				tmc_etr_in_replicator0: endpoint {
+					remote-endpoint = <&replicator0_out_tmc_etr>;
+				};
+			};
+		};
+	};
+
+	tmc_etf: tmc@6047000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb961>;
+
+		reg = <0x6047000 0x1000>;
+		reg-names = "tmc-base";
+
+		coresight-name = "coresight-tmc-etf";
+		coresight-ctis = <&cti0 &cti0>;
+		cti-reset-trig-num = <0>;
+		cti-flush-trig-num = <1>;
+		coresight-csr = <&csr>;
+		arm,default-sink;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tmc_etf_out_replicator0: endpoint {
+					remote-endpoint =
+						<&replicator0_in_tmc_etf>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				tmc_etf_in_funnel_merg: endpoint {
+					remote-endpoint =
+						<&funnel_merg_out_tmc_etf>;
+				};
+			};
+		};
+
+	};
+
+	funnel_merg: funnel@6045000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6045000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-merg";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				reg = <0>;
+				funnel_merg_out_tmc_etf: endpoint {
+					remote-endpoint =
+						<&tmc_etf_in_funnel_merg>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_merg_in_funnel_in0: endpoint {
+					remote-endpoint =
+						<&funnel_in0_out_funnel_merg>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_merg_in_funnel_in1: endpoint {
+					remote-endpoint =
+						<&funnel_in1_out_funnel_merg>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				funnel_merg_in_funnel_in2: endpoint {
+					remote-endpoint =
+						<&funnel_in2_out_funnel_merg>;
+				};
+			};
+		};
+	};
+
+	stm: stm@6002000 {
+		compatible = "arm,primecell";
+
+		reg = <0x6002000 0x1000>,
+		      <0x16280000 0x180000>,
+		      <0x7820f0 0x4>;
+		reg-names = "stm-base", "stm-stimulus-base", "stm-debug-status";
+
+		coresight-name = "coresight-stm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				stm_out_funnel_in0: endpoint {
+					remote-endpoint = <&funnel_in0_in_stm>;
+				};
+			};
+		};
+	};
+
+	hwevent: hwevent@0x091866F0 {
+		compatible = "qcom,coresight-hwevent";
+		reg = <0x091866F0 0x4>,
+		     <0x91966F0 0x4>,
+		      <0x9186038 0x4>,
+		      <0x9196038 0x4>,
+		      <0x17E00034 0x4>,
+		     <0x18200050 0x80>,
+		     <0x02C8D050 0x80>,
+		     <0x0AF20050 0x80>;
+		reg-names = "ddr-ch0-cfg", "ddr-ch23-cfg", "ddr-ch0-ctrl",
+			    "ddr-ch23-ctrl", "apss-testbus-mux-cfg",
+			    "apss-rsc-hwevent-mux0-select",
+			    "gpu-rsc-hwevent-mux0-select",
+			    "sde-rsc-hwevent-mux0-select";
+
+		coresight-name = "coresight-hwevent";
+		coresight-csr = <&csr>;
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	csr: csr@6001000 {
+		compatible = "qcom,coresight-csr";
+		reg = <0x6001000 0x1000>;
+		reg-names = "csr-base";
+
+		coresight-name = "coresight-csr";
+		qcom,usb-bam-support;
+		qcom,hwctrl-set-support;
+		qcom,set-byte-cntr-support;
+
+		qcom,blk-size = <1>;
+	};
+
+	swao_csr: csr@6b0e000 {
+		compatible = "qcom,coresight-csr";
+		reg = <0x6b0e000 0x1000>;
+		reg-names = "csr-base";
+
+		coresight-name = "coresight-swao-csr";
+		qcom,timestamp-support;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,blk-size = <1>;
+	};
+
+	funnel_in0: funnel@0x6041000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6041000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-in0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				funnel_in0_out_funnel_merg: endpoint {
+					remote-endpoint =
+						<&funnel_merg_in_funnel_in0>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <1>;
+				funnel_in0_in_funnel_spss: endpoint {
+					remote-endpoint =
+						<&funnel_spss_out_funnel_in0>;
+				};
+			};
+
+			port@1 {
+				reg = <6>;
+				funnel_in0_in_funnel_qatb: endpoint {
+					remote-endpoint =
+						<&funnel_qatb_out_funnel_in0>;
+				};
+			};
+
+			port@2 {
+				reg = <7>;
+				funnel_in0_in_stm: endpoint {
+					remote-endpoint = <&stm_out_funnel_in0>;
+				};
+			};
+		};
+	};
+
+	funnel_in1: funnel@0x6042000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6042000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-in1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				funnel_in1_out_funnel_merg: endpoint {
+					remote-endpoint =
+						<&funnel_merg_in_funnel_in1>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <2>;
+				funnel_in1_in_funnel_dl_south: endpoint {
+					remote-endpoint =
+						<&funnel_dl_south_out_funnel_in1>;
+				};
+			};
+
+			port@1 {
+				reg = <3>;
+				funnel_in1_in_modem_etm0: endpoint {
+					remote-endpoint =
+						<&modem_etm0_out_funnel_in1>;
+				};
+			};
+
+			port@2 {
+				reg = <4>;
+				funnel_in1_in_replicator_swao: endpoint {
+					remote-endpoint =
+					<&replicator_swao_out_funnel_in1>;
+				};
+			};
+
+			port@3 {
+				reg = <6>;
+				funnel_in1_in_funnel_dl_north: endpoint {
+					remote-endpoint =
+					<&funnel_dl_north_out_funnel_in1>;
+				};
+			};
+		};
+	};
+
+	funnel_in2: funnel@0x6043000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6043000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-in2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port@0 {
+				funnel_in2_out_funnel_merg: endpoint {
+					remote-endpoint =
+					  <&funnel_merg_in_funnel_in2>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <2>;
+				funnel_in2_in_funnel_apss_merg: endpoint {
+					remote-endpoint =
+					  <&funnel_apss_merg_out_funnel_in2>;
+				};
+			};
+
+			port@1 {
+				reg = <3>;
+				funnel_in2_in_funnel_gfx: endpoint {
+					remote-endpoint =
+					  <&funnel_gfx_out_funnel_in2>;
+				};
+			};
+
+			port@2 {
+				reg = <4>;
+				funnel_in2_in_tpda_modem: endpoint {
+					remote-endpoint =
+					  <&tpda_modem_out_funnel_in2>;
+				};
+			};
+		};
+	};
+
+	funnel_gfx: funnel@0x6943000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6943000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-gfx";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				funnel_gfx_out_funnel_in2: endpoint {
+					remote-endpoint =
+					<&funnel_in2_in_funnel_gfx>;
+				};
+			};
+		};
+	};
+
+	tpda: tpda@6004000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b969>;
+		reg = <0x6004000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda";
+
+		qcom,tpda-atid = <65>;
+		qcom,bc-elem-size = <10 32>,
+				    <13 32>;
+		qcom,tc-elem-size = <13 32>;
+		qcom,dsb-elem-size = <0 32>,
+				     <2 32>,
+				     <3 32>,
+				     <5 32>,
+				     <6 32>,
+				     <10 32>,
+				     <11 32>,
+				     <13 32>;
+		qcom,cmb-elem-size = <3 64>,
+				     <7 64>,
+				     <10 64>,
+				     <13 64>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpda_out_funnel_qatb: endpoint {
+					remote-endpoint =
+						<&funnel_qatb_in_tpda>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				tpda_in_funnel_dl_mm: endpoint {
+					remote-endpoint =
+						<&funnel_dl_mm_out_tpda>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				tpda_in_funnel_dl_mm1: endpoint {
+					remote-endpoint =
+						<&funnel_dl_mm1_out_tpda>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				tpda_in_tpdm_center: endpoint {
+					remote-endpoint =
+						<&tpdm_center_out_tpda>;
+				};
+			};
+
+			port@3 {
+				reg = <4>;
+				tpda_in_funnel_lpass: endpoint {
+					remote-endpoint =
+						<&funnel_lpass_out_tpda>;
+				};
+			};
+
+			port@4 {
+				reg = <5>;
+				tpda_in_funnel_turing: endpoint {
+					remote-endpoint =
+						<&funnel_turing_out_tpda>;
+				};
+			};
+
+			port@5 {
+				reg = <6>;
+				tpda_in_funnel_ddr_0: endpoint {
+					remote-endpoint =
+						<&funnel_ddr_0_out_tpda>;
+				};
+			};
+
+			port@6 {
+				reg = <8>;
+				tpda_in_tpdm_vsense: endpoint {
+					remote-endpoint =
+						<&tpdm_vsense_out_tpda>;
+				};
+			};
+
+			port@7 {
+				reg = <10>;
+				tpda_in_tpdm_prng: endpoint {
+					remote-endpoint =
+						<&tpdm_prng_out_tpda>;
+				};
+			};
+
+			port@8 {
+				reg = <13>;
+				tpda_in_tpdm_pimem: endpoint {
+					remote-endpoint =
+						<&tpdm_pimem_out_tpda>;
+				};
+			};
+		};
+	};
+
+	tpda_modem: tpda@6832000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b969>;
+		reg = <0x6832000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-modem";
+
+		qcom,tpda-atid = <67>;
+		qcom,dsb-elem-size = <0 32>;
+		qcom,cmb-elem-size = <0 64>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpda_modem_out_funnel_in2: endpoint {
+					remote-endpoint =
+						<&funnel_in2_in_tpda_modem>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				tpda_modem_in_tpdm_modem: endpoint {
+					remote-endpoint =
+						<&tpdm_modem_out_tpda_modem>;
+				};
+			};
+		};
+	};
+
+	tpdm_modem: tpdm@6830000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x6830000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-modem";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+
+		out-ports {
+			port {
+				tpdm_modem_out_tpda_modem: endpoint {
+					remote-endpoint = <&tpda_modem_in_tpdm_modem>;
+				};
+			};
+		};
+	};
+
+	funnel_lpass: funnel@6846000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6846000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-lpass";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				reg = <0>;
+				funnel_lpass_out_tpda: endpoint {
+					remote-endpoint =
+					    <&tpda_in_funnel_lpass>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				reg = <0>;
+				funnel_lpass_in_tpdm_lpass: endpoint {
+					remote-endpoint =
+					    <&tpdm_lpass_out_funnel_lpass>;
+				};
+			};
+		};
+	};
+
+	funnel_lpass_1: funnel_1@6846000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6867020 0x10>,
+			<0x6846000 0x1000>;
+		reg-names = "funnel-base-dummy", "funnel-base-real";
+
+		coresight-name = "coresight-funnel-lpass-1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,duplicate-funnel;
+
+		out-ports {
+			port {
+				reg = <0>;
+				funnel_lpass_1_out_funnel_qatb: endpoint {
+					remote-endpoint =
+					    <&funnel_qatb_in_funnel_lpass_1>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				reg = <2>;
+				funnel_lpass_1_in_audio_etm0: endpoint {
+					remote-endpoint =
+					    <&audio_etm0_out_funnel_lpass_1>;
+				};
+			};
+		};
+	};
+
+	tpdm_lpass: tpdm@6844000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x6844000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-lpass";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,msr-fix-req;
+
+		out-ports {
+			port {
+				tpdm_lpass_out_funnel_lpass: endpoint {
+					remote-endpoint = <&funnel_lpass_in_tpdm_lpass>;
+				};
+			};
+		};
+	};
+
+	tpdm_center: tpdm@6c28000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x6c28000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-center";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,msr-fix-req;
+
+		out-ports {
+			port {
+				tpdm_center_out_tpda: endpoint {
+					remote-endpoint = <&tpda_in_tpdm_center>;
+				};
+			};
+		};
+	};
+
+	tpdm_dl_north: tpdm@6ac0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x6ac0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-dl-north";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,msr-fix-req;
+
+		out-ports {
+			port {
+				tpdm_dl_north_out_tpda_dl_north: endpoint {
+					remote-endpoint =
+						<&tpda_dl_north_in_tpdm_dl_north>;
+				};
+			};
+		};
+	};
+
+	tpda_dl_north: tpda@6ac1000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b969>;
+		reg = <0x06ac1000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-dl-north";
+		qcom,tpda-atid = <97>;
+
+		qcom,cmb-elem-size = <0 32>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				reg = <0>;
+				tpda_dl_north_out_funnel_dl_north: endpoint {
+					remote-endpoint =
+					<&funnel_dl_north_in_tpda_dl_north>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				reg = <0>;
+				tpda_dl_north_in_tpdm_dl_north: endpoint {
+					remote-endpoint =
+					<&tpdm_dl_north_out_tpda_dl_north>;
+				};
+			};
+		};
+	};
+
+	funnel_dl_south: funnel@69c2000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+		reg = <0x69c2000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-dl-south";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				funnel_dl_south_out_funnel_in1: endpoint {
+					remote-endpoint =
+					<&funnel_in1_in_funnel_dl_south>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				funnel_dl_south_in_tpdm_dl_south: endpoint {
+					remote-endpoint =
+					<&tpdm_dl_south_out_funnel_dl_south>;
+				};
+			};
+		};
+	};
+
+	tpdm_dl_south: tpdm@69c0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x69c0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-dl-south";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_dl_south_out_funnel_dl_south: endpoint {
+					remote-endpoint =
+						<&funnel_dl_south_in_tpdm_dl_south>;
+				};
+			};
+		};
+	};
+
+	funnel_dl_north: funnel@6ac2000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6ac2000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-dl-north";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				funnel_dl_north_out_funnel_in1: endpoint {
+					remote-endpoint =
+					    <&funnel_in1_in_funnel_dl_north>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_dl_north_in_tpda_dl_north: endpoint {
+					remote-endpoint =
+					<&tpda_dl_north_out_funnel_dl_north>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_dl_north_in_tpdm_wcss: endpoint {
+					remote-endpoint =
+					<&tpdm_wcss_out_funnel_dl_north>;
+				};
+			};
+		};
+	};
+
+	tpdm_wcss: tpdm@699c000 {
+		compatible = "qcom,coresight-dummy";
+
+		coresight-name = "coresight-tpdm-wcss";
+		qcom,dummy-source;
+
+		out-ports {
+			port {
+				tpdm_wcss_out_funnel_dl_north: endpoint {
+					remote-endpoint = <&funnel_dl_north_in_tpdm_wcss>;
+				};
+			};
+		};
+	};
+
+	tpdm_prng: tpdm@684c000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x684c000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-prng";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_prng_out_tpda: endpoint {
+					remote-endpoint = <&tpda_in_tpdm_prng>;
+				};
+			};
+		};
+	};
+
+	funnel_spss: funnel@6883000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6883000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-spss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+
+			port@0 {
+				reg = <0>;
+				funnel_spss_out_funnel_in0: endpoint {
+					remote-endpoint =
+					    <&funnel_in0_in_funnel_spss>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				funnel_spss_in_tpda_spss: endpoint {
+					remote-endpoint =
+					<&tpda_spss_out_funnel_spss>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+				funnel_spss_in_spss_etm0: endpoint {
+					remote-endpoint =
+					<&spss_etm0_out_funnel_spss>;
+				};
+			};
+		};
+	};
+
+	tpda_spss: tpda@6882000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b969>;
+		reg = <0x06882000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-spss";
+
+		qcom,tpda-atid = <70>;
+		qcom,cmb-elem-size = <0 32>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port@0 {
+				reg = <0>;
+				tpda_spss_out_funnel_spss: endpoint {
+					remote-endpoint =
+					<&funnel_spss_in_tpda_spss>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <0>;
+				tpda_spss_in_tpdm_spss: endpoint {
+					remote-endpoint =
+					<&tpdm_spss_out_tpda_spss>;
+				};
+			};
+		};
+	};
+
+	tpdm_spss: tpdm@6880000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x6880000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-spss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_spss_out_tpda_spss: endpoint {
+					remote-endpoint = <&tpda_spss_in_tpdm_spss>;
+				};
+			};
+		};
+	};
+
+	spss_etm0 {
+		compatible = "qcom,coresight-dummy";
+
+		coresight-name = "coresight-spss-etm0";
+		qcom,dummy-source;
+
+		out-ports {
+			port {
+				spss_etm0_out_funnel_spss: endpoint {
+					remote-endpoint = <&funnel_spss_in_spss_etm0>;
+				};
+			};
+		};
+	};
+
+	tpdm_qm: tpdm@69d0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x69d0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-qm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			tpdm_qm_out_funnel_dl_mm: endpoint {
+				remote-endpoint = <&funnel_dl_mm_in_tpdm_qm>;
+			};
+		};
+	};
+
+	tpda_apss: tpda@7862000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b969>;
+		reg = <0x7862000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-apss";
+
+		qcom,tpda-atid = <66>;
+		qcom,dsb-elem-size = <0 32>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				reg = <0>;
+				tpda_apss_out_funnel_apss_merg: endpoint {
+					remote-endpoint =
+					       <&funnel_apss_merg_in_tpda_apss>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				reg = <0>;
+				tpda_apss_in_tpdm_apss: endpoint {
+					remote-endpoint =
+						<&tpdm_apss_out_tpda_apss>;
+				};
+			};
+		};
+	};
+
+	tpdm_apss: tpdm@7860000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x7860000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-apss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			tpdm_apss_out_tpda_apss: endpoint {
+				remote-endpoint = <&tpda_apss_in_tpdm_apss>;
+			};
+		};
+	};
+
+	tpda_llm_silver: tpda@78c0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b969>;
+		reg = <0x78c0000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-llm-silver";
+
+		qcom,tpda-atid = <72>;
+		qcom,cmb-elem-size = <0 32>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				reg = <0>;
+				tpda_llm_silver_out_funnel_apss_merg: endpoint {
+					remote-endpoint =
+					<&funnel_apss_merg_in_tpda_llm_silver>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				reg = <0>;
+				tpda_llm_silver_in_tpdm_llm_silver: endpoint {
+					remote-endpoint =
+					<&tpdm_llm_silver_out_tpda_llm_silver>;
+				};
+			};
+		};
+	};
+
+	tpdm_llm_silver: tpdm@78a0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x78a0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-llm-silver";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			tpdm_llm_silver_out_tpda_llm_silver: endpoint {
+				remote-endpoint =
+					<&tpda_llm_silver_in_tpdm_llm_silver>;
+			};
+		};
+	};
+
+	tpda_llm_gold: tpda@78d0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b969>;
+		reg = <0x78d0000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-llm-gold";
+
+		qcom,tpda-atid = <73>;
+		qcom,cmb-elem-size = <0 32>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				tpda_llm_gold_out_funnel_apss_merg: endpoint {
+					remote-endpoint =
+					  <&funnel_apss_merg_in_tpda_llm_gold>;
+				};
+				};
+			};
+
+		in-ports {
+			port {
+				reg = <0>;
+				tpda_llm_gold_in_tpdm_llm_gold: endpoint {
+					remote-endpoint =
+					  <&tpdm_llm_gold_out_tpda_llm_gold>;
+				};
+			};
+		};
+	};
+
+	tpdm_llm_gold: tpdm@78b0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x78b0000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-llm-gold";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_llm_gold_out_tpda_llm_gold: endpoint {
+					remote-endpoint =
+						<&tpda_llm_gold_in_tpdm_llm_gold>;
+				};
+			};
+		};
+	};
+
+	funnel_dl_mm: funnel@6c0b000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6c0b000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-dl-mm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				reg = <0>;
+				funnel_dl_mm_out_tpda: endpoint {
+					remote-endpoint =
+					    <&tpda_in_funnel_dl_mm>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				reg = <0>;
+				funnel_dl_mm_in_tpdm_qm: endpoint {
+					remote-endpoint =
+					    <&tpdm_qm_out_funnel_dl_mm>;
+				};
+			};
+		};
+	};
+
+	funnel_dl_mm1: funnel_1@6c0b000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6867000 0x10>,
+			<0x6c0b000 0x1000>;
+		reg-names = "funnel-base-dummy", "funnel-base-real";
+
+		coresight-name = "coresight-funnel-dl-mm1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,duplicate-funnel;
+
+		out-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port {
+				reg = <0>;
+				funnel_dl_mm1_out_tpda: endpoint {
+					remote-endpoint =
+					    <&tpda_in_funnel_dl_mm1>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				reg = <1>;
+				funnel_dl_mm1_in_tpdm_mm: endpoint {
+					remote-endpoint =
+						<&tpdm_mm_out_funnel_dl_mm1>;
+				};
+			};
+		};
+	};
+
+	tpdm_mm: tpdm@6c08000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x6c08000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-mm";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,msr-fix-req;
+
+		out-ports {
+				port {
+					tpdm_mm_out_funnel_dl_mm1: endpoint {
+					remote-endpoint = <&funnel_dl_mm1_in_tpdm_mm>;
+				};
+			};
+		};
+	};
+
+	funnel_turing: funnel@6861000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6861000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-turing";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				reg = <0>;
+				funnel_turing_out_tpda: endpoint {
+					remote-endpoint =
+					    <&tpda_in_funnel_turing>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				reg = <0>;
+				funnel_turing_in_tpdm_turing: endpoint {
+					remote-endpoint =
+					    <&tpdm_turing_out_funnel_turing>;
+				};
+			};
+		};
+	};
+
+	funnel_turing_1: funnel_1@6861000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6867010 0x10>,
+			<0x6861000 0x1000>;
+		reg-names = "funnel-base-dummy", "funnel-base-real";
+
+		coresight-name = "coresight-funnel-turing-1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,duplicate-funnel;
+
+		out-ports {
+
+			port {
+				reg = <0>;
+				funnel_turing_1_out_funnel_qatb: endpoint {
+					remote-endpoint =
+					    <&funnel_qatb_in_funnel_turing_1>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				reg = <1>;
+				funnel_turing_1_in_turing_etm0: endpoint {
+					remote-endpoint =
+					    <&turing_etm0_out_funnel_turing_1>;
+				};
+			};
+		};
+	};
+
+	tpdm_turing: tpdm@6860000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x6860000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-turing";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,msr-fix-req;
+
+		out-ports {
+			port {
+				tpdm_turing_out_funnel_turing: endpoint {
+					remote-endpoint =
+						<&funnel_turing_in_tpdm_turing>;
+				};
+			};
+		};
+	};
+
+	funnel_ddr_0: funnel@6a05000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6a05000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-ddr-0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				funnel_ddr_0_out_tpda: endpoint {
+					remote-endpoint =
+					    <&tpda_in_funnel_ddr_0>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				funnel_ddr_0_in_tpdm_ddr: endpoint {
+					remote-endpoint =
+					    <&tpdm_ddr_out_funnel_ddr_0>;
+				};
+			};
+		};
+	};
+
+	tpdm_ddr: tpdm@6A00000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x06A00000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-ddr";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,msr-fix-req;
+
+		out-ports {
+			port {
+				tpdm_ddr_out_funnel_ddr_0: endpoint {
+					remote-endpoint = <&funnel_ddr_0_in_tpdm_ddr>;
+				};
+			};
+		};
+	};
+
+	tpdm_pimem: tpdm@6850000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x6850000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-pimem";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_pimem_out_tpda: endpoint {
+					remote-endpoint = <&tpda_in_tpdm_pimem>;
+				};
+			};
+		};
+	};
+
+	tpdm_vsense: tpdm@6840000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x6840000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-vsense";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_vsense_out_tpda: endpoint {
+					remote-endpoint = <&tpda_in_tpdm_vsense>;
+				};
+			};
+		};
+	};
+
+	tpda_olc: tpda@7832000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b969>;
+		reg = <0x7832000 0x1000>;
+		reg-names = "tpda-base";
+
+		coresight-name = "coresight-tpda-olc";
+
+		qcom,tpda-atid = <69>;
+		qcom,cmb-elem-size = <0 64>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpda_olc_out_funnel_apss_merg: endpoint {
+					remote-endpoint =
+						<&funnel_apss_merg_in_tpda_olc>;
+				};
+			};
+		};
+
+		in-ports {
+			port {
+				tpda_olc_in_tpdm_olc: endpoint {
+					remote-endpoint =
+						<&tpdm_olc_out_tpda_olc>;
+				};
+			};
+		};
+	};
+
+	tpdm_olc: tpdm@7830000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b968>;
+		reg = <0x7830000 0x1000>;
+		reg-names = "tpdm-base";
+
+		coresight-name = "coresight-tpdm-olc";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				tpdm_olc_out_tpda_olc: endpoint {
+					remote-endpoint = <&tpda_olc_in_tpdm_olc>;
+				};
+			};
+		};
+	};
+
+	funnel_qatb: funnel@6005000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x6005000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-qatb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				funnel_qatb_out_funnel_in0: endpoint {
+					remote-endpoint =
+						<&funnel_in0_in_funnel_qatb>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <0>;
+				funnel_qatb_in_tpda: endpoint {
+					remote-endpoint =
+						<&tpda_out_funnel_qatb>;
+				};
+			};
+
+			port@2 {
+				reg = <4>;
+				funnel_qatb_in_funnel_lpass_1: endpoint {
+					remote-endpoint =
+					    <&funnel_lpass_1_out_funnel_qatb>;
+				};
+			};
+
+			port@3 {
+				reg = <5>;
+				funnel_qatb_in_funnel_turing_1: endpoint {
+					remote-endpoint =
+					    <&funnel_turing_1_out_funnel_qatb>;
+				};
+			};
+		};
+	};
+
+	cti0_apss: cti@78e0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x78e0000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-apss_cti0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti1_apss: cti@78f0000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x78f0000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-apss_cti1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti2_apss: cti@7900000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x7900000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-apss_cti2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti0_ddr0: cti@6a02000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x6a02000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-ddr_dl_0_cti_0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti1_ddr0: cti@6a03000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x6a03000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-ddr_dl_0_cti_1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti0_ddr1: cti@6a10000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x6a10000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-ddr_dl_1_cti_0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti1_ddr1: cti@6a11000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x6a11000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-ddr_dl_1_cti_1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti0_dlmm: cti@6c09000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x6c09000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-dlmm_cti0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti1_dlmm: cti@6c0a000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x6c0a000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-dlmm_cti1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti0_dlct: cti@6c29000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x6c29000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-dlct_cti0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti1_dlct: cti@6c2a000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x6c2a000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-dlct_cti1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti0: cti@6010000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x6010000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti1: cti@6011000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x6011000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti2: cti@6012000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x6012000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		qcom,cti-gpio-trigout = <4>;
+		pinctrl-names = "cti-trigout-pctrl";
+		pinctrl-0 = <&trigout_a>;
+	};
+
+	cti3: cti@6013000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x6013000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti3";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti4: cti@6014000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x6014000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti4";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti5: cti@6015000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x6015000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti5";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti6: cti@6016000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x6016000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti6";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti7: cti@6017000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x6017000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti7";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti8: cti@6018000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x6018000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti8";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti9: cti@6019000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x6019000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti9";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti10: cti@601a000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x601a000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti10";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti11: cti@601b000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x601b000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti11";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti12: cti@601c000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x601c000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti12";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti13: cti@601d000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x601d000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti13";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti14: cti@601e000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x601e000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti14";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti15: cti@601f000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x601f000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti15";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti_cpu0: cti@7020000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x7020000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-cpu0";
+		cpu = <&CPU0>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+	};
+
+	cti_cpu1: cti@7120000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x7120000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-cpu1";
+		cpu = <&CPU1>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_cpu2: cti@7220000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x7220000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-cpu2";
+		cpu = <&CPU2>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_cpu3: cti@7320000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x7320000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-cpu3";
+		cpu = <&CPU3>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_cpu4: cti@7420000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x7420000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-cpu4";
+		cpu = <&CPU4>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_cpu5: cti@7520000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x7520000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-cpu5";
+		cpu = <&CPU5>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_cpu6: cti@7620000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x7620000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-cpu6";
+		cpu = <&CPU6>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti_cpu7: cti@7720000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x7720000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-cpu7";
+		cpu = <&CPU7>;
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	cti0_swao:cti@6b04000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b966>;
+		reg = <0x6b04000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-swao_cti0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	ipcb_tgu: tgu@6b0c000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x0003b999>;
+		reg = <0x06B0C000 0x1000>;
+		reg-names = "tgu-base";
+		tgu-steps = <3>;
+		tgu-conditions = <4>;
+		tgu-regs = <4>;
+		tgu-timer-counters = <8>;
+
+		coresight-name = "coresight-tgu-ipcb";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
+	turing_etm0 {
+		compatible = "qcom,coresight-remote-etm";
+
+		coresight-name = "coresight-turing-etm0";
+		qcom,inst-id = <13>;
+
+		out-ports {
+			port {
+				turing_etm0_out_funnel_turing_1: endpoint {
+					remote-endpoint =
+						<&funnel_turing_1_in_turing_etm0>;
+				};
+			};
+		};
+	};
+
+	dummy_eud: dummy_sink {
+		compatible = "qcom,coresight-dummy";
+
+		coresight-name = "coresight-eud";
+		qcom,dummy-sink;
+
+		out-ports {
+			port {
+				eud_in_replicator_swao: endpoint {
+					remote-endpoint =
+						<&replicator_swao_out_eud>;
+				};
+			};
+		};
+	};
+
+	modem_etm0 {
+		compatible = "qcom,coresight-remote-etm";
+
+		coresight-name = "coresight-modem-etm0";
+		qcom,inst-id = <2>;
+
+		out-ports {
+			port {
+				modem_etm0_out_funnel_in1: endpoint {
+					remote-endpoint =
+						<&funnel_in1_in_modem_etm0>;
+				};
+			};
+		};
+	};
+
+	audio_etm0 {
+		compatible = "qcom,coresight-remote-etm";
+
+		coresight-name = "coresight-audio-etm0";
+		qcom,inst-id = <5>;
+
+		out-ports {
+			port {
+				audio_etm0_out_funnel_lpass_1: endpoint {
+					remote-endpoint =
+						<&funnel_lpass_1_in_audio_etm0>;
+				};
+			};
+		};
+	};
+
+	ssc_etm0 {
+		compatible = "qcom,coresight-remote-etm";
+
+		coresight-name = "coresight-ssc-etm0";
+		qcom,inst-id = <8>;
+
+		out-ports {
+			port {
+				ssc_etm0_out_funnel_swao: endpoint {
+					remote-endpoint =
+						<&funnel_swao_in_ssc_etm0>;
+				};
+			};
+		};
+	};
+
+	funnel_apss_merg: funnel@7810000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x7810000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-apss-merg";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+
+			port@0 {
+				reg = <0>;
+				funnel_apss_merg_out_funnel_in2: endpoint {
+					remote-endpoint =
+					    <&funnel_in2_in_funnel_apss_merg>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <0>;
+				funnel_apss_merg_in_funnel_apss: endpoint {
+					remote-endpoint =
+					    <&funnel_apss_out_funnel_apss_merg>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				funnel_apss_merg_in_tpda_olc: endpoint {
+					remote-endpoint =
+					    <&tpda_olc_out_funnel_apss_merg>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+				funnel_apss_merg_in_tpda_llm_silver: endpoint {
+					remote-endpoint =
+					<&tpda_llm_silver_out_funnel_apss_merg>;
+				};
+			};
+
+			port@4 {
+				reg = <4>;
+				funnel_apss_merg_in_tpda_llm_gold: endpoint {
+					remote-endpoint =
+					  <&tpda_llm_gold_out_funnel_apss_merg>;
+				};
+			};
+
+			port@5 {
+				reg = <5>;
+				funnel_apss_merg_in_tpda_apss: endpoint {
+					remote-endpoint =
+					  <&tpda_apss_out_funnel_apss_merg>;
+				};
+			};
+
+		};
+	};
+
+	etm0: etm@7040000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+
+		reg = <0x7040000 0x1000>;
+		cpu = <&CPU0>;
+
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm0";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				etm0_out_funnel_apss: endpoint {
+					remote-endpoint = <&funnel_apss_in_etm0>;
+				};
+			};
+		};
+	};
+
+	etm1: etm@7140000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+
+		reg = <0x7140000 0x1000>;
+		cpu = <&CPU1>;
+
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm1";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				etm1_out_funnel_apss: endpoint {
+					remote-endpoint = <&funnel_apss_in_etm1>;
+				};
+			};
+		};
+	};
+
+	etm2: etm@7240000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+
+		reg = <0x7240000 0x1000>;
+		cpu = <&CPU2>;
+
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm2";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				etm2_out_funnel_apss: endpoint {
+					remote-endpoint = <&funnel_apss_in_etm2>;
+				};
+			};
+		};
+	};
+
+	etm3: etm@7340000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+
+		reg = <0x7340000 0x1000>;
+		cpu = <&CPU3>;
+
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm3";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				etm3_out_funnel_apss: endpoint {
+					remote-endpoint = <&funnel_apss_in_etm3>;
+				};
+			};
+		};
+	};
+
+	etm4: etm@7440000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+
+		reg = <0x7440000 0x1000>;
+		cpu = <&CPU4>;
+
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm4";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				etm4_out_funnel_apss: endpoint {
+					remote-endpoint = <&funnel_apss_in_etm4>;
+				};
+			};
+		};
+	};
+
+	etm5: etm@7540000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+
+		reg = <0x7540000 0x1000>;
+		cpu = <&CPU5>;
+
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm5";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				etm5_out_funnel_apss: endpoint {
+					remote-endpoint = <&funnel_apss_in_etm5>;
+				};
+			};
+		};
+	};
+
+	etm6: etm@7640000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+
+		reg = <0x7640000 0x1000>;
+		cpu = <&CPU6>;
+
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm6";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				etm6_out_funnel_apss: endpoint {
+					remote-endpoint = <&funnel_apss_in_etm6>;
+				};
+			};
+		};
+	};
+
+	etm7: etm@7740000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb95d>;
+
+		reg = <0x7740000 0x1000>;
+		cpu = <&CPU7>;
+
+		qcom,tupwr-disable;
+		coresight-name = "coresight-etm7";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port {
+				etm7_out_funnel_apss: endpoint {
+					remote-endpoint = <&funnel_apss_in_etm7>;
+				};
+			};
+		};
+	};
+
+	funnel_apss: funnel@7800000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb908>;
+
+		reg = <0x7800000 0x1000>;
+		reg-names = "funnel-base";
+
+		coresight-name = "coresight-funnel-apss";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+
+		out-ports {
+			port@0 {
+				reg = <0>;
+				funnel_apss_out_funnel_apss_merg: endpoint {
+					remote-endpoint =
+					    <&funnel_apss_merg_in_funnel_apss>;
+				};
+			};
+		};
+
+		in-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <0>;
+				funnel_apss_in_etm0: endpoint {
+					remote-endpoint =
+						<&etm0_out_funnel_apss>;
+				};
+			};
+
+			port@2 {
+				reg = <1>;
+				funnel_apss_in_etm1: endpoint {
+					remote-endpoint =
+						<&etm1_out_funnel_apss>;
+				};
+			};
+
+			port@3 {
+				reg = <2>;
+				funnel_apss_in_etm2: endpoint {
+					remote-endpoint =
+						<&etm2_out_funnel_apss>;
+				};
+			};
+
+			port@4 {
+				reg = <3>;
+				funnel_apss_in_etm3: endpoint {
+					remote-endpoint =
+						<&etm3_out_funnel_apss>;
+				};
+			};
+
+			port@5 {
+				reg = <4>;
+				funnel_apss_in_etm4: endpoint {
+					remote-endpoint =
+						<&etm4_out_funnel_apss>;
+				};
+			};
+
+			port@6 {
+				reg = <5>;
+				funnel_apss_in_etm5: endpoint {
+					remote-endpoint =
+						<&etm5_out_funnel_apss>;
+				};
+			};
+
+			port@7 {
+				reg = <6>;
+				funnel_apss_in_etm6: endpoint {
+					remote-endpoint =
+						<&etm6_out_funnel_apss>;
+				};
+			};
+
+			port@8 {
+				reg = <7>;
+				funnel_apss_in_etm7: endpoint {
+					remote-endpoint =
+						<&etm7_out_funnel_apss>;
+				};
+			};
+		};
+	};
+};
diff --git a/qcom/sm8150-dma-heaps.dtsi b/qcom/sm8150-dma-heaps.dtsi
index c2a1bed8..4c1aa3a5 100755
--- a/qcom/sm8150-dma-heaps.dtsi
+++ b/qcom/sm8150-dma-heaps.dtsi
@@ -31,8 +31,9 @@
 
 		qcom,qseecom {
 			qcom,dma-heap-name = "qcom,qseecom";
-			qcom,dma-heap-type = <HEAP_TYPE_CARVEOUT>;
+			qcom,dma-heap-type = <HEAP_TYPE_CMA>;
 			memory-region = <&qseecom_mem>;
+			qcom,uncached-heap;
 		};
 
 		qcom,qseecom_ta {
diff --git a/qcom/sm8150-thermal.dtsi b/qcom/sm8150-thermal.dtsi
index 7742408a..e7a931c2 100755
--- a/qcom/sm8150-thermal.dtsi
+++ b/qcom/sm8150-thermal.dtsi
@@ -204,6 +204,11 @@
 				qcom,qmi-dev-name = "cpuv_restriction_cold";
 				#cooling-cells = <2>;
 			};
+
+			cdsp_sw: cdsp_sw {
+				qcom,qmi-dev-name = "cdsp_sw";
+				#cooling-cells = <2>;
+			};
 		};
 
 		slpi {
@@ -266,6 +271,14 @@
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			gpu_cdev {
+				trip = <&gpuss0_trip0>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	gpuss-1 {
@@ -297,6 +310,14 @@
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			gpu1_cdev {
+				trip = <&gpuss1_trip0>;
+				cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+			};
+		};
 	};
 
 	pop-mem {
@@ -899,6 +920,18 @@
 				type = "passive";
 			};
 		};
+
+		cooling-maps {
+			hvx_cdev_lvl0 {
+				trip = <&q6_hvx_step0>;
+				cooling-device = <&cdsp_sw 0 6>;
+			};
+
+			hvx_cdev_lvl1 {
+				trip = <&q6_hvx_step1>;
+				cooling-device = <&cdsp_sw 6 6>;
+			};
+		};
 	};
 
 	aoss-1 {
diff --git a/qcom/sm8150-usb.dtsi b/qcom/sm8150-usb.dtsi
index 76042da1..1a89d08e 100755
--- a/qcom/sm8150-usb.dtsi
+++ b/qcom/sm8150-usb.dtsi
@@ -134,6 +134,7 @@
 				"ss_phy_irq","dm_hs_phy_irq";
 		qcom,use-pdc-interrupts;
 		qcom,default-mode-host;
+		qcom,force-gen1;
 		qcom,host-poweroff-in-pm-suspend;
 
 		USB3_GDSC-supply = <&usb30_sec_gdsc>;
@@ -172,7 +173,6 @@
 			snps,usb2-gadget-lpm-disable;
 			snps,dis-u1-entry-quirk;
 			snps,dis-u2-entry-quirk;
-			snps,force-gen1;
 			tx-fifo-resize;
 			maximum-speed = "super-speed";
 			dr_mode = "otg";
diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi
index 843eabbb..149b1198 100755
--- a/qcom/sm8150.dtsi
+++ b/qcom/sm8150.dtsi
@@ -1225,7 +1225,6 @@
 		iommus = <&apps_smmu 0x300 0x0>;
 		qcom,iommu-dma = "bypass";
 		dma-coherent;
-		qcom,disable-lpm;
 
 		status = "disabled";
 		qos0 {
@@ -2082,6 +2081,8 @@
 				"l3-scu-errirq",
 				"l3-scu-faultirq";
 	};
+
+	msm_gpu: qcom,kgsl-3d0@2c00000 { };
 };
 
 &firmware {
@@ -2121,6 +2122,7 @@
 #include "sm8150-slpi-pinctrl.dtsi"
 #include "sm8150-gdsc.dtsi"
 #include "msm-arm-smmu-sm8150.dtsi"
+#include "sm8150-coresight.dtsi"
 #include "sm8150-smp2p.dtsi"
 #include "sm8150-usb.dtsi"
 #include "sm8150-debug.dtsi"