diff options
| author | QC Publisher <qcpublisher@qti.qualcomm.com> | 2022-07-15 10:13:02 -0700 |
|---|---|---|
| committer | Andrew Evans <andrewevans@google.com> | 2022-08-26 19:14:28 +0000 |
| commit | 6ff51b23d14be1560c18c9cbc756b6b58da83ee6 (patch) | |
| tree | 71c00631c0ec5ee5b28b6b5856caacf7c897d54f | |
| parent | 85ab2df842a30453ae7a3cb66ad56c121c8fd3e8 (diff) | |
| download | devicetree-6ff51b23d14be1560c18c9cbc756b6b58da83ee6.tar.gz | |
Commit label r00236.2 - Post-CS2 0.0.236.2
TRACKING-ID:cafbf2af-4ecc-41ed-ba80-498b0a1e2a7f
104 files changed, 7237 insertions, 449 deletions
diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index b2de1ffd..38aa8617 100755 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -335,9 +335,15 @@ compatible = "qcom,direwolf-adas-rumi" compatible = "qcom,direwolf-adas-adp-star" compatible = "qcom,direwolf-adas-adp-ride" compatible = "qcom,lemans-rumi" -compatible = "qcom,lemans-adp-air" -compatible = "qcom,lemans-adp-star" +compatible = "qcom,lemans-ivi" +compatible = "qcom,lemans-ivi-adp-star" +compatible = "qcom,lemans-ivi-adp-air" +compatible = "qcom,lemans-adas-high" +compatible = "qcom,lemans-adas-high-adp-star" +compatible = "qcom,lemans-adas-high-adp-air" compatible = "qcom,quinvm" compatible = "qcom,sa410m-idp" compatible = "qcom,sa410m-qrd" compatible = "qcom,sa410m-rumi" +compatible = "qcom,sa415m-ccard" +compatible = "qcom,sa415m" diff --git a/bindings/arm/msm/qcom,llcc.txt b/bindings/arm/msm/qcom,llcc.txt index 2705ee9b..807e54e2 100755 --- a/bindings/arm/msm/qcom,llcc.txt +++ b/bindings/arm/msm/qcom,llcc.txt @@ -16,6 +16,7 @@ Properties: or "qcom,yupik-llcc" or "qcom,sm8150-llcc" or "qcom,sdmshrike-llcc" or "qcom,sm6150-llcc" or "qcom,direwolf-llcc" + or "qcom,lemans-llcc" "qcom,llcc-v2" must be appended for V2 hardware. - reg: diff --git a/bindings/interconnect/qcom,epss-l3.txt b/bindings/interconnect/qcom,epss-l3.txt index 0839062f..2103fe2d 100755 --- a/bindings/interconnect/qcom,epss-l3.txt +++ b/bindings/interconnect/qcom,epss-l3.txt @@ -12,6 +12,7 @@ Required properties : "qcom,shima-epss-l3-shared", "qcom,yupik-epss-l3-cpu", "qcom,direwolf-epss-l3-cpu"; + "qcom,lemans-epss-l3-cpu"; - reg : Address and length of the register set for the device - clock-names: should contain "xo", "alternate" - clocks: list of phandle and clock specifier pairs corresponding to diff --git a/bindings/pinctrl/qcom,pmic-gpio.txt b/bindings/pinctrl/qcom,pmic-gpio.txt index b3106f10..b63db7ca 100755 --- a/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/bindings/pinctrl/qcom,pmic-gpio.txt @@ -39,6 +39,7 @@ PMIC's from Qualcomm. "qcom,pm7325b-gpio" "qcom,pm5100-gpio" "qcom,pmx55-gpio" + "qcom,pm8775-gpio" And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio" if the device is on an spmi bus or an ssbi bus respectively diff --git a/bindings/pinctrl/qcom,sa415m-pinctrl.txt b/bindings/pinctrl/qcom,sa415m-pinctrl.txt new file mode 100755 index 00000000..4ddb63e7 --- /dev/null +++ b/bindings/pinctrl/qcom,sa415m-pinctrl.txt @@ -0,0 +1,199 @@ +Qualcomm Technologies, Inc. SA415M TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +SDXPOORWILLS platform. + +- compatible: + Usage: required + Value type: <string> + Definition: must be "qcom,sa415m-pinctrl" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: the base address and size of the TLMM register space + provided as "pinctrl_regs", optional base address of + PDC mux selection registers provided as "pdc_regs" + and optional base address of shared SPI config + registers provided as "spi_cfg_regs". + +- reg-names: + Usage: required + Value type: <prop-encoded-array> + Definition: Provides labels for the reg property. + + +- interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: <none> + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/interrupt-controller/irq.h> + +- gpio-controller: + Usage: required + Value type: <none> + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/gpio/gpio.h> + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: <string-array> + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins are: + gpio0-gpio149 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + +- function: + Usage: required + Value type: <string> + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + + blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio + +- bias-disable: + Usage: optional + Value type: <none> + Definition: The specified pins should be configured as no pull. + +- bias-pull-down: + Usage: optional + Value type: <none> + Definition: The specified pins should be configured as pull down. + +- bias-pull-up: + Usage: optional + Value type: <none> + Definition: The specified pins should be configured as pull up. + +- output-high: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + high. + Not valid for sdc pins. + +- output-low: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + low. + Not valid for sdc pins. + +- drive-strength: + Usage: optional + Value type: <u32> + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + tlmm: pinctrl@03900000 { + compatible = "qcom,sa415m-pinctrl"; + reg = <0x3900000 0x300000>, + <0xB204900 0x280>; + reg-names = "pinctrl", "pinctrl_reg"; + interrupts = <0 212 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; diff --git a/bindings/pinctrl/qcom,sa415m-pinctrl.yaml b/bindings/pinctrl/qcom,sa415m-pinctrl.yaml new file mode 100755 index 00000000..4a997b53 --- /dev/null +++ b/bindings/pinctrl/qcom,sa415m-pinctrl.yaml @@ -0,0 +1,198 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,sa415m-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SA415M TLMM block + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + SA415M platform. + +properties: + compatible: + Usage: required + Value type: <string> + Definition: must be "qcom,sa415m-pinctrl" + + reg: + Usage: required + Value type: <prop-encoded-array> + Definition: the base address and size of the TLMM register space. + + interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: should specify the TLMM summary IRQ. + + interrupt-controller: + Usage: required + Value type: <none> + Definition: identifies this node as an interrupt controller + + #interrupt-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/interrupt-controller/irq.h> + + gpio-controller: + Usage: required + Value type: <none> + Definition: identifies this node as a gpio controller + + #gpio-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/gpio/gpio.h> + + wakeup-parent: + Usage: optional + Value type: <phandle> + Definition: A phandle to the wakeup interrupt controller for the SoC. + + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for + a general description of GPIO and interrupt bindings. + + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + The pin configuration nodes act as a container for an arbitrary number of + subnodes. Each of these subnodes represents some desired configuration for a + pin, a group, or a list of pins or groups. This configuration can include the + mux function to select on those pin(s)/group(s), and various pin configuration + parameters, such as pull-up, drive strength, etc. + + + PIN CONFIGURATION NODES: + + The name of each subnode is not important; all subnodes should be enumerated + and processed purely based on their content. + + Each subnode only affects those parameters that are explicitly listed. In + other words, a subnode that lists a mux function but no pin configuration + parameters implies no information about any pin configuration parameters. + Similarly, a pin subnode that describes a pullup parameter implies no + information about e.g. the mux function. + + + The following generic properties as defined in pinctrl-bindings.txt are valid + to specify in a pin configuration subnode: + + pins: + Usage: required + Value type: <string-array> + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins: + gpio0-gpio155 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + + function: + Usage: required + Value type: <string> + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values: + blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio + + bias-disable: + Usage: optional + Value type: <none> + Definition: The specified pins should be configured as no pull. + + bias-pull-down: + Usage: optional + Value type: <none> + Definition: The specified pins should be configured as pull down. + + bias-pull-up: + Usage: optional + Value type: <none> + Definition: The specified pins should be configured as pull up. + + output-high: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven high. + Not valid for sdc pins. + + output-low: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven low. + Not valid for sdc pins. + + drive-strength: + Usage: optional + Value type: <u32> + Definition: Selects the drive strength for the specified pins, in mA. + Valid values: 2, 4, 6, 8, 10, 12, 14 and 16 + +examples: + - | + tlmm: pinctrl@03900000 { + compatible = "qcom,sa415m-pinctrl"; + reg = <0x3900000 0x300000>, + <0xB204900 0x280>; + reg-names = "pinctrl", "pinctrl_reg"; + interrupts = <0 212 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; diff --git a/bindings/sound/qcom-audio-dev.txt b/bindings/sound/qcom-audio-dev.txt index 3c0ac9ca..f780188d 100755 --- a/bindings/sound/qcom-audio-dev.txt +++ b/bindings/sound/qcom-audio-dev.txt @@ -346,6 +346,13 @@ Required properties: property enable apr driver to receive subsystem up/down notification from modem/adsp. +Optional properties: + + - compatible : "qcom,msm-audio-apr-dummy" + Add this compatible as child device to msm-audio-apr device. + This child device is added after lpass is up to invoke + deferred probe devices. + * Bolero codec Required properties: @@ -2822,6 +2829,79 @@ Example: "msm-dai-q6-dev.32770", "msm-dai-q6-dev.32774"; }; +* SDX ASoC Auto Machine driver + +Required properties: +- compatible : "qcom,sdx-asoc-snd-auto" +- qcom,model : The user-visible name of this sound card. +- qcom,prim_mi2s_aux_master : Handle to prim_master pinctrl configurations +- qcom,prim_mi2s_aux_slave : Handle to prim_slave pinctrl configurations +- qcom,sec_mi2s_aux_master : Handle to sec_master pinctrl configurations +- qcom,sec_mi2s_aux_slave : Handle to sec_slave pinctrl configurations +- asoc-platform: This is phandle list containing the references to platform device + nodes that are used as part of the sound card dai-links. +- asoc-platform-names: This property contains list of platform names. The order of + the platform names should match to that of the phandle order + given in "asoc-platform". +- asoc-cpu: This is phandle list containing the references to cpu dai device nodes + that are used as part of the sound card dai-links. +- asoc-cpu-names: This property contains list of cpu dai names. The order of the + cpu dai names should match to that of the phandle order give + in "asoc-cpu". The cpu names are in the form of "%s.%d" form, + where the id (%d) field represents the back-end AFE port id that + this CPU dai is associated with. +- asoc-codec: This is phandle list containing the references to codec dai device + nodes that are used as part of the sound card dai-links. +- asoc-codec-names: This property contains list of codec dai names. The order of the + codec dai names should match to that of the phandle order given + in "asoc-codec". + +Example: + + sound-auto { + compatible = "qcom,sdx-asoc-snd-auto"; + qcom,model = "sdx-auto-i2s-snd-card"; + qcom,prim_mi2s_aux_master = <&prim_master>; + qcom,prim_mi2s_aux_slave = <&prim_slave>; + qcom,sec_mi2s_aux_master = <&sec_master>; + qcom,sec_mi2s_aux_slave = <&sec_slave>; + + asoc-platform = <&pcm0>, <&pcm1>, <&voip>, <&voice>, + <&loopback>, <&hostless>, <&afe>, <&routing>, + <&pcm_dtmf>, <&host_pcm>, <&compress>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-voip-dsp", "msm-pcm-voice", + "msm-pcm-loopback", "msm-pcm-hostless", + "msm-pcm-afe", "msm-pcm-routing", + "msm-pcm-dtmf", "msm-voice-host-pcm", + "msm-compress-dsp"; + asoc-cpu = <&dai_pri_auxpcm>, <&mi2s_prim>, <&mi2s_sec>, + <&dtmf_tx>, + <&rx_capture_tx>, <&rx_playback_rx>, + <&tx_capture_tx>, <&tx_playback_rx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_sec_auxpcm>, <&incall2_record_rx>, + <&incall_music_2_rx>, <&incall_music_dl_rx>; + asoc-cpu-names = "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-stub-dev.4", "msm-dai-stub-dev.5", + "msm-dai-stub-dev.6", "msm-dai-stub-dev.7", + "msm-dai-stub-dev.8", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-dev.32769", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.32774"; + asoc-codec = <&tlv320aic3x_codec>, <&stub_codec>; + asoc-codec-names = "tlv320aic3x-codec", "msm-stub-codec.1"; + }; + * SA8295 ASoC Machine driver Required properties: diff --git a/bindings/thermal/qti-qmi-sensor.txt b/bindings/thermal/qti-qmi-sensor.txt index f414fbda..b5bb0955 100755 --- a/bindings/thermal/qti-qmi-sensor.txt +++ b/bindings/thermal/qti-qmi-sensor.txt @@ -101,6 +101,8 @@ Subsystem properties: 68. qfe_wtr_pa6_fr1 69. qfe_ret_pa1 70. qfe_ret_pa1_fr1 + 71. sdr0_pa + 72. sdr1_pa Example: diff --git a/bindings/ufs/ufs-qcom.txt b/bindings/ufs/ufs-qcom.txt index 054ac776..20422a40 100755 --- a/bindings/ufs/ufs-qcom.txt +++ b/bindings/ufs/ufs-qcom.txt @@ -24,6 +24,8 @@ Required properties: present on holi chipset. "qcom,ufs-phy-qmp-v3-660" for V3 ufs phy present on SM6150 chipset. + "qcom,ufs-phy-qmp-v4-waipio" for V4 ufs phy + present on Lemans chipset. - reg : should contain PHY register address space (mandatory), - reg-names : indicates various resources passed to driver (via reg proptery) by name. diff --git a/qcom/Makefile b/qcom/Makefile index 0200d916..1ef071ea 100755 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -531,6 +531,19 @@ dtb-$(CONFIG_ARCH_SA515M) += sa515m-ccard.dtb \ sa515m-v2-ttp-usb-ep.dtb \ sa515m-v2-ttp.dtb +dtb-$(CONFIG_ARCH_SA415M) += sa415m-ccard.dtb \ + sa415m-ccard-usb-ep.dtb \ + sa415m-ccard-ga.dtb \ + sa415m-ccard-pcie-ep.dtb \ + sa415m-ccard-usb-ep-ga.dtb \ + sa415m-cdp.dtb \ + sa415m-mtp-256.dtb \ + sa415m-ttp-pcie-ep.dtb \ + sa415m-ttp-usb-ep.dtb \ + sa415m-ttp.dtb \ + sa415m-v2-cdp.dtb \ + sa415m-v2-mtp.dtb + ifeq ($(CONFIG_ARCH_SHIMA), y) ifeq ($(CONFIG_ARCH_QTI_VM), y) dtb-$(CONFIG_ARCH_QTI_VM) += shima-vm-rumi.dtb \ @@ -641,16 +654,22 @@ endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_LEMANS) += lemans-rumi-overlay.dtbo \ - lemans-adp-air-overlay.dtbo \ - lemans-adp-star-overlay.dtbo - -lemans-rumi-overlay.dtbo-base := lemans.dtb -lemans-adp-air-overlay.dtbo-base := lemans.dtb -lemans-adp-star-overlay.dtbo-base := lemans.dtb + lemans-adas-high-adp-air-overlay.dtbo \ + lemans-adas-high-adp-star-overlay.dtbo \ + lemans-ivi-adp-air-overlay.dtbo \ + lemans-ivi-adp-star-overlay.dtbo + +lemans-rumi-overlay.dtbo-base := lemans-adas-high.dtb +lemans-adas-high-adp-air-overlay.dtbo-base := lemans-adas-high.dtb +lemans-adas-high-adp-star-overlay.dtbo-base := lemans-adas-high.dtb +lemans-ivi-adp-air-overlay.dtbo-base := lemans-ivi.dtb +lemans-ivi-adp-star-overlay.dtbo-base := lemans-ivi.dtb else dtb-$(CONFIG_ARCH_LEMANS) += lemans-rumi.dtb \ - lemans-adp-air.dtb \ - lemans-adp-star.dtb + lemans-adas-high-adp-air.dtb \ + lemans-adas-high-adp-star.dtb \ + lemans-ivi-adp-air.dtb \ + lemans-ivi-adp-star.dtb endif always := $(dtb-y) diff --git a/qcom/direwolf-audio.dtsi b/qcom/direwolf-audio.dtsi index e1e59c1a..64ea89f3 100755 --- a/qcom/direwolf-audio.dtsi +++ b/qcom/direwolf-audio.dtsi @@ -1,4 +1,5 @@ #include "msm-audio-lpass.dtsi" +#include "msm-arm-smmu-direwolf.dtsi" / { aliases { @@ -7,13 +8,22 @@ }; +&soc { + spf_core_platform: spf_core_platform { + compatible = "qcom,spf-core-platform"; + }; + + audio_pkt_core_platform: audio-pkt-platform { + compatible = "qcom,audio-pkt-core-platform"; + }; +}; + &msm_audio_ion { iommus = <&apps_smmu 0x0c01 0x0>; qcom,smmu-sid-mask = /bits/ 64 <0xf>; /delete-property/ qcom,iommu-dma-addr-pool; }; - &soc { tdm_pri_rx: qcom,msm-dai-tdm-pri-rx { compatible = "qcom,msm-dai-tdm"; @@ -1093,7 +1103,6 @@ }; - &audio_apr { q6core: qcom,q6core-audio { compatible = "qcom,q6core-audio"; @@ -1288,6 +1297,59 @@ }; }; +&spf_core_platform { + spf_msm_audio_ion: qcom,spf-msm-audio-ion { + compatible = "qcom,msm-audio-ion"; + qcom,smmu-version = <2>; + qcom,smmu-enabled; + iommus = <&apps_smmu 0x0c01 0x0>; + qcom,smmu-sid-mask = /bits/ 64 <0xf>; + }; + + spf_tdm_pri_rx: qcom,spf-msm-dai-tdm-pri-rx { + compatible = "qcom,msm-pcm-pinctrl"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pri_tdm_sck_active &pri_tdm_ws_active + &pri_tdm_din_active &pri_tdm_dout_active>; + pinctrl-1 = <&pri_tdm_sck_sleep &pri_tdm_ws_sleep + &pri_tdm_din_sleep &pri_tdm_dout_sleep>; + #gpio-cells = <0>; + }; + + spf_tdm_tert_rx: qcom,spf-msm-dai-tdm-tert-rx { + compatible = "qcom,msm-pcm-pinctrl"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&tert_tdm_sck_active &tert_tdm_ws_active + &tert_tdm_din_active &tert_tdm_dout_active>; + pinctrl-1 = <&tert_tdm_sck_sleep &tert_tdm_ws_sleep + &tert_tdm_din_sleep &tert_tdm_dout_sleep>; + #gpio-cells = <0>; + }; + + spf_internal_mclk1: qcom,spf-msm-internal-mclk1 { + compatible = "qcom,msm-pcm-pinctrl"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&audio_internal_mclk1_active>; + pinctrl-1 = <&audio_internal_mclk1_sleep>; + #gpio-cells = <0>; + }; + + spf_snd_8295: spf-sound-adp-star { + compatible = "qcom,sa8295-asoc-snd-adp-star"; + qcom,model = "sa8295-adp-star-snd-card"; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; + + qcom,pri-tdm-gpios = <&spf_tdm_pri_rx>; + qcom,tert-tdm-gpios = <&spf_tdm_tert_rx>; + qcom,internal-mclk1-gpios = <&spf_internal_mclk1>; + + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + }; +}; + &qupv3_se21_i2c { status = "ok"; }; diff --git a/qcom/direwolf-cnss-dual.dtsi b/qcom/direwolf-cnss-dual.dtsi index fd85d732..9ca45c52 100755 --- a/qcom/direwolf-cnss-dual.dtsi +++ b/qcom/direwolf-cnss-dual.dtsi @@ -67,7 +67,6 @@ qcom,wlan-rc-num = <4>; qcom,pld_bus_ops_name = "pld_pcie_cnss2"; qcom,bus-type=<0>; - qcom,qrtr_node_id = <0x10>; qcom,notify-modem-status; #address-cells=<1>; @@ -112,7 +111,7 @@ chip_cfg@1 { reg = <0xb0000000 0x10000>; reg-names = "smmu_iova_ipa"; - + qcom,qrtr_node_id = <0x10>; supported-ids = <0x1101>; wlan_vregs = "vdd-wlan-vl", "vdd-wlan-vm", "vdd-wlan-vh"; @@ -338,7 +337,6 @@ qcom,wlan-rc-num = <0>; qcom,pld_bus_ops_name = "pld_pcie_cnss0"; qcom,bus-type=<0>; - qcom,qrtr_node_id = <0x20>; qcom,notify-modem-status; #address-cells=<1>; @@ -382,7 +380,7 @@ chip_cfg@1 { reg = <0xd0000000 0x10000>; reg-names = "smmu_iova_ipa"; - + qcom,qrtr_node_id = <0x20>; supported-ids = <0x1101>; wlan_vregs = "vdd-wlan-vl", "vdd-wlan-vm", "vdd-wlan-vh"; diff --git a/qcom/direwolf-vm-ufs.dtsi b/qcom/direwolf-vm-ufs.dtsi index 37ce81e3..9f4462ff 100755 --- a/qcom/direwolf-vm-ufs.dtsi +++ b/qcom/direwolf-vm-ufs.dtsi @@ -180,10 +180,6 @@ qcom,iommu-dma = "bypass"; dma-coherent; - qcom,disable-lpm; - rpm-level = <0>; - spm-level = <0>; - status = "disabled"; }; }; diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 8645ebba..8fe8f655 100755 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,direwolf.h> #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h> +#include <dt-bindings/sound/qcom,gpr.h> #define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) #define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;} @@ -2006,6 +2007,29 @@ qcom,notify-edges = <&glink_cdsp0>, <&glink_cdsp1>; }; + + audio_gpr: qcom,gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,intents = <0x200 20>; + reg = <GPR_DOMAIN_ADSP>; + + spf_core { + compatible = "qcom,spf_core"; + reg = <GPR_SVC_ADSP_CORE>; + }; + + audio-pkt { + compatible = "qcom,audio-pkt"; + qcom,audiopkt-ch-name = "apr_audio_svc"; + reg = <GPR_SVC_MAX>; + }; + + audio_prm { + compatible = "qcom,audio_prm"; + reg = <GPR_SVC_ASM>; + }; + }; }; glink_cdsp0: cdsp0 { diff --git a/qcom/kona-cvp.dtsi b/qcom/kona-cvp.dtsi index e910b6ae..94df267a 100755 --- a/qcom/kona-cvp.dtsi +++ b/qcom/kona-cvp.dtsi @@ -30,13 +30,23 @@ resets = <&clock_gcc GCC_VIDEO_AXI1_CLK_ARES>, <&clock_videocc VIDEO_CC_MVS1C_CLK_ARES>; reset-names = "cvp_axi_reset", "cvp_core_reset"; + reset-power-status = <0x2 0x1>; qcom,reg-presets = <0xB0088 0x0>; + qcom,ipcc-reg = <0x400000 0x100000>; + + pas-id = <26>; + memory-region = <&pil_cvp_mem>; + + /* CVP Firmware ELF image name */ + cvp,firmware-name = "cvpss"; /* Buses */ cvp_cnoc { compatible = "qcom,msm-cvp,bus"; label = "cvp-cnoc"; + qcom,bus-master = <MASTER_APPSS_PROC>; + qcom,bus-slave = <SLAVE_VENUS_CFG>; qcom,bus-governor = "performance"; qcom,bus-range-kbps = <1000 1000>; }; @@ -44,6 +54,8 @@ cvp_bus_ddr { compatible = "qcom,msm-cvp,bus"; label = "cvp-ddr"; + qcom,bus-master = <MASTER_VIDEO_PROC>; + qcom,bus-slave = <SLAVE_EBI1>; qcom,bus-governor = "performance"; qcom,bus-range-kbps = <1000 6533000>; }; @@ -55,7 +67,9 @@ iommus = <&apps_smmu 0x2120 0x400>; buffer-types = <0xfff>; + dma-coherent-hint-cached; qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; + qcom,iommu-faults = "non-fatal"; }; @@ -67,6 +81,7 @@ buffer-types = <0x741>; qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>; qcom,iommu-vmid = <0xB>; + qcom,iommu-faults = "non-fatal"; }; cvp_secure_pixel_cb { @@ -77,6 +92,7 @@ buffer-types = <0x106>; qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; qcom,iommu-vmid = <0xA>; + qcom,iommu-faults = "non-fatal"; }; /* Memory Heaps */ diff --git a/qcom/kona-pinctrl.dtsi b/qcom/kona-pinctrl.dtsi index 51c240c3..a7456b8e 100755 --- a/qcom/kona-pinctrl.dtsi +++ b/qcom/kona-pinctrl.dtsi @@ -500,160 +500,55 @@ }; }; - storage_cd: storage_cd { - mux { - pins = "gpio77"; - function = "gpio"; - }; - - config { - pins = "gpio77"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_clk_on: sdc2_clk_on { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_clk_off: sdc2_clk_off { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc2_clk_ds_400KHz: sdc2_clk_ds_400KHz { - config { + sdc2_on: sdc2_on { + clk { pins = "sdc2_clk"; bias-disable; /* NO pull */ drive-strength = <16>; /* 16 MA */ }; - }; - sdc2_clk_ds_50MHz: sdc2_clk_ds_50MHz { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_clk_ds_100MHz: sdc2_clk_ds_100MHz { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_clk_ds_200MHz: sdc2_clk_ds_200MHz { - config { - pins = "sdc2_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_cmd_on: sdc2_cmd_on { - config { + cmd { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; - }; - - sdc2_cmd_off: sdc2_cmd_off { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - sdc2_cmd_ds_400KHz: sdc2_cmd_ds_400KHz { - config { - pins = "sdc2_cmd"; + data { + pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; - }; - sdc2_cmd_ds_50MHz: sdc2_cmd_ds_50MHz { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ + sd-cd { + pins = "gpio77"; + drive-strength = <2>; + bias-pull-up; }; }; - sdc2_cmd_ds_100MHz: sdc2_cmd_ds_100MHz { - config { - pins = "sdc2_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ + sdc2_off: sdc2_off { + clk { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ }; - }; - sdc2_cmd_ds_200MHz: sdc2_cmd_ds_200MHz { - config { + cmd { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_data_on: sdc2_data_on { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_data_off: sdc2_data_off { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; - }; - sdc2_data_ds_400KHz: sdc2_data_ds_400KHz { - config { + data { pins = "sdc2_data"; bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_data_ds_50MHz: sdc2_data_ds_50MHz { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc2_data_ds_100MHz: sdc2_data_ds_100MHz { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ + drive-strength = <2>; /* 2 MA */ }; - }; - sdc2_data_ds_200MHz: sdc2_data_ds_200MHz { - config { - pins = "sdc2_data"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ + sd_cd { + pins = "gpio77"; + drive-strength = <2>; + bias-disable; }; }; diff --git a/qcom/kona-qrd.dtsi b/qcom/kona-qrd.dtsi index 5e3a766a..e595bfbb 100755 --- a/qcom/kona-qrd.dtsi +++ b/qcom/kona-qrd.dtsi @@ -750,21 +750,21 @@ }; &sdhc_2 { - vdd-supply = <&pm8150a_l9>; + vdd-supply = <&L9C>; qcom,vdd-voltage-level = <2950000 2960000>; qcom,vdd-current-level = <200 800000>; - vdd-io-supply = <&pm8150a_l6>; + vdd-io-supply = <&L6C>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; - pinctrl-names = "active", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; - status = "disabled"; + status = "ok"; }; &vendor { @@ -772,21 +772,20 @@ compatible = "qcom,qca6390"; pinctrl-names = "default"; pinctrl-0 = <&bt_en_sleep>; - qca,bt-reset-gpio = <&tlmm 21 0>; /* BT_EN */ - qca,bt-sw-ctrl-gpio = <&tlmm 124 0>; /* SW_CTRL */ - qca,bt-vdd-aon-supply = <&pm8150_s6>; - qca,bt-vdd-dig-supply = <&pm8009_s2>; - qca,bt-vdd-rfa1-supply = <&pm8150_s5>; - qca,bt-vdd-rfa2-supply = <&pm8150a_s8>; - qca,bt-vdd-asd-supply = <&pm8150_l16>; - - qca,bt-vdd-aon-voltage-level = <950000 950000>; - qca,bt-vdd-dig-voltage-level = <950000 952000>; - qca,bt-vdd-rfa1-voltage-level = <1900000 1900000>; - qca,bt-vdd-rfa2-voltage-level = <1350000 1350000>; - qca,bt-vdd-asd-voltage-level = <3024000 3304000>; - - qca,bt-vdd-asd-current-level = <10000>; + qcom,bt-reset-gpio = <&tlmm 21 0>; /* BT_EN */ + qcom,bt-sw-ctrl-gpio = <&tlmm 124 0>; /* SW_CTRL */ + qcom,bt-vdd-aon-supply = <&pm8150_s6>; + qcom,bt-vdd-dig-supply = <&pm8009_s2>; + qcom,bt-vdd-rfa1-supply = <&pm8150_s5>; + qcom,bt-vdd-rfa2-supply = <&pm8150a_s8>; + qcom,bt-vdd-asd-supply = <&pm8150_l16>; + + qcom,bt-vdd-aon-config = <950000 950000 0 1>; + qcom,bt-vdd-dig-config = <950000 952000 0 1>; + qcom,bt-vdd-rfa1-config = <1900000 1900000 0 1>; + qcom,bt-vdd-rfa2-config = <1350000 1350000 0 1>; + qcom,bt-vdd-asd-config = <3024000 3304000 10000 1>; + }; }; diff --git a/qcom/kona-usb.dtsi b/qcom/kona-usb.dtsi index e797a82a..0c2f73b5 100755 --- a/qcom/kona-usb.dtsi +++ b/qcom/kona-usb.dtsi @@ -304,7 +304,7 @@ clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, - <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&clock_gcc USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK>, <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", diff --git a/qcom/kona-v2.1-iot-rb5.dtsi b/qcom/kona-v2.1-iot-rb5.dtsi index 21863124..9b02566a 100755 --- a/qcom/kona-v2.1-iot-rb5.dtsi +++ b/qcom/kona-v2.1-iot-rb5.dtsi @@ -45,6 +45,10 @@ }; }; +&L11C { + regulator-always-on; +}; + <9611_pins { mux { pins = "gpio63"; @@ -100,7 +104,7 @@ &qupv3_se0_spi { status = "okay"; can@0 { - compatible = "microchip,mcp2517fd"; + compatible = "microchip,mcp2518fd"; reg = <0>; clocks = <&clk40M>; interrupt-parent = <&tlmm>; diff --git a/qcom/kona-vidc.dtsi b/qcom/kona-vidc.dtsi index 8f74bd02..667c191d 100755 --- a/qcom/kona-vidc.dtsi +++ b/qcom/kona-vidc.dtsi @@ -36,7 +36,7 @@ <&clock_videocc VIDEO_CC_MVS0C_CLK_ARES>; reset-names = "video_axi_reset", "video_core_reset"; - qcom,reg-presets = <0xB0088 0x0>; + qcom,reg-presets = <0xB0088 0x0 0x11>; /* Bus Interconnects */ interconnect-names = "venus-cnoc", "venus-ddr", "venus-llcc"; diff --git a/qcom/kona.dtsi b/qcom/kona.dtsi index 876d3140..9a59a631 100755 --- a/qcom/kona.dtsi +++ b/qcom/kona.dtsi @@ -54,6 +54,7 @@ pci-domain2 = &pcie2; /* PCIe2 domain */ serial0 = &qupv3_se2_2uart; /* RUMI */ mhi-netdev0 = &mhi_netdev_0; + hsuart0 = &qupv3_se6_4uart; }; cpus { @@ -878,7 +879,7 @@ }; snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive { - compatible = "qcom,devbw"; + compatible = "qcom,devfreq-icc"; governor = "powersave"; interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IMEM_CFG>; qcom,active-only; @@ -949,7 +950,7 @@ }; cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw { - compatible = "qcom,devbw"; + compatible = "qcom,devfreq-icc"; governor = "performance"; interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>; qcom,active-only; @@ -968,7 +969,7 @@ }; cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw { - compatible = "qcom,devbw-ddr"; + compatible = "qcom,devfreq-icc-ddr"; governor = "performance"; interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; qcom,active-only; @@ -986,7 +987,7 @@ }; npu_npu_llcc_bw: qcom,npu-npu-llcc-bw { - compatible = "qcom,devbw"; + compatible = "qcom,devfreq-icc"; governor = "performance"; interconnects = <&compute_noc MASTER_NPU &gem_noc SLAVE_LLCC>; operating-points-v2 = <&suspendable_llcc_bw_opp_table>; @@ -1008,7 +1009,7 @@ }; npu_llcc_ddr_bw: qcom,npu-llcc-ddr-bw { - compatible = "qcom,devbw-ddr"; + compatible = "qcom,devfreq-icc-ddr"; governor = "performance"; interconnects = <&gem_noc SLAVE_LLCC &mc_virt SLAVE_EBI1>; operating-points-v2 = <&suspendable_ddr_bw_opp_table>; @@ -1025,7 +1026,7 @@ }; npudsp_npu_ddr_bw: qcom,npudsp-npu-ddr-bw { - compatible = "qcom,devbw-ddr"; + compatible = "qcom,devfreq-icc-ddr"; governor = "performance"; interconnects = <&compute_noc MASTER_NPU &mc_virt SLAVE_EBI1>; operating-points-v2 = <&suspendable_ddr_bw_opp_table>; @@ -1047,7 +1048,7 @@ }; npu_npu_ddr_latfloor: qcom,npu-npu-ddr-latfloor { - compatible = "qcom,devbw-ddr"; + compatible = "qcom,devfreq-icc-ddr"; governor = "powersave"; interconnects = <&compute_noc MASTER_NPU &mc_virt SLAVE_EBI1>; operating-points-v2 = <&suspendable_ddr_bw_opp_table>; @@ -1070,7 +1071,7 @@ }; cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { - compatible = "qcom,devbw"; + compatible = "qcom,devfreq-icc"; governor = "performance"; interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>; qcom,active-only; @@ -1078,7 +1079,7 @@ }; cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat { - compatible = "qcom,devbw"; + compatible = "qcom,devfreq-icc"; governor = "performance"; interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>; qcom,active-only; @@ -1086,7 +1087,7 @@ }; cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat { - compatible = "qcom,devbw-ddr"; + compatible = "qcom,devfreq-icc-ddr"; governor = "performance"; interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; qcom,active-only; @@ -1094,7 +1095,7 @@ }; cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat { - compatible = "qcom,devbw-ddr"; + compatible = "qcom,devfreq-icc-ddr"; governor = "performance"; interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; qcom,active-only; @@ -1102,7 +1103,7 @@ }; cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor { - compatible = "qcom,devbw-ddr"; + compatible = "qcom,devfreq-icc-ddr"; governor = "performance"; interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; qcom,active-only; @@ -1309,7 +1310,7 @@ }; snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive { - compatible = "qcom,devbw"; + compatible = "qcom,devfreq-icc"; governor = "powersave"; interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IMEM_CFG>; qcom,active-only; @@ -2920,8 +2921,19 @@ }; }; + aggre1_noc: interconnect@16E0000 { + reg = <0x16E0000 0x1F180>; + compatible = "qcom,kona-aggre1_noc"; + #interconnect-cells = <1>; + qcom,bcm-voter-names = "hlos"; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; + }; + aggre2_noc: interconnect@1700000 { - reg = <0x1700000 0x3B100>; + reg = <0x1700000 0x3D180>; compatible = "qcom,kona-aggre2_noc"; #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; @@ -2959,7 +2971,7 @@ }; gem_noc: interconnect@9100000 { - reg = <0x9100000 0xAE200>; + reg = <0x9100000 0xB4000>; compatible = "qcom,kona-gem_noc"; #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos", "disp"; @@ -2997,17 +3009,6 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; - aggre1_noc: interconnect@16E0000 { - reg = <0x16E0000 0xD080>; - compatible = "qcom,kona-aggre1_noc"; - #interconnect-cells = <1>; - qcom,bcm-voter-names = "hlos"; - qcom,bcm-voters = <&apps_bcm_voter>; - clocks = <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; - }; - ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>, <0x1d90000 0x8000>; /* PHY regs */ reg-names = "phy_mem", "ufs_ice"; @@ -3153,8 +3154,7 @@ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - qcom,bus-width = <4>; - qcom,large-address-bus; + bus-width = <4>; interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>; @@ -3190,28 +3190,26 @@ 100750000 200000000 4294967295>; qcom,restore-after-cx-collapse; - - qcom,clk-rates = <400000 20000000 25000000 - 50000000 100000000 201500000>; - qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", - "SDR104"; - qcom,devfreq,freq-table = <50000000 201500000>; clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>, <&clock_gcc GCC_SDCC2_APPS_CLK>; - clock-names = "iface_clk", "core_clk"; - - /* PM QoS */ - qcom,pm-qos-irq-type = "affine_irq"; - qcom,pm-qos-irq-latency = <44 44>; - qcom,pm-qos-cpu-groups = <0x3f 0xc0>; - qcom,pm-qos-legacy-latency-us = <44 44>, <44 44>; + clock-names = "iface", "core"; /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */ qcom,dll-hsr-list = <0x0007642C 0xA800 0x10 0x2C010800 0x80040868>; status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <44>; + }; + + qos1 { + mask = <0xf0>; + vote = <44>; + }; }; ipcc_mproc: qcom,ipcc@408000 { @@ -3931,7 +3929,7 @@ clock-names = "xo"; qcom,proxy-clock-names = "xo"; qcom,pil-generic-irq-handler; - status = "disabled"; + status = "ok"; qcom,signal-aop; qcom,complete-ramdump; @@ -4150,7 +4148,7 @@ qcom,ce-hw-shared; qcom,bam-ee = <0>; interconnect-names = "data_path"; - interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; qcom,smmu-s1-enable; qcom,no-clock-support; iommus = <&apps_smmu 0x0586 0x0011>, @@ -4191,7 +4189,7 @@ qcom,ce-hw-shared; qcom,clk-mgmt-sus-res; interconnect-names = "data_path"; - interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; qcom,use-sw-aes-cbc-ecb-ctr-algo; qcom,use-sw-aes-xts-algo; qcom,use-sw-aes-ccm-algo; @@ -4764,7 +4762,6 @@ qcom,wlan-rc-num = <0>; qcom,wlan-ramdump-dynamic = <0x420000>; qcom,smmu-s1-enable; - qcom,converged-dt; cnss-daemon-support; qcom,cmd_db_name = "smpf2"; qcom,set-wlaon-pwr-ctrl; @@ -4970,15 +4967,6 @@ bits = <7 1>; }; }; - - clocks { - usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk { - compatible = "fixed-clock"; - clock-frequency = <1000>; - clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk"; - #clock-cells = <0>; - }; - }; }; #include "kona-regulators.dtsi" diff --git a/qcom/lemans-adas-high-adp-air-overlay.dts b/qcom/lemans-adas-high-adp-air-overlay.dts new file mode 100755 index 00000000..b0a45845 --- /dev/null +++ b/qcom/lemans-adas-high-adp-air-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "lemans-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans ADAS HIGH ADP AIR"; + compatible = "qcom,lemans-adas-high", "qcom,lemans", "qcom,adp-air", "qcom,lemans-adas-high-adp-air"; + qcom,msm-id = <533 0x10000>; + qcom,board-id = <0x1010019 0>; +}; diff --git a/qcom/lemans-adas-high-adp-air.dts b/qcom/lemans-adas-high-adp-air.dts new file mode 100755 index 00000000..dcbae540 --- /dev/null +++ b/qcom/lemans-adas-high-adp-air.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "lemans-adas-high.dtsi" +#include "lemans-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans ADAS HIGH ADP AIR"; + compatible = "qcom,lemans-adas-high", "qcom,lemans", "qcom,adp-air", "qcom,lemans-adas-high-adp-air"; +}; diff --git a/qcom/lemans-adas-high-adp-star-overlay.dts b/qcom/lemans-adas-high-adp-star-overlay.dts new file mode 100755 index 00000000..26b74371 --- /dev/null +++ b/qcom/lemans-adas-high-adp-star-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "lemans-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans ADAS HIGH ADP STAR"; + compatible = "qcom,lemans-adas-high", "qcom,lemans", "qcom,adp-star", "qcom,lemans-adas-high-adp-star"; + qcom,msm-id = <533 0x10000>; + qcom,board-id = <0x10019 0>; +}; diff --git a/qcom/lemans-adas-high-adp-star.dts b/qcom/lemans-adas-high-adp-star.dts new file mode 100755 index 00000000..c3c26dd9 --- /dev/null +++ b/qcom/lemans-adas-high-adp-star.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "lemans-adas-high.dtsi" +#include "lemans-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans ADAS HIGH ADP STAR"; + compatible = "qcom,lemans-adas-high", "qcom,lemans", "qcom,adp-star", "qcom,lemans-adas-high-adp-star"; +}; diff --git a/qcom/lemans-adas-high.dts b/qcom/lemans-adas-high.dts new file mode 100755 index 00000000..7fb12d85 --- /dev/null +++ b/qcom/lemans-adas-high.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +#include "lemans-adas-high.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Lemans ADAS HIGH SoC"; + compatible = "qcom,lemans-adas-high", "qcom,lemans"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/lemans-adas-high.dtsi b/qcom/lemans-adas-high.dtsi new file mode 100755 index 00000000..6db38a9f --- /dev/null +++ b/qcom/lemans-adas-high.dtsi @@ -0,0 +1,7 @@ +#include "lemans.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. LeMans ADAS HIGH SoC"; + compatible = "qcom,lemans-adas-high", "qcom,lemans"; + qcom,msm-id = <533 0x10000>; +}; diff --git a/qcom/lemans-adp-air-overlay.dts b/qcom/lemans-adp-air-overlay.dts deleted file mode 100755 index 26b4fed1..00000000 --- a/qcom/lemans-adp-air-overlay.dts +++ /dev/null @@ -1,10 +0,0 @@ -/dts-v1/; -/plugin/; - -#include "lemans-adp-air.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Lemans ADP AIR"; - compatible = "qcom,lemans", "qcom,adp-air", "qcom,lemans-adp-air"; - qcom,board-id = <0x1010019 0>; -}; diff --git a/qcom/lemans-adp-air.dts b/qcom/lemans-adp-air.dts deleted file mode 100755 index 9f58cd5b..00000000 --- a/qcom/lemans-adp-air.dts +++ /dev/null @@ -1,8 +0,0 @@ -/dts-v1/; - -#include "lemans-adp-air.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Lemans ADP AIR"; - compatible = "qcom,lemans", "qcom,adp-air", "qcom,lemans-adp-air"; -}; diff --git a/qcom/lemans-adp-common.dtsi b/qcom/lemans-adp-common.dtsi index 612056c7..a71710fe 100755 --- a/qcom/lemans-adp-common.dtsi +++ b/qcom/lemans-adp-common.dtsi @@ -1,7 +1,49 @@ -#include "lemans.dtsi" +#include "lemans-pmic-overlay.dtsi" -/ { - model = "Qualcomm Technologies, Inc. Lemans ADP"; - compatible = "qcom,lemans", "qcom,adp"; - qcom,board-id = <25 0>; +&soc { + +}; + +&pm8775_3_gpios { + usb201_vbus_boost { + usb20_vbus_boost_default: usb20_vbus_boost_default { + pins = "gpio3"; + function = "normal"; + output-high; + power-source = <0>; + }; + + usb21_vbus_boost_default: usb21_vbus_boost_default { + pins = "gpio10"; + function = "normal"; + output-high; + power-source = <0>; + }; + }; +}; + +&pm8775_2_gpios { + usb22_vbus_boost { + usb22_vbus_boost_default: usb22_vbus_boost_default { + pins = "gpio9"; + function = "normal"; + output-high; + power-source = <0>; + }; + }; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb20_vbus_boost_default>; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb21_vbus_boost_default>; +}; + +&usb2 { + pinctrl-names = "default"; + pinctrl-0 = <&usb22_vbus_boost_default>; }; diff --git a/qcom/lemans-adp-star-overlay.dts b/qcom/lemans-adp-star-overlay.dts deleted file mode 100755 index 8cb6127f..00000000 --- a/qcom/lemans-adp-star-overlay.dts +++ /dev/null @@ -1,10 +0,0 @@ -/dts-v1/; -/plugin/; - -#include "lemans-adp-star.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Lemans ADP STAR"; - compatible = "qcom,lemans", "qcom,adp-star", "qcom,lemans-adp-star"; - qcom,board-id = <0x10019 0>; -}; diff --git a/qcom/lemans-adp-star.dts b/qcom/lemans-adp-star.dts deleted file mode 100755 index 6babf5b4..00000000 --- a/qcom/lemans-adp-star.dts +++ /dev/null @@ -1,8 +0,0 @@ -/dts-v1/; - -#include "lemans-adp-star.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Lemans ADP STAR"; - compatible = "qcom,lemans", "qcom,adp-star", "qcom,lemans-adp-star"; -}; diff --git a/qcom/lemans-ion.dtsi b/qcom/lemans-ion.dtsi index fbd71987..5e5f5899 100755 --- a/qcom/lemans-ion.dtsi +++ b/qcom/lemans-ion.dtsi @@ -10,5 +10,11 @@ reg = <ION_SYSTEM_HEAP_ID>; qcom,ion-heap-type = "MSM_SYSTEM"; }; + + qcom,ion-heap@22 { /* ADSP HEAP */ + reg = <ION_ADSP_HEAP_ID>; + memory-region = <&adsp_mem>; + qcom,ion-heap-type = "DMA"; + }; }; }; diff --git a/qcom/lemans-ivi-adp-air-overlay.dts b/qcom/lemans-ivi-adp-air-overlay.dts new file mode 100755 index 00000000..a9e55687 --- /dev/null +++ b/qcom/lemans-ivi-adp-air-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "lemans-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans IVI ADP AIR"; + compatible = "qcom,lemans-ivi", "qcom,lemans", "qcom,adp-air", "qcom,lemans-ivi-adp-air"; + qcom,msm-id = <532 0x10000>; + qcom,board-id = <0x1010019 0>; +}; diff --git a/qcom/lemans-ivi-adp-air.dts b/qcom/lemans-ivi-adp-air.dts new file mode 100755 index 00000000..7d5daad2 --- /dev/null +++ b/qcom/lemans-ivi-adp-air.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "lemans-ivi.dtsi" +#include "lemans-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans IVI ADP AIR"; + compatible = "qcom,lemans-ivi", "qcom,lemans", "qcom,adp-air", "qcom,lemans-ivi-adp-air"; +}; diff --git a/qcom/lemans-ivi-adp-star-overlay.dts b/qcom/lemans-ivi-adp-star-overlay.dts new file mode 100755 index 00000000..af6b9692 --- /dev/null +++ b/qcom/lemans-ivi-adp-star-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "lemans-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans IVI ADP STAR"; + compatible = "qcom,lemans-ivi", "qcom,lemans", "qcom,adp-star", "qcom,lemans-ivi-adp-star"; + qcom,msm-id = <532 0x10000>; + qcom,board-id = <0x10019 0>; +}; diff --git a/qcom/lemans-ivi-adp-star.dts b/qcom/lemans-ivi-adp-star.dts new file mode 100755 index 00000000..03cec51d --- /dev/null +++ b/qcom/lemans-ivi-adp-star.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "lemans-ivi.dtsi" +#include "lemans-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans IVI ADP STAR"; + compatible = "qcom,lemans-ivi", "qcom,lemans", "qcom,adp-star", "qcom,lemans-ivi-adp-star"; +}; diff --git a/qcom/lemans-ivi.dts b/qcom/lemans-ivi.dts new file mode 100755 index 00000000..24cb48e5 --- /dev/null +++ b/qcom/lemans-ivi.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +#include "lemans-ivi.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Lemans IVI SoC"; + compatible = "qcom,lemans-ivi", "qcom,lemans"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/lemans-ivi.dtsi b/qcom/lemans-ivi.dtsi new file mode 100755 index 00000000..dcf35584 --- /dev/null +++ b/qcom/lemans-ivi.dtsi @@ -0,0 +1,7 @@ +#include "lemans.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. LeMans IVI SoC"; + compatible = "qcom,lemans-ivi", "qcom,lemans"; + qcom,msm-id = <532 0x10000>; +}; diff --git a/qcom/lemans-pcie.dtsi b/qcom/lemans-pcie.dtsi index f054ff77..d7592de9 100755 --- a/qcom/lemans-pcie.dtsi +++ b/qcom/lemans-pcie.dtsi @@ -48,10 +48,13 @@ gdsc-vdd-supply = <&gcc_pcie_0_gdsc>; vreg-1p8-supply = <&L1C>; vreg-0p9-supply = <&L5A>; + vreg-cx-supply = <&VDD_CX_LEVEL>; vreg-mx-supply = <&VDD_MXC_LEVEL>; qcom,vreg-1p8-voltage-level = <1200000 1200000 25800>; qcom,vreg-0p9-voltage-level = <880000 880000 186000>; + qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX + RPMH_REGULATOR_LEVEL_NOM 0>; qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX RPMH_REGULATOR_LEVEL_NOM 0>; @@ -108,12 +111,31 @@ <0>, <0>, <0>, <0>, <0>; resets = <&gcc GCC_PCIE_0_BCR>, - <&gcc GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR>; + <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "pcie_0_core_reset", - "pcie_phy_nocsr_com_phy_reset"; + "pcie_0_phy_reset"; dma-coherent; + msi-map = <0x0 &gic_its 0x5000 0x1>, + <0x100 &gic_its 0x5001 0x1>; + qcom,smmu-sid-base = <0x0000>; + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>, + <0x200 &pcie_smmu 0x0002 0x1>, + <0x300 &pcie_smmu 0x0003 0x1>, + <0x400 &pcie_smmu 0x0004 0x1>, + <0x500 &pcie_smmu 0x0005 0x1>, + <0x600 &pcie_smmu 0x0006 0x1>, + <0x700 &pcie_smmu 0x0007 0x1>, + <0x800 &pcie_smmu 0x0008 0x1>, + <0x900 &pcie_smmu 0x0009 0x1>, + <0xa00 &pcie_smmu 0x000a 0x1>, + <0xb00 &pcie_smmu 0x000b 0x1>, + <0xc00 &pcie_smmu 0x000c 0x1>, + <0xd00 &pcie_smmu 0x000d 0x1>, + <0xe00 &pcie_smmu 0x000e 0x1>, + <0xf00 &pcie_smmu 0x000f 0x1>; qcom,boot-option = <0x0>; qcom,aux-clk-freq = <20>; /* 19.2 MHz */ @@ -121,55 +143,169 @@ qcom,ep-latency = <10>; qcom,core-preset = <0x77777777>; + qcom,pcie-phy-ver = <109>; qcom,phy-status-offset = <0x1214>; qcom,phy-status-bit = <7>; qcom,phy-power-down-offset = <0x1240>; + qcom,phy-sequence = <0x1240 0x03 0x0 + 0x101c 0x31 0x0 + 0x1020 0x01 0x0 + 0x1024 0xde 0x0 + 0x1028 0x07 0x0 + 0x1030 0x97 0x0 + 0x1034 0x0c 0x0 + 0x1044 0x14 0x0 + 0x1048 0x90 0x0 + 0x1058 0x0f 0x0 + 0x1074 0x06 0x0 + 0x1078 0x06 0x0 + 0x107c 0x16 0x0 + 0x1080 0x16 0x0 + 0x1084 0x36 0x0 + 0x1088 0x36 0x0 + 0x1094 0x08 0x0 + 0x10a4 0x46 0x0 + 0x10a8 0x04 0x0 + 0x10ac 0x0a 0x0 + 0x10b0 0x1a 0x0 + 0x10b4 0x14 0x0 + 0x10b8 0x34 0x0 + 0x10bc 0x82 0x0 + 0x10c4 0xd0 0x0 + 0x10cc 0x55 0x0 + 0x10d0 0x55 0x0 + 0x10d4 0x03 0x0 + 0x10d8 0x55 0x0 + 0x10dc 0x55 0x0 + 0x10e0 0x05 0x0 + 0x110c 0x02 0x0 + 0x1154 0x34 0x0 + 0x1158 0x12 0x0 + 0x115c 0x00 0x0 + 0x1168 0x0a 0x0 + 0x116c 0x04 0x0 + 0x119c 0x88 0x0 + 0x1174 0x60 0x0 + 0x117c 0x06 0x0 + 0x11a0 0x14 0x0 + 0x11a8 0x0f 0x0 + 0x0220 0x16 0x0 + 0x03c0 0x38 0x0 + 0x0a20 0x16 0x0 + 0x0bc0 0x38 0x0 + 0x0360 0x9a 0x0 + 0x0364 0xb0 0x0 + 0x0368 0x12 0x0 + 0x036c 0xf0 0x0 + 0x0370 0x42 0x0 + 0x0374 0x99 0x0 + 0x0378 0x29 0x0 + 0x037c 0x9a 0x0 + 0x0380 0xb0 0x0 + 0x0384 0x12 0x0 + 0x0388 0xf0 0x0 + 0x038c 0x43 0x0 + 0x0390 0xdd 0x0 + 0x0394 0x0d 0x0 + 0x0398 0xdb 0x0 + 0x039c 0xb0 0x0 + 0x03a0 0x64 0x0 + 0x03a4 0xf0 0x0 + 0x03a8 0xc3 0x0 + 0x03ac 0xfd 0x0 + 0x03b0 0x7f 0x0 + 0x0b60 0x9a 0x0 + 0x0b64 0xb0 0x0 + 0x0b68 0x12 0x0 + 0x0b6c 0xf0 0x0 + 0x0b70 0x42 0x0 + 0x0b74 0x99 0x0 + 0x0b78 0x29 0x0 + 0x0b7c 0x9a 0x0 + 0x0b80 0xb0 0x0 + 0x0b84 0x12 0x0 + 0x0b88 0xf0 0x0 + 0x0b8c 0x43 0x0 + 0x0b90 0xdd 0x0 + 0x0b94 0x0d 0x0 + 0x0b98 0xdb 0x0 + 0x0b9c 0xb0 0x0 + 0x0ba0 0x64 0x0 + 0x0ba4 0xf0 0x0 + 0x0ba8 0xc3 0x0 + 0x0bac 0xfd 0x0 + 0x0bb0 0x7f 0x0 + 0x03b4 0x20 0x0 + 0x022c 0x3f 0x0 + 0x0230 0x37 0x0 + 0x0bb4 0x20 0x0 + 0x0a2c 0x3f 0x0 + 0x0a30 0x37 0x0 + 0x0078 0x05 0x0 + 0x007c 0x10 0x0 + 0x0878 0x05 0x0 + 0x087c 0x10 0x0 + 0x0290 0x05 0x0 + 0x0a90 0x05 0x0 + 0x03f8 0x1f 0x0 + 0x0400 0x1f 0x0 + 0x0408 0x1f 0x0 + 0x0410 0x1f 0x0 + 0x0418 0x1f 0x0 + 0x0420 0x1f 0x0 + 0x03f4 0x1f 0x0 + 0x03fc 0x1f 0x0 + 0x0404 0x1f 0x0 + 0x0bf8 0x1f 0x0 + 0x0c00 0x1f 0x0 + 0x0c08 0x1f 0x0 + 0x0c10 0x1f 0x0 + 0x0c18 0x1f 0x0 + 0x0c20 0x1f 0x0 + 0x0bf4 0x1f 0x0 + 0x0bfc 0x1f 0x0 + 0x0c04 0x1f 0x0 + 0x0208 0x0c 0x0 + 0x0a08 0x0c 0x0 + 0x020c 0x0a 0x0 + 0x0a0c 0x0a 0x0 + 0x02dc 0x0a 0x0 + 0x0adc 0x0a 0x0 + 0x0308 0x0b 0x0 + 0x0b08 0x0b 0x0 + 0x027c 0x10 0x0 + 0x0a7c 0x10 0x0 + 0x02b4 0x00 0x0 + 0x0ab4 0x00 0x0 + 0x02ec 0x0f 0x0 + 0x0aec 0x0f 0x0 + 0x02c4 0x00 0x0 + 0x02c8 0x1f 0x0 + 0x0ac4 0x00 0x0 + 0x0ac8 0x1f 0x0 + 0x0030 0x1a 0x0 + 0x0034 0x0c 0x0 + 0x0830 0x1a 0x0 + 0x0834 0x0c 0x0 + 0x141c 0xc1 0x0 + 0x1404 0x00 0x0 + 0x13e0 0x16 0x0 + 0x13e4 0x22 0x0 + 0x1508 0x02 0x0 + 0x14a0 0x16 0x0 + 0x1584 0x28 0x0 + 0x1370 0x2e 0x0 + 0x155c 0x2e 0x0 + 0x140c 0x1d 0x0 + 0x1388 0xaa 0x0 + 0x1200 0x00 0x0 + 0x1244 0x03 0x0>; pcie0_rp: pcie0_rp { reg = <0 0 0 0 0>; }; }; - pcie0_msi: qcom,pcie0_msi@0x17a00040 { - compatible = "qcom,pci-msi"; - msi-controller; - reg = <0x17a00040 0x0>; - interrupt-parent = <&intc>; - interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; - }; - - pcie1: qcom,pcie@0x01c10000 { compatible = "qcom,pci-msm"; @@ -216,10 +352,13 @@ gdsc-vdd-supply = <&gcc_pcie_1_gdsc>; vreg-1p8-supply = <&L1C>; vreg-0p9-supply = <&L5A>; + vreg-cx-supply = <&VDD_CX_LEVEL>; vreg-mx-supply = <&VDD_MXC_LEVEL>; qcom,vreg-1p8-voltage-level = <1200000 1200000 33300>; qcom,vreg-0p9-voltage-level = <880000 880000 439000>; + qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX + RPMH_REGULATOR_LEVEL_NOM 0>; qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX RPMH_REGULATOR_LEVEL_NOM 0>; @@ -276,12 +415,30 @@ <0>, <0>, <0>, <0>, <0>; resets = <&gcc GCC_PCIE_1_BCR>, - <&gcc GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR>; + <&gcc GCC_PCIE_1_PHY_BCR>; reset-names = "pcie_1_core_reset", - "pcie_phy_nocsr_com_phy_reset"; + "pcie_1_phy_reset"; dma-coherent; + msi-map = <0x0 &gic_its 0x5080 0x1>, + <0x100 &gic_its 0x5081 0x1>; qcom,smmu-sid-base = <0x0080>; + iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, + <0x100 &pcie_smmu 0x0081 0x1>, + <0x200 &pcie_smmu 0x0082 0x1>, + <0x300 &pcie_smmu 0x0083 0x1>, + <0x400 &pcie_smmu 0x0084 0x1>, + <0x500 &pcie_smmu 0x0085 0x1>, + <0x600 &pcie_smmu 0x0086 0x1>, + <0x700 &pcie_smmu 0x0087 0x1>, + <0x800 &pcie_smmu 0x0088 0x1>, + <0x900 &pcie_smmu 0x0089 0x1>, + <0xa00 &pcie_smmu 0x008a 0x1>, + <0xb00 &pcie_smmu 0x008b 0x1>, + <0xc00 &pcie_smmu 0x008c 0x1>, + <0xd00 &pcie_smmu 0x008d 0x1>, + <0xe00 &pcie_smmu 0x008e 0x1>, + <0xf00 &pcie_smmu 0x008f 0x1>; qcom,boot-option = <0x0>; qcom,aux-clk-freq = <20>; /* 19.2 MHz */ @@ -289,52 +446,119 @@ qcom,ep-latency = <10>; qcom,core-preset = <0x77777777>; + qcom,pcie-phy-ver = <1093>; qcom,phy-status-offset = <0x2214>; qcom,phy-status-bit = <7>; qcom,phy-power-down-offset = <0x2240>; + qcom,phy-sequence = <0x2240 0x03 0x0 + 0x201c 0x31 0x0 + 0x2020 0x01 0x0 + 0x2024 0xde 0x0 + 0x2028 0x07 0x0 + 0x2030 0x97 0x0 + 0x2034 0x0c 0x0 + 0x2044 0x1c 0x0 + 0x2048 0x90 0x0 + 0x2058 0x0f 0x0 + 0x2074 0x06 0x0 + 0x2078 0x06 0x0 + 0x207c 0x16 0x0 + 0x2080 0x16 0x0 + 0x2084 0x36 0x0 + 0x2088 0x36 0x0 + 0x2094 0x08 0x0 + 0x20a4 0x46 0x0 + 0x20a8 0x04 0x0 + 0x20ac 0x0a 0x0 + 0x20b0 0x1a 0x0 + 0x20b4 0x14 0x0 + 0x20b8 0x34 0x0 + 0x20bc 0x82 0x0 + 0x20c4 0xd0 0x0 + 0x20cc 0x55 0x0 + 0x20d0 0x55 0x0 + 0x20d4 0x03 0x0 + 0x20d8 0x55 0x0 + 0x20dC 0x55 0x0 + 0x20e0 0x05 0x0 + 0x210c 0x02 0x0 + 0x2154 0x34 0x0 + 0x2158 0x12 0x0 + 0x215c 0x00 0x0 + 0x2168 0x0a 0x0 + 0x216c 0x04 0x0 + 0x219c 0x88 0x0 + 0x2174 0x60 0x0 + 0x217c 0x06 0x0 + 0x21a0 0x14 0x0 + 0x21a8 0x0f 0x0 + 0x3a2c 0x3f 0x0 + 0x3a30 0x37 0x0 + 0x3a90 0x05 0x0 + 0x3bc0 0x38 0x0 + 0x3ab4 0x00 0x0 + 0x3aec 0x0f 0x0 + 0x3bb4 0x20 0x0 + 0x3b08 0x0b 0x0 + 0x3a7c 0x10 0x0 + 0x3bf4 0x1f 0x0 + 0x3bf8 0x1f 0x0 + 0x3bfc 0x1f 0x0 + 0x3c00 0x1f 0x0 + 0x3c04 0x1f 0x0 + 0x3c08 0x1f 0x0 + 0x3c10 0x1f 0x0 + 0x3c18 0x1f 0x0 + 0x3c20 0x1f 0x0 + 0x3b60 0x9a 0x0 + 0x3b64 0xb0 0x0 + 0x3b68 0x12 0x0 + 0x3b6c 0xf0 0x0 + 0x3b70 0x42 0x0 + 0x3b74 0x99 0x0 + 0x3b78 0x29 0x0 + 0x3b7c 0x9a 0x0 + 0x3b80 0xb0 0x0 + 0x3b84 0x12 0x0 + 0x3b88 0xf0 0x0 + 0x3b8c 0x43 0x0 + 0x3b90 0xdd 0x0 + 0x3b94 0x0d 0x0 + 0x3b98 0xdb 0x0 + 0x3b9c 0xb0 0x0 + 0x3ba0 0x64 0x0 + 0x3ba4 0xf0 0x0 + 0x3ba8 0xc3 0x0 + 0x3bac 0xfd 0x0 + 0x3bb0 0x7f 0x0 + 0x3ac4 0x00 0x0 + 0x3ac8 0x1f 0x0 + 0x3a08 0x0c 0x0 + 0x3a0C 0x0a 0x0 + 0x3a20 0x16 0x0 + 0x3adc 0x0a 0x0 + 0x3878 0x05 0x0 + 0x387c 0x10 0x0 + 0x3834 0x0c 0x0 + 0x3830 0x1a 0x0 + 0x241c 0xc1 0x0 + 0x2490 0x00 0x0 + 0x23e0 0x16 0x0 + 0x23e4 0x22 0x0 + 0x2508 0x02 0x0 + 0x24a0 0x16 0x0 + 0x2584 0x28 0x0 + 0x2370 0x2e 0x0 + 0x255c 0x2e 0x0 + 0x2388 0x99 0x0 + 0x240c 0x1d 0x0 + 0x2200 0x00 0x0 + 0x2244 0x03 0x0>; + pcie1_rp: pcie1_rp { reg = <0 0 0 0 0>; }; }; - - pcie1_msi: qcom,pcie1_msi@17a00040 { - compatible = "qcom,pci-msi"; - msi-controller; - reg = <0x17a00040 0x0>; - interrupt-parent = <&intc>; - interrupts = <GIC_SPI 800 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 801 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 802 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 803 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 804 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 805 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 806 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 807 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 808 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 809 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 810 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 811 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 812 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 813 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 814 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 815 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 816 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 817 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 818 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 819 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 820 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 821 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 822 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 823 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 824 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 825 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 826 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 827 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 828 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 829 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 830 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 831 IRQ_TYPE_EDGE_RISING>; - }; }; diff --git a/qcom/lemans-pinctrl.dtsi b/qcom/lemans-pinctrl.dtsi index b235842b..854a8a1f 100755 --- a/qcom/lemans-pinctrl.dtsi +++ b/qcom/lemans-pinctrl.dtsi @@ -53,7 +53,7 @@ config { pins = "gpio20", "gpio21", "gpio22", "gpio23"; - drive-strength = <0>; + drive-strength = <2>; bias-disable; }; }; @@ -113,7 +113,7 @@ config { pins = "gpio24", "gpio25", "gpio26", "gpio27"; - drive-strength = <0>; + drive-strength = <2>; bias-disable; }; }; @@ -173,7 +173,7 @@ config { pins = "gpio36", "gpio37", "gpio38", "gpio39"; - drive-strength = <0>; + drive-strength = <2>; bias-disable; }; }; @@ -233,7 +233,7 @@ config { pins = "gpio28", "gpio29", "gpio30", "gpio31"; - drive-strength = <0>; + drive-strength = <2>; bias-disable; }; }; @@ -293,7 +293,7 @@ config { pins = "gpio32", "gpio33", "gpio34", "gpio35"; - drive-strength = <0>; + drive-strength = <2>; bias-disable; }; }; @@ -353,7 +353,7 @@ config { pins = "gpio36", "gpio37", "gpio38", "gpio39"; - drive-strength = <0>; + drive-strength = <2>; bias-disable; }; }; @@ -441,7 +441,7 @@ config { pins = "gpio40", "gpio41", "gpio42", "gpio43"; - drive-strength = <0>; + drive-strength = <2>; bias-disable; }; }; @@ -501,7 +501,7 @@ config { pins = "gpio42", "gpio43", "gpio40", "gpio41"; - drive-strength = <0>; + drive-strength = <2>; bias-disable; }; }; @@ -561,7 +561,7 @@ config { pins = "gpio46", "gpio47", "gpio44", "gpio45"; - drive-strength = <0>; + drive-strength = <2>; bias-disable; }; }; @@ -649,7 +649,7 @@ config { pins = "gpio44", "gpio45", "gpio46", "gpio47"; - drive-strength = <0>; + drive-strength = <2>; bias-disable; }; }; @@ -737,7 +737,7 @@ config { pins = "gpio48", "gpio49", "gpio50", "gpio51"; - drive-strength = <0>; + drive-strength = <2>; bias-disable; }; }; @@ -797,10 +797,90 @@ config { pins = "gpio52", "gpio53", "gpio54", "gpio55"; - drive-strength = <0>; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se12_4uart_pins: qupv3_se12_4uart_pins { + qupv3_se12_default_cts: qupv3_se12_default_cts { + mux { + pins = "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; bias-disable; }; }; + + qupv3_se12_default_rtsrx: qupv3_se12_default_rtsrx { + mux { + pins = "gpio53", "gpio55"; + function = "gpio"; + }; + + config { + pins = "gpio53", "gpio55"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se12_default_tx: qupv3_se12_default_tx { + mux { + pins = "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se12_ctsrx: qupv3_se12_ctsrx { + mux { + pins = "gpio52", "gpio55"; + function = "qup1_se5"; + }; + + config { + pins = "gpio52", "gpio55"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se12_rts: qupv3_se12_rts { + mux { + pins = "gpio53"; + function = "qup1_se5"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se12_tx: qupv3_se12_tx { + mux { + pins = "gpio54"; + function = "qup1_se5"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { @@ -885,7 +965,7 @@ config { pins = "gpio80", "gpio81", "gpio82", "gpio83"; - drive-strength = <0>; + drive-strength = <2>; bias-disable; }; }; @@ -945,7 +1025,7 @@ config { pins = "gpio84", "gpio85", "gpio99", "gpio100"; - drive-strength = <0>; + drive-strength = <2>; bias-disable; }; }; @@ -1005,7 +1085,7 @@ config { pins = "gpio86", "gpio87", "gpio88", "gpio89"; - drive-strength = <0>; + drive-strength = <2>; bias-disable; }; }; @@ -1065,12 +1145,92 @@ config { pins = "gpio91", "gpio92", "gpio93", "gpio94"; - drive-strength = <0>; + drive-strength = <2>; bias-disable; }; }; }; + qupv3_se17_4uart_pins: qupv3_se17_4uart_pins { + qupv3_se17_default_cts: qupv3_se17_default_cts { + mux { + pins = "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio91"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se17_default_rtsrx: qupv3_se17_default_rtsrx { + mux { + pins = "gpio92", "gpio94"; + function = "gpio"; + }; + + config { + pins = "gpio92", "gpio94"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se17_default_tx: qupv3_se17_default_tx { + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se17_ctsrx: qupv3_se17_ctsrx { + mux { + pins = "gpio91", "gpio94"; + function = "qup2_se3"; + }; + + config { + pins = "gpio91", "gpio94"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se17_rts: qupv3_se17_rts { + mux { + pins = "gpio92"; + function = "qup2_se3"; + }; + + config { + pins = "gpio92"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se17_tx: qupv3_se17_tx { + mux { + pins = "gpio93"; + function = "qup2_se3"; + }; + + config { + pins = "gpio93"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + qupv3_se18_i2c_pins: qupv3_se18_i2c_pins { qupv3_se18_i2c_active: qupv3_se18_i2c_active { mux { @@ -1125,7 +1285,7 @@ config { pins = "gpio95", "gpio96", "gpio97", "gpio98"; - drive-strength = <0>; + drive-strength = <2>; bias-disable; }; }; @@ -1185,7 +1345,7 @@ config { pins = "gpio99", "gpio100", "gpio84", "gpio95"; - drive-strength = <0>; + drive-strength = <2>; bias-disable; }; }; @@ -1245,7 +1405,7 @@ config { pins = "gpio97", "gpio98", "gpio95", "gpio96"; - drive-strength = <0>; + drive-strength = <2>; bias-disable; }; }; @@ -1305,7 +1465,7 @@ config { pins = "gpio13", "gpio14", "gpio15", "gpio16"; - drive-strength = <0>; + drive-strength = <2>; bias-disable; }; }; diff --git a/qcom/lemans-pmic-overlay.dtsi b/qcom/lemans-pmic-overlay.dtsi new file mode 100755 index 00000000..20b72446 --- /dev/null +++ b/qcom/lemans-pmic-overlay.dtsi @@ -0,0 +1,217 @@ +#include "pm8775.dtsi" + +&pm8775_1 { + /delete-node/ pon_pbs@800; + /delete-node/ pon_hlos@1200; + + pon_hlos@1200 { + compatible = "qcom,qpnp-power-on"; + reg = <0x1200>; + interrupts = <0x0 0x12 0x7 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "kpdpwr", "resin"; + + qcom,pon_1 { + qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>; + linux,code = <KEY_POWER>; + }; + + qcom,pon_2 { + qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; +}; + +&pm8775_2 { + /delete-node/ pon_pbs@800; + /delete-node/ pon_hlos@1200; + + pon_hlos@1200 { + compatible = "qcom,qpnp-power-on"; + reg = <0x1200>; + interrupts = <0x2 0x12 0x7 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "kpdpwr", "resin"; + + qcom,pon_1 { + qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>; + linux,code = <KEY_POWER>; + }; + + qcom,pon_2 { + qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; +}; + +&pm8775_3 { + /delete-node/ pon_pbs@800; + /delete-node/ pon_hlos@1200; + + pon_hlos@1200 { + compatible = "qcom,qpnp-power-on"; + reg = <0x1200>; + interrupts = <0x4 0x12 0x7 IRQ_TYPE_EDGE_BOTH>, + <0x4 0x12 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "kpdpwr", "resin"; + + qcom,pon_1 { + qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>; + linux,code = <KEY_POWER>; + }; + + qcom,pon_2 { + qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; +}; + +&pm8775_4 { + /delete-node/ pon_pbs@800; + /delete-node/ pon_hlos@1200; + + pon_hlos@1200 { + compatible = "qcom,qpnp-power-on"; + reg = <0x1200>; + interrupts = <0x6 0x12 0x7 IRQ_TYPE_EDGE_BOTH>, + <0x6 0x12 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "kpdpwr", "resin"; + + qcom,pon_1 { + qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>; + linux,code = <KEY_POWER>; + }; + + qcom,pon_2 { + qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; +}; + +&soc { + pmic-pon-log { + compatible = "qcom,pmic-pon-log"; + nvmem = <&pm8775_1_sdam_5>; + nvmem-names = "pon_log"; + }; + + reboot_reason { + compatible = "qcom,reboot-reason"; + nvmem-cells = <&restart_reason>; + nvmem-cell-names = "restart_reason"; + }; +}; + +&thermal_zones { + pm8775_1_temp_alarm: pm8775_1_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8775_1_tz>; + + trips { + pm8775_1_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_1_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + + pm8775_1_trip2: trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8775_2_temp_alarm: pm8775_2_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8775_2_tz>; + + trips { + pm8775_2_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_2_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + + pm8775_2_trip2: trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8775_3_temp_alarm: pm8775_3_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8775_3_tz>; + + trips { + pm8775_3_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_3_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + + pm8775_3_trip2: trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8775_4_temp_alarm: pm8775_4_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8775_4_tz>; + + trips { + pm8775_4_trip0: trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8775_4_trip1: trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + + pm8775_4_trip2: trip2 { + temperature = <155000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; +}; diff --git a/qcom/lemans-qupv3.dtsi b/qcom/lemans-qupv3.dtsi index cea38a2f..366f8b9b 100755 --- a/qcom/lemans-qupv3.dtsi +++ b/qcom/lemans-qupv3.dtsi @@ -11,7 +11,7 @@ qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; - status = "disabled"; + status = "ok"; }; /* QUPv3_1 wrapper instance */ @@ -41,7 +41,7 @@ qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; - status = "disabled"; + status = "ok"; }; /* QUPv3_3 wrapper instance */ @@ -541,6 +541,27 @@ status = "disabled"; }; + /* GNSS with 4W UART instance */ + qupv3_se12_4uart: qcom,qup_uart@a94000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa94000 0x4000>; + reg-names = "se_phys"; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se12_default_cts>, + <&qupv3_se12_default_rtsrx>, <&qupv3_se12_default_tx>; + pinctrl-1 = <&qupv3_se12_ctsrx>, <&qupv3_se12_rts>, + <&qupv3_se12_tx>; + pinctrl-2 = <&qupv3_se12_ctsrx>, <&qupv3_se12_rts>, + <&qupv3_se12_tx>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + qupv3_se13_i2c: i2c@a98000 { compatible = "qcom,i2c-geni"; reg = <0xa98000 0x4000>; @@ -702,6 +723,29 @@ status = "disabled"; }; + /* 4W BT UART instance */ + qupv3_se17_4uart: qcom,qup_uart@88c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x88c000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 94 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se17_default_cts>, + <&qupv3_se17_default_rtsrx>, <&qupv3_se17_default_tx>; + pinctrl-1 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>, + <&qupv3_se17_tx>; + pinctrl-2 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>, + <&qupv3_se17_tx>; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + qupv3_se18_i2c: i2c@890000 { compatible = "qcom,i2c-geni"; reg = <0x890000 0x4000>; diff --git a/qcom/lemans-rumi.dts b/qcom/lemans-rumi.dts index c3b64fec..d7ef1c58 100755 --- a/qcom/lemans-rumi.dts +++ b/qcom/lemans-rumi.dts @@ -1,5 +1,5 @@ /dts-v1/; -/memreserve/ 0x90000000 0x00000100; +/memreserve/ 0xC0000000 0x00000100; #include "lemans.dtsi" #include "lemans-rumi.dtsi" diff --git a/qcom/lemans-thermal.dtsi b/qcom/lemans-thermal.dtsi index 906c8975..7d5d7760 100755 --- a/qcom/lemans-thermal.dtsi +++ b/qcom/lemans-thermal.dtsi @@ -7,8 +7,8 @@ <0x0C263000 0x1ff>; reg-names = "tsens_srot_physical", "tsens_tm_physical"; - interrupts-extended = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tsens-upper-lower", "tsens-critical"; #thermal-sensor-cells = <1>; }; @@ -19,8 +19,8 @@ <0x0C265000 0x1ff>; reg-names = "tsens_srot_physical", "tsens_tm_physical"; - interrupts-extended = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tsens-upper-lower", "tsens-critical"; #thermal-sensor-cells = <1>; }; @@ -31,20 +31,20 @@ <0x0C251000 0x1ff>; reg-names = "tsens_srot_physical", "tsens_tm_physical"; - interrupts-extended = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tsens-upper-lower", "tsens-critical"; #thermal-sensor-cells = <1>; }; tsens3:tsens@c225000 { compatible = "qcom,tsens26xx"; - reg = <0x0C223000 0x8>, + reg = <0x0C225000 0x8>, <0x0C252000 0x1ff>; reg-names = "tsens_srot_physical", "tsens_tm_physical"; - interrupts-extended = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tsens-upper-lower", "tsens-critical"; #thermal-sensor-cells = <1>; }; @@ -125,6 +125,49 @@ #cooling-cells = <2>; }; }; + + qcom,cpu-hotplug { + compatible = "qcom,cpu-hotplug"; + cpu0_hotplug: cpu0-hotplug { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_hotplug: cpu1-hotplug { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_hotplug: cpu2-hotplug { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_hotplug: cpu3-hotplug { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + + cpu4_hotplug: cpu4-hotplug { + qcom,cpu = <&CPU4>; + #cooling-cells = <2>; + }; + + cpu5_hotplug: cpu5-hotplug { + qcom,cpu = <&CPU5>; + #cooling-cells = <2>; + }; + + cpu6_hotplug: cpu6-hotplug { + qcom,cpu = <&CPU6>; + #cooling-cells = <2>; + }; + + cpu7_hotplug: cpu7-hotplug { + qcom,cpu = <&CPU7>; + #cooling-cells = <2>; + }; + }; }; &thermal_zones { diff --git a/qcom/lemans-usb.dtsi b/qcom/lemans-usb.dtsi index 6ef47db9..488baf0a 100755 --- a/qcom/lemans-usb.dtsi +++ b/qcom/lemans-usb.dtsi @@ -494,7 +494,7 @@ snps,usb2-gadget-lpm-disable; tx-fifo-resize; maximum-speed = "high-speed"; - dr_mode = "otg"; + dr_mode = "host"; }; }; diff --git a/qcom/lemans.dts b/qcom/lemans.dts deleted file mode 100755 index 1c13ba73..00000000 --- a/qcom/lemans.dts +++ /dev/null @@ -1,8 +0,0 @@ -/dts-v1/; - -#include "lemans.dtsi" -/ { - model = "Qualcomm Technologies, Inc. Lemans SoC"; - compatible = "qcom,lemans"; - qcom,board-id = <0 0>; -}; diff --git a/qcom/lemans.dtsi b/qcom/lemans.dtsi index 388ad4d4..ec003ec8 100755 --- a/qcom/lemans.dtsi +++ b/qcom/lemans.dtsi @@ -2,6 +2,7 @@ #include <dt-bindings/clock/qcom,camcc-lemans.h> #include <dt-bindings/clock/qcom,dispcc-lemans.h> #include <dt-bindings/clock/qcom,gcc-lemans.h> +#include <dt-bindings/clock/qcom,aop-qmp.h> #include <dt-bindings/clock/qcom,gpucc-lemans.h> #include <dt-bindings/clock/qcom,videocc-lemans.h> #include <dt-bindings/interconnect/qcom,epss-l3.h> @@ -15,7 +16,7 @@ / { model = "Qualcomm Technologies, Inc. Lemans"; compatible = "qcom,lemans"; - qcom,msm-id = <532 0x10000>, <534 0x10000>; + qcom,msm-id = <534 0x10000>, <535 0x10000>; interrupt-parent = <&intc>; #address-cells = <2>; @@ -240,6 +241,7 @@ &firmware { scm { compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; }; }; @@ -404,6 +406,21 @@ reg = <0x0 0xd1800000 0x0 0x3900000>; }; + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0 0x3000000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + /* global autoconfigured region for contiguous allocations */ linux,cma { compatible = "shared-dma-pool"; @@ -461,11 +478,21 @@ compatible = "arm,gic-v3"; #interrupt-cells = <3>; interrupt-controller; + #address-cells = <1>; + #size-cells = <1>; + ranges; #redistributor-regions = <1>; redistributor-stride = <0x0 0x20000>; reg = <0x17a00000 0x10000>, /* GICD */ <0x17a60000 0x100000>; /* GICR * 8 */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gic_its: gic-its@17a40000 { + compatible = "arm,gic-v3-its"; + reg = <0x17a40000 0x20000>; + msi-controller; + #msi-cells = <1>; + }; }; pdc: interrupt-controller@b220000 { @@ -583,6 +610,11 @@ reg = <0x94c 0xc8>; }; + pil@6dc { + compatible = "qcom,msm-imem-pil-disable-timeout"; + reg = <0x6dc 0x4>; + }; + diag_dload@c8 { compatible = "qcom,msm-imem-diag-dload"; reg = <0xc8 0xc8>; @@ -781,6 +813,19 @@ #reset-cells = <1>; }; + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + wdog: qcom,wdt@17c10000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + }; + cpufreq_hw: qcom,cpufreq-hw@18591000 { compatible = "qcom,cpufreq-hw-epss"; reg = <0x18591000 0x1000>, <0x18593000 0x1000>; @@ -850,6 +895,16 @@ #mbox-cells = <2>; }; + cache-controller@9200000 { + compatible = "qcom,lemans-llcc", "qcom,llcc-v2"; + reg = <0x9200000 0x580000> , <0x9a00000 0x80000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + cap-based-alloc-and-pwr-collapse; + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&aopcc QDSS_CLK>; + clock-names = "qdss_clk"; + }; + clk_virt: interconnect@0 { compatible = "qcom,lemans-clk_virt"; #interconnect-cells = <1>; @@ -886,6 +941,11 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; }; aggre2_noc: interconnect@01700000 { @@ -894,6 +954,8 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; }; pcie_anoc: interconnect@01760000 { @@ -942,6 +1004,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>; }; nspa_noc: interconnect@260C0000 { @@ -961,13 +1024,324 @@ }; epss_l3_cpu: l3_cpu@18590000 { - compatible = "lahaina-epss-l3-cpu"; + reg = <0x18590000 0x4000>; + compatible = "qcom,lemans-epss-l3-cpu"; #interconnect-cells = <1>; + clock-names = "xo", "alternate"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + }; + + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + }; + + kryo_erp: erp { + compatible = "arm,arm64-kryo-cpu-erp"; + interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "l1-l2-faultirq", "l3-c0-scu-faultirq", + "l3-c1-scu-faultirq"; }; thermal_zones: thermal-zones { }; + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + rpmh { + qcom,dump-size = <0x2000000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x80000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + tmc_etf { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf0>; + }; + + etf_swao { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + l1_icache0 { + qcom,dump-size = <0x26100>; + qcom,dump-id = <0x60>; + }; + + l1_icache100 { + qcom,dump-size = <0x26100>; + qcom,dump-id = <0x61>; + }; + + l1_icache200 { + qcom,dump-size = <0x26100>; + qcom,dump-id = <0x62>; + }; + + l1_icache300 { + qcom,dump-size = <0x26100>; + qcom,dump-id = <0x63>; + }; + + l1_icache10000 { + qcom,dump-size = <0x26100>; + qcom,dump-id = <0x64>; + }; + + l1_icache10100 { + qcom,dump-size = <0x26100>; + qcom,dump-id = <0x65>; + }; + + l1_icache10200 { + qcom,dump-size = <0x26100>; + qcom,dump-id = <0x66>; + }; + + l1_icache10300 { + qcom,dump-size = <0x26100>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x80>; + }; + + l1_dcache100 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x81>; + }; + + l1_dcache200 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x82>; + }; + + l1_dcache300 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x83>; + }; + + l1_dcache10000 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x84>; + }; + + l1_dcache10100 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x85>; + }; + + l1_dcache10200 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x86>; + }; + + l1_dcache10300 { + qcom,dump-size = <0x12100>; + qcom,dump-id = <0x87>; + }; + + l1_itlb10000 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x24>; + }; + + l1_itlb10100 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x25>; + }; + + l1_itlb10200 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x26>; + }; + + l1_itlb10300 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x27>; + }; + + l1_dtlb10000 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x44>; + }; + + l1_dtlb10100 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x45>; + }; + + l1_dtlb10200 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x46>; + }; + + l1_dtlb10300 { + qcom,dump-size = <0x300>; + qcom,dump-id = <0x47>; + }; + + l2_cache10000 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc4>; + }; + + l2_cache10100 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc5>; + }; + + l2_cache10200 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc6>; + }; + + l2_cache10300 { + qcom,dump-size = <0x90100>; + qcom,dump-id = <0xc7>; + }; + + l2_tlb0 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x120>; + }; + + l2_tlb100 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x121>; + }; + + l2_tlb200 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x122>; + }; + + l2_tlb300 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x123>; + }; + + l2_tlb10000 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x124>; + }; + + l2_tlb10100 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x125>; + }; + + l2_tlb10200 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x126>; + }; + + l2_tlb10300 { + qcom,dump-size = <0x6100>; + qcom,dump-id = <0x127>; + }; + + c0_scandump: c0_scandump { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x130>; + }; + + c100_scandump: c100_scandump { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x131>; + }; + + c200_scandump: c200_scandump { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x132>; + }; + + c300_scandump: c300_scandump { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x133>; + }; + + c10000_scandump: c10000_scandump { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x134>; + }; + + c10100_scandump: c10100_scandump { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x135>; + }; + + c10200_scandump: c10200_scandump { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x136>; + }; + + c10300_scandump: c10300_scandump { + qcom,dump-size = <0x40000>; + qcom,dump-id = <0x137>; + }; + + cpuss_reg: cpuss_reg { + qcom,dump-size = <0x20000>; + qcom,dump-id = <0xef>; + }; + }; + ipcc_mproc: qcom,ipcc@408000 { compatible = "qcom,ipcc"; reg = <0x408000 0x1000>; @@ -977,6 +1351,15 @@ #mbox-cells = <2>; }; + dload_mode { + compatible = "qcom,dload-mode"; + }; + + tcsr: syscon@1fc0000 { + compatible = "syscon"; + reg = <0x1fc0000 0x30000>; + }; + tcsr_mutex_block: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x20000>; @@ -1059,7 +1442,7 @@ }; }; - glink_cdsp0: cdsp0 { + glink_cdsp0: cdsp { qcom,remote-pid = <5>; transport = "smem"; mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP @@ -1070,8 +1453,8 @@ IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; - label = "cdsp0"; - qcom,glink-label = "cdsp0"; + label = "cdsp"; + qcom,glink-label = "cdsp"; qcom,cdsp0_qrtr { qcom,glink-channels = "IPCRTR"; @@ -1488,8 +1871,10 @@ lanes-per-direction = <2>; clock-names = "ref_clk_src", + "ref_clk", "ref_aux_clk"; clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; resets = <&ufshc_mem 0>; status = "disabled"; @@ -1730,6 +2115,59 @@ }; }; + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + }; + + msm_fastrpc: qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-audio-pdr; + qcom,rpc-latency-us = <235>; + qcom,fastrpc-gids = <2908>; + qcom,qos-cores = <0 1 2 3>; + + qcom,msm_fastrpc_compute_adsp_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x3003 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_adsp_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x3004 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_adsp_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x3005 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + dma-coherent-hint-cached; + }; + }; + + qcom,chd { + compatible = "qcom,core-hang-detect"; + label = "core"; + qcom,threshold-arr = <0x18000058 0x18010058 0x18020058 0x18030058 + 0x18040058 0x18050058 0x18060058 0x18070058>; + qcom,config-arr = <0x18000060 0x18010060 0x18020060 0x18030060 + 0x18040060 0x18050060 0x18060060 0x18070060>; + }; + + qcom-secure-buffer { + compatible = "qcom,secure-buffer"; + }; }; #include "lemans-4pmic-regulators.dtsi" @@ -1949,7 +2387,7 @@ }; &ufsphy_mem { - compatible = "qcom,ufs-phy-qmp-v4-lahaina"; + compatible = "qcom,ufs-phy-qmp-v4-waipio"; vdda-phy-supply = <&L4A>; vdda-pll-supply = <&L1C>; @@ -1964,11 +2402,14 @@ vdd-hba-fixed-regulator; vcc-supply = <&L8A>; - vcc-voltage-level = <2950000 2960000>; - vcc-max-microamp = <800000>; + vcc-voltage-level = <2504000 2506000>; + vcc-max-microamp = <1100000>; vccq-supply = <&L4C>; - vccq-max-microamp = <800000>; + vccq-max-microamp = <1200000>; + + vccq2-supply = <&S4A>; + vccq2-max-microamp = <800000>; qcom,vddp-ref-clk-supply = <&L4C>; qcom,vddp-ref-clk-max-microamp = <100>; diff --git a/qcom/monaco-audio-overlay.dtsi b/qcom/monaco-audio-overlay.dtsi index d19ec515..8be21f2e 100755 --- a/qcom/monaco-audio-overlay.dtsi +++ b/qcom/monaco-audio-overlay.dtsi @@ -10,6 +10,7 @@ pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>; pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>; qcom,lpi-gpios; + #gpio-cells = <0>; }; cdc_dmic23_gpios: cdc_dmic23_pinctrl { @@ -18,6 +19,7 @@ pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>; pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>; qcom,lpi-gpios; + #gpio-cells = <0>; }; rx_swr_gpios: rx_swr_clk_data_pinctrl { @@ -26,6 +28,7 @@ pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active>; pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep>; qcom,lpi-gpios; + #gpio-cells = <0>; }; va_swr_gpios: va_swr_clk_data_pinctrl { @@ -39,6 +42,7 @@ qcom,chip-wakeup-reg = <0x003ca064>; qcom,chip-wakeup-maskbit = <0>; qcom,chip-wakeup-default-val = <0x1>; + #gpio-cells = <0>; }; bolero: bolero-cdc { diff --git a/qcom/monaco-audio.dtsi b/qcom/monaco-audio.dtsi index 8d82a345..be46164c 100755 --- a/qcom/monaco-audio.dtsi +++ b/qcom/monaco-audio.dtsi @@ -383,6 +383,10 @@ }; bolero: bolero-cdc { + bolero-clk-rsc-mngr { + compatible = "qcom,bolero-clk-rsc-mngr"; + }; + va_macro: va-macro@0a730000 { swr0: va_swr_master { }; diff --git a/qcom/monaco-pmic.dtsi b/qcom/monaco-pmic.dtsi index b2eb10c2..ff015d9e 100755 --- a/qcom/monaco-pmic.dtsi +++ b/qcom/monaco-pmic.dtsi @@ -169,6 +169,7 @@ qcom,batt-id-range-pct = <15>; #include "qbg-battery-profile-alium-860-89032-0000-3600mAh.dtsi" #include "qbg-battery-profile-qrd-zwd-520mAh.dtsi" + #include "qbg-battery-profile-305mAh.dtsi" }; }; diff --git a/qcom/monaco-standalone-idp-v1.dtsi b/qcom/monaco-standalone-idp-v1.dtsi index a75c6d68..369440e7 100755 --- a/qcom/monaco-standalone-idp-v1.dtsi +++ b/qcom/monaco-standalone-idp-v1.dtsi @@ -53,6 +53,7 @@ &icnss { qcom,rf_subtype = <1>; + vdd-1.8-xo-supply = <>; }; &qupv3_se5_4uart { diff --git a/qcom/msm-arm-smmu-lemans.dtsi b/qcom/msm-arm-smmu-lemans.dtsi index 5090b5af..cf6693b7 100755 --- a/qcom/msm-arm-smmu-lemans.dtsi +++ b/qcom/msm-arm-smmu-lemans.dtsi @@ -1,6 +1,173 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> &soc { + kgsl_smmu: kgsl-smmu@3da0000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x3DA0000 0x20000>, + <0x3DCA000 0x28>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,split-tables; + #global-interrupts = <2>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cc_cx_gdsc>; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + + clock-names = "gcc_gpu_memnoc_gfx", + "gcc_gpu_snoc_dvm_gfx", + "gpu_cc_ahb", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + + + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; + + gfx_0_tbu: gfx_0_tbu@3dd1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3DD1000 0x1000>, + <0x3DCA200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + }; + + gfx_1_tbu: gfx_1_tbu@3dd3000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3DD3000 0x1000>, + <0x3DCA208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + }; + + gfx_2_tbu: gfx_2_tbu@3dd9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3DD9000 0x1000>, + <0x3DCB200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + }; + + gfx_3_tbu: gfx_3_tbu@3ddb000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3DDB000 0x1000>, + <0x3DCB208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xC00 0x400>; + }; + + }; + + pcie_smmu: pcie-smmu@0x15200000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15200000 0x80000>, + <0x152F2000 0x28>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,split-tables; + #global-interrupts = <2>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + + interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&pcie_anoc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>, + <&pcie_anoc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>; + }; + apps_smmu: apps-smmu@15000000 { compatible = "qcom,qsmmu-v500"; reg = <0x15000000 0x100000>, @@ -148,6 +315,28 @@ &config_noc SLAVE_IMEM_CFG>; }; + kgsl_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x7 0x0C00>; + qcom,iommu-dma = "disabled"; + status = "disabled"; + }; + + kgsl_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x0407 0x0C00>; + qcom,iommu-dma = "disabled"; + dma-coherent; + status = "disabled"; + }; + + pcie_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&pcie_smmu 0x440 0x0>; + qcom,iommu-dma = "disabled"; + status = "disabled"; + }; + apps_iommu_test_device { compatible = "iommu-debug-test"; iommus = <&apps_smmu 0x580 0>; diff --git a/qcom/pm8540-vm.dtsi b/qcom/pm8540-vm.dtsi index 56cce106..9c3ede78 100755 --- a/qcom/pm8540-vm.dtsi +++ b/qcom/pm8540-vm.dtsi @@ -16,6 +16,15 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pm8540_1_rtc: qcom,pm8540_1_rtc { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + disable-alarm-wakeup; + }; + }; diff --git a/qcom/pm8775.dtsi b/qcom/pm8775.dtsi new file mode 100755 index 00000000..32b34cfe --- /dev/null +++ b/qcom/pm8775.dtsi @@ -0,0 +1,238 @@ +#include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/input/qcom,qpnp-power-on.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + pm8775_1: qcom,pm8775@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8775_1_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pon_pbs@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + qcom,system-reset; + qcom,store-hard-reset-reason; + }; + + pon_hlos@1200 { + compatible = "qcom,qpnp-power-on"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + interrupts = <0x0 0x12 0x7 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "kpdpwr", "resin"; + qcom,kpdpwr-sw-debounce; + + qcom,pon_1 { + qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>; + linux,code = <KEY_POWER>; + }; + + qcom,pon_2 { + qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; + + pm8775_1_clkdiv: clock-controller@5700 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5700>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8775_1_div_clk1", + "pm8775_1_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8775_1_rtc: qcom,pm8775_1_rtc { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, <0x6200>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_NONE>; + }; + + pm8775_1_gpios: pinctrl@8800 { + compatible = "qcom,pm8775-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8775_1_sdam_2: sdam@7100 { + compatible = "qcom,spmi-sdam"; + reg = <0x7100>; + #address-cells = <1>; + #size-cells = <1>; + + restart_reason: restart@48 { + reg = <0x48 0x1>; + bits = <1 7>; + }; + }; + + pm8775_1_sdam_5: sdam@7400 { + compatible = "qcom,spmi-sdam"; + reg = <0x7400>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + /* below definitions are for the second instance of pm8775 */ + pm8775_2: qcom,pm8775@2 { + compatible = "qcom,spmi-pmic"; + reg = <2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8775_2_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pon_pbs@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + }; + + pon_hlos@1200 { + compatible = "qcom,qpnp-power-on"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + }; + + pm8775_2_clkdiv: clock-controller@5700 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5700>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8775_2_div_clk1", + "pm8775_2_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8775_2_gpios: pinctrl@8800 { + compatible = "qcom,pm8775-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + /* below definitions are for the third instance of pm8775 */ + pm8775_3: qcom,pm8775@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8775_3_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pon_pbs@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + }; + + pon_hlos@1200 { + compatible = "qcom,qpnp-power-on"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + }; + + pm8775_3_clkdiv: clock-controller@5700 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5700>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8775_3_div_clk1", + "pm8775_3_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8775_3_gpios: pinctrl@8800 { + compatible = "qcom,pm8775-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + /* below definitions are for the fourth instance of pm8775 */ + pm8775_4: qcom,pm8775@6 { + compatible = "qcom,spmi-pmic"; + reg = <6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8775_4_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pon_pbs@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + }; + + pon_hlos@1200 { + compatible = "qcom,qpnp-power-on"; + reg = <0x1200>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + }; + + pm8775_4_clkdiv: clock-controller@5700 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5700>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8775_4_div_clk1", + "pm8775_4_div_clk2"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8775_4_gpios: pinctrl@8800 { + compatible = "qcom,pm8775-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/qcom/prairie-iot-idp.dtsi b/qcom/prairie-iot-idp.dtsi index c9c6183a..46fd7e9e 100755 --- a/qcom/prairie-iot-idp.dtsi +++ b/qcom/prairie-iot-idp.dtsi @@ -217,7 +217,7 @@ vdda-phy-max-microamp = <30000>; vdda-pll-max-microamp = <12000>; - status = "ok"; + status="disabled"; }; &ufshc_mem { @@ -234,7 +234,7 @@ qcom,vddp-ref-clk-min-uV = <1232000>; qcom,vddp-ref-clk-max-uV = <1260000>; - status = "ok"; + status="disabled"; }; &qupv3_se1_i2c { diff --git a/qcom/qbg-battery-profile-305mAh.dtsi b/qcom/qbg-battery-profile-305mAh.dtsi new file mode 100755 index 00000000..ab5846ac --- /dev/null +++ b/qcom/qbg-battery-profile-305mAh.dtsi @@ -0,0 +1,661 @@ +qcom,qbg-305mAh-averaged { + qcom,battery-type = "305MAH_AVERAGED"; + qcom,batt-id-kohm = <10>; + qcom,capacity = <306>; + qcom,max-voltage-uv = <4400000>; + qcom,fastchg-current-ma = <305>; + qcom,checksum = <4291097>; /*@5, 0.005V, 4% */ + qcom,soh-range = <0 100>; + /*Nominal_Impedance in 10nohm @ SOC 50% 25C* 0:fresh cell, 1: aged cell*/ + qcom,battery-impedance = <95906000 191812000>; + /*Nominal_Capacity in mAh. 0: fresh cell, 1:aged cell*/ + qcom,battery-capacity = <290 229>; + /*SOC delta (in percent) dropped from EOC SOC to enable recharge*/ + qcom,recharge-soc-delta =<5>; + /*vfloat delta (in mV) dropped from regular vfloat in recharge*/ + qcom,recharge-vflt-delta =<50>; + /*termination current (in mA) in recharge*/ + qcom,recharge-iterm-ma = <6>; + + qcom,jeita-fcc-ranges = <0 150 300000 + 151 420 300000 + 421 450 300000>; + + qcom,jeita-fv-ranges = <0 150 4350000 + 151 420 4400000 + 421 450 4350000>; + + qcom,jeita-soft-fcc-ua = <156000 200000>; + qcom,jeita-soft-fv-uv = <4350000 4350000>; + + /* COOL = 15 DegC, WARM = 45 DegC */ + qcom,jeita-soft-thresholds = <0x084E 0x02F5>; + /* COLD = 0 DegC, HOT = 45.1 DegC */ + qcom,jeita-hard-thresholds = <0x0E46 0x02F2>; + /* COOL = 18 DegC, WARM = 44 DegC*/ + qcom,jeita-soft-hys-thresholds = <0x0775 0x030E>; + + qcom,bp-c-table-0 { + qcom,temperature = <25>; + qcom,soc = < 0 39 58 78 97>, + < 136 195 292 429 605>, + < 703 820 1230 1660 2089>, + < 2519 2949 3378 3808 4238>, + < 4668 5097 5527 5957 6386>, + < 6679 7011 7441 7793 8046>, + < 8476 8906 9335 9765 10000>; + qcom,ocv = <30000 31624 32313 32890 33333>, + <33923 34535 35328 36111 36802>, + <36976 37009 37107 37404 37703>, + <37930 38068 38190 38327 38495>, + <38696 38937 39240 39626 40124>, + <40429 40749 41160 41525 41800>, + <42271 42754 43237 43691 43888>; + }; + + qcom,bp-c-table-1 { + qcom,temperature = <(-20)>; + qcom,nrows = <35>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 57242 33162 43935 47433 43683 43715 55044>, + <43661 53533 33154 43966 47535 43707 43717 53512>, + <43664 54313 33152 43605 47154 43711 43736 53256>, + <43748 10827 33152 43587 47238 43699 43743 54029>, + <43723 10257 33152 43640 47977 43703 43730 53790>, + <43554 12213 33164 43532 48042 43663 43732 56388>, + <43625 11560 33206 43730 47803 43655 43567 56850>, + <43918 8255 32859 43724 42418 43678 43559 55529>, + <43783 9997 33173 43744 42220 43753 43583 56047>, + <43255 15048 33252 43672 42915 43765 43581 50963>, + <43029 14912 33276 43648 42942 43712 43576 50743>, + <43422 15280 33244 43698 43005 43534 43579 49501>, + <44644 15111 33212 43659 42051 43576 43570 50814>, + <44246 14406 33270 43675 48101 43712 43577 50428>, + <41603 16039 33087 43666 47963 43760 43570 50947>, + <41853 15987 33222 43759 47130 43751 43577 50697>, + <41263 16376 33173 43718 47602 43670 43579 49503>, + <42904 16145 33183 43559 48866 43674 43579 50856>, + <42058 15543 33257 43313 47326 43664 43994 51104>, + <47652 15573 33214 42336 41919 43716 45031 50181>, + <47254 15760 32774 47854 41975 43719 44905 50334>, + <47427 12947 32811 42307 41914 43719 44978 50721>, + <48957 13263 32831 42199 41777 43719 43504 49549>, + <48623 12326 32865 42222 41119 43718 43129 49576>, + <45656 12574 33192 42352 41210 43713 43476 49464>, + <45245 13834 32976 47687 41196 43713 44793 49501>, + <45513 14161 32968 47714 41132 43718 43331 49435>, + <47035 13682 32986 47768 41794 43738 43116 49621>, + <46299 3001 32780 47692 41445 43728 43037 50616>, + <46532 2216 32855 48003 42610 43743 43021 55738>, + <35766 2306 33037 47884 48090 43713 43202 55029>, + <34912 4057 33124 47963 48182 43713 43196 11457>, + <36573 3528 34768 41839 36598 43753 43935 15406>, + <35983 1015 34644 43082 33289 43655 43549 2911>, + <36282 225 34228 43555 35807 43657 43740 13762>; + }; + + qcom,bp-c-table-2 { + qcom,temperature = <(-10)>; + qcom,nrows = <35>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 57242 33162 43935 47433 43683 43715 55044>, + <43661 53533 33154 43966 47535 43707 43717 53512>, + <43664 54313 33152 43605 47154 43711 43736 53256>, + <43748 10827 33152 43587 47238 43699 43743 54029>, + <43723 10257 33152 43640 47977 43703 43730 53790>, + <43554 12213 33164 43532 48042 43663 43732 56388>, + <43625 11560 33206 43730 47803 43655 43567 56850>, + <43918 8255 32859 43724 42418 43678 43559 55529>, + <43783 9997 33173 43744 42220 43753 43583 56047>, + <43255 15048 33252 43672 42915 43765 43581 50963>, + <43029 14912 33276 43648 42942 43712 43576 50743>, + <43422 15280 33244 43698 43005 43534 43579 49501>, + <44644 15111 33212 43659 42051 43576 43570 50814>, + <44246 14406 33270 43675 48101 43712 43577 50428>, + <41603 16039 33087 43666 47963 43760 43570 50947>, + <41853 15987 33222 43759 47130 43751 43577 50697>, + <41263 16376 33173 43718 47602 43670 43579 49503>, + <42904 16145 33183 43559 48866 43674 43579 50856>, + <42058 15543 33257 43313 47326 43664 43994 51104>, + <47652 15573 33214 42336 41919 43716 45031 50181>, + <47254 15760 32774 47854 41975 43719 44905 50334>, + <47427 12947 32811 42307 41914 43719 44978 50721>, + <48957 13263 32831 42199 41777 43719 43504 49549>, + <48623 12326 32865 42222 41119 43718 43129 49576>, + <45656 12574 33192 42352 41210 43713 43476 49464>, + <45245 13834 32976 47687 41196 43713 44793 49501>, + <45513 14161 32968 47714 41132 43718 43331 49435>, + <47035 13682 32986 47768 41794 43738 43116 49621>, + <46299 3001 32780 47692 41445 43728 43037 50616>, + <46532 2216 32855 48003 42610 43743 43021 55738>, + <35766 2306 33037 47884 48090 43713 43202 55029>, + <34912 4057 33124 47963 48182 43713 43196 11457>, + <36573 3528 34768 41839 36598 43753 43935 15406>, + <35983 1015 34644 43082 33289 43655 43549 2911>, + <36282 225 34228 43555 35807 43657 43740 13762>; + }; + + qcom,bp-c-table-3 { + qcom,temperature = <0>; + qcom,nrows = <35>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 57242 33162 43935 47433 43683 43715 55044>, + <43661 53533 33154 43966 47535 43707 43717 53512>, + <43664 54313 33152 43605 47154 43711 43736 53256>, + <43748 10827 33152 43587 47238 43699 43743 54029>, + <43723 10257 33152 43640 47977 43703 43730 53790>, + <43554 12213 33164 43532 48042 43663 43732 56388>, + <43625 11560 33206 43730 47803 43655 43567 56850>, + <43918 8255 32859 43724 42418 43678 43559 55529>, + <43783 9997 33173 43744 42220 43753 43583 56047>, + <43255 15048 33252 43672 42915 43765 43581 50963>, + <43029 14912 33276 43648 42942 43712 43576 50743>, + <43422 15280 33244 43698 43005 43534 43579 49501>, + <44644 15111 33212 43659 42051 43576 43570 50814>, + <44246 14406 33270 43675 48101 43712 43577 50428>, + <41603 16039 33087 43666 47963 43760 43570 50947>, + <41853 15987 33222 43759 47130 43751 43577 50697>, + <41263 16376 33173 43718 47602 43670 43579 49503>, + <42904 16145 33183 43559 48866 43674 43579 50856>, + <42058 15543 33257 43313 47326 43664 43994 51104>, + <47652 15573 33214 42336 41919 43716 45031 50181>, + <47254 15760 32774 47854 41975 43719 44905 50334>, + <47427 12947 32811 42307 41914 43719 44978 50721>, + <48957 13263 32831 42199 41777 43719 43504 49549>, + <48623 12326 32865 42222 41119 43718 43129 49576>, + <45656 12574 33192 42352 41210 43713 43476 49464>, + <45245 13834 32976 47687 41196 43713 44793 49501>, + <45513 14161 32968 47714 41132 43718 43331 49435>, + <47035 13682 32986 47768 41794 43738 43116 49621>, + <46299 3001 32780 47692 41445 43728 43037 50616>, + <46532 2216 32855 48003 42610 43743 43021 55738>, + <35766 2306 33037 47884 48090 43713 43202 55029>, + <34912 4057 33124 47963 48182 43713 43196 11457>, + <36573 3528 34768 41839 36598 43753 43935 15406>, + <35983 1015 34644 43082 33289 43655 43549 2911>, + <36282 225 34228 43555 35807 43657 43740 13762>; + }; + + qcom,bp-c-table-4 { + qcom,temperature = <10>; + qcom,nrows = <35>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 57242 35713 43533 42854 43686 43740 58470>, + <43661 53556 35433 43557 42989 43699 43734 59267>, + <43664 54518 35387 43563 42926 43662 43562 59135>, + <43748 10753 35528 43736 42603 43672 43561 57641>, + <43723 10460 35485 43721 42539 43753 43567 57373>, + <43554 11897 46404 43756 42659 43718 43553 58261>, + <43625 11665 46340 43661 41428 43538 43579 60704>, + <43918 8447 46434 43711 41387 43982 43571 60589>, + <43783 10183 46336 43694 41015 43442 43531 61136>, + <43255 14983 46394 43688 41822 44783 43522 59466>, + <43029 14959 46578 43688 41738 44688 43575 60224>, + <43422 14916 46572 43688 41841 44668 43569 60206>, + <44644 15297 46473 43154 41827 43968 43898 59625>, + <44246 14545 46519 41863 44885 43565 44059 61155>, + <41603 14603 46465 41969 44264 43555 44443 59728>, + <41853 15908 46160 41731 44193 43564 44152 59493>, + <41263 16302 46146 41855 44208 43566 44248 60287>, + <42904 16321 46147 41128 44185 43560 44175 60369>, + <42058 16244 46195 41167 44231 43733 44196 60193>, + <47652 15553 46086 40980 44460 43732 44897 60252>, + <47254 15805 46122 41038 41679 43732 44945 59515>, + <47427 15733 46090 41394 40998 43733 44919 60971>, + <48957 12885 46209 41392 41024 43729 44372 61171>, + <48623 12311 46929 41005 44104 43732 44202 38362>, + <45656 13978 46956 40966 44239 43562 44805 38105>, + <45245 14211 46877 41087 44138 43562 44908 37920>, + <45513 13328 46951 41832 44210 43563 43332 38848>, + <47035 2810 46915 41197 44171 43733 44773 38140>, + <46299 2877 46940 41060 44251 43735 44757 38162>, + <46532 2102 46967 41028 44132 43734 44699 60127>, + <35766 3788 46899 41229 44332 43728 44696 59634>, + <34912 3220 46902 42649 41815 43731 43281 60675>, + <36573 648 46929 42683 47850 43729 43008 63899>, + <35983 852 46174 41925 48379 43729 43882 63418>, + <36282 91 35476 44681 48555 43767 43633 63337>; + }; + + qcom,bp-c-table-5 { + qcom,temperature = <25>; + qcom,nrows = <35>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 57242 47424 44718 44638 43713 43932 32945>, + <43661 53538 48772 44779 44557 43738 43859 33766>, + <43664 54419 48879 44799 44754 43736 43239 33357>, + <43748 10960 48893 44745 44780 43743 43058 33321>, + <43723 10399 48841 44742 44734 43730 43123 33420>, + <43554 11817 48837 44760 43283 43733 43414 36316>, + <43625 11341 48837 44739 43460 43565 43472 35895>, + <43918 8362 48820 43351 43306 43579 43101 36612>, + <43783 10149 47437 44558 43115 43569 44623 36431>, + <43255 9576 47361 44796 43126 43534 44740 36530>, + <43029 15066 47384 44779 43219 43530 44973 35269>, + <43422 14907 47362 44791 43040 43575 45000 35300>, + <44644 14937 47581 44976 44675 43572 44817 36477>, + <44246 14518 47607 44832 44646 43575 44139 36825>, + <41603 14829 47612 44851 44981 43572 44427 36804>, + <41853 16000 47591 44205 45009 43571 44316 36727>, + <41263 15902 47491 44160 45030 43581 41713 36840>, + <42904 16260 47534 44170 44974 43580 44315 36600>, + <42058 16157 47218 44180 44627 43577 44433 35157>, + <47652 15605 47200 44244 44964 43557 44078 36539>, + <47254 15746 47208 44152 44842 43559 44834 36406>, + <47427 12979 47130 44475 44094 43559 44649 36707>, + <48957 13282 47165 44477 44383 43578 44742 35937>, + <48623 12384 47311 44075 41502 43576 44177 36037>, + <45656 13846 47311 44871 44570 43582 45041 35617>, + <45245 14151 47307 44871 44732 43582 45041 35757>, + <45513 13703 47346 44887 43346 43582 45009 35411>, + <47035 2658 47334 44223 44770 43583 44928 35778>, + <46299 2207 47252 44214 44592 43583 44597 35653>, + <46532 2530 47263 44173 44660 43582 44756 35019>, + <35766 4021 47258 44247 45002 43582 44552 35223>, + <34912 3496 47294 44145 44204 43582 44556 36572>, + <36573 591 47320 44427 41595 43577 43373 33328>, + <35983 1 47539 44668 42550 43557 43855 34343>, + <36282 474 48838 44588 41374 43731 43829 34533>; + }; + + qcom,bp-c-table-6 { + qcom,temperature = <40>; + qcom,nrows = <35>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 57242 42133 43465 43515 43567 43802 48586>, + <43661 53744 42121 43460 43454 43553 43412 48219>, + <43664 55132 42175 43482 43103 43556 44718 48145>, + <43748 10895 42157 43480 43135 43579 44651 48173>, + <43723 11109 42835 43483 43036 43582 45019 48382>, + <43554 11961 42826 43463 43222 43571 44088 48990>, + <43625 11485 42863 43464 43157 43530 44543 49119>, + <43918 9018 42756 43395 43194 43522 44238 48736>, + <43783 9743 42793 43101 43187 43527 45015 48840>, + <43255 9712 42945 43106 43190 43548 44988 47445>, + <43029 15030 42959 43052 43868 43542 44978 47404>, + <43422 15083 42993 43063 43842 43551 44818 47400>, + <44644 14899 42987 43429 43500 43549 44559 49054>, + <44246 15214 42905 43400 43517 43550 44858 49031>, + <41603 14415 42891 43470 43319 43536 44101 48933>, + <41853 14691 42919 43309 43271 43546 44465 48897>, + <41263 16065 42587 43476 43270 43547 44430 49115>, + <42904 15940 42619 43313 43465 43524 44328 49077>, + <42058 16174 42503 43282 43508 43522 44154 49083>, + <47652 15504 42537 43328 43475 43529 44913 49043>, + <47254 15804 42712 44723 43377 43528 44652 48924>, + <47427 12938 42697 44686 44753 43529 43356 48381>, + <48957 13252 42721 44711 44636 43533 43314 48188>, + <48623 12731 42730 43320 44638 43526 43323 48981>, + <45656 13916 42629 43496 43009 43533 44948 47599>, + <45245 13475 42637 43415 43008 43520 44963 47506>, + <45513 13801 42637 43412 43026 43521 44561 47593>, + <47035 2655 42628 43490 43448 43520 44769 47365>, + <46299 2267 42629 43492 43471 43526 43329 48828>, + <46532 2349 42653 43472 43320 43524 44685 48683>, + <35766 4035 42723 43361 43332 43525 44756 49145>, + <34912 3576 42751 43382 44583 43525 44730 48304>, + <36573 902 42695 44672 44941 43544 44769 48514>, + <35983 114 42608 43313 41563 43526 43115 45139>, + <36282 265 42141 43253 44158 43539 43805 45990>; + }; + + qcom,bp-c-table-7 { + qcom,temperature = <50>; + qcom,nrows = <35>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 57242 41227 43112 43026 43569 43403 47305>, + <43661 53643 41253 43118 43069 43573 44718 47282>, + <43664 55052 41260 43112 43052 43531 44591 47961>, + <43748 54633 41431 43028 43228 43528 44963 47994>, + <43723 11214 41438 43024 43212 43534 44833 47879>, + <43554 10499 41423 43013 43245 43522 44252 48070>, + <43625 11454 41464 43016 43189 43526 44539 48063>, + <43918 9115 41365 43047 43842 43544 44300 47627>, + <43783 9955 41355 43217 43878 43551 44289 47845>, + <43255 9634 41377 43213 43781 43627 44387 42320>, + <43029 9585 41387 43196 43824 43616 44109 42287>, + <43422 15021 41055 43860 43825 43619 44105 42434>, + <44644 15092 41029 43230 43025 43631 44641 47702>, + <44246 15150 41034 43200 43033 43625 44918 47734>, + <41603 14337 41086 43203 43089 43616 44202 48056>, + <41853 14628 41064 43218 43402 43627 44887 48025>, + <41263 16022 40975 43209 43396 43625 44811 48045>, + <42904 15995 41005 43042 43027 43536 44082 47625>, + <42058 16346 41176 43022 43119 43551 44900 47636>, + <47652 15492 41162 43114 43434 43524 44571 48033>, + <47254 15803 41188 43105 43481 43524 43279 47915>, + <47427 12943 41108 43121 43378 43546 43519 47937>, + <48957 13265 41093 43122 43333 43545 43501 47966>, + <48623 12682 41097 43219 43300 43538 43458 48045>, + <45656 13904 41138 43190 43157 43541 44746 42470>, + <45245 13484 41150 43187 43232 43624 44726 42491>, + <45513 13806 41145 43166 43254 43627 44768 42451>, + <47035 2647 41139 43225 43044 43626 44548 42323>, + <46299 2257 41096 43055 43125 43540 44738 47861>, + <46532 2367 41102 43042 43407 43541 44686 47621>, + <35766 4054 41088 43060 43320 43543 43359 48021>, + <34912 3528 41112 43108 43329 43537 44681 47997>, + <36573 914 41108 43094 44581 43626 44686 47213>, + <35983 117 40995 43438 44225 43624 43457 48705>, + <36282 263 41340 43829 44176 43645 43807 48659>; + }; + + qcom,bp-d-table-0 { + qcom,temperature = <25>; + qcom,soc = < 0 39 58 78 97>, + < 136 195 292 429 605>, + < 703 820 1230 1660 2089>, + < 2519 2949 3378 3808 4238>, + < 4668 5097 5527 5957 6386>, + < 6679 7011 7441 7793 8046>, + < 8476 8906 9335 9765 10000>; + qcom,ocv = <31073 31787 32126 32450 32757>, + <33307 33966 34776 35568 36347>, + <36629 36779 36885 37084 37355>, + <37558 37757 37937 38107 38291>, + <38507 38759 39063 39479 39993>, + <40313 40635 41062 41430 41705>, + <42182 42666 43143 43619 43880>; + }; + + qcom,bp-d-table-1 { + qcom,temperature = <(-20)>; + qcom,nrows = <35>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 53660 64259 21845 21845 43689 43705 21845>, + <43661 55283 63747 21845 21845 43688 43685 21845>, + <43664 54516 65027 21845 21845 43691 43707 21845>, + <43748 54781 65312 21845 21845 43691 43711 21845>, + <43723 10979 64671 21845 21845 43690 43697 21845>, + <43554 10413 64559 21845 21845 43690 43650 21845>, + <43625 11995 65471 21845 21845 43690 43768 21845>, + <43918 11772 65193 21845 21845 43690 43556 21845>, + <43783 9046 63525 21845 12654 43690 43541 21845>, + <43255 9875 64334 21845 62536 43690 43642 21845>, + <43029 10122 64245 21845 64090 43690 43632 21845>, + <43422 10052 58432 21845 61360 43690 43646 21845>, + <44644 9577 58479 21845 60678 43690 43941 21845>, + <44246 14944 58905 21845 37937 43690 43613 21845>, + <41603 15156 57646 21845 38947 43690 43936 21845>, + <41853 14584 57594 30648 33702 43691 43917 21845>, + <41263 14427 60725 27562 36567 43691 43908 21845>, + <42904 14628 60593 3502 35555 43691 44003 21845>, + <42058 16013 60942 9504 46887 43691 44024 21845>, + <47652 15979 59707 54774 45349 43691 44020 21845>, + <47254 16375 59901 55359 45899 43691 43992 21845>, + <47427 16213 59745 52773 45785 43691 43987 21845>, + <48957 15390 59604 61929 48535 43691 43813 21845>, + <48623 15678 59596 61556 48189 43691 43885 21845>, + <45656 12909 60290 61479 48571 43691 43146 21845>, + <45245 13157 59995 61550 45702 43691 43256 21845>, + <45513 12699 59988 63155 45060 43691 43042 21845>, + <47035 14233 60017 52167 46878 43691 43300 21845>, + <46299 13643 60023 49709 33362 43691 44591 21845>, + <46532 3038 59973 49605 33792 43691 44671 21845>, + <35766 2091 60209 49630 33206 43691 43171 21845>, + <34912 3638 60014 53309 35892 43691 43236 21845>, + <36573 3469 59923 8750 35237 43691 43149 21845>, + <35983 186 60411 14552 35339 43691 43993 21845>, + <36282 379 60263 15528 46403 43691 43599 21845>; + }; + + qcom,bp-d-table-2 { + qcom,temperature = <(-10)>; + qcom,nrows = <35>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 54802 38511 21845 21845 43708 43690 21845>, + <43661 54507 38770 21845 21845 43685 43706 21845>, + <43664 54697 38133 21845 21845 43681 43700 21845>, + <43748 54638 38012 21845 21845 43682 43674 21845>, + <43723 10798 38302 21845 21845 43694 43759 21845>, + <43554 11093 38352 21845 21845 43690 43741 21845>, + <43625 11926 38099 21845 26496 43690 43594 21845>, + <43918 11742 38511 17769 63508 43690 43826 21845>, + <43783 8197 36957 6979 33067 43690 43253 21845>, + <43255 10134 37434 11872 46839 43691 43115 21845>, + <43029 9351 40418 55369 45818 43691 43080 21845>, + <43422 9308 40097 53114 48256 43691 43116 21845>, + <44644 15047 40617 51903 45701 43691 43232 21845>, + <44246 15336 39176 63993 47360 43691 43165 21845>, + <41603 15195 39341 57419 47910 43691 43195 21845>, + <41853 14393 40628 60164 47721 43691 43851 21845>, + <41263 14745 39321 38593 47752 43688 43865 21845>, + <42904 14701 39386 40090 47661 43688 43880 21678>, + <42058 16115 40618 39879 47661 43688 43805 23876>, + <47652 15943 39269 34621 47760 43688 43797 22748>, + <47254 16163 39392 32897 47752 43688 43880 17639>, + <47427 15509 39233 33481 47846 43688 43883 17982>, + <48957 15770 40653 33286 42310 43688 43143 17979>, + <48623 13013 39191 33379 47966 43688 43066 18219>, + <45656 13140 39385 33336 48818 43688 43220 17499>, + <45245 12787 39380 32865 48374 43688 43413 22649>, + <45513 14314 39185 39738 45069 43688 44835 22280>, + <47035 13569 39340 39696 36710 43688 43349 21845>, + <46299 2657 39328 38978 36513 43688 43041 21845>, + <46532 2853 39348 40563 35809 43688 43194 21845>, + <35766 2519 39310 38436 46217 43688 43221 21845>, + <34912 3883 38978 61153 46097 43688 43206 21845>, + <36573 3351 39018 58953 46669 43688 43165 21845>, + <35983 149 38922 64705 48475 43691 43892 21845>, + <36282 278 38920 61786 48986 43691 43803 21845>; + }; + + qcom,bp-d-table-3 { + qcom,temperature = <0>; + qcom,nrows = <35>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 53322 33863 21845 21845 43708 43690 21845>, + <43661 55283 34269 21845 21845 43685 43690 21845>, + <43664 54316 34256 21845 21845 43686 43673 21845>, + <43748 54543 34294 21845 21845 43682 43730 21845>, + <43723 10782 34189 21845 21845 43695 43540 21845>, + <43554 10290 33841 6719 19581 43691 44006 21845>, + <43625 11898 34689 56657 63547 43691 43165 21845>, + <43918 11526 32845 61446 35202 43691 43513 21845>, + <43783 8312 33572 38179 48098 43691 43379 21594>, + <43255 10006 33686 40556 42268 43691 44774 17106>, + <43029 9219 33700 39137 42289 43691 43343 20084>, + <43422 9717 33316 34286 42425 43691 43404 19116>, + <44644 15062 36217 39155 42200 43691 43256 19098>, + <44246 15246 36132 33160 41293 43691 43188 30752>, + <41603 15172 33415 36549 41325 43688 43232 27956>, + <41853 14444 36216 46143 42557 43688 43050 5309>, + <41263 14786 33442 45669 42558 43688 43236 7830>, + <42904 14683 36160 48664 42559 43688 43197 1950>, + <42058 16088 36183 47657 42931 43689 43881 701>, + <47652 15953 33454 42987 42970 43689 43791 2362>, + <47254 16138 36198 42505 42912 43689 43881 13587>, + <47427 15403 36193 42244 42639 43689 43226 14166>, + <48957 15645 33414 47258 42212 43694 43127 13661>, + <48623 13232 33411 48814 47742 43694 43123 2532>, + <45656 12343 33436 48939 47339 43692 43131 3977>, + <45245 14050 33522 48174 48368 43701 43319 311>, + <45513 13314 33323 48604 46167 43721 44868 4246>, + <47035 13695 36319 48194 46605 43774 43038 7383>, + <46299 2962 36155 46822 48393 43750 43361 4642>, + <46532 2301 36101 46419 49096 43756 44559 4387>, + <35766 3748 36350 46384 48252 43678 43504 5425>, + <34912 3246 36279 35769 48415 43675 43440 28174>, + <36573 672 36322 36309 48558 43699 43048 24705>, + <35983 237 36172 39178 48677 43690 43998 31375>, + <36282 309 33509 37768 47195 43690 43585 31013>; + }; + + qcom,bp-d-table-4 { + qcom,temperature = <10>; + qcom,nrows = <35>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 53271 35077 22500 21845 43664 43690 21845>, + <43661 55175 34854 31526 21845 43674 43690 21845>, + <43664 54513 35674 7356 21974 43651 43690 21845>, + <43748 54741 35833 13192 30774 43659 43549 21845>, + <43723 10812 35350 55025 3927 43699 43826 21845>, + <43554 10300 46360 57507 64861 43681 43395 21845>, + <43625 11863 46177 36167 35314 43689 44670 26318>, + <43918 11622 46227 46964 48874 43689 44183 81>, + <43783 8301 46261 48620 42875 43689 44663 12523>, + <43255 10014 46935 48002 42614 43689 43488 10129>, + <43029 9339 46959 47988 42924 43694 43290 8490>, + <43422 9513 46873 42332 42530 43694 43123 8719>, + <44644 15085 46992 42601 41093 43694 43235 11942>, + <44246 15272 47011 42578 41498 43693 43084 56599>, + <41603 14504 46976 41110 41773 43709 43434 50432>, + <41853 14414 47078 41145 44352 43743 44210 50116>, + <41263 14810 47081 41943 44097 43734 45020 51453>, + <42904 14709 47050 41679 44258 43563 44716 61813>, + <42058 16074 47007 41703 44806 43560 44710 64931>, + <47652 16266 47030 41560 44198 43560 44912 64648>, + <47254 15540 47094 41735 41641 43561 44444 64959>, + <47427 15805 47101 41149 41538 43554 44211 64920>, + <48957 13036 46985 41384 41127 43560 44825 62142>, + <48623 13062 47037 42658 41218 43734 45033 61588>, + <45656 12751 47060 42824 42219 43741 44812 62670>, + <45245 13944 47059 41996 47951 43743 45024 51312>, + <45513 13374 47012 42380 48566 43736 43300 52568>, + <47035 2737 46709 47294 47275 43721 43488 52316>, + <46299 3028 46710 47279 48111 43773 43420 52578>, + <46532 2104 46708 47987 48038 43769 43416 50102>, + <35766 3800 47020 47296 47747 43775 43298 49554>, + <34912 3273 47018 47150 47850 43768 43463 51026>, + <36573 767 46689 47245 42096 43751 43415 50437>, + <35983 245 46837 48031 41435 43757 43095 55964>, + <36282 289 46721 47688 41007 43753 43133 50459>; + }; + + qcom,bp-d-table-5 { + qcom,temperature = <25>; + qcom,nrows = <35>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 54219 48371 21845 21845 43690 43690 21845>, + <43661 54913 49007 21845 21845 43690 43690 21845>, + <43664 55252 49112 29304 21845 43709 43577 21845>, + <43748 54376 49035 14095 21845 43667 43187 21845>, + <43723 54623 48767 52307 206 43773 43306 21845>, + <43554 10417 48846 46060 34294 43562 44814 56827>, + <43625 11780 48798 41983 47583 43561 44156 58008>, + <43918 11634 48775 44406 42177 43741 44292 60060>, + <43783 8282 47486 44470 41913 43729 44378 37438>, + <43255 10065 47457 44045 44442 43565 44323 39292>, + <43029 9663 47397 44133 44300 43552 44125 39294>, + <43422 9473 47413 44057 44266 43554 44902 39755>, + <44644 15039 47405 45020 44676 43567 44643 34664>, + <44246 14966 47593 44942 44777 43577 44610 32807>, + <41603 15169 47563 44934 44714 43569 44915 33463>, + <41853 14364 47196 44965 43367 43530 44240 36070>, + <41263 14807 47547 45004 44663 43573 44377 36281>, + <42904 16027 47521 45021 44816 43529 44536 36227>, + <42058 15985 47531 45012 44861 43528 44256 35896>, + <47652 16185 47223 44836 44985 43530 44198 36654>, + <47254 15553 47208 44813 44649 43572 44186 36449>, + <47427 15821 47215 44816 44547 43569 44283 36566>, + <48957 12861 47116 44925 44985 43570 44198 36429>, + <48623 12445 47104 44071 44510 43581 44894 36162>, + <45656 13971 47315 44434 41441 43580 44690 34454>, + <45245 14291 47301 44332 41440 43577 43519 34545>, + <45513 13329 47322 44393 41915 43554 43076 32803>, + <47035 2764 47302 44387 44525 43560 43320 33769>, + <46299 2940 47308 44296 44042 43563 44707 33307>, + <46532 2115 47307 44504 44239 43563 44773 33501>, + <35766 3692 47301 44425 44179 43564 44569 33511>, + <34912 3072 47308 44128 44275 43555 44553 33335>, + <36573 557 47142 44248 44167 43556 44760 33295>, + <35983 201 47174 44214 44810 43582 44682 33493>, + <36282 450 47543 44888 45049 43581 43347 33510>; + }; + + qcom,bp-d-table-6 { + qcom,temperature = <40>; + qcom,nrows = <35>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 53902 42383 33702 40084 43665 43923 53967>, + <43661 53736 42104 46522 34491 43737 43111 51998>, + <43664 54804 41999 45870 36264 43552 43312 65357>, + <43748 54412 42195 48804 34951 43572 44746 57387>, + <43723 54736 42235 42413 46864 43524 44978 60067>, + <43554 11108 42174 44291 48176 43624 44264 39592>, + <43625 11982 42846 44962 48039 43539 44425 35956>, + <43918 11739 42877 44683 42986 43582 41645 35605>, + <43783 8392 42815 43388 41558 43577 41494 46618>, + <43255 10133 42998 43291 44765 43528 41582 48436>, + <43029 9255 42983 43387 44704 43522 41611 48531>, + <43422 9677 42985 43342 43274 43522 44819 48255>, + <44644 9595 42892 43448 43245 43526 44856 48889>, + <44246 14889 42580 43435 43220 43537 44925 48820>, + <41603 15161 42597 43078 43065 43539 44202 47462>, + <41853 14528 42502 43126 43128 43539 44182 47466>, + <41263 14821 42507 43454 43363 43626 44203 48748>, + <42904 16004 42540 43516 44658 43627 44805 48298>, + <42058 15943 42715 43491 44561 43626 44624 49001>, + <47652 16141 42738 43402 43356 43543 44603 48640>, + <47254 15569 42653 43455 43498 43551 44556 47459>, + <47427 15839 42638 43400 43079 43524 44959 47559>, + <48957 12811 42685 43405 43454 43524 45035 47399>, + <48623 12432 42680 43295 44608 43547 44954 48979>, + <45656 13956 42687 44775 44102 43525 43423 45666>, + <45245 14287 42672 44598 44093 43520 43101 45599>, + <45513 13322 42676 44665 44576 43575 43479 48209>, + <47035 2789 42632 44678 43358 43580 43488 49000>, + <46299 2923 42624 43346 43479 43581 43321 49037>, + <46532 2169 42654 43380 43414 43571 43329 48754>, + <35766 3588 42746 43317 43439 43574 44688 48861>, + <34912 3130 42739 43511 43091 43531 44744 48874>, + <36573 710 42691 43516 43085 43533 44658 48875>, + <35983 146 42536 43505 43109 43525 44807 48839>, + <36282 390 42533 43470 43114 43545 44199 48653>; + }; + + qcom,bp-d-table-7 { + qcom,temperature = <50>; + qcom,nrows = <35>; + qcom,ncols = <8>; + qcom,conv-factor = <10000 10000 10000 10000 10000 100000 100000 10000>; + qcom,data = <43690 53934 41328 47651 35472 43932 43196 60132>, + <43661 53365 41244 42846 46743 43953 43491 37497>, + <43664 55019 41231 42697 45215 43943 43343 40560>, + <43748 55101 41278 40981 45727 43946 44756 39496>, + <43723 54389 41257 41911 48354 43614 44987 34720>, + <43554 11165 41423 44189 47224 43639 44211 35992>, + <43625 11944 41448 43351 42398 43626 44419 46439>, + <43918 11651 41395 43422 42669 43530 41659 45354>, + <43783 8320 41054 43083 41872 43529 41489 45735>, + <43255 9819 41060 43115 44692 43524 41570 47211>, + <43029 9361 40983 43107 43398 43544 41477 47872>, + <43422 9631 40985 43452 43428 43525 44063 47991>, + <44644 9482 41010 43160 43851 43541 45010 42279>, + <44246 15096 41173 43185 43149 43622 44632 42296>, + <41603 15299 41160 43239 43258 43646 44074 42341>, + <41853 14485 41197 43149 43221 43623 44891 42346>, + <41263 14734 41118 43166 43452 43621 45028 47847>, + <42904 16052 41102 43237 44787 43647 44764 47921>, + <42058 15936 41146 43158 44773 43644 43360 48091>, + <47652 16142 41812 43162 43509 43643 43390 47818>, + <47254 15575 41819 43258 43023 43622 44665 42269>, + <47427 15824 41807 43263 43263 43628 44839 42443>, + <48957 12802 41840 43210 43051 43626 44839 42297>, + <48623 12437 41851 43116 44697 43541 44622 47879>, + <45656 13954 41850 43477 44990 43536 43518 47556>, + <45245 14326 41850 43275 44668 43545 43395 47609>, + <45513 13374 41854 43278 43511 43523 43373 47951>, + <47035 2796 41841 43314 43221 43523 44984 48063>, + <46299 2834 41800 43394 43223 43535 44789 47662>, + <46532 2144 41795 43119 43051 43529 43365 47770>, + <35766 3599 41811 43058 43153 43524 44783 42340>, + <34912 3106 41135 43253 43136 43545 44751 42285>, + <36573 715 41150 43161 43137 43542 44755 42441>, + <35983 130 41090 43199 43158 43616 44591 42441>, + <36282 434 41112 43172 43237 43642 44591 42452>; + }; +}; diff --git a/qcom/qcs610-iot.dtsi b/qcom/qcs610-iot.dtsi index ab1d6536..c69038b0 100755 --- a/qcom/qcs610-iot.dtsi +++ b/qcom/qcs610-iot.dtsi @@ -8,12 +8,10 @@ #include <dt-bindings/clock/qcom,dispcc-sm6150.h> #include <dt-bindings/clock/qcom,gpucc-sm6150.h> #include <dt-bindings/iio/qti_power_supply_iio.h> - #include "camera/qcs610-camera-sensor-idp.dtsi" #include "sm6150-audio.dtsi" -#include "sm6150-ext-codec-audio-overlay.dtsi" -#include "sm6150-external-codec.dtsi" +#include "sm6150-audio-overlay.dtsi" / { model = "Qualcomm Technologies, Inc. QCS610 IOT"; diff --git a/qcom/qcs610.dtsi b/qcom/qcs610.dtsi index a9816f46..552828d4 100755 --- a/qcom/qcs610.dtsi +++ b/qcom/qcs610.dtsi @@ -14,16 +14,6 @@ swr2 = &swr2; }; -&reserved_memory { - memshare_mem: memshare_region { - compatible = "shared-dma-pool"; - no-map; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - alignment = <0x0 0x100000>; - size = <0x0 0x800000>; - }; -}; - &soc { qcom,memshare { compatible = "qcom,memshare"; @@ -46,7 +36,6 @@ qcom,client_3 { compatible = "qcom,memshare-peripheral"; qcom,peripheral-size = <0x500000>; - memory-region = <&memshare_mem>; qcom,client-id = <1>; qcom,allocate-on-request; label = "modem"; diff --git a/qcom/sa410m.dtsi b/qcom/sa410m.dtsi index 53e32cc8..438433b1 100755 --- a/qcom/sa410m.dtsi +++ b/qcom/sa410m.dtsi @@ -394,11 +394,6 @@ #address-cells = <1>; #size-cells = <1>; - download_mode@0 { - compatible = "qcom,msm-imem-download_mode"; - reg = <0x0 0x8>; - }; - mem_dump_table@10 { compatible = "qcom,msm-imem-mem_dump_table"; reg = <0x10 0x8>; @@ -433,16 +428,6 @@ compatible = "qcom,msm-imem-diag-dload"; reg = <0xc8 0xc8>; }; - - emergency_download_mode@fe0 { - compatible = "qcom,msm-imem-emergency_download_mode"; - reg = <0xfe0 0xc>; - }; - - ss_mdump@b88 { - compatible = "qcom,msm-imem-minidump"; - reg = <0xb88 0x1c>; - }; }; dload_mode { diff --git a/qcom/sa415m-ccard-ga.dts b/qcom/sa415m-ccard-ga.dts new file mode 100755 index 00000000..05ff078b --- /dev/null +++ b/qcom/sa415m-ccard-ga.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "sa415m.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA415M CCARD GA"; + compatible = "qcom,sa415m-ccard", + "qcom,sa415m", "qcom,ccard"; + qcom,board-id = <0x10119 0>; + +}; + diff --git a/qcom/sa415m-ccard-pcie-ep.dts b/qcom/sa415m-ccard-pcie-ep.dts new file mode 100755 index 00000000..63e97995 --- /dev/null +++ b/qcom/sa415m-ccard-pcie-ep.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa415m.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA415M CCARD PCIE-EP"; + compatible = "qcom,sa415m-ccard", + "qcom,sa415m", "qcom,ccard"; + qcom,board-id = <25 1>, <25 0x101>; +}; + diff --git a/qcom/sa415m-ccard-usb-ep-ga.dts b/qcom/sa415m-ccard-usb-ep-ga.dts new file mode 100755 index 00000000..3f80c7cb --- /dev/null +++ b/qcom/sa415m-ccard-usb-ep-ga.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa415m.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA415M CCARD USB-EP GA"; + compatible = "qcom,sa415m-ccard", + "qcom,sa415m", "qcom,ccard"; + qcom,board-id = <0x10119 2>; +}; + diff --git a/qcom/sa415m-ccard-usb-ep.dts b/qcom/sa415m-ccard-usb-ep.dts new file mode 100755 index 00000000..816b9b26 --- /dev/null +++ b/qcom/sa415m-ccard-usb-ep.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa415m.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA415M CCARD USB-EF"; + compatible = "qcom,sa415m-ccard", + "qcom,sa415m", "qcom,ccard"; + qcom,board-id = <25 2>, <25 0x102>; +}; + diff --git a/qcom/sa415m-ccard.dts b/qcom/sa415m-ccard.dts new file mode 100755 index 00000000..0f74c2bb --- /dev/null +++ b/qcom/sa415m-ccard.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa415m.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA415M CCARD"; + compatible = "qcom,sa415m-ccard", + "qcom,sa415m", "qcom,ccard"; + qcom,board-id = <25 0>, <25 0x100>; +}; + diff --git a/qcom/sa415m-cdp.dts b/qcom/sa415m-cdp.dts new file mode 100755 index 00000000..ca9c5767 --- /dev/null +++ b/qcom/sa415m-cdp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa415m.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA415M CDP"; + compatible = "qcom,sa415m-ccard", + "qcom,sa415m", "qcom,ccard"; + qcom,board-id = <1 0x104>; +}; + diff --git a/qcom/sa415m-mtp-256.dts b/qcom/sa415m-mtp-256.dts new file mode 100755 index 00000000..dfe15e6f --- /dev/null +++ b/qcom/sa415m-mtp-256.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa415m.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA415M MTP (256MB)"; + compatible = "qcom,sa415m-ccard", + "qcom,sa415m", "qcom,ccard"; + qcom,board-id = <8 0x106>; +}; + diff --git a/qcom/sa415m-pinctrl.dtsi b/qcom/sa415m-pinctrl.dtsi new file mode 100755 index 00000000..0eeb0753 --- /dev/null +++ b/qcom/sa415m-pinctrl.dtsi @@ -0,0 +1,1769 @@ +&soc { + tlmm: pinctrl@3900000 { + compatible = "qcom,sa415m-pinctrl"; + reg = <0x3900000 0x300000>, + <0xB204900 0x280>; + reg-names = "pinctrl", "pinctrl_reg"; + interrupts = <0 212 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + + uart2_console_active: uart2_console_active { + mux { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + + uart3_console_active: uart3_console_active { + mux { + pins = "gpio8", "gpio9"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + + uart3_console_sleep: uart3_console_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* I2C CONFIGURATION */ + i2c_1 { + i2c_1_active: i2c_1_active { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_1_sleep: i2c_1_sleep { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_2 { + i2c_2_active: i2c_2_active { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_2_sleep: i2c_2_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_3 { + i2c_3_active: i2c_3_active { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_3_sleep: i2c_3_sleep { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_4 { + i2c_4_active: i2c_4_active { + mux { + pins = "gpio76", "gpio77"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio76", "gpio77"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_4_sleep: i2c_4_sleep { + mux { + pins = "gpio76", "gpio77"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio76", "gpio77"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_5 { + i2c_5_active: i2c_5_active { + mux { + pins = "gpio74", "gpio75"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio74", "gpio75"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_5_sleep: i2c_5_sleep { + mux { + pins = "gpio74", "gpio75"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio74", "gpio75"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_6 { + i2c_6_active: i2c_6_active { + mux { + pins = "gpio65", "gpio66"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio65", "gpio66"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_6_sleep: i2c_6_sleep { + mux { + pins = "gpio65", "gpio66"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio65", "gpio66"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_7 { + i2c_7_active: i2c_7_active { + mux { + pins = "gpio18", "gpio19"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_7_sleep: i2c_7_sleep { + mux { + pins = "gpio18", "gpio19"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /* SPI CONFIGURATION */ + spi_1 { + spi_1_active: spi_1_active { + mux { + pins = "gpio72", "gpio73", + "gpio74", "gpio75"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio72", "gpio73", + "gpio74", "gpio75"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_1_sleep: spi_1_sleep { + mux { + pins = "gpio72", "gpio73", + "gpio74", "gpio75"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio72", "gpio73", + "gpio74", "gpio75"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_2 { + spi_2_active: spi_2_active { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_2_sleep: spi_2_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_3 { + spi_3_active: spi_3_active { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_3_sleep: spi_3_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_4 { + spi_4_active: spi_4_active { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_4_sleep: spi_4_sleep { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + pcie0 { + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio56"; + function = "pcie_clkreq"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /* HS UART CONFIGURATION */ + + blsp1_uart1a: blsp1_uart1a { + blsp1_uart1a_tx_active: blsp1_uart1a_tx_active { + mux { + pins = "gpio0"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1a_tx_sleep: blsp1_uart1a_tx_sleep { + mux { + pins = "gpio0"; + function = "gpio"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart1a_rxcts_active: blsp1_uart1a_rxcts_active { + mux { + pins = "gpio1", "gpio2"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio1", "gpio2"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1a_rxcts_sleep: blsp1_uart1a_rxcts_sleep { + mux { + pins = "gpio1", "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio1", "gpio2"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + blsp1_uart1a_rfr_active: blsp1_uart1a_rfr_active { + mux { + pins = "gpio3"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1a_rfr_sleep: blsp1_uart1a_rfr_sleep { + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + blsp1_uart1b: blsp1_uart1b { + blsp1_uart1b_tx_active: blsp1_uart1b_tx_active { + mux { + pins = "gpio20"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1b_tx_sleep: blsp1_uart1b_tx_sleep { + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart1b_rxcts_active: blsp1_uart1b_rxcts_active { + mux { + pins = "gpio21", "gpio22"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio21", "gpio22"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1b_rxcts_sleep: blsp1_uart1b_rxcts_sleep { + mux { + pins = "gpio21", "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio21", "gpio22"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + blsp1_uart1b_rfr_active: blsp1_uart1b_rfr_active { + mux { + pins = "gpio23"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1b_rfr_sleep: blsp1_uart1b_rfr_sleep { + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + blsp1_uart2a: blsp1_uart2a { + blsp1_uart2a_tx_active: blsp1_uart2a_tx_active { + mux { + pins = "gpio4"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2a_tx_sleep: blsp1_uart2a_tx_sleep { + mux { + pins = "gpio4"; + function = "gpio"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart2a_rxcts_active: blsp1_uart2a_rxcts_active { + mux { + pins = "gpio5", "gpio6"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio5", "gpio6"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2a_rxcts_sleep: blsp1_uart2a_rxcts_sleep { + mux { + pins = "gpio5", "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio1", "gpio2"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + blsp1_uart2a_rfr_active: blsp1_uart2a_rfr_active { + mux { + pins = "gpio7"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2a_rfr_sleep: blsp1_uart2a_rfr_sleep { + mux { + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + blsp1_uart2b: blsp1_uart2b { + blsp1_uart2b_tx_active: blsp1_uart2b_tx_active { + mux { + pins = "gpio63"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2b_tx_sleep: blsp1_uart2b_tx_sleep { + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart2b_rxcts_active: blsp1_uart2b_rxcts_active { + mux { + pins = "gpio64", "gpio65"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio64", "gpio65"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2b_rxcts_sleep: blsp1_uart2b_rxcts_sleep { + mux { + pins = "gpio64", "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio64", "gpio65"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + blsp1_uart2b_rfr_active: blsp1_uart2b_rfr_active { + mux { + pins = "gpio66"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2b_rfr_sleep: blsp1_uart2b_rfr_sleep { + mux { + pins = "gpio66"; + function = "gpio"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + blsp1_uart3: blsp1_uart3 { + blsp1_uart3_tx_active: blsp1_uart3_tx_active { + mux { + pins = "gpio8"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_tx_sleep: blsp1_uart3_tx_sleep { + mux { + pins = "gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart3_rxcts_active: blsp1_uart3_rxcts_active { + mux { + pins = "gpio9", "gpio10"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio9", "gpio10"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_rxcts_sleep: blsp1_uart3_rxcts_sleep { + mux { + pins = "gpio9", "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio9", "gpio10"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + blsp1_uart3_rfr_active: blsp1_uart3_rfr_active { + mux { + pins = "gpio11"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_rfr_sleep: blsp1_uart3_rfr_sleep { + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + blsp1_uart4a: blsp1_uart4a { + blsp1_uart4a_tx_active: blsp1_uart4a_tx_active { + mux { + pins = "gpio20"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4a_tx_sleep: blsp1_uart4a_tx_sleep { + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart4a_rxcts_active: blsp1_uart4a_rxcts_active { + mux { + pins = "gpio21", "gpio22"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio21", "gpio22"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4a_rxcts_sleep: blsp1_uart4a_rxcts_sleep { + mux { + pins = "gpio21", "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio21", "gpio22"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + blsp1_uart4a_rfr_active: blsp1_uart4a_rfr_active { + mux { + pins = "gpio23"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4a_rfr_sleep: blsp1_uart4a_rfr_sleep { + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + blsp1_uart4b: blsp1_uart4b { + blsp1_uart4b_tx_active: blsp1_uart4b_tx_active { + mux { + pins = "gpio16"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4b_tx_sleep: blsp1_uart4b_tx_sleep { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart4b_rxcts_active: blsp1_uart4b_rxcts_active { + mux { + pins = "gpio17", "gpio18"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio17", "gpio18"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4b_rxcts_sleep: blsp1_uart4b_rxcts_sleep { + mux { + pins = "gpio17", "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio17", "gpio18"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + blsp1_uart4b_rfr_active: blsp1_uart4b_rfr_active { + mux { + pins = "gpio19"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4b_rfr_sleep: blsp1_uart4b_rfr_sleep { + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + pcie_ep { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio56"; + function = "pcie_clkreq"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default { + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + cdc_reset_ctrl { + cdc_reset_sleep: cdc_reset_sleep { + mux { + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_reset_active:cdc_reset_active { + mux { + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <8>; + bias-pull-down; + output-high; + }; + }; + }; + + i2s_mclk { + i2s_mclk_sleep: i2s_mclk_sleep { + mux { + pins = "gpio62"; + function = "i2s_mclk"; + }; + + config { + pins = "gpio62"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + i2s_mclk_active: i2s_mclk_active { + mux { + pins = "gpio62"; + function = "i2s_mclk"; + }; + + config { + pins = "gpio62"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + pmx_pri_mi2s_aux { + pri_ws_sleep: pri_ws_sleep { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_sck_sleep: pri_sck_sleep { + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_dout_sleep: pri_dout_sleep { + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_ws_active_master: pri_ws_active_master { + mux { + pins = "gpio12"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + pri_sck_active_master: pri_sck_active_master { + mux { + pins = "gpio15"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio15"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + pri_ws_active_slave: pri_ws_active_slave { + mux { + pins = "gpio12"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + pri_sck_active_slave: pri_sck_active_slave { + mux { + pins = "gpio15"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio15"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + pri_dout_active: pri_dout_active { + mux { + pins = "gpio14"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio14"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + pmx_pri_mi2s_aux_din { + pri_din_sleep: pri_din_sleep { + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_din_active: pri_din_active { + mux { + pins = "gpio13"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio13"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pmx_sec_mi2s_aux { + sec_ws_sleep: sec_ws_sleep { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_sck_sleep: sec_sck_sleep { + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_dout_sleep: sec_dout_sleep { + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_ws_active_master: sec_ws_active_master { + mux { + pins = "gpio16"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio16"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_sck_active_master: sec_sck_active_master { + mux { + pins = "gpio19"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio19"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_ws_active_slave: sec_ws_active_slave { + mux { + pins = "gpio16"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio16"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_sck_active_slave: sec_sck_active_slave { + mux { + pins = "gpio19"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio19"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_dout_active: sec_dout_active { + mux { + pins = "gpio18"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio18"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + mdss_cs_active: mdss_cs_active { + mux { + pins = "gpio21"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio21"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_cs_sleep: mdss_cs_sleep { + mux { + pins = "gpio21"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_te_active: mdss_te_active { + mux { + pins = "gpio22"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio22"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_te_sleep: mdss_te_sleep { + mux { + pins = "gpio22"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_rs_active: mdss_rs_active { + mux { + pins = "gpio23"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio23"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_rs_sleep: mdss_rs_sleep { + mux { + pins = "gpio23"; + function = "ebi2_lcd"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_ad_active: mdss_ad_active { + mux { + pins = "gpio20"; + function = "ebi2_a"; + }; + + config { + pins = "gpio20"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_ad_sleep: mdss_ad_sleep { + mux { + pins = "gpio20"; + function = "ebi2_a"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + }; + }; + + mdss_bl_active: mdss_bl_active { + mux { + pins = "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio91"; + drive-strength = <10>; /* 10 mA */ + bias-disable; /* NO pull */ + output-high; + }; + }; + + mdss_bl_sleep: mdss_bl_sleep { + mux { + pins = "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio91"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO pull */ + output-low; + }; + }; + + pmx_sec_mi2s_aux_din { + sec_din_sleep: sec_din_sleep { + mux { + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_din_active: sec_din_active { + mux { + pins = "gpio17"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio17"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + /* SDC pin type */ + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + num-grp-pins = <1>; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cd_on: cd_on { + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc1_cd_off: cd_off { + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + drive-strength = <2>; + bias-disable; + }; + }; + + sdc1_wlan_gpio_active: sdc1_wlan_gpio_active { + mux { + pins = "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio81"; + output-high; + drive-strength = <8>; + bias-pull-up; + }; + }; + + sdc1_wlan_gpio_sleep: sdc1_wlan_gpio_sleep { + mux { + pins = "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + smb_int_default: smb_int_default { + mux { + pins = "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio42"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio52"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + + cnss_sdio_active: cnss_sdio_active { + mux { + pins = "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio31"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_sdio_sleep: cnss_sdio_sleep { + mux { + pins = "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio31"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + }; + + emac { + emac_pin_pps_0: emac_pin_pps_0 { + mux { + pins = "gpio89"; + function = "emac_pps"; + }; + + config { + pins = "gpio89"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + }; + + sensor_int1_default: sensor_int1_default { + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + drive-strength = <16>; /* 16 mA */ + bias-pull-down; /* pull down */ + }; + }; + + sensor_int2_default: sensor_int2_default { + mux { + pins = "gpio79"; + function = "gpio"; + }; + + config { + pins = "gpio79"; + drive-strength = <16>; /* 16 mA */ + bias-pull-down; /* pull down */ + }; + }; + + pinctrl_pps: ppsgrp { + mux { + pins = "gpio42"; + function = "nav_dr"; + }; + + config { + pins = "gpio42"; + bias-pull-down; + }; + }; + + pmx_can_reset: pmx_can_reset { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + sensor_enable_default: sensor_enable_default { + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + bias-pull-up; + drive-strength = <16>; + output-low; + }; + }; + }; +}; diff --git a/qcom/sa415m-ttp-pcie-ep.dts b/qcom/sa415m-ttp-pcie-ep.dts new file mode 100755 index 00000000..830b57ce --- /dev/null +++ b/qcom/sa415m-ttp-pcie-ep.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa415m.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA415M TTP PCIE-EP"; + compatible = "qcom,sa415m-ccard", + "qcom,sa415m", "qcom,ccard"; + qcom,board-id = <30 0x101>; +}; + diff --git a/qcom/sa415m-ttp-usb-ep.dts b/qcom/sa415m-ttp-usb-ep.dts new file mode 100755 index 00000000..0d4584da --- /dev/null +++ b/qcom/sa415m-ttp-usb-ep.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa415m.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA415M TTP USB-EP"; + compatible = "qcom,sa415m-ccard", + "qcom,sa415m", "qcom,ccard"; + qcom,board-id = <30 0x102>; +}; + diff --git a/qcom/sa415m-ttp.dts b/qcom/sa415m-ttp.dts new file mode 100755 index 00000000..e26ba054 --- /dev/null +++ b/qcom/sa415m-ttp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa415m.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA415M TTP V2"; + compatible = "qcom,sa415m-ccard", + "qcom,sa415m", "qcom,ccard"; + qcom,board-id = <30 0x100>; +}; + diff --git a/qcom/sa415m-v2-cdp.dts b/qcom/sa415m-v2-cdp.dts new file mode 100755 index 00000000..82da70d0 --- /dev/null +++ b/qcom/sa415m-v2-cdp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa415m.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA415M CDP V2"; + compatible = "qcom,sa415m-ccard", + "qcom,sa415m", "qcom,ccard"; + qcom,board-id = <1 0x104>; +}; + diff --git a/qcom/sa415m-v2-mtp.dts b/qcom/sa415m-v2-mtp.dts new file mode 100755 index 00000000..7522bb74 --- /dev/null +++ b/qcom/sa415m-v2-mtp.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa415m.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA415M MTP V2"; + compatible = "qcom,sa415m-ccard", + "qcom,sa415m", "qcom,ccard"; + qcom,board-id = <8 0x106>; +}; + diff --git a/qcom/sa415m.dtsi b/qcom/sa415m.dtsi new file mode 100755 index 00000000..965a83be --- /dev/null +++ b/qcom/sa415m.dtsi @@ -0,0 +1,241 @@ +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Qualcomm Technologies, Inc. SA415M"; + compatible = "qcom,sa415m"; + qcom,msm-id = <334 0x0>, <335 0x0>, <408 0x0>; + + interrupt-parent = <&intc>; + + memory { device_type = "memory"; reg = <0 0>; }; + + chosen: chosen { }; + + aliases { + }; + + reserved_mem: reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + peripheral2_mem: peripheral2_region@8fe00000 { + no-map; + reg = <0x8fe00000 0xe00000>; + label = "peripheral2_mem"; + }; + + sbl_region: sbl_region@8fd00000 { + no-map; + reg = <0x8fd00000 0x100000>; + label = "sbl_mem"; + }; + + flex_sec_apps_mem: flex_sec_apps_regions@8fcfd000 { + no-map; + reg = <0x8fcfd000 0x3000>; + }; + + access_control_mem: access_control_mem@8fc80000 { + no-map; + reg = <0x8fc80000 0x40000>; + }; + + hyp_region: hyp_region@8fc00000 { + no-map; + reg = <0x8fc00000 0x80000>; + label = "hyp_mem"; + }; + + mss_mem: mss_region@87400000 { + no-map; + reg = <0x86c00000 0x8b00000>; + label = "mss_mem"; + }; + + audio_mem: audio_region@0 { + reusable; + size = <0x400000>; + }; + + dump_mem: mem_dump_region { + reusable; + size = <0x400000>; + }; + + qseecom_mem: qseecom_region@0 { + reusable; + alignment = <0x400000>; + size = <0x800000>; + status = "disabled"; + }; + + qseecom_ta_mem: qseecom_ta_region@0 { + reusable; + alignment = <0x400000>; + size = <0x400000>; + status = "disabled"; + }; + + subsys_backup_region: subsys_backup_region { + reusable; + size = <0xC00000>; + }; + }; + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + enable-method = "psci"; + reg = <0x0>; + #cooling-cells = <2>; + }; + }; + + soc: soc { }; + + firmware: firmware {}; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@17800000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + reg = <0x17800000 0x1000>, + <0x17802000 0x1000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 12 0xf08>, + <1 10 0xf08>, + <1 11 0xf08>; + clock-frequency = <19200000>; + }; + + timer@17820000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17820000 0x1000>; + clock-frequency = <19200000>; + + frame@17821000 { + frame-number = <0>; + interrupts = <0 7 0x4>, + <0 6 0x4>; + reg = <0x17821000 0x1000>, + <0x17822000 0x1000>; + }; + + frame@17823000 { + frame-number = <1>; + interrupts = <0 8 0x4>; + reg = <0x17823000 0x1000>; + status = "disabled"; + }; + + frame@17824000 { + frame-number = <2>; + interrupts = <0 9 0x4>; + reg = <0x17824000 0x1000>; + status = "disabled"; + }; + + frame@17825000 { + frame-number = <3>; + interrupts = <0 10 0x4>; + reg = <0x17825000 0x1000>; + status = "disabled"; + }; + + frame@17826000 { + frame-number = <4>; + interrupts = <0 11 0x4>; + reg = <0x17826000 0x1000>; + status = "disabled"; + }; + + frame@17827000 { + frame-number = <5>; + interrupts = <0 12 0x4>; + reg = <0x17827000 0x1000>; + status = "disabled"; + }; + + frame@17828000 { + frame-number = <6>; + interrupts = <0 13 0x4>; + reg = <0x17828000 0x1000>; + status = "disabled"; + }; + + frame@17829000 { + frame-number = <7>; + interrupts = <0 14 0x4>; + reg = <0x17829000 0x1000>; + status = "disabled"; + }; + }; + + qcom,msm-imem@1468B000 { + compatible = "qcom,msm-imem"; + reg = <0x1468B000 0x1000>; /* Address and size of IMEM */ + ranges = <0x0 0x1468B000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + restart_pshold: restart@c264000 { + compatible = "qcom,pshold"; + reg = <0x0c264000 0x4>, + <0x01fd3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; +}; + +#include "sa415m-pinctrl.dtsi" diff --git a/qcom/sa515m-audio-lpass.dtsi b/qcom/sa515m-audio-lpass.dtsi new file mode 100755 index 00000000..39c2b83d --- /dev/null +++ b/qcom/sa515m-audio-lpass.dtsi @@ -0,0 +1,391 @@ +&soc { + qcom,msm-adsp-loader { + compatible = "qcom,adsp-loader"; + qcom,adsp-state = <0>; + qcom,proc-img-to-load = "modem"; + }; + + qcom,msm-audio-ion { + compatible = "qcom,msm-audio-ion"; + qcom,scm-mp-enabled; + memory-region = <&audio_mem>; + }; + + pcm0: qcom,msm-pcm { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <0>; + }; + + routing: qcom,msm-pcm-routing { + compatible = "qcom,msm-pcm-routing"; + }; + + pcm1: qcom,msm-pcm-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <1>; + qcom,msm-pcm-low-latency; + qcom,latency-level = "ultra"; + }; + + qcom,msm-compr-dsp { + compatible = "qcom,msm-compr-dsp"; + }; + + voip: qcom,msm-voip-dsp { + compatible = "qcom,msm-voip-dsp"; + }; + + voice: qcom,msm-pcm-voice { + compatible = "qcom,msm-pcm-voice"; + qcom,destroy-cvd; + }; + + stub_codec: qcom,msm-stub-codec { + compatible = "qcom,msm-stub-codec"; + }; + + qcom,msm-dai-fe { + compatible = "qcom,msm-dai-fe"; + }; + + afe: qcom,msm-pcm-afe { + compatible = "qcom,msm-pcm-afe"; + }; + + hostless: qcom,msm-pcm-hostless { + compatible = "qcom,msm-pcm-hostless"; + }; + + audio_apr: qcom,msm-audio-apr { + compatible = "qcom,msm-audio-apr"; + qcom,subsys-name = "apr_modem"; + msm_audio_apr_dummy { + compatible = "qcom,msm-audio-apr-dummy"; + }; + }; + + q6core: qcom,q6core-audio { + compatible = "qcom,q6core-audio"; + }; + + host_pcm: qcom,msm-voice-host-pcm { + compatible = "qcom,msm-voice-host-pcm"; + }; + + loopback: qcom,msm-pcm-loopback { + compatible = "qcom,msm-pcm-loopback"; + }; + + compress: qcom,msm-compress-dsp { + compatible = "qcom,msm-compress-dsp"; + qcom,adsp-version = "MDSP 2.9"; + }; + + qcom,msm-dai-stub { + compatible = "qcom,msm-dai-stub"; + dtmf_tx: qcom,msm-dai-stub-dtmf-tx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <4>; + }; + + rx_capture_tx: qcom,msm-dai-stub-host-rx-capture-tx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <5>; + }; + + rx_playback_rx: qcom,msm-dai-stub-host-rx-playback-rx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <6>; + }; + + tx_capture_tx: qcom,msm-dai-stub-host-tx-capture-tx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <7>; + }; + + tx_playback_rx: qcom,msm-dai-stub-host-tx-playback-rx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <8>; + }; + }; + + qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + afe_pcm_rx: qcom,msm-dai-q6-be-afe-pcm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <224>; + }; + + afe_pcm_tx: qcom,msm-dai-q6-be-afe-pcm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <225>; + }; + + afe_proxy_rx: qcom,msm-dai-q6-afe-proxy-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <241>; + }; + + afe_proxy_tx: qcom,msm-dai-q6-afe-proxy-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <240>; + }; + + incall_record_rx: qcom,msm-dai-q6-incall-record-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32771>; + }; + + incall_record_tx: qcom,msm-dai-q6-incall-record-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32772>; + }; + + incall_music_rx: qcom,msm-dai-q6-incall-music-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32773>; + }; + + incall2_record_rx: qcom,msm-dai-q6-incall2-record-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32769>; + }; + + incall_music_2_rx: qcom,msm-dai-q6-incall-music-2-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32770>; + }; + + incall_music_dl_rx: qcom,msm-dai-q6-incall-music-dl-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32774>; + }; + }; + + pcm_dtmf: qcom,msm-pcm-dtmf { + compatible = "qcom,msm-pcm-dtmf"; + }; + + cpu-pmu { + compatible = "arm,cortex-a7-pmu"; + qcom,irq-is-percpu; + interrupts = <1 8 0x100>; + }; + + dai_pri_auxpcm: qcom,msm-pri-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "primary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + dai_sec_auxpcm: qcom,msm-sec-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "secondary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + qcom,msm-dai-tdm-pri-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37120>; + qcom,msm-cpudai-tdm-group-num-ports = <2>; + qcom,msm-cpudai-tdm-group-port-id = <36864 36866>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36864>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_1: qcom,msm-dai-q6-tdm-pri-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36866>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-pri-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37121>; + qcom,msm-cpudai-tdm-group-num-ports = <2>; + qcom,msm-cpudai-tdm-group-port-id = <36865 36867>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + + dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36865>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_1: qcom,msm-dai-q6-tdm-pri-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36867>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-sec-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <2>; + qcom,msm-cpudai-tdm-group-port-id = <36880 36882>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + + dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36880>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_1: qcom,msm-dai-q6-tdm-sec-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36882>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-sec-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37137>; + qcom,msm-cpudai-tdm-group-num-ports = <2>; + qcom,msm-cpudai-tdm-group-port-id = <36881 36883>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + + dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36881>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_1: qcom,msm-dai-q6-tdm-sec-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36883>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + }; + + qcom,msm-dai-mi2s { + compatible = "qcom,msm-dai-mi2s"; + + mi2s_prim: qcom,msm-dai-q6-mi2s-prim { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <0>; + qcom,msm-mi2s-rx-lines = <2>; + qcom,msm-mi2s-tx-lines = <1>; + }; + + mi2s_sec: qcom,msm-dai-q6-mi2s-sec { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <1>; + qcom,msm-mi2s-rx-lines = <2>; + qcom,msm-mi2s-tx-lines = <1>; + }; + + }; + + prim_master: prim_master_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&pri_ws_active_master + &pri_sck_active_master + &pri_dout_active + &pri_din_active>; + pinctrl-1 = <&pri_ws_sleep + &pri_sck_sleep + &pri_dout_sleep + &pri_din_sleep>; + qcom,mi2s-auxpcm-cdc-gpios; + }; + + prim_slave: prim_slave_pinctrl { + status = "disabled"; + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&pri_ws_active_slave + &pri_sck_active_slave + &pri_dout_active + &pri_din_active>; + pinctrl-1 = <&pri_ws_sleep + &pri_sck_sleep + &pri_dout_sleep + &pri_din_sleep>; + qcom,mi2s-auxpcm-cdc-gpios; + }; + + sec_master_slave: sec_master_slave_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep", "aud_alt_active"; + pinctrl-0 = <&sec_ws_active_master + &sec_sck_active_master + &sec_dout_active + &sec_din_active>; + pinctrl-1 = <&sec_ws_sleep + &sec_sck_sleep + &sec_dout_sleep + &sec_din_sleep>; + pinctrl-2 = <&sec_ws_active_slave + &sec_sck_active_slave + &sec_dout_active + &sec_din_active>; + qcom,mi2s-auxpcm-cdc-gpios; + }; + + sec_slave: sec_slave_pinctrl { + status = "disabled"; + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&sec_ws_active_slave + &sec_sck_active_slave + &sec_dout_active + &sec_din_active>; + pinctrl-1 = <&sec_ws_sleep + &sec_sck_sleep + &sec_dout_sleep + &sec_din_sleep>; + qcom,mi2s-auxpcm-cdc-gpios; + }; +}; diff --git a/qcom/sa515m-audio-overlay.dtsi b/qcom/sa515m-audio-overlay.dtsi new file mode 100755 index 00000000..155aaa86 --- /dev/null +++ b/qcom/sa515m-audio-overlay.dtsi @@ -0,0 +1,133 @@ +#include "sa515m-wcd.dtsi" +#include "sa515m-wsa881x.dtsi" +#include <dt-bindings/clock/qcom,audio-ext-clk.h> + +&snd_934x { + qcom,audio-routing = + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "AMIC2", "Headset Mic", + "Headset Mic", "MIC BIAS2", + "AMIC3", "ANCRight Headset Mic", + "ANCRight Headset Mic", "MIC BIAS2", + "AMIC4", "ANCLeft Headset Mic", + "ANCLeft Headset Mic", "MIC BIAS2", + "AMIC5", "Handset Mic", + "Handset Mic", "MIC BIAS3", + "DMIC1", "Digital Mic1", + "DMIC1", "MIC BIAS1", + "DMIC2", "Digital Mic2", + "DMIC2", "MIC BIAS3", + "DMIC3", "Digital Mic3", + "DMIC3", "MIC BIAS3", + "DMIC4", "Digital Mic4", + "DMIC4", "MIC BIAS4", + "DMIC5", "Digital Mic5", + "DMIC5", "MIC BIAS4", + "SpkrLeft IN", "SPK2 OUT"; + + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,msm-mbhc-hs-mic-max-threshold-mv = <1700>; + qcom,msm-mbhc-hs-mic-min-threshold-mv = <50>; + qcom,cdc-ext-clk-rate = <19200000>; + qcom,tavil-mclk-clk-freq = <9600000>; + + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + + qcom,wsa-max-devs = <2>; + qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, + <&wsa881x_0213>, <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&wcd934x_cdc>, + <&q6core>; +}; + +&soc { + wcd9xxx_intc: wcd9xxx-irq { + status = "ok"; + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&tlmm>; + qcom,gpio-connect = <&tlmm 96 0>; + pinctrl-names = "default"; + pinctrl-0 = <&wcd_intr_default>; + }; + + clock_audio_up: audio_ext_clk_up { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_3>; + qcom,codec-lpass-clk-id = <770>; + qcom,codec-lpass-ext-clk-freq = <9600000>; + qcom,use-pinctrl = <1>; + pinctrl-names = "sleep", "active"; + pinctrl-0 = <&i2s_mclk_sleep>; + pinctrl-1 = <&i2s_mclk_active>; + #clock-cells = <1>; + }; + + wcd_rst_gpio: msm_cdc_pinctrl@92 { + compatible = "qcom,msm-cdc-pinctrl"; + qcom,cdc-rst-n-gpio = <&tlmm 92 0>; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_reset_active>; + pinctrl-1 = <&cdc_reset_sleep>; + }; +}; + +&i2c_3 { + status = "ok"; + wcd934x_cdc: tavil_codec { + compatible = "qcom,tavil-i2c"; + reg = <0x0d>; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30 31>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk"; + clocks = <&clock_audio_up 0>; + + cdc-vdd-buck-supply = <&pmx55_l6>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-buck-sido-supply = <&pmx55_l6>; + qcom,cdc-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-buck-sido-current = <250000>; + + cdc-vdd-tx-h-supply = <&pmx55_l6>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&pmx55_l6>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vddpx-1-supply = <&pmx55_l6>; + qcom,cdc-vddpx-1-voltage = <1800000 1800000>; + qcom,cdc-vddpx-1-current = <10000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-buck-sido", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vddpx-1"; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-dmic-sample-rate = <4800000>; + + qcom,wdsp-cmpnt-dev-name = "tavil_codec"; + }; +}; diff --git a/qcom/sa515m-audio.dtsi b/qcom/sa515m-audio.dtsi new file mode 100755 index 00000000..a862fbd2 --- /dev/null +++ b/qcom/sa515m-audio.dtsi @@ -0,0 +1,49 @@ +#include "sa515m-audio-lpass.dtsi" + +&soc { + snd_934x: sound-tavil { + compatible = "qcom,sdx-asoc-snd-tavil"; + qcom,model = "sdx-tavil-i2s-snd-card"; + qcom,prim_mi2s_aux_master = <&prim_master>; + qcom,prim_mi2s_aux_slave = <&prim_slave>; + qcom,sec_mi2s_aux_master = <&sec_master_slave>; + qcom,sec_mi2s_aux_slave = <&sec_slave>; + + asoc-platform = <&pcm0>, <&pcm1>, <&voip>, <&voice>, + <&loopback>, <&hostless>, <&afe>, <&routing>, + <&pcm_dtmf>, <&host_pcm>, <&compress>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-voip-dsp", "msm-pcm-voice", + "msm-pcm-loopback", "msm-pcm-hostless", + "msm-pcm-afe", "msm-pcm-routing", + "msm-pcm-dtmf", "msm-voice-host-pcm", + "msm-compress-dsp"; + asoc-cpu = <&dai_pri_auxpcm>, <&mi2s_prim>, <&mi2s_sec>, + <&dtmf_tx>, + <&rx_capture_tx>, <&rx_playback_rx>, + <&tx_capture_tx>, <&tx_playback_rx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_pri_tdm_rx_1>, <&dai_pri_tdm_tx_1>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_sec_tdm_rx_1>, <&dai_sec_tdm_tx_1>, + <&dai_sec_auxpcm>, <&incall2_record_rx>, + <&incall_music_2_rx>, <&incall_music_dl_rx>; + asoc-cpu-names = "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-stub-dev.4", "msm-dai-stub-dev.5", + "msm-dai-stub-dev.6", "msm-dai-stub-dev.7", + "msm-dai-stub-dev.8", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36866", "msm-dai-q6-tdm.36867", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36882", "msm-dai-q6-tdm.36883", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-dev.32769", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.32774"; + }; +}; diff --git a/qcom/sa515m-blsp.dtsi b/qcom/sa515m-blsp.dtsi index 09a01c25..5abac944 100755 --- a/qcom/sa515m-blsp.dtsi +++ b/qcom/sa515m-blsp.dtsi @@ -90,7 +90,7 @@ pinctrl-names = "i2c_active", "i2c_sleep"; pinctrl-0 = <&i2c_3_active>; pinctrl-1 = <&i2c_3_sleep>; - status = "disabled"; + status = "ok"; }; i2c_4: i2c@838000 { /* BLSP1 QUP4 */ diff --git a/qcom/sa515m-ccard-cnss.dtsi b/qcom/sa515m-ccard-cnss.dtsi new file mode 100755 index 00000000..27a67366 --- /dev/null +++ b/qcom/sa515m-ccard-cnss.dtsi @@ -0,0 +1,57 @@ +#include "pmx55.dtsi" +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +&pmx55_gpios { + + bt_en { + bt_en_default: bt_en_default { + pins = "gpio6"; + function = "normal"; + output-low; + bias-pull-down; + qcom,drive-strength = <2>; + power-source = <1>; + }; + }; +}; + +&soc { + + vreg_conn_pa: vreg_conn_pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pmx55_gpios 2 GPIO_ACTIVE_HIGH>; + }; + + vreg_conn_1p8: vreg_conn_1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pmx55_gpios 1 GPIO_ACTIVE_HIGH>; + }; + + bluetooth: bt-qca-auto-converged { + compatible = "qcom,qca-auto-converged"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_default>; + qcom,bt-reset-gpio = <&pmx55_gpios 6 0>; + qcom,wl-reset-gpio = <&tlmm 52 0>; + + qcom,bt-vdd-ctrl1-supply = <&vreg_conn_pa>; + qcom,bt-vdd-ctrl2-supply = <&vreg_conn_1p8>; + qcom,bt-vdd-aon-supply = <&pmx55_s3>; + qcom,bt-vdd-rfa1-supply = <&pmx55_s2>; + qcom,bt-vdd-rfa3-supply = <&pmx55_s4>; + + qcom,bt-vdd-aon-config = <1000000 1000000 0 0>; + qcom,bt-vdd-rfa1-config = <1370000 1370000 0 0>; + qcom,bt-vdd-rfa3-config = <1904000 1904000 0 0>; + }; +}; + +&blsp1_uart2b_hs { + status = "okay"; +}; diff --git a/qcom/sa515m-ccard-eth-ep.dts b/qcom/sa515m-ccard-eth-ep.dts index c8afd203..46ee7798 100755 --- a/qcom/sa515m-ccard-eth-ep.dts +++ b/qcom/sa515m-ccard-eth-ep.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "sa515m.dtsi" +#include "sa515m-ccard.dtsi" / { model = "Qualcomm Technologies, Inc. SA515M CCARD ETH"; diff --git a/qcom/sa515m-ccard-pcie-ep.dts b/qcom/sa515m-ccard-pcie-ep.dts index 08aa1f1d..ca38d76a 100755 --- a/qcom/sa515m-ccard-pcie-ep.dts +++ b/qcom/sa515m-ccard-pcie-ep.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "sa515m.dtsi" +#include "sa515m-ccard.dtsi" / { model = "Qualcomm Technologies, Inc. SA515M CCARD PCIE-EP"; @@ -8,3 +9,11 @@ "qcom,sa515m", "qcom,ccard"; qcom,board-id = <25 1>, <25 0x101>; }; + +&pcie0 { + status = "disabled"; +}; + +&pcie_ep { + status = "ok"; +}; diff --git a/qcom/sa515m-ccard-usb-ep.dts b/qcom/sa515m-ccard-usb-ep.dts index d9ae9b7f..c5f8fc67 100755 --- a/qcom/sa515m-ccard-usb-ep.dts +++ b/qcom/sa515m-ccard-usb-ep.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "sa515m.dtsi" +#include "sa515m-ccard.dtsi" / { model = "Qualcomm Technologies, Inc. SA515M CCARD USB-EP"; diff --git a/qcom/sa515m-ccard.dts b/qcom/sa515m-ccard.dts index 4cc5730a..3583f637 100755 --- a/qcom/sa515m-ccard.dts +++ b/qcom/sa515m-ccard.dts @@ -7,5 +7,5 @@ model = "Qualcomm Technologies, Inc. SA515M CCARD"; compatible = "qcom,sa515m-ccard", "qcom,sa515m", "qcom,ccard"; - qcom,board-id = <25 2>, <25 0x102>; + qcom,board-id = <25 0>, <25 0x100>; }; diff --git a/qcom/sa515m-ccard.dtsi b/qcom/sa515m-ccard.dtsi index 7c408d1e..420067fa 100755 --- a/qcom/sa515m-ccard.dtsi +++ b/qcom/sa515m-ccard.dtsi @@ -1,5 +1,6 @@ #include "sdx55-mtp.dtsi" #include "sa515m.dtsi" +#include "sa515m-ccard-cnss.dtsi" &soc { codec_vreg: regulator-codec-tlv320aic3x { @@ -9,8 +10,94 @@ gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + snd_tlv3x: sound-auto { + compatible = "qcom,sdx-asoc-snd-auto"; + qcom,model = "sdx-auto-i2s-snd-card"; + qcom,prim_mi2s_aux_master = <&prim_master>; + qcom,prim_mi2s_aux_slave = <&prim_slave>; + qcom,sec_mi2s_aux_master = <&sec_master_slave>; + qcom,sec_mi2s_aux_slave = <&sec_slave>; + + pinctrl-names = "default"; + pinctrl-0 = <&a2b_cdc_sel_default>, <&i2s_mclk_active>; + + asoc-platform = <&pcm0>, <&pcm1>, <&voip>, <&voice>, + <&loopback>, <&hostless>, <&afe>, <&routing>, + <&pcm_dtmf>, <&host_pcm>, <&compress>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-voip-dsp", "msm-pcm-voice", + "msm-pcm-loopback", "msm-pcm-hostless", + "msm-pcm-afe", "msm-pcm-routing", + "msm-pcm-dtmf", "msm-voice-host-pcm", + "msm-compress-dsp"; + asoc-cpu = <&dai_pri_auxpcm>, <&mi2s_prim>, <&mi2s_sec>, + <&dtmf_tx>, + <&rx_capture_tx>, <&rx_playback_rx>, + <&tx_capture_tx>, <&tx_playback_rx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_pri_tdm_rx_1>, <&dai_pri_tdm_tx_1>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_sec_tdm_rx_1>, <&dai_sec_tdm_tx_1>, + <&dai_sec_auxpcm>, <&incall2_record_rx>, + <&incall_music_2_rx>, <&incall_music_dl_rx>; + asoc-cpu-names = "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-stub-dev.4", "msm-dai-stub-dev.5", + "msm-dai-stub-dev.6", "msm-dai-stub-dev.7", + "msm-dai-stub-dev.8", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36866", "msm-dai-q6-tdm.36867", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36882", "msm-dai-q6-tdm.36883", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-dev.32769", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.32774"; + asoc-codec = <&tlv320aic3x_codec>, <&stub_codec>; + asoc-codec-names = "tlv320aic3x-codec", "msm-stub-codec.1"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; + }; + +}; + +&snd_934x { + status = "disabled"; +}; + +&wcd9xxx_intc { + status = "disabled"; +}; + +&clock_audio_up { + status = "disabled"; +}; + +&wcd_rst_gpio { + status = "disabled"; +}; + +&wcd934x_cdc { + status = "disabled"; }; &vbus_detect { status = "okay"; }; + +&i2c_3 { + tlv320aic3x_codec: tlv320aic3x@18 { + compatible = "ti,tlv320aic3x"; + reg = <0x18>; + gpio-reset = <&tlmm 92 0>; + reset-inverted; + AVDD-supply = <&codec_vreg>; + IOVDD-supply = <&codec_vreg>; + ai3x-ocmv = <1>; + }; +}; + diff --git a/qcom/sa515m-ion.dtsi b/qcom/sa515m-ion.dtsi index bb3da3f7..70737b78 100755 --- a/qcom/sa515m-ion.dtsi +++ b/qcom/sa515m-ion.dtsi @@ -8,7 +8,7 @@ system_heap: qcom,ion-heap@25 { reg = <ION_SYSTEM_HEAP_ID>; - qcom,ion-heap-type = "SYSTEM"; + qcom,ion-heap-type = "MSM_SYSTEM"; }; qcom,ion-heap@27 { /* QSEECOM HEAP */ diff --git a/qcom/sa515m-mtp-audio-overlay.dtsi b/qcom/sa515m-mtp-audio-overlay.dtsi new file mode 100755 index 00000000..ca72ab34 --- /dev/null +++ b/qcom/sa515m-mtp-audio-overlay.dtsi @@ -0,0 +1,10 @@ +#include "sa515m-audio-overlay.dtsi" + +&soc { + sound-tavil { + qcom,wsa-max-devs = <1>; + qcom,wsa-devs = <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrRight"; + }; +}; + diff --git a/qcom/sa515m-pcie.dtsi b/qcom/sa515m-pcie.dtsi new file mode 100755 index 00000000..19b0bdda --- /dev/null +++ b/qcom/sa515m-pcie.dtsi @@ -0,0 +1,424 @@ +#include <dt-bindings/clock/qcom,gcc-sdx55.h> + +&soc { + pcie0: qcom,pcie@1c00000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c00000 0x4000>, + <0x1c06000 0x2000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>, + <0x1c03000 0x1000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "mhi"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH + 0 0 0 1 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + + qcom,phy-sequence = <0x1240 0x03 0x0 + 0x1010 0x00 0x0 + 0x101c 0x31 0x0 + 0x1020 0x01 0x0 + 0x1024 0xce 0x0 + 0x1028 0x0b 0x0 + 0x1030 0x97 0x0 + 0x1034 0x0c 0x0 + 0x1044 0x18 0x0 + 0x1048 0x90 0x0 + 0x1058 0x0f 0x0 + 0x1074 0x06 0x0 + 0x1078 0x06 0x0 + 0x107c 0x16 0x0 + 0x1080 0x16 0x0 + 0x1084 0x36 0x0 + 0x1088 0x36 0x0 + 0x1094 0x08 0x0 + 0x10a4 0x46 0x0 + 0x10a8 0x04 0x0 + 0x10ac 0x04 0x0 + 0x10b0 0x0d 0x0 + 0x10b4 0x0a 0x0 + 0x10b8 0x1a 0x0 + 0x10bc 0xc3 0x0 + 0x10c4 0xd0 0x0 + 0x10d4 0x05 0x0 + 0x10d8 0x55 0x0 + 0x10dc 0x55 0x0 + 0x10e0 0x05 0x0 + 0x110c 0x02 0x0 + 0x1154 0x34 0x0 + 0x1158 0x12 0x0 + 0x115c 0x00 0x0 + 0x1168 0x05 0x0 + 0x116c 0x04 0x0 + 0x119c 0x88 0x0 + 0x11a0 0x03 0x0 + 0x11ac 0xca 0x0 + 0x11b0 0x1e 0x0 + 0x11b4 0xd8 0x0 + 0x11b8 0x20 0x0 + 0x11bc 0x22 0x0 + 0x106c 0x0a 0x0 + 0x1070 0x10 0x0 + 0x11a4 0x05 0x0 + 0x11a8 0x0f 0x0 + 0x008c 0x06 0x0 + 0x00e0 0x01 0x0 + 0x00c4 0x01 0x0 + 0x0258 0x16 0x0 + 0x0378 0x83 0x0 + 0x0360 0xe2 0x0 + 0x0364 0x04 0x0 + 0x0368 0x30 0x0 + 0x0370 0xff 0x0 + 0x03cc 0x42 0x0 + 0x03d0 0x0d 0x0 + 0x03d4 0x77 0x0 + 0x03d8 0x2d 0x0 + 0x03dc 0x39 0x0 + 0x03e0 0x9f 0x0 + 0x03e4 0x0f 0x0 + 0x03e8 0x63 0x0 + 0x03ec 0xbf 0x0 + 0x03f0 0x79 0x0 + 0x03f4 0x4f 0x0 + 0x03f8 0x0f 0x0 + 0x03fc 0xd5 0x0 + 0x02ac 0x7f 0x0 + 0x0310 0x55 0x0 + 0x0334 0x0c 0x0 + 0x0338 0x00 0x0 + 0x0350 0x0f 0x0 + 0x088c 0x06 0x0 + 0x08e0 0x01 0x0 + 0x08c4 0x01 0x0 + 0x0a58 0x16 0x0 + 0x0b78 0x83 0x0 + 0x0b60 0xe2 0x0 + 0x0b64 0x04 0x0 + 0x0b68 0x30 0x0 + 0x0b70 0xff 0x0 + 0x0bcc 0x42 0x0 + 0x0bd0 0x0d 0x0 + 0x0bd4 0x77 0x0 + 0x0bd8 0x2d 0x0 + 0x0bdc 0x39 0x0 + 0x0be0 0x9f 0x0 + 0x0be4 0x0f 0x0 + 0x0be8 0x63 0x0 + 0x0bec 0xbf 0x0 + 0x0bf0 0x79 0x0 + 0x0bf4 0x4f 0x0 + 0x0bf8 0x0f 0x0 + 0x0bfc 0xd5 0x0 + 0x0aac 0x7f 0x0 + 0x0b10 0x55 0x0 + 0x0b34 0x0c 0x0 + 0x0b38 0x00 0x0 + 0x0b50 0x0f 0x0 + 0x161c 0xc1 0x0 + 0x1690 0x00 0x0 + 0x13e4 0x03 0x0 + 0x1708 0x03 0x0 + 0x16a0 0x16 0x0 + 0x13e0 0x16 0x0 + 0x13d8 0x01 0x0 + 0x16fc 0x01 0x0 + 0x13dc 0x00 0x0 + 0x1700 0x00 0x0 + 0x1828 0x50 0x0 + 0x1c28 0x50 0x0 + 0x1200 0x00 0x0 + 0x1244 0x03 0x0>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + pinctrl-1 = <&pcie0_clkreq_sleep + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 57 0>; + wake-gpio = <&tlmm 53 0>; + + gdsc-vdd-supply = <&gdsc_pcie>; + vreg-1p8-supply = <&L1E>; + vreg-0p9-supply = <&L4E>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 15000>; + qcom,vreg-0p9-voltage-level = <872000 872000 47900>; + qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX + RPMH_REGULATOR_LEVEL_NOM 0>; + + msi-parent = <&pcie0_msi>; + + qcom,target-link-speed = <0x3>; + + qcom,no-l0s-supported; + + qcom,l1-2-th-scale = <2>; /* 1us */ + qcom,l1-2-th-value = <70>; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x40000000>; + + qcom,pcie-phy-ver = <0x1096>; + qcom,use-19p2mhz-aux-clk; + qcom,phy-status-offset = <0x1214>; + qcom,phy-status-bit = <7>; + qcom,phy-power-down-offset = <0x1240>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <0>; + + qcom,smmu-sid-base = <0x0200>; + iommu-map = <0x0 &apps_smmu 0x0200 0x1>, + <0x100 &apps_smmu 0x0201 0x1>, + <0x200 &apps_smmu 0x0202 0x1>, + <0x300 &apps_smmu 0x0203 0x1>, + <0x400 &apps_smmu 0x0204 0x1>, + <0x208 &apps_smmu 0x0205 0x1>, + <0x210 &apps_smmu 0x0206 0x1>; + + interconnect-names = "icc_path"; + interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_0_sleep_clk", "pcie_phy_refgen_clk"; + + max-clock-frequency-hz = <0>, <0>, <0>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>; + + resets = <&gcc GCC_PCIE_BCR>, + <&gcc GCC_PCIE_PHY_BCR>; + + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + }; + + pcie0_msi: qcom,pcie0_msi@a0000000 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0xa0000000 0x0>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + qcom,snps; + }; + + pcie_ep: qcom,pcie@40002000 { + compatible = "qcom,pcie-ep"; + + reg = <0x40002000 0x1000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40002000 0x2000>, + <0x01c00000 0x3000>, + <0x01c06000 0x2000>, + <0x01c03000 0x1000>, + <0x01fcb000 0x1000>, + <0xc2f0020 0x4>; + reg-names = "msi", "dm_core", "elbi", "iatu", "edma", "parf", + "phy", "mmio", "tcsr_pcie_perst_en", "aoss_cc_reset"; + + #address-cells = <0>; + interrupt-parent = <&pcie_ep>; + interrupts = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 140 0>; + interrupt-names = "int_global"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default + &pcie_ep_wake_default>; + + clkreq-gpio = <&tlmm 56 0>; + perst-gpio = <&tlmm 57 0>; + wake-gpio = <&tlmm 53 0>; + + gdsc-vdd-supply = <&gdsc_pcie>; + vreg-1p8-supply = <&L1E>; + vreg-0p9-supply = <&L4E>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0p9-voltage-level = <872000 872000 24000>; + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>; + + clock-names = "pcie_pipe_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_aux_clk", "pcie_ldo", + "pcie_sleep_clk", + "pcie_slv_q2a_axi_clk"; + + resets = <&gcc GCC_PCIE_BCR>, + <&gcc GCC_PCIE_PHY_BCR>; + + reset-names = "pcie_core_reset", + "pcie_phy_reset"; + + interconnect-names = "icc_path"; + interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + + qcom,pcie-vendor-id = /bits/ 16 <0x17cb>; + qcom,pcie-device-id = /bits/ 16 <0x0306>; + qcom,pcie-link-speed = <3>; + qcom,pcie-phy-ver = <6>; + qcom,pcie-active-config; + qcom,pcie-aggregated-irq; + qcom,pcie-mhi-a7-irq; + qcom,tcsr-not-supported; + qcom,pcie-perst-enum; + qcom,phy-status-reg2 = <0x1214>; + qcom,mhi-soc-reset-offset = <0xb01b8>; + + qcom,phy-init = <0x1240 0x001 0x0 + 0x100c 0x002 0x0 + 0x1044 0x018 0x0 + 0x104c 0x007 0x0 + 0x1058 0x00f 0x0 + 0x1074 0x009 0x0 + 0x1078 0x00a 0x0 + 0x107c 0x018 0x0 + 0x1080 0x019 0x0 + 0x1084 0x006 0x0 + 0x1088 0x003 0x0 + 0x1094 0x000 0x0 + 0x10a4 0x046 0x0 + 0x10a8 0x004 0x0 + 0x10ac 0x07f 0x0 + 0x10b0 0x002 0x0 + 0x10b4 0x0ff 0x0 + 0x10b8 0x004 0x0 + 0x10bc 0x025 0x0 + 0x10c4 0x028 0x0 + 0x10d4 0x008 0x0 + 0x10f4 0x0fb 0x0 + 0x10f8 0x001 0x0 + 0x110c 0x002 0x0 + 0x1158 0x012 0x0 + 0x115c 0x000 0x0 + 0x1168 0x005 0x0 + 0x116c 0x004 0x0 + 0x119c 0x088 0x0 + 0x11a0 0x003 0x0 + 0x11ac 0x056 0x0 + 0x11b0 0x01d 0x0 + 0x11b4 0x04b 0x0 + 0x11b8 0x01f 0x0 + 0x11bc 0x022 0x0 + 0x11a4 0x015 0x0 + 0x11a8 0x00f 0x0 + 0x008c 0x006 0x0 + 0x00e0 0x001 0x0 + 0x00c4 0x001 0x0 + 0x0258 0x016 0x0 + 0x0378 0x083 0x0 + 0x0360 0x0e2 0x0 + 0x0364 0x004 0x0 + 0x0368 0x030 0x0 + 0x0370 0x0ff 0x0 + 0x03cc 0x042 0x0 + 0x03d0 0x00d 0x0 + 0x03d4 0x077 0x0 + 0x03d8 0x02d 0x0 + 0x03dc 0x039 0x0 + 0x03e0 0x09f 0x0 + 0x03e4 0x00f 0x0 + 0x03e8 0x063 0x0 + 0x03ec 0x0bf 0x0 + 0x03f0 0x079 0x0 + 0x03f4 0x04f 0x0 + 0x03f8 0x00f 0x0 + 0x03fc 0x0d5 0x0 + 0x02ac 0x075 0x0 + 0x0310 0x055 0x0 + 0x0334 0x00c 0x0 + 0x0338 0x000 0x0 + 0x0350 0x00f 0x0 + 0x088c 0x006 0x0 + 0x08e0 0x001 0x0 + 0x08c4 0x001 0x0 + 0x0a58 0x016 0x0 + 0x0b78 0x083 0x0 + 0x0b60 0x0e2 0x0 + 0x0b64 0x004 0x0 + 0x0b68 0x030 0x0 + 0x0b70 0x0ff 0x0 + 0x0bcc 0x042 0x0 + 0x0bd0 0x00d 0x0 + 0x0bd4 0x077 0x0 + 0x0bd8 0x02d 0x0 + 0x0bdc 0x039 0x0 + 0x0be0 0x09f 0x0 + 0x0be4 0x00f 0x0 + 0x0be8 0x063 0x0 + 0x0bec 0x0bf 0x0 + 0x0bf0 0x079 0x0 + 0x0bf4 0x04f 0x0 + 0x0bf8 0x00f 0x0 + 0x0bfc 0x0d5 0x0 + 0x0aac 0x07f 0x0 + 0x0b10 0x055 0x0 + 0x0b34 0x00c 0x0 + 0x0b38 0x000 0x0 + 0x0b50 0x00f 0x0 + 0x13e4 0x003 0x0 + 0x1708 0x003 0x0 + 0x16a0 0x016 0x0 + 0x13e0 0x016 0x0 + 0x13d8 0x001 0x0 + 0x16fc 0x001 0x0 + 0x13dc 0x000 0x0 + 0x1700 0x000 0x0 + 0x1828 0x050 0x0 + 0x1c28 0x050 0x0 + 0x1200 0x000 0x0 + 0x1244 0x003 0x0>; + status = "disabled"; + }; +}; diff --git a/qcom/sa515m-pinctrl.dtsi b/qcom/sa515m-pinctrl.dtsi index 6e056230..60903f3e 100755 --- a/qcom/sa515m-pinctrl.dtsi +++ b/qcom/sa515m-pinctrl.dtsi @@ -1520,6 +1520,60 @@ }; /* SDC pin type */ + + sdc1_on: sdc1_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio99"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc1_off: sdc1_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio99"; + bias-disable; + drive-strength = <2>; + }; + }; + + sdc1_clk_on: sdc1_clk_on { config { pins = "sdc1_clk"; diff --git a/qcom/sa515m-pm.dtsi b/qcom/sa515m-pm.dtsi new file mode 100755 index 00000000..e894acf7 --- /dev/null +++ b/qcom/sa515m-pm.dtsi @@ -0,0 +1,104 @@ +#include <dt-bindings/interrupt-controller/arm-gic.h> + +&soc { + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm-cluster@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + idle-state-name = "system"; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + + CX_ACTIVE: qcom,pm-cluster-level@0 { + reg = <0>; + idle-state-name = "cx-active"; + compatible = "arm,idle-state"; + qcom,psci-mode = <0>; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <120>; + exit-latency-us = <150>; + min-residency-us = <6488>; + }; + + CX_MIN: qcom,pm-cluster-level@1 {/* C8=>XO off in f/w */ + reg = <1>; + idle-state-name = "cx-min"; + compatible = "arm,idle-state"; + qcom,psci-mode = <0x4>; + arm,psci-suspend-param = <0x40000008>; + entry-latency-us = <140>; + exit-latency-us = <200>; + min-residency-us = <8000>; + local-timer-stop; + qcom,min-child-idx = <2>; + qcom,notify-rpm; + qcom,is-reset; + }; + + qcom,pm-cpu@0 { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,disable-ipi-prediction; + qcom,cpu = <&CPU0>; + + qcom,pm-cpu-level@0 { + reg = <0>; + idle-state-name = "wfi"; + compatible = "arm,idle-state"; + qcom,psci-cpu-mode = <0x1>; + arm,psci-suspend-param = <0x1>; + entry-latency-us = <57>; + exit-latency-us = <43>; + min-residency-us = <83>; + }; + + A7_SPC: qcom,pm-cpu-level@1 {/* C3 */ + reg = <1>; + idle-state-name ="standalone-pc"; + compatible = "arm,idle-state"; + qcom,psci-cpu-mode = <0x3>; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <120>; + exit-latency-us = <120>; + min-residency-us = <4488>; + local-timer-stop; + qcom,use-broadcast-timer; + qcom,is-reset; + }; + + A7_PC: qcom,pm-cpu-level@2 { /* C4 */ + reg = <2>; + idle-state-name = "pc"; + compatible = "arm,idle-state"; + qcom,psci-cpu-mode = <0x4>; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <120>; + exit-latency-us = <150>; + min-residency-us = <6488>; + local-timer-stop; + qcom,use-broadcast-timer; + qcom,is-reset; + }; + + }; + }; + }; + + rpmh-master-stats@b211200 { + compatible = "qcom,rpmh-master-stats-v1"; + reg = <0xb211200 0x60>; + }; + + soc-sleep-stats@C370000 { + compatible = "qcom,rpmh-sleep-stats"; + reg = <0xc370000 0x400>; + }; + +}; diff --git a/qcom/sa515m-v2-ccard-eth-ep.dts b/qcom/sa515m-v2-ccard-eth-ep.dts index 76293214..0686183c 100755 --- a/qcom/sa515m-v2-ccard-eth-ep.dts +++ b/qcom/sa515m-v2-ccard-eth-ep.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "sa515m-v2.dtsi" +#include "sa515m-ccard.dtsi" / { model = "Qualcomm Technologies, Inc. SA515M CCARD ETH V2"; diff --git a/qcom/sa515m-v2-ccard-pcie-ep.dts b/qcom/sa515m-v2-ccard-pcie-ep.dts index d9f79703..c967203b 100755 --- a/qcom/sa515m-v2-ccard-pcie-ep.dts +++ b/qcom/sa515m-v2-ccard-pcie-ep.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "sa515m-v2.dtsi" +#include "sa515m-ccard.dtsi" / { model = "Qualcomm Technologies, Inc. SA515M CCARD PCIE-EP V2"; @@ -8,3 +9,27 @@ "qcom,sa515m", "qcom,ccard"; qcom,board-id = <25 1>, <25 0x101>; }; + +&pcie0 { + status = "disabled"; +}; + +&pcie_ep { + status = "ok"; +}; + +&ipa_hw { + qcom,use-ipa-in-mhi-mode; + qcom,mhi-event-ring-id-limits = <7 13>; /* start and end */ + ipa_smmu_ap: ipa_smmu_ap { + qcom,iommu-dma = "bypass"; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + qcom,iommu-dma = "bypass"; + }; + + ipa_smmu_uc: ipa_smmu_uc { + qcom,iommu-dma = "bypass"; + }; +}; diff --git a/qcom/sa515m-v2-ccard-usb-ep.dts b/qcom/sa515m-v2-ccard-usb-ep.dts index 703b2b85..192d847f 100755 --- a/qcom/sa515m-v2-ccard-usb-ep.dts +++ b/qcom/sa515m-v2-ccard-usb-ep.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "sa515m-v2.dtsi" +#include "sa515m-ccard.dtsi" / { model = "Qualcomm Technologies, Inc. SA515M CCARD USB-EP V2"; diff --git a/qcom/sa515m-v2-ccard.dts b/qcom/sa515m-v2-ccard.dts index 34d2f155..fcc8a7ca 100755 --- a/qcom/sa515m-v2-ccard.dts +++ b/qcom/sa515m-v2-ccard.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "sa515m-v2.dtsi" +#include "sa515m-ccard.dtsi" / { model = "Qualcomm Technologies, Inc. SA515M CCARD V2"; diff --git a/qcom/sa515m-v2.dtsi b/qcom/sa515m-v2.dtsi index 1746852b..465d364b 100755 --- a/qcom/sa515m-v2.dtsi +++ b/qcom/sa515m-v2.dtsi @@ -15,3 +15,244 @@ status="ok"; }; }; + +&pcie0 { + qcom,pcie-phy-ver = <2102>; + qcom,phy-sequence = <0x1240 0x03 0x0 + 0x1010 0x01 0x0 + 0x101c 0x31 0x0 + 0x1020 0x01 0x0 + 0x1024 0xce 0x0 + 0x1028 0x0b 0x0 + 0x1030 0x97 0x0 + 0x1034 0x0c 0x0 + 0x1044 0x18 0x0 + 0x1048 0x90 0x0 + 0x1058 0x0f 0x0 + 0x1074 0x06 0x0 + 0x1078 0x06 0x0 + 0x107c 0x16 0x0 + 0x1080 0x16 0x0 + 0x1084 0x36 0x0 + 0x1088 0x36 0x0 + 0x1094 0x08 0x0 + 0x10a4 0x46 0x0 + 0x10a8 0x04 0x0 + 0x10ac 0x04 0x0 + 0x10b0 0x0d 0x0 + 0x10b4 0x0a 0x0 + 0x10b8 0x1a 0x0 + 0x10bc 0xc3 0x0 + 0x10c4 0xd0 0x0 + 0x10d4 0x05 0x0 + 0x10d8 0x55 0x0 + 0x10dc 0x55 0x0 + 0x10e0 0x05 0x0 + 0x110c 0x02 0x0 + 0x1154 0x34 0x0 + 0x1158 0x12 0x0 + 0x115c 0x00 0x0 + 0x1168 0x05 0x0 + 0x116c 0x04 0x0 + 0x119c 0x88 0x0 + 0x11a0 0x03 0x0 + 0x11ac 0xca 0x0 + 0x11b0 0x1e 0x0 + 0x11b4 0xd8 0x0 + 0x11b8 0x20 0x0 + 0x11bc 0x22 0x0 + 0x106c 0x0a 0x0 + 0x1070 0x10 0x0 + 0x11a4 0x17 0x0 + 0x11a8 0x0b 0x0 + 0x0088 0x05 0x0 + 0x008c 0xf6 0x0 + 0x0090 0x13 0x0 + 0x00e0 0x00 0x0 + 0x00c4 0x00 0x0 + 0x0208 0x0c 0x0 + 0x0258 0x16 0x0 + 0x0378 0x27 0x0 + 0x03c8 0x1a 0x0 + 0x03cc 0x5a 0x0 + 0x03d0 0x09 0x0 + 0x03d4 0x37 0x0 + 0x03d8 0xbd 0x0 + 0x03dc 0xf9 0x0 + 0x03e0 0xbf 0x0 + 0x03e4 0xce 0x0 + 0x03e8 0x62 0x0 + 0x03ec 0xbf 0x0 + 0x03f0 0x7d 0x0 + 0x03f4 0xbf 0x0 + 0x03f8 0xcf 0x0 + 0x03fc 0xd6 0x0 + 0x02ac 0x7f 0x0 + 0x0310 0x55 0x0 + 0x0334 0x0c 0x0 + 0x0338 0x00 0x0 + 0x0350 0x08 0x0 + 0x0400 0xa0 0x0 + 0x043c 0x12 0x0 + 0x040c 0x38 0x0 + 0x0888 0x05 0x0 + 0x088c 0xf6 0x0 + 0x0890 0x13 0x0 + 0x08e0 0x00 0x0 + 0x08c4 0x00 0x0 + 0x0a08 0x0c 0x0 + 0x0a58 0x16 0x0 + 0x0b78 0x27 0x0 + 0x0bc8 0x1a 0x0 + 0x0bcc 0x5a 0x0 + 0x0bd0 0x09 0x0 + 0x0bd4 0x37 0x0 + 0x0bd8 0xbd 0x0 + 0x0bdc 0xf9 0x0 + 0x0be0 0xbf 0x0 + 0x0be4 0xce 0x0 + 0x0be8 0x62 0x0 + 0x0bec 0xbf 0x0 + 0x0bf0 0x7d 0x0 + 0x0bf4 0xbf 0x0 + 0x0bf8 0xcf 0x0 + 0x0bfc 0xd6 0x0 + 0x0aac 0x7f 0x0 + 0x0b10 0x55 0x0 + 0x0b34 0x0c 0x0 + 0x0b38 0x00 0x0 + 0x0b50 0x08 0x0 + 0x0c00 0xa0 0x0 + 0x0c3c 0x12 0x0 + 0x0c0c 0x38 0x0 + 0x161c 0xc1 0x0 + 0x1690 0x00 0x0 + 0x13e0 0x16 0x0 + 0x13e4 0x02 0x0 + 0x1708 0x02 0x0 + 0x16a0 0x17 0x0 + 0x13d8 0x01 0x0 + 0x16fc 0x01 0x0 + 0x16f0 0x13 0x0 + 0x16f4 0x13 0x0 + 0x1388 0x77 0x0 + 0x1200 0x00 0x0 + 0x1244 0x03 0x0>; +}; + +&pcie_ep { + qcom,pcie-phy-ver = <2103>; + qcom,phy-init = <0x1240 0x001 0x0 + 0x100c 0x02 0x0 + 0x1044 0x18 0x0 + 0x104c 0x07 0x0 + 0x1058 0x0f 0x0 + 0x1074 0x0a 0x0 + 0x1078 0x0a 0x0 + 0x107c 0x19 0x0 + 0x1080 0x19 0x0 + 0x1084 0x03 0x0 + 0x1088 0x03 0x0 + 0x1094 0x00 0x0 + 0x10a4 0x46 0x0 + 0x10a8 0x04 0x0 + 0x10ac 0x7f 0x0 + 0x10b0 0x02 0x0 + 0x10b4 0xff 0x0 + 0x10b8 0x04 0x0 + 0x10bc 0x4b 0x0 + 0x10c4 0x50 0x0 + 0x10d4 0x00 0x0 + 0x10ec 0xfb 0x0 + 0x10f0 0x01 0x0 + 0x10f4 0xfb 0x0 + 0x10f8 0x01 0x0 + 0x110c 0x02 0x0 + 0x1158 0x12 0x0 + 0x115c 0x00 0x0 + 0x1168 0x05 0x0 + 0x116c 0x04 0x0 + 0x119c 0x88 0x0 + 0x11a0 0x03 0x0 + 0x11ac 0x56 0x0 + 0x11b0 0x1d 0x0 + 0x11b4 0x4b 0x0 + 0x11b8 0x1f 0x0 + 0x11bc 0x22 0x0 + 0x11a4 0x17 0x0 + 0x11a8 0x0b 0x0 + 0x117c 0x04 0x0 + 0x0088 0x05 0x0 + 0x008c 0xf6 0x0 + 0x0090 0x13 0x0 + 0x00e0 0x00 0x0 + 0x00c4 0x00 0x0 + 0x0208 0x0c 0x0 + 0x0258 0x16 0x0 + 0x0378 0x27 0x0 + 0x03c8 0x1a 0x0 + 0x03cc 0x5a 0x0 + 0x03d0 0x09 0x0 + 0x03d4 0x37 0x0 + 0x03d8 0xbd 0x0 + 0x03dc 0xf9 0x0 + 0x03e0 0xbf 0x0 + 0x03e4 0xce 0x0 + 0x03e8 0x62 0x0 + 0x03ec 0xbf 0x0 + 0x03f0 0x7d 0x0 + 0x03f4 0xbf 0x0 + 0x03f8 0xcf 0x0 + 0x03fc 0xd6 0x0 + 0x02ac 0x7f 0x0 + 0x0310 0x55 0x0 + 0x0334 0x0c 0x0 + 0x0338 0x00 0x0 + 0x0350 0x08 0x0 + 0x0400 0xa0 0x0 + 0x043c 0x12 0x0 + 0x040c 0x38 0x0 + 0x0888 0x05 0x0 + 0x088c 0xf6 0x0 + 0x0890 0x13 0x0 + 0x08e0 0x00 0x0 + 0x08c4 0x00 0x0 + 0x0a08 0x0c 0x0 + 0x0a58 0x16 0x0 + 0x0b78 0x27 0x0 + 0x0bc8 0x1a 0x0 + 0x0bcc 0x5a 0x0 + 0x0bd0 0x09 0x0 + 0x0bd4 0x37 0x0 + 0x0bd8 0xbd 0x0 + 0x0bdc 0xf9 0x0 + 0x0be0 0xbf 0x0 + 0x0be4 0xce 0x0 + 0x0be8 0x62 0x0 + 0x0bec 0xbf 0x0 + 0x0bf0 0x7d 0x0 + 0x0bf4 0xbf 0x0 + 0x0bf8 0xcf 0x0 + 0x0bfc 0xd6 0x0 + 0x0aac 0x7f 0x0 + 0x0b10 0x55 0x0 + 0x0b34 0x0c 0x0 + 0x0b38 0x00 0x0 + 0x0b50 0x08 0x0 + 0x0c00 0xa0 0x0 + 0x0c3c 0x12 0x0 + 0x0c0c 0x38 0x0 + 0x13e0 0x16 0x0 + 0x13e4 0x02 0x0 + 0x1708 0x02 0x0 + 0x16a0 0x17 0x0 + 0x13d8 0x01 0x0 + 0x16fc 0x01 0x0 + 0x16f0 0x13 0x0 + 0x16f4 0x13 0x0 + 0x1e24 0x00 0x0 + 0x1e28 0x00 0x0 + 0x1388 0x77 0x0 + 0x1200 0x000 0x0 + 0x1244 0x003 0x0>; +}; diff --git a/qcom/sa515m-wcd.dtsi b/qcom/sa515m-wcd.dtsi new file mode 100755 index 00000000..40853ca6 --- /dev/null +++ b/qcom/sa515m-wcd.dtsi @@ -0,0 +1,68 @@ +&i2c_3 { + tavil_codec { + wcd: wcd_pinctrl@5 { + compatible = "qcom,wcd-pinctrl"; + qcom,gpios-count = <5>; + gpio-controller; + #gpio-cells = <2>; + + spkr_1_wcd_en_active: spkr_1_wcd_en_active { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + output-high; + }; + }; + + spkr_1_wcd_en_sleep: spkr_1_wcd_en_sleep { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + input-enable; + }; + }; + + spkr_2_wcd_en_active: spkr_2_sd_n_active { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + output-high; + }; + }; + + spkr_2_wcd_en_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + input-enable; + }; + }; + }; + + wsa_spkr_wcd_sd1: msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_wcd_en_active>; + pinctrl-1 = <&spkr_1_wcd_en_sleep>; + }; + + wsa_spkr_wcd_sd2: msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_2_wcd_en_active>; + pinctrl-1 = <&spkr_2_wcd_en_sleep>; + }; + }; +}; diff --git a/qcom/sa515m-wsa881x.dtsi b/qcom/sa515m-wsa881x.dtsi new file mode 100755 index 00000000..cc40c4a2 --- /dev/null +++ b/qcom/sa515m-wsa881x.dtsi @@ -0,0 +1,17 @@ +&i2c_3 { + tavil_codec { + swr_master { + compatible = "qcom,swr-wcd"; + #address-cells = <2>; + #size-cells = <0>; + qcom,swr-num-dev = <1>; + + wsa881x_0214: wsa881x@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; + qcom,wsa-prefix = "SpkrLeft"; + }; + }; + }; +}; diff --git a/qcom/sa515m.dtsi b/qcom/sa515m.dtsi index deead392..488a86bd 100755 --- a/qcom/sa515m.dtsi +++ b/qcom/sa515m.dtsi @@ -20,6 +20,8 @@ chosen: chosen { }; aliases { + pci-domain0 = &pcie0; /* PCIe0 domain */ + sdhc1 = &sdhc_1; /* SDC1 eMMC/SD/SDIO slot */ }; reserved_mem: reserved-memory { @@ -135,6 +137,7 @@ compatible = "arm,cortex-a7"; reg = <0x0>; enable-method = "psci"; + cpu-idle-states = <&A7_SPC &A7_PC &CX_MIN>; #cooling-cells = <2>; }; }; @@ -179,6 +182,10 @@ apps_bcm_voter: bcm_voter { compatible = "qcom,bcm-voter"; }; + + system_pm { + compatible = "qcom,system-pm"; + }; }; intc: interrupt-controller@17800000 { @@ -197,7 +204,7 @@ reg-names = "base", "mux-base"; qcom,pdc-ranges = <0 147 52>; qcom,pdc-mux-ranges = <20 28 0>, <21 32 1>, <22 35 2>, - <23 57 3>, <24 49 4>, <25 103 5>; + <23 57 3>, <24 49 4>, <25 58 5>; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupt-controller; @@ -448,10 +455,83 @@ qcom,rtb-size = <0x100000>; }; + + qnand_1: nand@1b00000 { + compatible = "qcom,msm-nand"; + reg = <0x01b00000 0x1000>, + <0x01b04000 0x1c000>; + reg-names = "nand_phys", + "bam_phys"; + qcom,reg-adjustment-offset = <0x4000>; + + interrupts = <0 135 0>; + interrupt-names = "bam_irq"; + + qcom,msm-bus,name = "qpic_nand"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <91 512 0 0>, + /* Voting for max b/w on PNOC bus for now */ + <91 512 400000 400000>; + + clock-names = "core_clk"; + clocks = <&rpmhcc RPMH_QPIC_CLK>; + + status = "ok"; + }; + + + sdhc_1: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = <GIC_SPI 210 IRQ_TYPE_NONE>, + <GIC_SPI 227 IRQ_TYPE_NONE>; + interrupt-names = "hc_irq", "pwr_irq"; + + bus-width = <4>; + + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ + <78 512 1600 3200>, /* 400 KB/s*/ + <78 512 80000 160000>, /* 20 MB/s */ + <78 512 100000 200000>, /* 25 MB/s */ + <78 512 200000 400000>, /* 50 MB/s */ + <78 512 400000 800000>, /* 100 MB/s */ + <78 512 400000 800000>, /* 200 MB/s */ + <78 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100000000 200000000 4294967295>; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>; + clock-names = "iface", "core"; + + //qcom,restore-after-cx-collapse; + + /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0xa800 0x10 + 0x2c010800 0x80040868>; + + qcom,devfreq,freq-table = <50000000 200000000>; + no-sdio; + no-mmc; + + status = "disabled"; + }; + + serial_uart: serial@831000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x831000 0x200>; interrupts = <0 26 0>; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart3_console_active>; pinctrl-1 = <&uart3_console_sleep>; @@ -788,6 +868,7 @@ qcom,msm-bus,name = "ipa"; qcom,ipa-wdi2_over_gsi; qcom,ipa-endp-delay-wa; + qcom,ipa-config-is-auto; qcom,ipa-wdi3-holb-2g = <8>; qcom,ipa-wdi3-holb-5g = <15>; qcom,msm-bus,num-cases = <5>; @@ -799,11 +880,11 @@ qcom,interconnect,num-cases = <5>; qcom,interconnect,num-paths = <5>; interconnects = <&system_noc MASTER_IPA &system_noc SLAVE_SNOC_MEM_NOC_GC>, - <&system_noc MASTER_IPA &mc_virt SLAVE_EBI1>, + <&mem_noc MASTER_SNOC_GC_MEM_NOC &mc_virt SLAVE_EBI1>, <&system_noc MASTER_IPA &system_noc SLAVE_IMEM>, <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>, <&ipa_virt MASTER_IPA_CORE &ipa_virt SLAVE_IPA_CORE>; - interconnect-names = "ipa_to_memnoc", "ipa_to_ebi1", "ipa_to_imem", "ipacore_to_ipacore", "ipacore_to_ipacore"; + interconnect-names = "ipa_to_memnoc", "ipa_to_ebi1", "ipa_to_imem", "appsproc_to_ipacfg", "ipacore_to_ipacore"; /* No vote */ qcom,no-vote = @@ -877,6 +958,9 @@ #include "sa515m-ion.dtsi" #include "msm-arm-smmu-sa515m.dtsi" #include "sa515m-usb.dtsi" +#include "sa515m-pcie.dtsi" +#include "sa515m-pm.dtsi" +#include "sa515m-audio.dtsi" &vreg_rgmii_io_pads { regulator-min-microvolt = <1800000>; @@ -892,3 +976,24 @@ &gdsc_usb30 { status = "ok"; }; + +&sdhc_1 { + vdd-supply = <&vreg_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&vreg_vddpx_2>; + qcom,vdd-io-voltage-level = <1800000 2850000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 200000000>; + qcom,devfreq,freq-table = <50000000 200000000>; + + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; + status = "ok"; +}; diff --git a/qcom/sa8195-vm-lv-cnss-lxc.dtsi b/qcom/sa8195-vm-lv-cnss-lxc.dtsi index a2d30e60..c9f997ca 100755 --- a/qcom/sa8195-vm-lv-cnss-lxc.dtsi +++ b/qcom/sa8195-vm-lv-cnss-lxc.dtsi @@ -41,7 +41,6 @@ qcom,wlan-rc-num = <0>; qcom,pld_bus_ops_name = "pld_pcie_cnss0"; qcom,bus-type=<0>; - qcom,qrtr_node_id = <0x10>; qcom,notify-modem-status; #address-cells=<1>; @@ -80,7 +79,7 @@ chip_cfg@1 { reg = <0xb0000000 0x10000>; reg-names = "smmu_iova_ipa"; - + qcom,qrtr_node_id = <0x10>; supported-ids = <0x1101>; wlan_vregs = "vdd-wlan-vl", "vdd-wlan-vm", "vdd-wlan-s5c", "vdd-wlan-vh"; @@ -308,7 +307,6 @@ qcom,wlan-rc-num = <2>; qcom,pld_bus_ops_name = "pld_pcie_cnss2"; qcom,bus-type=<0>; - qcom,qrtr_node_id = <0x20>; qcom,notify-modem-status; #address-cells=<1>; @@ -345,7 +343,7 @@ chip_cfg@1 { reg = <0xd0000000 0x10000>; reg-names = "smmu_iova_ipa"; - + qcom,qrtr_node_id = <0x20>; supported-ids = <0x1101>; wlan_vregs = "vdd-wlan-vl", "vdd-wlan-vm", "vdd-wlan-s5c", "vdd-wlan-vh"; diff --git a/qcom/scuba-thermal.dtsi b/qcom/scuba-thermal.dtsi index 561b4e08..bad6999e 100755 --- a/qcom/scuba-thermal.dtsi +++ b/qcom/scuba-thermal.dtsi @@ -374,7 +374,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&pm2250_adc_tm_iio ADC5_GPIO1_100K_PU>; + thermal-sensors = <&pm2250_adc_tm_iio ADC5_GPIO3_100K_PU>; trips { active-config0 { temperature = <125000>; diff --git a/qcom/sdx55-mtp.dtsi b/qcom/sdx55-mtp.dtsi index 2506d0e8..cdfef23f 100755 --- a/qcom/sdx55-mtp.dtsi +++ b/qcom/sdx55-mtp.dtsi @@ -1,4 +1,5 @@ #include "sdx55-pmic-overlay.dtsi" +#include "sa515m-mtp-audio-overlay.dtsi" &pmx55_vadc { vph_pwr { diff --git a/qcom/sdxlemur-thermal-modem.dtsi b/qcom/sdxlemur-thermal-modem.dtsi index e54074ab..e04948b3 100755 --- a/qcom/sdxlemur-thermal-modem.dtsi +++ b/qcom/sdxlemur-thermal-modem.dtsi @@ -140,7 +140,9 @@ "mmw1", "mmw2", "mmw3", - "mmw_ific0"; + "mmw_ific0", + "sdr0_pa", + "sdr1_pa"; }; }; }; @@ -619,4 +621,44 @@ }; }; }; + + modem-sdr0-pa { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR0_PA)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-sdr1-pa { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_SDR1_PA)>; + trips { + thermal-engine-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; }; diff --git a/qcom/sm6150-coresight.dtsi b/qcom/sm6150-coresight.dtsi index ac10268f..3f5d62c3 100755 --- a/qcom/sm6150-coresight.dtsi +++ b/qcom/sm6150-coresight.dtsi @@ -422,7 +422,7 @@ tpdm_wcss: tpdm@699c000 { compatible = "qcom,coresight-dummy"; - + arm,primecell-periphid = <0x0003b968>; coresight-name = "coresight-tpdm-wcss"; qcom,dummy-source; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index 1855c6dc..4ef75b7e 100755 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -1702,6 +1702,12 @@ #mbox-cells = <1>; }; + aop-msg-client { + compatible = "qcom,debugfs-qmp-client"; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + }; + slim_aud: slim@62dc0000 { cell-index = <1>; compatible = "qcom,slim-ngd"; diff --git a/qcom/sm8150-coresight.dtsi b/qcom/sm8150-coresight.dtsi index f2997ded..782819b0 100755 --- a/qcom/sm8150-coresight.dtsi +++ b/qcom/sm8150-coresight.dtsi @@ -1276,8 +1276,10 @@ clock-names = "apb_pclk"; out-ports { - tpdm_qm_out_funnel_dl_mm: endpoint { - remote-endpoint = <&funnel_dl_mm_in_tpdm_qm>; + port { + tpdm_qm_out_funnel_dl_mm: endpoint { + remote-endpoint = <&funnel_dl_mm_in_tpdm_qm>; + }; }; }; }; @@ -1329,8 +1331,10 @@ clock-names = "apb_pclk"; out-ports { - tpdm_apss_out_tpda_apss: endpoint { - remote-endpoint = <&tpda_apss_in_tpdm_apss>; + port { + tpdm_apss_out_tpda_apss: endpoint { + remote-endpoint = <&tpda_apss_in_tpdm_apss>; + }; }; }; }; @@ -1382,9 +1386,11 @@ clock-names = "apb_pclk"; out-ports { - tpdm_llm_silver_out_tpda_llm_silver: endpoint { - remote-endpoint = - <&tpda_llm_silver_in_tpdm_llm_silver>; + port { + tpdm_llm_silver_out_tpda_llm_silver: endpoint { + remote-endpoint = + <&tpda_llm_silver_in_tpdm_llm_silver>; + }; }; }; }; |