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| author | Siddhartha Agrawal <agrawals@codeaurora.org> | 2013-04-21 16:16:57 -0700 |
|---|---|---|
| committer | Siddhartha Agrawal <agrawals@codeaurora.org> | 2013-04-24 14:30:38 -0700 |
| commit | 7317e48dd0047af0df473645af2ff2c1978c841e (patch) | |
| tree | 23fc7c428bce34c5fdf5842d827a319eb8660a54 | |
| parent | 7dc3aa920cdfff9415f94e3a2255422a0bfbc4cf (diff) | |
| download | lk-7317e48dd0047af0df473645af2ff2c1978c841e.tar.gz | |
msm_shared: mipi: Add MIPI DSI support for command mode panel
Add support for command mode panels.
Change-Id: Iab4d4ec905c3ab618c2d816cde25b24a7768ec5c
| -rw-r--r-- | platform/msm_shared/mipi_dsi.c | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c index 64fe03d3..055de7d6 100644 --- a/platform/msm_shared/mipi_dsi.c +++ b/platform/msm_shared/mipi_dsi.c @@ -774,6 +774,65 @@ int mipi_dsi_video_mode_config(unsigned short disp_width, return status; } +int mdss_dsi_cmd_mode_config(uint16_t disp_width, + uint16_t disp_height, + uint16_t img_width, + uint16_t img_height, + uint16_t dst_format, + uint16_t traffic_mode) +{ + uint8_t DST_FORMAT; + uint8_t TRAFIC_MODE; + uint8_t DLNx_EN; + // video mode data ctrl + int status = 0; + uint8_t interleav = 0; + uint8_t ystride = 0x03; + // disable mdp first + + writel(0x00000000, DSI_CLK_CTRL); + writel(0x00000000, DSI_CLK_CTRL); + writel(0x00000000, DSI_CLK_CTRL); + writel(0x00000000, DSI_CLK_CTRL); + writel(0x00000002, DSI_CLK_CTRL); + writel(0x00000006, DSI_CLK_CTRL); + writel(0x0000000e, DSI_CLK_CTRL); + writel(0x0000001e, DSI_CLK_CTRL); + writel(0x0000023f, DSI_CLK_CTRL); + + writel(0, DSI_CTRL); + + writel(0, DSI_ERR_INT_MASK0); + + writel(0x02020202, DSI_INT_CTRL); + + DST_FORMAT = 8; // RGB888 + dprintf(SPEW, "DSI_Cmd_Mode - Dst Format: RGB888\n"); + + DLNx_EN = 0xf; // 4 lane with clk programming + dprintf(SPEW, "Data Lane: 4 lane\n"); + + TRAFIC_MODE = 0; // non burst mode with sync pulses + dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n"); + + writel(DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL); + writel((img_width * ystride + 1) << 16 | 0x0039, + DSI_COMMAND_MODE_MDP_STREAM0_CTRL); + writel((img_width * ystride + 1) << 16 | 0x0039, + DSI_COMMAND_MODE_MDP_STREAM1_CTRL); + writel(img_height << 16 | img_width, + DSI_COMMAND_MODE_MDP_STREAM0_TOTAL); + writel(img_height << 16 | img_width, + DSI_COMMAND_MODE_MDP_STREAM1_TOTAL); + writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL); + writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105, + DSI_CTRL); + writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL); + writel(0x10000000, DSI_MISR_CMD_CTRL); + + return NO_ERROR; +} + int mipi_dsi_cmd_mode_config(unsigned short disp_width, unsigned short disp_height, unsigned short img_width, |