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authorFei Wang <w.f@huawei.com>2015-02-05 23:55:05 +0800
committerGuodong Xu <guodong.xu@linaro.org>2015-10-21 20:53:28 +0800
commit5b7b17f0fb4bf962f89f680e8bb9647d3ef89881 (patch)
treef2e9e2830df109d149b6bb826896e86d22af082e
parent9033ec8a33e64ec790575ef49e9364e6ce0a1fb1 (diff)
downloadlinux-linaro-tracking-5b7b17f0fb4bf962f89f680e8bb9647d3ef89881.tar.gz
misc: hi6220: Add driver to config some device host chips resided on hi6220 SoC
This driver is used to configure the hi6220 SoC to control some device hosts(e.g. UART), reset the host or disable the reset. Signed-off-by: Bintian Wang <bintian.wang@huawei.com> Conflicts: arch/arm64/Kconfig
-rw-r--r--arch/arm64/Kconfig.platforms1
-rw-r--r--drivers/misc/Kconfig8
-rw-r--r--drivers/misc/Makefile1
-rw-r--r--drivers/misc/hi6220-sysconfig.c63
4 files changed, 73 insertions, 0 deletions
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 6d730fbf00df..bb4b1d043407 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -36,6 +36,7 @@ config ARCH_FSL_LS2085A
config ARCH_HISI
bool "Hisilicon SoC Family"
select ARM_TIMER_SP804
+ select HI6220_SYSCFG
help
This enables support for Hisilicon ARMv8 SoC family
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index ccccc2943f2f..ed742d9acc54 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -525,6 +525,14 @@ config VEXPRESS_SYSCFG
bus. System Configuration interface is one of the possible means
of generating transactions on this bus.
+config HI6220_SYSCFG
+ bool "Hisilicon HI6220 System Configuration driver"
+ depends on ARCH_HISI
+ default y
+ help
+ Hisilicon HI6220 uses some registers to configure some chip hosts to
+ work or not, e.g. disable the UART hosts reset and let's them work.
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 537d7f3b78da..eeeefbf5e149 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -56,3 +56,4 @@ obj-$(CONFIG_GENWQE) += genwqe/
obj-$(CONFIG_ECHO) += echo/
obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o
obj-$(CONFIG_CXL_BASE) += cxl/
+obj-$(CONFIG_HI6220_SYSCFG) += hi6220-sysconfig.o
diff --git a/drivers/misc/hi6220-sysconfig.c b/drivers/misc/hi6220-sysconfig.c
new file mode 100644
index 000000000000..ef5e017fdfb6
--- /dev/null
+++ b/drivers/misc/hi6220-sysconfig.c
@@ -0,0 +1,63 @@
+/*
+ * For Hisilicon Hi6220 SoC, the reset of some hosts (e.g. UART) should be disabled
+ * before using them, this driver will handle the host chip reset disable.
+ *
+ * Copyright (C) 2015 Hisilicon Ltd.
+ * Author: Bintian Wang <bintian.wang@huawei.com>
+ *
+ */
+
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#define reset_offset 0x334
+#define pclk_offset 0x230
+
+static int __init hi6220_sysconf(void)
+{
+ static void __iomem *base = NULL;
+ struct device_node *node;
+
+ node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
+ if (!node)
+ return -ENOENT;
+
+ base = of_iomap(node, 0);
+ if (base == NULL) {
+ printk(KERN_ERR "hi6220: sysctrl reg iomap failed!\n");
+ return -ENOMEM;
+ }
+
+ /*Disable UART1 reset and set pclk*/
+ writel(BIT(5), base + reset_offset);
+ writel(BIT(5), base + pclk_offset);
+
+ /*Disable UART2 reset and set pclk*/
+ writel(BIT(6), base + reset_offset);
+ writel(BIT(6), base + pclk_offset);
+
+ /*Disable UART3 reset and set pclk*/
+ writel(BIT(7), base + reset_offset);
+ writel(BIT(7), base + pclk_offset);
+
+ /*Disable UART4 reset and set pclk*/
+ writel(BIT(8), base + reset_offset);
+ writel(BIT(8), base + pclk_offset);
+
+ iounmap(base);
+
+ return 0;
+}
+postcore_initcall(hi6220_sysconf);
+
+#ifdef CONFIG_ARM64
+#ifdef CONFIG_SPARSE_IRQ
+#define NR_IRQS_LEGACY_HI6220 16
+
+int __init arch_probe_nr_irqs(void)
+{
+ return NR_IRQS_LEGACY_HI6220;
+}
+
+#endif
+#endif