diff options
| author | Victor Hsu <hsuvictor@google.com> | 2022-10-15 02:13:55 +0000 |
|---|---|---|
| committer | Victor Hsu <hsuvictor@google.com> | 2022-10-15 03:10:36 +0000 |
| commit | f1e4f83eee69172b3e2dded860807ac6feeb148d (patch) | |
| tree | 229b09e557e1a56230c744b69e5e11b3980f9787 | |
| parent | 28d3dc9e4bef4b4626e810d5cec81bd5c91904e7 (diff) | |
| download | cnss2-f1e4f83eee69172b3e2dded860807ac6feeb148d.tar.gz | |
cnss: Avoid flodding of logs
Remove debug messges and print them only when
error happens.
Bug: 240393428
Signed-off-by: Victor Hsu <hsuvictor@google.com>
Change-Id: I217d25b3a24951c0079b8f0af43ed55423412fbc
| -rw-r--r-- | cnss2/pci.c | 2 | ||||
| -rw-r--r-- | cnss2/pci_platform_google.c | 13 |
2 files changed, 12 insertions, 3 deletions
diff --git a/cnss2/pci.c b/cnss2/pci.c index dc78895..fdb3417 100644 --- a/cnss2/pci.c +++ b/cnss2/pci.c @@ -1709,10 +1709,12 @@ retry_mhi_suspend: cnss_pci_allow_l1(&pci_priv->pci_dev->dev); } else { #if IS_ENABLED(CONFIG_WCN_GOOGLE) + cnss_pr_dbg("Disable PCIe L1ss\n"); cnss_pci_prevent_l1(&pci_priv->pci_dev->dev); #endif ret = mhi_pm_resume(pci_priv->mhi_ctrl); #if IS_ENABLED(CONFIG_WCN_GOOGLE) + cnss_pr_dbg("Enable PCIe L1ss\n"); cnss_pci_allow_l1(&pci_priv->pci_dev->dev); #endif } diff --git a/cnss2/pci_platform_google.c b/cnss2/pci_platform_google.c index 1effec6..9154915 100644 --- a/cnss2/pci_platform_google.c +++ b/cnss2/pci_platform_google.c @@ -171,7 +171,10 @@ int cnss_pci_prevent_l1(struct device *dev) } ret = exynos_pcie_rc_l1ss_ctrl(0, PCIE_L1SS_CTRL_WIFI, pci_priv->plat_priv->rc_num); - cnss_pr_dbg("disable PCIe rc L1ss, ret=%d\n", ret); + if (ret) { + cnss_pr_err("Disable PCIe L1ss failed\n"); + } + return ret; } EXPORT_SYMBOL(cnss_pci_prevent_l1); @@ -180,6 +183,7 @@ void cnss_pci_allow_l1(struct device *dev) { struct pci_dev *pci_dev = to_pci_dev(dev); struct cnss_pci_data *pci_priv = cnss_get_pci_priv(pci_dev); + int ret; if (!pci_priv) { cnss_pr_err("pci_priv is NULL\n"); @@ -196,8 +200,11 @@ void cnss_pci_allow_l1(struct device *dev) return; } - cnss_pr_dbg("enable PCIe rc L1ss\n"); - exynos_pcie_rc_l1ss_ctrl(1, PCIE_L1SS_CTRL_WIFI, pci_priv->plat_priv->rc_num); + ret = exynos_pcie_rc_l1ss_ctrl(1, PCIE_L1SS_CTRL_WIFI, pci_priv->plat_priv->rc_num); + if (ret) { + cnss_pr_err("Enable PCIe L1ss failed\n"); + } + } EXPORT_SYMBOL(cnss_pci_allow_l1); |