Merge android14-gs-pixel-5.15-udc-d1 into android14-gs-pixel-5.15-udc-qpr1

SBMerger: 526756187
Change-Id: Idbdb258413ab0c643eee97e956a234b4bfc765dc
Signed-off-by: SecurityBot <android-nexus-securitybot@system.gserviceaccount.com>

5 files changed, 29 insertions, 10 deletions

diff --git a/Kbuild b/Kbuild
index c871a40..4316398 100644
--- a/Kbuild
+++ b/Kbuild
@@ -328,7 +328,7 @@ ifneq ($(CONFIG_SOC_GOOGLE),)
 	# Tasklet load detection and balancing
 	DHDCFLAGS += -DRESCHED_CNT_CHECK_PERIOD_SEC=2
 	DHDCFLAGS += -DAFFINITY_UPDATE_MIN_PERIOD_SEC=6
-	DHDCFLAGS += -DRESCHED_STREAK_MAX_HIGH=10
+	DHDCFLAGS += -DRESCHED_STREAK_MAX_HIGH=20
 	DHDCFLAGS += -DRESCHED_STREAK_MAX_LOW=2
 	DHDCFLAGS += -DCLEAN_IRQ_AFFINITY_HINT
 	DHDCFLAGS += -DIRQ_AFFINITY_BIG_CORE=7
diff --git a/dhd_custom_google.c b/dhd_custom_google.c
index 13a2296..3e0438c 100644
--- a/dhd_custom_google.c
+++ b/dhd_custom_google.c
@@ -80,6 +80,7 @@ static uint64 last_affinity_update_time_ns = 0;
 static uint hw_stage_val = 0;
 /* force to switch to small core at beginning */
 static bool is_irq_on_big_core = TRUE;
+static bool is_plat_pcie_resume = FALSE;
 
 static int pcie_ch_num = EXYNOS_PCIE_CH_NUM;
 #if defined(CONFIG_SOC_GOOGLE)
@@ -784,11 +785,13 @@ irq_affinity_hysteresis_control(struct pci_dev *pdev, int resched_streak_max,
 			DHD_ERROR(("%s switches to big core unsuccessfully!\n", __FUNCTION__));
 		}
 	}
-	if (is_irq_on_big_core && (resched_streak_max <= RESCHED_STREAK_MAX_LOW) &&
-		!has_recent_affinity_update) {
+	if (is_plat_pcie_resume ||
+            (is_irq_on_big_core && (resched_streak_max <= RESCHED_STREAK_MAX_LOW) &&
+             !has_recent_affinity_update)) {
 		err = set_affinity(pdev->irq, cpumask_of(IRQ_AFFINITY_SMALL_CORE));
 		if (!err) {
 			is_irq_on_big_core = FALSE;
+                        is_plat_pcie_resume = FALSE;
 			last_affinity_update_time_ns = curr_time_ns;
 			DHD_INFO(("%s switches to all cores successfully\n", __FUNCTION__));
 		} else {
@@ -811,7 +814,8 @@ void dhd_plat_report_bh_sched(void *plat_info, int resched)
 
 	if (resched > 0) {
 		resched_streak++;
-		return;
+		if (resched_streak <= RESCHED_STREAK_MAX_HIGH)
+			return;
 	}
 
 	if (resched_streak > resched_streak_max) {
@@ -978,8 +982,8 @@ int dhd_plat_pcie_resume(void *plat_info)
 {
 	int ret = 0;
 	ret = exynos_pcie_pm_resume(pcie_ch_num);
-	is_irq_on_big_core = true;
-	return ret;
+        is_plat_pcie_resume = TRUE;
+        return ret;
 }
 
 void dhd_plat_pin_dbg_show(void *plat_info)
@@ -1032,7 +1036,10 @@ void dhd_plat_pcie_skip_config_set(bool val)
 	exynos_pcie_set_skip_config(pcie_ch_num, val);
 #endif /* DHD_TREAT_D3ACKTO_AS_LINKDWN */
 }
-
+ bool dhd_plat_pcie_enable_big_core(void)
+ {
+	return is_irq_on_big_core;
+ }
 #ifndef BCMDHD_MODULAR
 /* Required only for Built-in DHD */
 device_initcall(dhd_wlan_init);
diff --git a/dhd_linux_platdev.c b/dhd_linux_platdev.c
index 71aee02..b087e64 100644
--- a/dhd_linux_platdev.c
+++ b/dhd_linux_platdev.c
@@ -1111,7 +1111,10 @@ void __attribute__ ((weak)) dhd_plat_pcie_skip_config_set(bool val)
 {
 	return;
 }
-
+bool __attribute__ ((weak)) dhd_plat_pcie_enable_big_core(void)
+{
+	return false;
+}
 int
 __attribute__ ((weak)) dhd_get_platform_naming_for_nvram_clmblob_file(download_type_t component,
 	char *file_name)
diff --git a/dhd_msgbuf.c b/dhd_msgbuf.c
index 2c139b1..db7f0e6 100644
--- a/dhd_msgbuf.c
+++ b/dhd_msgbuf.c
@@ -1794,8 +1794,16 @@ BCMFASTPATH(dhd_prot_d2h_sync_xorcsum)(dhd_pub_t *dhd, msgbuf_ring_t *ring,
 			 * complete message has arrived.
 			 */
 			if (msg->epoch == ring_seqnum) {
-				prot_checksum = bcm_compute_xor32((volatile uint32 *)msg,
-					num_words);
+				/* Based on customer request, to avoid tput regression
+				 * skip xorcsum for high tput case
+				 */
+				bool use_big_core = dhd_plat_pcie_enable_big_core();
+				if (use_big_core) {
+					prot_checksum = 0;
+				} else {
+					prot_checksum = bcm_compute_xor32((volatile uint32 *)msg,
+						num_words);
+				}
 				if (prot_checksum == 0U) { /* checksum is OK */
 					ring->seqnum++; /* next expected sequence number */
 					/* Check for LIVELOCK induce flag, which is set by firing
diff --git a/dhd_plat.h b/dhd_plat.h
index 32b37d8..0c42811 100644
--- a/dhd_plat.h
+++ b/dhd_plat.h
@@ -96,5 +96,6 @@ extern uint32 dhd_plat_get_rc_device_id(void);
 
 extern uint16 dhd_plat_align_rxbuf_size(uint16 rxbufpost_sz);
 extern void dhd_plat_pcie_skip_config_set(bool val);
+extern bool dhd_plat_pcie_enable_big_core(void);
 #endif /* __linux__ */
 #endif /* __DHD_PLAT_H__ */