diff options
| author | Anthony Huang <anthony.huang@broadcom.corp-partner.google.com> | 2020-06-04 13:24:00 +0800 |
|---|---|---|
| committer | Ahmed ElArabawy <arabawy@google.com> | 2020-06-04 11:17:09 -0700 |
| commit | 9a4cdd5594f10a327b88b40c304cdf5b82e208b7 (patch) | |
| tree | 6fc27c2ed1546dbbc4fab243ce66ca127ef88af4 | |
| parent | 9102db1d57a3fc73aacad6203cad3aaa6881b50b (diff) | |
| download | bcm43752-9a4cdd5594f10a327b88b40c304cdf5b82e208b7.tar.gz | |
wifi: debug: SError happened in R_REG
1. Because this problem cannot be reproduced. We enable the
exynos_pcie_l1_exit(0) in R_REG and W_REG.
2. "exynos_pcie_l1_exit" can make sure the PCIe link is in L0 before
we accessing it. Then keep monitoring this issue will happened again
or not.
Change-Id: I6b399bc7c72efeec2cedf7ec3355cf5758b1fe15
Bug: 157711644
Signed-off-by: Ahmed ElArabawy <arabawy@google.com>
| -rw-r--r-- | include/linux_osl.h | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/include/linux_osl.h b/include/linux_osl.h index e3b46dc..d58cfe9 100644 --- a/include/linux_osl.h +++ b/include/linux_osl.h @@ -307,20 +307,21 @@ extern uint64 osl_systztime_us(void); #define bcmp(b1, b2, len) memcmp((b1), (b2), (len)) #define bzero(b, len) memset((b), '\0', (len)) -#if defined(CONFIG_SOC_EXYNOS9830) +#if defined(CONFIG_SOC_EXYNOS9830) || defined(CONFIG_SOC_GS101) +extern int pcie_ch_num; extern int exynos_pcie_l1_exit(int ch_num); -#endif /* CONFIG_SOC_EXYNOS9830 */ +#endif /* CONFIG_SOC_EXYNOS9830 || CONFIG_SOC_GS101 */ /* register access macros */ #ifdef CONFIG_64BIT /* readq is defined only for 64 bit platform */ -#if defined(CONFIG_SOC_EXYNOS9830) +#if defined(CONFIG_SOC_EXYNOS9830) || defined(CONFIG_SOC_GS101) #define R_REG(osh, r) (\ SELECT_BUS_READ(osh, \ ({ \ __typeof(*(r)) __osl_v = 0; \ - exynos_pcie_l1_exit(0); \ + exynos_pcie_l1_exit(pcie_ch_num); \ BCM_REFERENCE(osh); \ switch (sizeof(*(r))) { \ case sizeof(uint8): __osl_v = \ @@ -356,7 +357,7 @@ extern int exynos_pcie_l1_exit(int ch_num); }), \ OSL_READ_REG(osh, r)) \ ) -#endif /* CONFIG_SOC_EXYNOS9830 */ +#endif /* CONFIG_SOC_EXYNOS9830 || CONFIG_SOC_GS101 */ #else /* !CONFIG_64BIT */ #define R_REG(osh, r) (\ SELECT_BUS_READ(osh, \ @@ -378,11 +379,11 @@ extern int exynos_pcie_l1_exit(int ch_num); #ifdef CONFIG_64BIT /* writeq is defined only for 64 bit platform */ -#if defined(CONFIG_SOC_EXYNOS9830) +#if defined(CONFIG_SOC_EXYNOS9830) || defined(CONFIG_SOC_GS101) #define W_REG(osh, r, v) do { \ SELECT_BUS_WRITE(osh, \ ({ \ - exynos_pcie_l1_exit(0); \ + exynos_pcie_l1_exit(pcie_ch_num); \ switch (sizeof(*(r))) { \ case sizeof(uint8): writeb((uint8)(v), \ (volatile uint8*)(r)); break; \ @@ -407,7 +408,7 @@ extern int exynos_pcie_l1_exit(int ch_num); }, \ (OSL_WRITE_REG(osh, r, v))); \ } while (0) -#endif /* CONFIG_SOC_EXYNOS9830 */ +#endif /* CONFIG_SOC_EXYNOS9830 || CONFIG_SOC_GS101 */ #else /* !CONFIG_64BIT */ #define W_REG(osh, r, v) do { \ SELECT_BUS_WRITE(osh, \ |