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| author | Anthony Huang <anthony.huang@broadcom.corp-partner.google.com> | 2020-05-01 19:28:00 +0800 |
|---|---|---|
| committer | Ahmed ElArabawy <arabawy@google.com> | 2020-06-03 07:34:51 -0700 |
| commit | 47862f36f0e112059a71554499e82e93ee8952ad (patch) | |
| tree | 265bf12567ed313c42b4baa7b8aa307f79fe5146 | |
| parent | 873af36bad6829756f5505e9aa3e3d894abbf0bf (diff) | |
| download | bcm43752-47862f36f0e112059a71554499e82e93ee8952ad.tar.gz | |
pcie: In-band device wake
Enable the new feature "In-band device wake" to avoid the latency caused
by deep sleep of wifi chip. We also need to enable this in wifi
firmware.
Also include the debug check for latency of PCIe read.
Bug: 155212501
Test: Android 10 + Hikey960 + BCM43752 PCIe
Change-Id: Ia7a63059ced37e40ae2fc610170812ad1ae58589
Signed-off-by: Ahmed ElArabawy <arabawy@google.com>
| -rwxr-xr-x | Kbuild | 5 | ||||
| -rw-r--r-- | dhd_msgbuf.c | 18 |
2 files changed, 22 insertions, 1 deletions
@@ -134,7 +134,10 @@ DHDCFLAGS += -DDHD_TRACE_WAKE_LOCK DHDCFLAGS += -DDHD_SBN # Enable inband device wake feature -#DHDCFLAGS += -DPCIE_INB_DW +DHDCFLAGS += -DPCIE_INB_DW + +# Debug check for PCIe read latency +#DHDCFLAGS += -DDBG_DW_CHK_PCIE_READ_LATENCY # Hikey sched is not so optimized and hence need a higher timeout DHDCFLAGS += -DWAIT_FOR_DISCONNECT_MAX=20 diff --git a/dhd_msgbuf.c b/dhd_msgbuf.c index 51fa875..71bf334 100644 --- a/dhd_msgbuf.c +++ b/dhd_msgbuf.c @@ -8149,6 +8149,11 @@ dhd_fillup_ioct_reqst(dhd_pub_t *dhd, uint16 len, uint cmd, void* buf, int ifidx unsigned long flags; uint16 alloced = 0; msgbuf_ring_t *ring = &prot->h2dring_ctrl_subn; +#ifdef DBG_DW_CHK_PCIE_READ_LATENCY + ulong addr = dhd->bus->ring_sh[ring->idx].ring_state_r; + ktime_t begin_time, end_time; + s64 diff_ns; +#endif /* DBG_DW_CHK_PCIE_READ_LATENCY */ if (dhd_query_bus_erros(dhd)) { return -EIO; @@ -8166,6 +8171,19 @@ dhd_fillup_ioct_reqst(dhd_pub_t *dhd, uint16 len, uint cmd, void* buf, int ifidx #ifdef PCIE_INB_DW if (dhd_prot_inc_hostactive_devwake_assert(dhd->bus) != BCME_OK) return BCME_ERROR; + +#ifdef DBG_DW_CHK_PCIE_READ_LATENCY + preempt_disable(); + begin_time = ktime_get(); + R_REG(dhd->osh, (volatile uint16 *)(dhd->bus->tcm + addr)); + end_time = ktime_get(); + preempt_enable(); + diff_ns = ktime_to_ns(ktime_sub(end_time, begin_time)); + if (diff_ns > 1000000) { // 1ms = 1000000ns + DHD_ERROR(("%s: found latency over 1ms (%lld ns), ds state=%d\n", __func__, + diff_ns, dhdpcie_bus_get_pcie_inband_dw_state(dhd->bus))); + } +#endif /* DBG_DW_CHK_PCIE_READ_LATENCY */ #endif /* PCIE_INB_DW */ DHD_RING_LOCK(ring->ring_lock, flags); |