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| author | Cedar Li <tingyingli@google.com> | 2023-03-21 06:35:05 +0000 |
|---|---|---|
| committer | Cedar Li <tingyingli@google.com> | 2023-04-27 08:20:15 +0000 |
| commit | 66720be64b84034b2e5bc8e5efce7271ac266c2a (patch) | |
| tree | 984ad5d882a6a27adcf0aae5dead5768da45bba4 | |
| parent | 11631539457ccb74ce762a96e15a57d9017ff11f (diff) | |
| download | msm-66720be64b84034b2e5bc8e5efce7271ac266c2a.tar.gz | |
dts: add sdhc3 node for sw5100
Create a dtsi file for adding the sdhc3 node on sw5100.
Bug: 274023865
Change-Id: I9d945ec571be46f1e9e1da0869ba4c8a47b38578
Signed-off-by: Cedar Li <tingyingli@google.com>
| -rw-r--r-- | dts/google/sw5100-sdhc.dtsi | 50 | ||||
| -rw-r--r-- | dts/google/sw5100.dtsi | 1 |
2 files changed, 51 insertions, 0 deletions
diff --git a/dts/google/sw5100-sdhc.dtsi b/dts/google/sw5100-sdhc.dtsi new file mode 100644 index 0000000..33cce61 --- /dev/null +++ b/dts/google/sw5100-sdhc.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Google SDHC3 device tree source + +#include <dt-bindings/clock/qcom,gcc-monaco.h> +#include <dt-bindings/interconnect/qcom,monaco.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +&soc { + sdhc_3: sdhci@4784000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x04784000 0x1000>; + reg-names = "hc_mem"; + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; + clock-names = "core", "iface"; + interconnects = <&system_noc MASTER_SDCC_2 &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + qcom,msm-bus,name = "sdhc3"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No Vote */ + <0 0>, <0 0>, + /* 400 KB/s*/ + <1046 3200>, <1600 1600>, + /* 25 MB/s */ + <65360 250000>, <100000 133320>, + /* 50 MB/s */ + <130718 250000>, <133320 133320>, + /* 100 MB/s */ + <261438 250000>, <150000 133320>, + /* 200 MB/s */ + <261438 800000>, <300000 300000>, + /* Max. bandwidth */ + <1338562 4096000>, <1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000 + 100000000 200000000 4294967295>; + /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x0 0x00010800 0x80040868>; + bus-width = <4>; + iommus = <&apps_smmu 0xA0 0x0>; + qcom,iommu-dma = "bypass"; + qcom,devfreq,freq-table = <400000 20000000 25000000 50000000 100000000>; + status = "disabled"; + }; +}; diff --git a/dts/google/sw5100.dtsi b/dts/google/sw5100.dtsi index da32deb..d5e07aa 100644 --- a/dts/google/sw5100.dtsi +++ b/dts/google/sw5100.dtsi @@ -11,6 +11,7 @@ #include "sw5100-i2s.dtsi" #include "sw5100-pinctrl.dtsi" #include "sw5100-qupv3.dtsi" +#include "sw5100-sdhc.dtsi" &firmware { /delete-node/ android; |