diff options
35 files changed, 655 insertions, 170 deletions
diff --git a/Documentation/ABI/testing/sysfs-devices-virtual-mitigation b/Documentation/ABI/testing/sysfs-devices-virtual-mitigation index e8261e81d..7148ad30f 100644 --- a/Documentation/ABI/testing/sysfs-devices-virtual-mitigation +++ b/Documentation/ABI/testing/sysfs-devices-virtual-mitigation @@ -102,6 +102,13 @@ Description: The reported value indicates if brownout mitigation is enabled. 1 means enabled; 0 means disabled. +What: /sys/devices/virtual/pmic/mitigation/instruction/enable_rffe_mitigation +Date: Mar, 2024 +Contact: "Hiroshi Akiyama" <hiroshiakiyama@google.com> +Description: + Enable rffe peak power && BATOILO triggered modem crash. + 1 means enabled; 0 means disabled. + What: /sys/devices/virtual/pmic/mitigation/instruction/pwronsrc Date: May, 2023 Contact: "George Lee" <geolee@google.com> diff --git a/arch/arm64/boot/dts/google/zuma-isp-event-info.dtsi b/arch/arm64/boot/dts/google/zuma-isp-event-info.dtsi index 25d1fc1a6..9f84fd00b 100644 --- a/arch/arm64/boot/dts/google/zuma-isp-event-info.dtsi +++ b/arch/arm64/boot/dts/google/zuma-isp-event-info.dtsi @@ -4104,6 +4104,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_ERR_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_ERR_CRC_PH>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_ERR_SKEW>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_ERR_DESKEW_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE2>, @@ -4115,7 +4117,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE2>, - <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE3>; + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_PHY_TIMING_ERR>; int-reg-bits = <ISP_FE_CSIS_INT0_CTX0_ERR_ID>, <ISP_FE_CSIS_INT0_CTX0_ERR_CRC>, @@ -4124,6 +4127,8 @@ <ISP_FE_CSIS_INT0_CTX0_ERR_OVER>, <ISP_FE_CSIS_INT0_CTX0_ERR_CRC_PH>, <ISP_FE_CSIS_INT0_CTX0_MAL_CRC>, + <ISP_FE_CSIS_INT0_CTX0_ERR_SKEW>, + <ISP_FE_CSIS_INT0_CTX0_ERR_DESKEW_OVER>, <ISP_FE_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE2>, @@ -4135,7 +4140,8 @@ <ISP_FE_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE2>, - <ISP_FE_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE3>; + <ISP_FE_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE3>, + <ISP_FE_CSIS_INT0_CTX0_PHY_TIMING_ERR>; }; isp_fe_ctx1_csis_int0: isp_fe-event-info@155 { irq-reg-space = "csis-link-phy"; @@ -4151,6 +4157,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_ERR_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_ERR_CRC_PH>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_ERR_SKEW>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_ERR_DESKEW_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE2>, @@ -4162,7 +4170,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE2>, - <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE3>; + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_PHY_TIMING_ERR>; int-reg-bits = <ISP_FE_CSIS_INT0_CTX1_ERR_ID>, <ISP_FE_CSIS_INT0_CTX1_ERR_CRC>, @@ -4171,6 +4180,8 @@ <ISP_FE_CSIS_INT0_CTX1_ERR_OVER>, <ISP_FE_CSIS_INT0_CTX1_ERR_CRC_PH>, <ISP_FE_CSIS_INT0_CTX1_MAL_CRC>, + <ISP_FE_CSIS_INT0_CTX1_ERR_SKEW>, + <ISP_FE_CSIS_INT0_CTX1_ERR_DESKEW_OVER>, <ISP_FE_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE2>, @@ -4182,7 +4193,8 @@ <ISP_FE_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE2>, - <ISP_FE_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE3>; + <ISP_FE_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE3>, + <ISP_FE_CSIS_INT0_CTX1_PHY_TIMING_ERR>; }; isp_fe_ctx2_csis_int0: isp_fe-event-info@156 { irq-reg-space = "csis-link-phy"; @@ -4198,6 +4210,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_ERR_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_ERR_CRC_PH>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_ERR_SKEW>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_ERR_DESKEW_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE2>, @@ -4209,7 +4223,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE2>, - <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE3>; + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_PHY_TIMING_ERR>; int-reg-bits = <ISP_FE_CSIS_INT0_CTX2_ERR_ID>, <ISP_FE_CSIS_INT0_CTX2_ERR_CRC>, @@ -4218,6 +4233,8 @@ <ISP_FE_CSIS_INT0_CTX2_ERR_OVER>, <ISP_FE_CSIS_INT0_CTX2_ERR_CRC_PH>, <ISP_FE_CSIS_INT0_CTX2_MAL_CRC>, + <ISP_FE_CSIS_INT0_CTX2_ERR_SKEW>, + <ISP_FE_CSIS_INT0_CTX2_ERR_DESKEW_OVER>, <ISP_FE_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE2>, @@ -4229,7 +4246,8 @@ <ISP_FE_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE2>, - <ISP_FE_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE3>; + <ISP_FE_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE3>, + <ISP_FE_CSIS_INT0_CTX2_PHY_TIMING_ERR>; }; isp_fe_ctx3_csis_int0: isp_fe-event-info@157 { irq-reg-space = "csis-link-phy"; @@ -4245,6 +4263,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_ERR_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_ERR_CRC_PH>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_ERR_SKEW>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_ERR_DESKEW_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE2>, @@ -4256,7 +4276,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE2>, - <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE3>; + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_PHY_TIMING_ERR>; int-reg-bits = <ISP_FE_CSIS_INT0_CTX3_ERR_ID>, <ISP_FE_CSIS_INT0_CTX3_ERR_CRC>, @@ -4265,6 +4286,8 @@ <ISP_FE_CSIS_INT0_CTX3_ERR_OVER>, <ISP_FE_CSIS_INT0_CTX3_ERR_CRC_PH>, <ISP_FE_CSIS_INT0_CTX3_MAL_CRC>, + <ISP_FE_CSIS_INT0_CTX3_ERR_SKEW>, + <ISP_FE_CSIS_INT0_CTX3_ERR_DESKEW_OVER>, <ISP_FE_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE2>, @@ -4276,7 +4299,8 @@ <ISP_FE_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE2>, - <ISP_FE_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE3>; + <ISP_FE_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE3>, + <ISP_FE_CSIS_INT0_CTX3_PHY_TIMING_ERR>; }; isp_fe_ctx4_csis_int0: isp_fe-event-info@158 { irq-reg-space = "csis-link-phy"; @@ -4292,6 +4316,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_ERR_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_ERR_CRC_PH>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_ERR_SKEW>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_ERR_DESKEW_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE2>, @@ -4303,7 +4329,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE2>, - <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE3>; + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_PHY_TIMING_ERR>; int-reg-bits = <ISP_FE_CSIS_INT0_CTX4_ERR_ID>, <ISP_FE_CSIS_INT0_CTX4_ERR_CRC>, @@ -4312,6 +4339,8 @@ <ISP_FE_CSIS_INT0_CTX4_ERR_OVER>, <ISP_FE_CSIS_INT0_CTX4_ERR_CRC_PH>, <ISP_FE_CSIS_INT0_CTX4_MAL_CRC>, + <ISP_FE_CSIS_INT0_CTX4_ERR_SKEW>, + <ISP_FE_CSIS_INT0_CTX4_ERR_DESKEW_OVER>, <ISP_FE_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE2>, @@ -4323,7 +4352,8 @@ <ISP_FE_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE2>, - <ISP_FE_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE3>; + <ISP_FE_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE3>, + <ISP_FE_CSIS_INT0_CTX4_PHY_TIMING_ERR>; }; isp_fe_ctx5_csis_int0: isp_fe-event-info@159 { irq-reg-space = "csis-link-phy"; @@ -4339,6 +4369,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_ERR_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_ERR_CRC_PH>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_ERR_SKEW>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_ERR_DESKEW_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE2>, @@ -4350,7 +4382,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE2>, - <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE3>; + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_PHY_TIMING_ERR>; int-reg-bits = <ISP_FE_CSIS_INT0_CTX5_ERR_ID>, <ISP_FE_CSIS_INT0_CTX5_ERR_CRC>, @@ -4359,6 +4392,8 @@ <ISP_FE_CSIS_INT0_CTX5_ERR_OVER>, <ISP_FE_CSIS_INT0_CTX5_ERR_CRC_PH>, <ISP_FE_CSIS_INT0_CTX5_MAL_CRC>, + <ISP_FE_CSIS_INT0_CTX5_ERR_SKEW>, + <ISP_FE_CSIS_INT0_CTX5_ERR_DESKEW_OVER>, <ISP_FE_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE2>, @@ -4370,7 +4405,8 @@ <ISP_FE_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE2>, - <ISP_FE_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE3>; + <ISP_FE_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE3>, + <ISP_FE_CSIS_INT0_CTX5_PHY_TIMING_ERR>; }; isp_fe_ctx6_csis_int0: isp_fe-event-info@160 { irq-reg-space = "csis-link-phy"; @@ -4386,6 +4422,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_ERR_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_ERR_CRC_PH>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_ERR_SKEW>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_ERR_DESKEW_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE2>, @@ -4397,7 +4435,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE2>, - <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE3>; + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_PHY_TIMING_ERR>; int-reg-bits = <ISP_FE_CSIS_INT0_CTX6_ERR_ID>, <ISP_FE_CSIS_INT0_CTX6_ERR_CRC>, @@ -4406,6 +4445,8 @@ <ISP_FE_CSIS_INT0_CTX6_ERR_OVER>, <ISP_FE_CSIS_INT0_CTX6_ERR_CRC_PH>, <ISP_FE_CSIS_INT0_CTX6_MAL_CRC>, + <ISP_FE_CSIS_INT0_CTX6_ERR_SKEW>, + <ISP_FE_CSIS_INT0_CTX6_ERR_DESKEW_OVER>, <ISP_FE_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE2>, @@ -4417,7 +4458,8 @@ <ISP_FE_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE2>, - <ISP_FE_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE3>; + <ISP_FE_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE3>, + <ISP_FE_CSIS_INT0_CTX6_PHY_TIMING_ERR>; }; isp_fe_ctx7_csis_int0: isp_fe-event-info@161 { irq-reg-space = "csis-link-phy"; @@ -4433,6 +4475,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_ERR_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_ERR_CRC_PH>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_ERR_SKEW>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_ERR_DESKEW_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE2>, @@ -4444,7 +4488,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE2>, - <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE3>; + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_PHY_TIMING_ERR>; int-reg-bits = <ISP_FE_CSIS_INT0_CTX7_ERR_ID>, <ISP_FE_CSIS_INT0_CTX7_ERR_CRC>, @@ -4453,6 +4498,8 @@ <ISP_FE_CSIS_INT0_CTX7_ERR_OVER>, <ISP_FE_CSIS_INT0_CTX7_ERR_CRC_PH>, <ISP_FE_CSIS_INT0_CTX7_MAL_CRC>, + <ISP_FE_CSIS_INT0_CTX7_ERR_SKEW>, + <ISP_FE_CSIS_INT0_CTX7_ERR_DESKEW_OVER>, <ISP_FE_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE2>, @@ -4464,7 +4511,8 @@ <ISP_FE_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE2>, - <ISP_FE_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE3>; + <ISP_FE_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE3>, + <ISP_FE_CSIS_INT0_CTX7_PHY_TIMING_ERR>; }; isp_fe_ctx8_csis_int0: isp_fe-event-info@162 { irq-reg-space = "csis-link-phy"; @@ -4480,6 +4528,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_ERR_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_ERR_CRC_PH>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_ERR_SKEW>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_ERR_DESKEW_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_RX_INVALID_CODE_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_RX_INVALID_CODE_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_RX_INVALID_CODE_HS_LANE2>, @@ -4491,7 +4541,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_ERR_SOT_SYNC_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_ERR_SOT_SYNC_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_ERR_SOT_SYNC_HS_LANE2>, - <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_ERR_SOT_SYNC_HS_LANE3>; + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_ERR_SOT_SYNC_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_PHY_TIMING_ERR>; int-reg-bits = <ISP_FE_CSIS_INT0_CTX8_ERR_ID>, <ISP_FE_CSIS_INT0_CTX8_ERR_CRC>, @@ -4500,6 +4551,8 @@ <ISP_FE_CSIS_INT0_CTX8_ERR_OVER>, <ISP_FE_CSIS_INT0_CTX8_ERR_CRC_PH>, <ISP_FE_CSIS_INT0_CTX8_MAL_CRC>, + <ISP_FE_CSIS_INT0_CTX8_ERR_SKEW>, + <ISP_FE_CSIS_INT0_CTX8_ERR_DESKEW_OVER>, <ISP_FE_CSIS_INT0_CTX8_RX_INVALID_CODE_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX8_RX_INVALID_CODE_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX8_RX_INVALID_CODE_HS_LANE2>, @@ -4511,7 +4564,8 @@ <ISP_FE_CSIS_INT0_CTX8_ERR_SOT_SYNC_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX8_ERR_SOT_SYNC_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX8_ERR_SOT_SYNC_HS_LANE2>, - <ISP_FE_CSIS_INT0_CTX8_ERR_SOT_SYNC_HS_LANE3>; + <ISP_FE_CSIS_INT0_CTX8_ERR_SOT_SYNC_HS_LANE3>, + <ISP_FE_CSIS_INT0_CTX8_PHY_TIMING_ERR>; }; isp_fe_ctx9_csis_int0: isp_fe-event-info@163 { irq-reg-space = "csis-link-phy"; @@ -4527,6 +4581,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_ERR_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_ERR_CRC_PH>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_ERR_SKEW>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_ERR_DESKEW_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_RX_INVALID_CODE_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_RX_INVALID_CODE_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_RX_INVALID_CODE_HS_LANE2>, @@ -4538,7 +4594,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_ERR_SOT_SYNC_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_ERR_SOT_SYNC_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_ERR_SOT_SYNC_HS_LANE2>, - <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_ERR_SOT_SYNC_HS_LANE3>; + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_ERR_SOT_SYNC_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_PHY_TIMING_ERR>; int-reg-bits = <ISP_FE_CSIS_INT0_CTX9_ERR_ID>, <ISP_FE_CSIS_INT0_CTX9_ERR_CRC>, @@ -4547,6 +4604,8 @@ <ISP_FE_CSIS_INT0_CTX9_ERR_OVER>, <ISP_FE_CSIS_INT0_CTX9_ERR_CRC_PH>, <ISP_FE_CSIS_INT0_CTX9_MAL_CRC>, + <ISP_FE_CSIS_INT0_CTX9_ERR_SKEW>, + <ISP_FE_CSIS_INT0_CTX9_ERR_DESKEW_OVER>, <ISP_FE_CSIS_INT0_CTX9_RX_INVALID_CODE_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX9_RX_INVALID_CODE_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX9_RX_INVALID_CODE_HS_LANE2>, @@ -4558,7 +4617,8 @@ <ISP_FE_CSIS_INT0_CTX9_ERR_SOT_SYNC_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX9_ERR_SOT_SYNC_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX9_ERR_SOT_SYNC_HS_LANE2>, - <ISP_FE_CSIS_INT0_CTX9_ERR_SOT_SYNC_HS_LANE3>; + <ISP_FE_CSIS_INT0_CTX9_ERR_SOT_SYNC_HS_LANE3>, + <ISP_FE_CSIS_INT0_CTX9_PHY_TIMING_ERR>; }; isp_fe_ctx10_csis_int0: isp_fe-event-info@164 { irq-reg-space = "csis-link-phy"; @@ -4574,6 +4634,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_ERR_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_ERR_CRC_PH>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_ERR_SKEW>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_ERR_DESKEW_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_RX_INVALID_CODE_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_RX_INVALID_CODE_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_RX_INVALID_CODE_HS_LANE2>, @@ -4585,7 +4647,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_ERR_SOT_SYNC_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_ERR_SOT_SYNC_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_ERR_SOT_SYNC_HS_LANE2>, - <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_ERR_SOT_SYNC_HS_LANE3>; + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_ERR_SOT_SYNC_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_PHY_TIMING_ERR>; int-reg-bits = <ISP_FE_CSIS_INT0_CTX10_ERR_ID>, <ISP_FE_CSIS_INT0_CTX10_ERR_CRC>, @@ -4594,6 +4657,8 @@ <ISP_FE_CSIS_INT0_CTX10_ERR_OVER>, <ISP_FE_CSIS_INT0_CTX10_ERR_CRC_PH>, <ISP_FE_CSIS_INT0_CTX10_MAL_CRC>, + <ISP_FE_CSIS_INT0_CTX10_ERR_SKEW>, + <ISP_FE_CSIS_INT0_CTX10_ERR_DESKEW_OVER>, <ISP_FE_CSIS_INT0_CTX10_RX_INVALID_CODE_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX10_RX_INVALID_CODE_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX10_RX_INVALID_CODE_HS_LANE2>, @@ -4605,7 +4670,8 @@ <ISP_FE_CSIS_INT0_CTX10_ERR_SOT_SYNC_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX10_ERR_SOT_SYNC_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX10_ERR_SOT_SYNC_HS_LANE2>, - <ISP_FE_CSIS_INT0_CTX10_ERR_SOT_SYNC_HS_LANE3>; + <ISP_FE_CSIS_INT0_CTX10_ERR_SOT_SYNC_HS_LANE3>, + <ISP_FE_CSIS_INT0_CTX10_PHY_TIMING_ERR>; }; isp_fe_ctx11_csis_int0: isp_fe-event-info@165 { irq-reg-space = "csis-link-phy"; @@ -4621,6 +4687,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_ERR_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_ERR_CRC_PH>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_MAL_CRC>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_ERR_SKEW>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_ERR_DESKEW_OVER>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_RX_INVALID_CODE_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_RX_INVALID_CODE_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_RX_INVALID_CODE_HS_LANE2>, @@ -4632,7 +4700,8 @@ <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_ERR_SOT_SYNC_HS_LANE0>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_ERR_SOT_SYNC_HS_LANE1>, <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_ERR_SOT_SYNC_HS_LANE2>, - <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_ERR_SOT_SYNC_HS_LANE3>; + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_ERR_SOT_SYNC_HS_LANE3>, + <LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_PHY_TIMING_ERR>; int-reg-bits = <ISP_FE_CSIS_INT0_CTX11_ERR_ID>, <ISP_FE_CSIS_INT0_CTX11_ERR_CRC>, @@ -4641,6 +4710,8 @@ <ISP_FE_CSIS_INT0_CTX11_ERR_OVER>, <ISP_FE_CSIS_INT0_CTX11_ERR_CRC_PH>, <ISP_FE_CSIS_INT0_CTX11_MAL_CRC>, + <ISP_FE_CSIS_INT0_CTX11_ERR_SKEW>, + <ISP_FE_CSIS_INT0_CTX11_ERR_DESKEW_OVER>, <ISP_FE_CSIS_INT0_CTX11_RX_INVALID_CODE_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX11_RX_INVALID_CODE_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX11_RX_INVALID_CODE_HS_LANE2>, @@ -4652,7 +4723,8 @@ <ISP_FE_CSIS_INT0_CTX11_ERR_SOT_SYNC_HS_LANE0>, <ISP_FE_CSIS_INT0_CTX11_ERR_SOT_SYNC_HS_LANE1>, <ISP_FE_CSIS_INT0_CTX11_ERR_SOT_SYNC_HS_LANE2>, - <ISP_FE_CSIS_INT0_CTX11_ERR_SOT_SYNC_HS_LANE3>; + <ISP_FE_CSIS_INT0_CTX11_ERR_SOT_SYNC_HS_LANE3>, + <ISP_FE_CSIS_INT0_CTX11_PHY_TIMING_ERR>; }; isp_fe_ctx0_csis_int1: isp_fe-event-info@166 { diff --git a/arch/arm64/boot/dts/google/zuma-rmem.dtsi b/arch/arm64/boot/dts/google/zuma-rmem.dtsi index 9bf1e931e..9e5f46fa6 100644 --- a/arch/arm64/boot/dts/google/zuma-rmem.dtsi +++ b/arch/arm64/boot/dts/google/zuma-rmem.dtsi @@ -26,7 +26,7 @@ ect_binary: ect_binary { compatible = "exynos,ect_rmem"; - reg = <0x0 0x90000000 0x0003A000>; + reg = <0x0 0x90000000 0x00060000>; }; gsa_reserved_protected: gsa@0x90200000 { diff --git a/arch/arm64/boot/dts/google/zuma-usi.dtsi b/arch/arm64/boot/dts/google/zuma-usi.dtsi index 21b78491a..64e99e1d8 100644 --- a/arch/arm64/boot/dts/google/zuma-usi.dtsi +++ b/arch/arm64/boot/dts/google/zuma-usi.dtsi @@ -273,8 +273,9 @@ samsung,scl-clk-stretching; samsung,usi-i2c-v2; interrupts = <GIC_SPI IRQ_USI11_USI_PERIC1 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; + pinctrl-names = "default", "recovery"; pinctrl-0 = <&hsi2c11_bus>; + pinctrl-1 = <>; clocks = <&clock VDOUT_CLK_PERIC1_USI11_USI>, <&clock GATE_PERIC1_TOP0_USI11_USI>; clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; gpio_scl= <&gpp21 0 0x1>; diff --git a/arch/arm64/boot/dts/google/zuma.dtsi b/arch/arm64/boot/dts/google/zuma.dtsi index f74479dfe..29239af1f 100644 --- a/arch/arm64/boot/dts/google/zuma.dtsi +++ b/arch/arm64/boot/dts/google/zuma.dtsi @@ -86,7 +86,7 @@ }; chosen: chosen { - bootargs = "earlycon=exynos4210,mmio32,0x10870000 console=ttySAC0,115200n8 root=/dev/ram0 rw clocksource=arch_sys_counter androidboot.hardware=zuma androidboot.hardware.platform=zuma androidboot.debug_level=0x4948 clk_ignore_unused loop.max_part=7 loop.hw_queue_depth=31 coherent_pool=4M firmware_class.path=/vendor/firmware irqaffinity=0 swiotlb=noforce androidboot.slot_suffix=_a androidboot.secure_boot=NONE sysrq_always_enabled no_console_suspend softlockup_panic=1 kasan_multi_shot kvm-arm.protected_modules=exynos-pd,pkvm_s2mpu-v9"; + bootargs = "earlycon=exynos4210,mmio32,0x10870000 console=ttySAC0,115200n8 root=/dev/ram0 rw clocksource=arch_sys_counter androidboot.hardware=zuma androidboot.hardware.platform=zuma androidboot.debug_level=0x4948 clk_ignore_unused loop.max_part=7 loop.hw_queue_depth=31 coherent_pool=4M firmware_class.path=/vendor/firmware irqaffinity=0 swiotlb=noforce androidboot.slot_suffix=_a androidboot.secure_boot=NONE no_console_suspend softlockup_panic=1 kasan_multi_shot kvm-arm.protected_modules=exynos-pd,pkvm_s2mpu-v9"; }; odm: odm { diff --git a/device.bazelrc b/device.bazelrc index 88eac38c1..23c79995f 100644 --- a/device.bazelrc +++ b/device.bazelrc @@ -34,8 +34,8 @@ build:use_source_tree_aosp --//private/google-modules/soc/gs:gki_kernel_dir=aosp build:use_source_tree_aosp_staging --//private/google-modules/soc/gs:gki_kernel_dir=aosp-staging build:download_gki --use_prebuilt_gki -build:download_gki --use_signed_prebuilts -build:download_gki --action_env=KLEAF_DOWNLOAD_BUILD_NUMBER_MAP="gki_prebuilts=11490254" +#build:download_gki --use_signed_prebuilts +build:download_gki --action_env=KLEAF_DOWNLOAD_BUILD_NUMBER_MAP="gki_prebuilts=11649327" build:no_download_gki --use_prebuilt_gki=false # enable Pixel Staging Kernel (go/pixel-staging) by default diff --git a/drivers/devfreq/google/arm-memlat-mon.c b/drivers/devfreq/google/arm-memlat-mon.c index 9032c1c6d..820e2858a 100644 --- a/drivers/devfreq/google/arm-memlat-mon.c +++ b/drivers/devfreq/google/arm-memlat-mon.c @@ -204,10 +204,10 @@ static void read_pmu_counters(struct memlat_cpu_grp *cpu_grp) for (i = 0; i < NUM_COMMON_EVS; i++) read_event(&pmu_evs[i]); - if (cpu_grp->pmu_ev_ids[INST_IDX] != UINT_MAX) - cpu_data->cyc = pmu_evs[INST_IDX].last_delta; if (cpu_grp->pmu_ev_ids[CYCLE_IDX] != UINT_MAX) - cpu_data->inst = pmu_evs[CYCLE_IDX].last_delta; + cpu_data->cyc = pmu_evs[CYCLE_IDX].last_delta; + if (cpu_grp->pmu_ev_ids[INST_IDX] != UINT_MAX) + cpu_data->inst = pmu_evs[INST_IDX].last_delta; if (cpu_grp->pmu_ev_ids[STALL_BACKEND_MEM_IDX] != UINT_MAX) cpu_data->mem_stall = pmu_evs[STALL_BACKEND_MEM_IDX].last_delta; if (cpu_grp->pmu_ev_ids[STALL_IDX] != UINT_MAX) diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c index 198c2e818..51eeb4cb3 100644 --- a/drivers/i2c/busses/i2c-exynos5.c +++ b/drivers/i2c/busses/i2c-exynos5.c @@ -232,28 +232,32 @@ static const struct of_device_id exynos5_i2c_match[] = { MODULE_DEVICE_TABLE(of, exynos5_i2c_match); #ifdef CONFIG_GPIOLIB -static void change_i2c_gpio(struct exynos5_i2c *i2c) +static int change_i2c_pinctrl_state(struct exynos5_i2c *i2c, const char *state) { - struct pinctrl_state *default_i2c_pins; + struct pinctrl_state *i2c_pinctrl_state; struct pinctrl *default_i2c_pinctrl; int status = 0; default_i2c_pinctrl = devm_pinctrl_get(i2c->dev); if (IS_ERR(default_i2c_pinctrl)) { dev_err(i2c->dev, "Can't get i2c pinctrl!!!\n"); - return; + return -1; } - default_i2c_pins = pinctrl_lookup_state(default_i2c_pinctrl, - "default"); - if (!IS_ERR(default_i2c_pins)) { + i2c_pinctrl_state = pinctrl_lookup_state(default_i2c_pinctrl, + state); + if (!IS_ERR(i2c_pinctrl_state)) { status = pinctrl_select_state(default_i2c_pinctrl, - default_i2c_pins); - if (status) - dev_err(i2c->dev, "Can't set default i2c pins!!!\n"); + i2c_pinctrl_state); + if (status) { + dev_err(i2c->dev, "Can't set i2c pins to state %s!!!\n", state); + return -1; + } } else { - dev_err(i2c->dev, "Can't get default pinstate!!!\n"); + dev_err(i2c->dev, "Can't get %s pinstate!!!\n", state); + return -1; } + return 0; } static void recover_gpio_pins(struct exynos5_i2c *i2c) @@ -302,26 +306,30 @@ static void recover_gpio_pins(struct exynos5_i2c *i2c) sda_val = gpio_get_value(gpio_sda); if (sda_val == 0) { - gpio_direction_output(gpio_scl, 1); - gpio_direction_input(gpio_sda); + if (!change_i2c_pinctrl_state(i2c, "recovery")) { + gpio_direction_output(gpio_scl, 1); + gpio_direction_input(gpio_sda); - for (clk_cnt = 0; clk_cnt < 100; clk_cnt++) { + for (clk_cnt = 0; clk_cnt < 100; clk_cnt++) { /* Make clock for slave */ - gpio_set_value(gpio_scl, 0); - udelay(5); - gpio_set_value(gpio_scl, 1); - udelay(5); - if (gpio_get_value(gpio_sda) == 1) { - dev_err(i2c->dev, "SDA line is recovered.\n"); - break; + gpio_set_value(gpio_scl, 0); + udelay(5); + gpio_set_value(gpio_scl, 1); + udelay(5); + if (gpio_get_value(gpio_sda) == 1) { + dev_err(i2c->dev, "SDA line is recovered.\n"); + break; + } } + if (clk_cnt == 100) + dev_err(i2c->dev, "SDA line is not recovered!!!\n"); + } else { + dev_err(i2c->dev, "Recovery state doesn't exist, skip recovery!!!\n"); } - if (clk_cnt == 100) - dev_err(i2c->dev, "SDA line is not recovered!!!\n"); } /* Change I2C GPIO as default function */ - change_i2c_gpio(i2c); + change_i2c_pinctrl_state(i2c, "default"); } #endif @@ -718,11 +726,12 @@ static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id) */ if (reg_val & HSI2C_INT_CHK_TRANS_STATE) { trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); - dev_err(i2c->dev, "HSI2C Error Interrupt occurred(IS:0x%08x, TR:0x%08x)\n", - (unsigned int)reg_val, (unsigned int)trans_status); + dev_err(i2c->dev, "HSI2C Error Interrupt occurred(IS:0x%08x, TR:0x%08x) for %#x\n", + (unsigned int)reg_val, (unsigned int)trans_status, (i2c->msg->addr & 0x7f)); if (reg_val & HSI2C_INT_NODEV) { - dev_err(i2c->dev, "HSI2C NO ACK occurred\n"); + dev_err(i2c->dev, "HSI2C NO ACK occurred for %#x\n", + (i2c->msg->addr & 0x7f)); if (i2c->nack_restart) { if (reg_val & HSI2C_INT_TRANSFER_DONE) exynos5_i2c_stop(i2c); diff --git a/drivers/iommu/samsung-iommu-fault-v9.c b/drivers/iommu/samsung-iommu-fault-v9.c index 24bbaa802..34a6d9c41 100644 --- a/drivers/iommu/samsung-iommu-fault-v9.c +++ b/drivers/iommu/samsung-iommu-fault-v9.c @@ -550,7 +550,7 @@ static void sysmmu_show_secure_fault_information(struct sysmmu_drvdata *drvdata, char err_msg[128]; pgtable = read_sec_info(MMU_VM_ADDR(sfrbase + REG_MMU_CONTEXT0_CFG_FLPT_BASE_VM, vmid)); - pgtable <<= PAGE_SHIFT; + pgtable <<= PT_BASE_SHIFT; info0 = read_sec_info(MMU_VM_ADDR(sfrbase + REG_MMU_FAULT_INFO0_VM, vmid)); info1 = read_sec_info(MMU_VM_ADDR(sfrbase + REG_MMU_FAULT_INFO1_VM, vmid)); @@ -579,7 +579,7 @@ static void sysmmu_show_secure_fault_information(struct sysmmu_drvdata *drvdata, MMU_FAULT_INFO1_AXID(info1), MMU_FAULT_INFO2_PMMU_ID(info2), MMU_FAULT_INFO2_STREAM_ID(info2)); - if (!pfn_valid(pgtable >> PAGE_SHIFT)) { + if (!pfn_valid(PFN_DOWN(pgtable))) { pr_crit("Page table base is not in a valid memory region\n"); pgtable = 0; } @@ -611,7 +611,7 @@ static void sysmmu_show_fault_info_simple(struct sysmmu_drvdata *drvdata, int in pgtable = readl_relaxed(MMU_VM_ADDR(drvdata->sfrbase + REG_MMU_CONTEXT0_CFG_FLPT_BASE_VM, vmid)); - pgtable <<= PAGE_SHIFT; + pgtable <<= PT_BASE_SHIFT; sysmmu_get_fault_msg(drvdata, intr_type, vmid, fault_addr, false, err_msg, sizeof(err_msg)); @@ -630,7 +630,7 @@ static void sysmmu_show_fault_information(struct sysmmu_drvdata *drvdata, int in for (i = 0; i < MAX_VIDS; i++) { pgtable[i] = readl_relaxed(MMU_VM_ADDR(drvdata->sfrbase + REG_MMU_CONTEXT0_CFG_FLPT_BASE_VM, i)); - pgtable[i] <<= PAGE_SHIFT; + pgtable[i] <<= PT_BASE_SHIFT; } pr_crit("----------------------------------------------------------\n"); @@ -657,7 +657,7 @@ static void sysmmu_show_fault_information(struct sysmmu_drvdata *drvdata, int in if (pgtable[vmid] != drvdata->pgtable[vmid]) pr_crit("Page table base of driver: %p\n", &drvdata->pgtable[vmid]); - if (!pfn_valid(pgtable[vmid] >> PAGE_SHIFT)) { + if (!pfn_valid(PFN_DOWN(pgtable[vmid]))) { pr_crit("Page table base is not in a valid memory region\n"); pgtable[vmid] = 0; } else { diff --git a/drivers/iommu/samsung-iommu-fault.c b/drivers/iommu/samsung-iommu-fault.c index 2a2a17d35..405987223 100644 --- a/drivers/iommu/samsung-iommu-fault.c +++ b/drivers/iommu/samsung-iommu-fault.c @@ -354,7 +354,7 @@ static void sysmmu_show_secure_fault_information(struct sysmmu_drvdata *drvdata, char err_msg[128]; pgtable = read_sec_info(MMU_SEC_REG(drvdata, IDX_SEC_FLPT_BASE)); - pgtable <<= PAGE_SHIFT; + pgtable <<= PT_BASE_SHIFT; info = read_sec_info(MMU_SEC_REG(drvdata, IDX_FAULT_TRANS_INFO)); @@ -372,8 +372,7 @@ static void sysmmu_show_secure_fault_information(struct sysmmu_drvdata *drvdata, } pr_crit("AxID: %#x, AxLEN: %#x\n", info & 0xFFFF, (info >> 16) & 0xF); - - if (!pfn_valid(pgtable >> PAGE_SHIFT)) { + if (!pfn_valid(PFN_DOWN(pgtable))) { pr_crit("Page table base is not in a valid memory region\n"); pgtable = 0; } @@ -422,7 +421,7 @@ static void sysmmu_show_fault_information(struct sysmmu_drvdata *drvdata, for (i = 0; i < __max_vids(drvdata); i++) { pgtable[i] = readl_relaxed(MMU_VM_REG(drvdata, IDX_FLPT_BASE, i)); - pgtable[i] <<= PAGE_SHIFT; + pgtable[i] <<= PT_BASE_SHIFT; } pr_crit("----------------------------------------------------------\n"); @@ -438,7 +437,7 @@ static void sysmmu_show_fault_information(struct sysmmu_drvdata *drvdata, if (pgtable[i] != drvdata->pgtable[i]) pr_crit("Page table (VID %u) base of driver: %pa\n", i, &drvdata->pgtable[i]); - if (pgtable[i] && !pfn_valid(pgtable[i] >> PAGE_SHIFT)) { + if (pgtable[i] && !pfn_valid(PFN_DOWN(pgtable[i]))) { pr_crit("Page table (VID %u) base is not in a valid memory region\n", i); pgtable[i] = 0; } @@ -590,7 +589,7 @@ irqreturn_t samsung_sysmmu_irq_thread(int irq, void *dev_id) phys_addr_t pgtable; pgtable = readl_relaxed(MMU_VM_REG(drvdata, IDX_FLPT_BASE, vid)); - pgtable <<= PAGE_SHIFT; + pgtable <<= PT_BASE_SHIFT; if (!drvdata->hide_page_fault) sysmmu_show_fault_info_simple(drvdata, itype, vid, addr, &pgtable); sysmmu_clear_interrupt(drvdata, false); diff --git a/drivers/iommu/samsung-iommu-v9.c b/drivers/iommu/samsung-iommu-v9.c index 36bbaff12..9d0e99594 100644 --- a/drivers/iommu/samsung-iommu-v9.c +++ b/drivers/iommu/samsung-iommu-v9.c @@ -251,7 +251,7 @@ static inline void __sysmmu_enable_vid(struct sysmmu_drvdata *data, unsigned int { u32 ctrl_val; - writel_relaxed(data->pgtable[vid] / SPAGE_SIZE, + writel_relaxed(data->pgtable[vid] >> PT_BASE_SHIFT, MMU_VM_ADDR(data->sfrbase + REG_MMU_CONTEXT0_CFG_FLPT_BASE_VM, vid)); ctrl_val = readl_relaxed(MMU_VM_ADDR(data->sfrbase + REG_MMU_CTRL_VM, vid)); ctrl_val |= MMU_CTRL_ENABLE; @@ -266,7 +266,7 @@ static inline void __sysmmu_enable(struct sysmmu_drvdata *data) __sysmmu_modify_bits_all_vm(data, MMU_CTRL_ENABLE, MMU_CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL_VM); - __sysmmu_write_all_vm(data, data->pgtable[0] / SPAGE_SIZE, + __sysmmu_write_all_vm(data, data->pgtable[0] >> PT_BASE_SHIFT, data->sfrbase + REG_MMU_CONTEXT0_CFG_FLPT_BASE_VM); __sysmmu_init_config(data); __sysmmu_invalidate_all(data); diff --git a/drivers/iommu/samsung-iommu-v9.h b/drivers/iommu/samsung-iommu-v9.h index 34edb096b..3c3c280da 100644 --- a/drivers/iommu/samsung-iommu-v9.h +++ b/drivers/iommu/samsung-iommu-v9.h @@ -13,6 +13,8 @@ #include <soc/google/debug-snapshot.h> +#define PT_BASE_SHIFT 12 + #define MAX_VIDS 8U #define SYSMMU_VM_OFFSET 0x1000 diff --git a/drivers/iommu/samsung-iommu.c b/drivers/iommu/samsung-iommu.c index fc2f2bcd3..a8105ccc4 100644 --- a/drivers/iommu/samsung-iommu.c +++ b/drivers/iommu/samsung-iommu.c @@ -203,7 +203,7 @@ static inline void __sysmmu_enable_vid(struct sysmmu_drvdata *data, unsigned int { u32 ctrl_val; - writel_relaxed(data->pgtable[vid] / SPAGE_SIZE, MMU_VM_REG(data, IDX_FLPT_BASE, vid)); + writel_relaxed(data->pgtable[vid] >> PT_BASE_SHIFT, MMU_VM_REG(data, IDX_FLPT_BASE, vid)); __sysmmu_tlb_invalidate_all(data, vid); diff --git a/drivers/iommu/samsung-iommu.h b/drivers/iommu/samsung-iommu.h index c6162740b..8070a0127 100644 --- a/drivers/iommu/samsung-iommu.h +++ b/drivers/iommu/samsung-iommu.h @@ -13,6 +13,8 @@ #include <linux/interrupt.h> #include <linux/iommu.h> +#define PT_BASE_SHIFT 12 + #define MAX_VIDS 8U struct tlb_config { diff --git a/drivers/media/platform/exynos/mfc/mfc_core.c b/drivers/media/platform/exynos/mfc/mfc_core.c index b60fd094f..82490c4e6 100644 --- a/drivers/media/platform/exynos/mfc/mfc_core.c +++ b/drivers/media/platform/exynos/mfc/mfc_core.c @@ -492,7 +492,7 @@ static int __mfc_core_imgloader_desc_init(struct platform_device *pdev, struct m } #endif -#if IS_ENABLED(CONFIG_EXYNOS_ITMON) +#ifdef CONFIG_MFC_USE_ITMON static int __mfc_itmon_notifier(struct notifier_block *nb, unsigned long action, void *nb_data) { @@ -521,26 +521,23 @@ static int __mfc_itmon_notifier(struct notifier_block *nb, unsigned long action, is_client = 0; } - if (!is_mfc_itmon) + if (!is_mfc_itmon) { + dev_err(core->device, "[MFCITMON] It is not mfc itmon\n\n"); return ret; + } - dev_err(core->device, "mfc_itmon_notifier: +\n"); - dev_err(core->device, "MFC is %s\n", is_client ? "client" : "dest"); + dev_err(core->device, "[MFCITMON] mfc_itmon_notifier: +\n"); + dev_err(core->device, "[MFCITMON] MFC is %s\n", is_client ? "client" : "dest"); if (!core->itmon_notified) { - dev_err(core->device, "dump MFC information\n"); - if (is_client || (!is_client && itmon_info->onoff)) - call_dop(core, dump_and_stop_always, core); - else - call_dop(core, dump_info_without_regs, core); + dev_err(core->device, "[MFCITMON] dump MFC information\n"); + core->itmon_notified = 1; + call_dop(core, dump_and_stop_always, core); } else { - dev_err(core->device, "MFC notifier has already been called. skip MFC information\n"); + dev_err(core->device, "[MFCITMON] MFC notifier has already been called. skip MFC information\n"); } - dev_err(core->device, "mfc_itmon_notifier: -\n"); - core->itmon_notified = 1; + dev_err(core->device, "[MFCITMON] mfc_itmon_notifier: -\n"); ret = NOTIFY_BAD; - BUG(); - return ret; } #endif @@ -734,7 +731,7 @@ static int mfc_core_probe(struct platform_device *pdev) mfc_client_pt_register(core); -#if IS_ENABLED(CONFIG_EXYNOS_ITMON) +#ifdef CONFIG_MFC_USE_ITMON core->itmon_nb.notifier_call = __mfc_itmon_notifier; itmon_notifier_chain_register(&core->itmon_nb); #endif diff --git a/drivers/media/platform/exynos/mfc/mfc_core_meerkat.c b/drivers/media/platform/exynos/mfc/mfc_core_meerkat.c index 18321be1a..f75945471 100644 --- a/drivers/media/platform/exynos/mfc/mfc_core_meerkat.c +++ b/drivers/media/platform/exynos/mfc/mfc_core_meerkat.c @@ -1187,6 +1187,7 @@ static void __mfc_dump_info_and_stop_hw(struct mfc_core *core) struct mfc_core *main_core; struct mfc_ctx *ctx; int curr_ctx = __mfc_get_curr_ctx(core); + bool itmon_notified = core->itmon_notified; MFC_TRACE_CORE("** %s will stop!!!\n", core->name); @@ -1218,8 +1219,10 @@ static void __mfc_dump_info_and_stop_hw(struct mfc_core *core) #endif } + panic: - dbg_snapshot_emergency_reboot("MFC H/W issue\n"); + if (!itmon_notified) + dbg_snapshot_emergency_reboot("MFC H/W issue\n"); } static void __mfc_dump_info_and_stop_hw_debug(struct mfc_core *core) diff --git a/drivers/media/platform/exynos/mfc/mfc_data_struct.h b/drivers/media/platform/exynos/mfc/mfc_data_struct.h index 9facc4357..45dee8bb2 100644 --- a/drivers/media/platform/exynos/mfc/mfc_data_struct.h +++ b/drivers/media/platform/exynos/mfc/mfc_data_struct.h @@ -34,7 +34,8 @@ #include <soc/google/bts.h> #endif #include <linux/videodev2.h> -#if IS_ENABLED(CONFIG_EXYNOS_ITMON) +#if IS_ENABLED(CONFIG_EXYNOS_ITMON) || IS_ENABLED(CONFIG_EXYNOS_ITMON_V2) +#define CONFIG_MFC_USE_ITMON #include <soc/google/exynos-itmon.h> #endif #if IS_ENABLED(CONFIG_EXYNOS_MEMORY_LOGGER) @@ -1480,7 +1481,7 @@ struct mfc_core { struct platform_device *sscd_dev; /* ITMON */ -#if IS_ENABLED(CONFIG_EXYNOS_ITMON) +#ifdef CONFIG_MFC_USE_ITMON struct notifier_block itmon_nb; #endif int itmon_notified; diff --git a/drivers/media/platform/exynos/smfc/smfc-v4l2-ioctls.c b/drivers/media/platform/exynos/smfc/smfc-v4l2-ioctls.c index 72f40b403..fdc890f65 100644 --- a/drivers/media/platform/exynos/smfc/smfc-v4l2-ioctls.c +++ b/drivers/media/platform/exynos/smfc/smfc-v4l2-ioctls.c @@ -926,6 +926,10 @@ static int v4l2_smfc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, buf->type); + if (vq->num_buffers > SMFC_MAX_PLANES) { + return -EINVAL; + } + for (index = 0; index < vq->num_buffers; index++) { struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vq->bufs[index]); struct v4l2_m2m_buffer *mbuf = container_of(vbuf, typeof(*mbuf), vb); diff --git a/drivers/performance/gs_perf_mon/gs_perf_mon.c b/drivers/performance/gs_perf_mon/gs_perf_mon.c index 618dc5165..0d1d260bd 100644 --- a/drivers/performance/gs_perf_mon/gs_perf_mon.c +++ b/drivers/performance/gs_perf_mon/gs_perf_mon.c @@ -134,7 +134,7 @@ int read_perf_event_local(int cpu, unsigned int event_id, u64 *count) /* Ignoring input cpu parameter. */ cpu = raw_smp_processor_id(); - if (!perf_mon_metadata.perf_monitor_initialized) + if (!perf_mon_metadata.perf_monitor_initialized || event_id >= PERF_NUM_COMMON_EVS) return -EINVAL; cpu_data = &perf_mon_metadata.cpu_data_arr[cpu]; @@ -213,8 +213,8 @@ void gs_perf_mon_tick_update_counters(void) for (perf_idx = 0; perf_idx < PERF_NUM_COMMON_EVS; perf_idx++) { ev_data = &cpu_data->perf_ev_data[perf_idx]; if (read_perf_event(ev_data, &total)) { - pr_err("Perf event read failed on cpu=%u for event_idx=%u", cpu, - perf_idx); + pr_debug("Perf event read failed on cpu=%u for event_idx=%u", + cpu, perf_idx); continue; } ev_data->prev_count = ev_data->curr_count; diff --git a/drivers/soc/google/acpm/acpm_ipc.c b/drivers/soc/google/acpm/acpm_ipc.c index 4d1ca74f7..1ada74b5c 100644 --- a/drivers/soc/google/acpm/acpm_ipc.c +++ b/drivers/soc/google/acpm/acpm_ipc.c @@ -156,6 +156,12 @@ static int plugins_init(struct device_node *node) base_addr += offset; } + if (acpm_ipc->initdata->fvmap) { + base_addr = acpm_srambase; + offset = acpm_ipc->initdata->fvmap; + base_addr += offset; + } + fvmap_base_address = base_addr; } } diff --git a/drivers/soc/google/acpm/fw_header/framework.h b/drivers/soc/google/acpm/fw_header/framework.h index 682d897d6..c1423952a 100644 --- a/drivers/soc/google/acpm/fw_header/framework.h +++ b/drivers/soc/google/acpm/fw_header/framework.h @@ -76,7 +76,8 @@ struct acpm_framework { u32 preempt_log_buf_front; u32 preempt_log_data; u32 preempt_log_entry_len; - u32 reserved[63]; + u32 fvmap; + u32 reserved[62]; u32 err_log_async_channel; }; diff --git a/drivers/soc/google/cpif/link_device.c b/drivers/soc/google/cpif/link_device.c index eee95a1a0..1da887334 100644 --- a/drivers/soc/google/cpif/link_device.c +++ b/drivers/soc/google/cpif/link_device.c @@ -1663,6 +1663,16 @@ static int legacy_ipc_rx_func_napi(struct mem_link_device *mld, struct legacy_ip int rcvd = 0; int err = 0; + /* Make sure the in, out pointers are within bounds to avoid overflow. + * These pointers are passed from CP shared memory and must be + * validated before dma_sync below. */ + if ((in > qsize) || (out > qsize)) { + mif_err("OOB error! in:%u, out:%u, qsize:%u\n", in, out, qsize); + link_trigger_cp_crash(mld, CRASH_REASON_MIF_RX_BAD_DATA, + "OOB error"); + return -EINVAL; + } + if (unlikely(circ_empty(in, out))) return 0; @@ -1746,6 +1756,16 @@ static int legacy_ipc_rx_func(struct mem_link_device *mld, struct legacy_ipc_dev int rcvd = 0; int err = 0; + /* Make sure the in, out pointers are within bounds to avoid overflow. + * These pointers are passed from CP shared memory and must be + * validated before dma_sync below. */ + if ((in > qsize) || (out > qsize)) { + mif_err("OOB error! in:%u, out:%u, qsize:%u\n", in, out, qsize); + link_trigger_cp_crash(mld, CRASH_REASON_MIF_RX_BAD_DATA, + "OOB error"); + return -EINVAL; + } + if (unlikely(circ_empty(in, out))) return 0; diff --git a/drivers/soc/google/cpif/link_device_memory_legacy.c b/drivers/soc/google/cpif/link_device_memory_legacy.c index e3c5e0a9d..ad9501fc3 100644 --- a/drivers/soc/google/cpif/link_device_memory_legacy.c +++ b/drivers/soc/google/cpif/link_device_memory_legacy.c @@ -346,6 +346,19 @@ struct sk_buff *recv_from_legacy_link(struct mem_link_device *mld, char hdr[EXYNOS_HEADER_SIZE]; char pr_buff[BAD_MSG_BUFFER_SIZE]; + /* Make sure out pointer is within bounds. This pointer is read + * from CP shared memory and must be validated before + * circ_read below. */ + if (out > qsize) { + mif_err("OOB err! out:%u, qsize:%u\n", out, qsize); + if (ld->link_trigger_cp_crash) { + ld->link_trigger_cp_crash(mld, + CRASH_REASON_MIF_RX_BAD_DATA, "OOB error"); + } + *ret = -EINVAL; + goto no_mem; + } + /* Copy the header in a frame to the header buffer */ switch (ld->protocol) { case PROTOCOL_SIPC: diff --git a/drivers/soc/google/debug/zuma-itmon.c b/drivers/soc/google/debug/zuma-itmon.c index 6086d12e9..b96fd2484 100644 --- a/drivers/soc/google/debug/zuma-itmon.c +++ b/drivers/soc/google/debug/zuma-itmon.c @@ -82,6 +82,7 @@ #define PARSE_CPU_ID_DATA(x) (((x) & (0x0F << 20)) >> 20) #define PARSE_CPU_SRCATTR_TYPE(x) (((x) & (0x3 << 27)) >> 27) #define PARSE_CPU_SRCATTR_ACCS(x) (((x) & (0x1 << 29)) >> 29) +#define PARSE_CPU_WRITE_EVIC(x) (((x) & (0x1 << 26)) >> 26) #define AXID(x) (((x) & (0xFFFFFFFF))) #define AXUSER(x, y) ((u64)((x) & (0xFFFFFFFF)) | (((y) & (0xFFFFFFFF)) << 32ULL)) @@ -240,7 +241,7 @@ struct itmon_traceinfo { bool path_dirty; bool dirty; u32 path_type; - char buf[SZ_32]; + char buf[SZ_64]; u32 axsize; u32 axlen; u32 axburst; @@ -943,17 +944,18 @@ static const char *itmon_node_string[4] = { }; static const char *itmon_cpu_node_string[5] = { - "CLUSTER0_P", - "M_CPU", - "SCI_IRPM", - "SCI_CCM", "BOOKER", + "CPU0", + "CPU1", + "CPU2", + "CPU3", }; -static const char *itmon_cpu_attr_type[3] = { +static const char *itmon_cpu_attr_type[4] = { "Inst", /* Instruction */ "Data", /* Data */ "PTW", /* Page table walk */ + NO_NAME, }; static const char *itmon_cpu_attr_accs[2] = { @@ -1180,7 +1182,7 @@ static int itmon_parse_cpuinfo_by_name(struct itmon_dev *itmon, "CPU%d%s%s", core_num, el2 == 1 ? "EL2" : "", strong == 1 ? "Strng" : ""); } else { - scnprintf(cpu_name, CPU_NAME_LENGTH - 1, "CPU"); + strscpy(cpu_name, "CPU", CPU_NAME_LENGTH); } return 1; } @@ -1901,7 +1903,7 @@ static void itmon_post_handler(struct itmon_dev *itmon, bool err) pdata->last_errcnt++; if (pdata->last_errcnt > ERR_THRESHOLD) { - scnprintf(buf, sizeof(buf), "itmon triggering s2d start"); + strscpy(buf, "itmon triggering s2d start", sizeof(buf)); dbg_snapshot_do_dpm_policy(GO_S2D_ID, buf); } } else { @@ -2013,6 +2015,41 @@ static void itmon_report_pathinfo(struct itmon_dev *itmon, det_node->name, itmon_node_string[det_node->type], det_node->err_id); } +static void itmon_parse_cpuinfo_data(struct itmon_dev *itmon, + struct itmon_traceinfo *info, + unsigned int userbit) +{ + char core_str[SZ_16]; + const char *cache_str = NO_NAME; + int cache_dirty = -1; + int write_evict, core_num; + + core_num = PARSE_CPU_ID_DATA(userbit); + write_evict = PARSE_CPU_WRITE_EVIC(userbit); + + if (core_num == 0xE) { + strscpy(core_str, "ACP request", sizeof(core_str)); + } else if (core_num == 0xF) { + cache_dirty = (!write_evict) ? 1 : 0; + strscpy(core_str, "Cache copy back", sizeof(core_str)); + } else { + scnprintf(core_str, sizeof(core_str), "CPU%d", core_num); + } + + if (cache_dirty == 1) + cache_str = "YES"; + else if (cache_dirty == 0) + cache_str = "NO"; + + scnprintf(info->buf, sizeof(info->buf), + "%s, ATTR:[%s][%s], WRITE_EVICT[%d], Cache dirty[%s]", + core_str, + itmon_cpu_attr_type[PARSE_CPU_SRCATTR_TYPE(userbit)], + itmon_cpu_attr_accs[PARSE_CPU_SRCATTR_ACCS(userbit)], + write_evict, + cache_str); +} + static void itmon_parse_cpuinfo(struct itmon_dev *itmon, struct itmon_tracedata *data, struct itmon_traceinfo *info, @@ -2020,25 +2057,19 @@ static void itmon_parse_cpuinfo(struct itmon_dev *itmon, { struct itmon_platdata *pdata = itmon->pdata; struct itmon_nodeinfo *m_node = data->m_node; - int core_num = 0, cpu_attr_type = 0, cpu_attr_accs = 0, i; + int core_num = 0, i; for (i = 0; i < (int)ARRAY_SIZE(itmon_cpu_node_string); i++) { if (!strncmp(m_node->name, itmon_cpu_node_string[i], strlen(itmon_cpu_node_string[i]))) { if (!pdata->cpu_parsing) { - scnprintf(info->buf, sizeof(info->buf), "CPU"); + strscpy(info->buf, "CPU", sizeof(info->buf)); info->client = info->buf; } else if (info->path_type == CONFIG) { core_num = PARSE_CPU_ID_CONFIG(userbit); scnprintf(info->buf, sizeof(info->buf), "CPU%d ", core_num); info->client = info->buf; } else if (info->path_type == DATA && (userbit & BIT(25))) { - core_num = PARSE_CPU_ID_DATA(userbit); - cpu_attr_type = PARSE_CPU_SRCATTR_TYPE(userbit); - cpu_attr_accs = PARSE_CPU_SRCATTR_ACCS(userbit); - scnprintf(info->buf, sizeof(info->buf), - "CPU%d, ATTR:[%s][%s]", core_num, - itmon_cpu_attr_type[cpu_attr_type], - itmon_cpu_attr_accs[cpu_attr_accs]); + itmon_parse_cpuinfo_data(itmon, info, userbit); info->client = info->buf; } return; diff --git a/drivers/soc/google/perf_trace_counters.c b/drivers/soc/google/perf_trace_counters.c index b302f37ef..22a8a5cc2 100644 --- a/drivers/soc/google/perf_trace_counters.c +++ b/drivers/soc/google/perf_trace_counters.c @@ -31,6 +31,18 @@ DEFINE_PER_CPU(u32, old_pid); DEFINE_PER_CPU(u32, hotplug_flag); static DEFINE_MUTEX(perf_trace_lock); + +#if IS_ENABLED(CONFIG_GS_PERF_MON) + +const unsigned int ev_idx[NUM_EVENTS] = { + PERF_INST_IDX, + PERF_CYCLE_IDX, + PERF_STALL_BACKEND_MEM_IDX, + PERF_L3_CACHE_MISS_IDX +}; + +#else + const unsigned int ev_idx[NUM_EVENTS] = { INST_IDX, CYCLE_IDX, @@ -38,6 +50,8 @@ const unsigned int ev_idx[NUM_EVENTS] = { L3_CACHE_MISS_IDX }; +#endif + enum tp_pid_state_type { TP_DISABLED = 0, TP_ENABLED, @@ -55,7 +69,7 @@ static void setup_prev_cnts(u32 cpu) int i; u64 count; - /* Read the INST, CYC, L3DM counts from arm-memlat-mon */ + /* Read the INST, CYC, L3DM counts from performance monitor. */ for (i = 0; i < NUM_EVENTS; i++) { count = per_cpu(previous_cnts[i], cpu); per_cpu(previous_cnts[i], cpu) = diff --git a/drivers/soc/google/perf_trace_counters.h b/drivers/soc/google/perf_trace_counters.h index 3eca3201a..2f978a6b5 100644 --- a/drivers/soc/google/perf_trace_counters.h +++ b/drivers/soc/google/perf_trace_counters.h @@ -23,17 +23,27 @@ #include <linux/sched.h> #include <linux/tracepoint.h> +#if IS_ENABLED(CONFIG_GS_PERF_MON) #include <performance/gs_perf_mon/gs_perf_mon.h> +#else #include "../../devfreq/google/governor_memlat.h" +#endif /* - * PMU common event index + * Legacy AMU/PMU common event index * 0: STALL_IDX - skipped * 1: L2D_CACHE_REFILL_IDX - skipped * 2: STALL_BACKEND_MEM_IDX * 3: L3_CACHE_MISS_IDX * 4: INST_IDX * 5: CYCLE_IDX + * + * gs_perf_mon AMU/PMU common event index + * 0: PERF_L2D_CACHE_REFILL_IDX - skipped + * 1: PERF_STALL_BACKEND_MEM_IDX + * 2: PERF_L3_CACHE_MISS_IDX + * 3: PERF_INST_IDX + * 4: PERF_CYCLE_IDX */ #define NUM_EVENTS 4 extern const unsigned int ev_idx[NUM_EVENTS]; @@ -67,7 +77,7 @@ TRACE_EVENT(sched_switch_with_ctrs, memcpy(__entry->prev_comm, prev->comm, TASK_COMM_LEN); __entry->prev_pid = prev->pid; - /* Read the PMU event counts from arm-memlat-mon */ + /* Read the PMU event counts from performance monitor. */ for (i = 0; i < NUM_EVENTS; i++) { total_cnt = read_perf_event_local(cpu, ev_idx[i], &count) ? 0 : count; diff --git a/drivers/soc/google/pt/pt.c b/drivers/soc/google/pt/pt.c index 4dffd341e..84a9efcb8 100644 --- a/drivers/soc/google/pt/pt.c +++ b/drivers/soc/google/pt/pt.c @@ -110,9 +110,7 @@ struct { /* Data for resize_callback thread */ struct task_struct *resize_thread; - struct pt_pts *resize_pts_in_progress; /* callback is in progress */ struct list_head resize_list; /* callback to call */ - wait_queue_head_t resize_remove_wq; /* wait current callback return */ wait_queue_head_t resize_wq; /* wait for new callback */ } pt_internal_data; @@ -154,10 +152,10 @@ static void pt_trace(struct pt_handle *handle, int id, bool enable) */ static struct pt_pts *pt_resize_list_next(u32 *size) { - unsigned long flags; struct pt_pts *pts = NULL; - spin_lock_irqsave(&pt_internal_data.sl, flags); + lockdep_assert_held(&pt_internal_data.sl); + if (!list_empty(&pt_internal_data.resize_list)) { pts = list_first_entry(&pt_internal_data.resize_list, struct pt_pts, resize_list); @@ -166,14 +164,7 @@ static struct pt_pts *pt_resize_list_next(u32 *size) pts->resize_list.prev = NULL; *size = pts->size; } - pt_internal_data.resize_pts_in_progress = pts; - spin_unlock_irqrestore(&pt_internal_data.sl, flags); - wake_up(&pt_internal_data.resize_remove_wq); - - if (pts == NULL) - wait_event_interruptible(pt_internal_data.resize_wq, - !list_empty(&pt_internal_data.resize_list)); return pts; } @@ -189,8 +180,8 @@ static void pt_resize_list_add(struct pt_pts *pts, u32 size) spin_lock_irqsave(&pt_internal_data.sl, flags); if ((pts->resize_list.next == NULL) && (pts->enabled) && (pts->size != size)) { + waking = list_empty(&pt_internal_data.resize_list); list_add(&pts->resize_list, &pt_internal_data.resize_list); - waking = !pt_internal_data.resize_pts_in_progress; } pts->size = size; spin_unlock_irqrestore(&pt_internal_data.sl, flags); @@ -200,7 +191,7 @@ static void pt_resize_list_add(struct pt_pts *pts, u32 size) } /* - * FLush and disable pts resize callback. + * Flush and disable pts resize callback. * If a resize callback is in progress, we wait for its completion. */ static bool pt_resize_list_disable(struct pt_pts *pts) @@ -219,8 +210,6 @@ static bool pt_resize_list_disable(struct pt_pts *pts) } spin_unlock_irqrestore(&pt_internal_data.sl, flags); - wait_event(pt_internal_data.resize_remove_wq, - pt_internal_data.resize_pts_in_progress != pts); return enabled; } @@ -250,25 +239,37 @@ static int pt_resize_thread(void *data) pt_resize_callback_t resize_callback = NULL; int id; - while (1) { - /* - * We are size snapshot from pt_resize_list_next(). - * because pts->size can change after the return. - */ + while (!kthread_should_stop()) { + spin_lock(&pt_internal_data.sl); + pts = pt_resize_list_next(&size); - if (pts == NULL) - continue; - handle = pts->handle; - resize_callback = handle->resize_callback; - id = ((char *)pts - (char *)handle->pts) - / sizeof(handle->pts[0]); - resize_callback(handle->data, id, size); - - driver = pts->driver; - trace_pt_resize_callback(handle->node->name, - driver->properties->nodes[pts->property_index]->name, - false, (int)size, pts->ptid); + if (pts != NULL) { + handle = pts->handle; + resize_callback = handle->resize_callback; + id = ((char *)pts - (char *)handle->pts) / sizeof(handle->pts[0]); + resize_callback(handle->data, id, size); + driver = pts->driver; + trace_pt_resize_callback( + handle->node->name, + driver->properties->nodes[pts->property_index]->name, false, + (int)size, pts->ptid); + } + + spin_unlock(&pt_internal_data.sl); + + /* List was empty, wait to be notified by pt_resize_list_add */ + if (pts == NULL) { + int ret; + do { + ret = wait_event_interruptible( + pt_internal_data.resize_wq, + !list_empty(&pt_internal_data.resize_list) || + kthread_should_stop()); + } while (ret); + } } + + return 0; } /* @@ -1246,7 +1247,6 @@ static int __init pt_init(void) INIT_LIST_HEAD(&pt_internal_data.driver_list); INIT_LIST_HEAD(&pt_internal_data.resize_list); init_waitqueue_head(&pt_internal_data.resize_wq); - init_waitqueue_head(&pt_internal_data.resize_remove_wq); sysctl_table = &pt_internal_data.sysctl_table[0]; sysctl_table[0].procname = "dev"; sysctl_table[0].mode = 0550; diff --git a/drivers/soc/google/vh/kernel/sched/fair.c b/drivers/soc/google/vh/kernel/sched/fair.c index 424b6fb48..8634f461d 100644 --- a/drivers/soc/google/vh/kernel/sched/fair.c +++ b/drivers/soc/google/vh/kernel/sched/fair.c @@ -36,6 +36,8 @@ extern unsigned int vendor_sched_util_post_init_scale; extern bool vendor_sched_npi_packing; extern bool vendor_sched_boost_adpf_prio; +extern struct cpumask cpu_skip_mask; + static unsigned int early_boot_boost_uclamp_min = 563; module_param(early_boot_boost_uclamp_min, uint, 0644); @@ -1296,7 +1298,7 @@ compute_energy(struct task_struct *p, int dst_cpu, struct perf_domain *pd, unsig unsigned long sum_util, energy = 0; struct task_struct *tsk; int cpu; - bool count_idle = false; + bool count_idle; for (; pd; pd = pd->next) { struct cpumask *pd_mask = perf_domain_span(pd); @@ -1344,8 +1346,7 @@ compute_energy(struct task_struct *p, int dst_cpu, struct perf_domain *pd, unsig max_util = max(max_util, cpu_util); } - if (cpumask_test_cpu(dst_cpu, pd_mask) && exit_lat > C1_EXIT_LATENCY) - count_idle = true; + count_idle = cpumask_test_cpu(dst_cpu, pd_mask) && exit_lat > C1_EXIT_LATENCY; energy += em_cpu_energy_pixel_mod(pd->em_pd, max_util, sum_util, count_idle, dst_cpu); @@ -1848,7 +1849,9 @@ int find_energy_efficient_cpu(struct task_struct *p, int prev_cpu, preferred_idle_mask = get_preferred_idle_mask(p); cpumask_or(&idle_unpreferred, &idle_fit, &idle_unfit); cpumask_andnot(&idle_unpreferred, &idle_unpreferred, preferred_idle_mask); - cpumask_and(&idle_fit, &idle_fit, preferred_idle_mask); + // If there is no fit idle CPU in preferred_idle_mask, ignore it + if (task_fits_capacity(p, cpumask_last(preferred_idle_mask))) + cpumask_and(&idle_fit, &idle_fit, preferred_idle_mask); cpumask_and(&idle_unfit, &idle_unfit, preferred_idle_mask); } @@ -2404,7 +2407,8 @@ void rvh_select_task_rq_fair_pixel_mod(void *data, struct task_struct *p, int pr set_prefer_high_cap(p, sync && cpu >= pixel_cluster_start_cpu[1]); if (sync && cpu_rq(cpu)->nr_running == 1 && cpumask_test_cpu(cpu, p->cpus_ptr) && - cpu_is_in_target_set(p, cpu) && task_fits_capacity(p, cpu)) { + cpu_is_in_target_set(p, cpu) && task_fits_capacity(p, cpu) && + !cpumask_test_cpu(cpu, &cpu_skip_mask)) { *target_cpu = cpu; sync_wakeup = true; goto out; @@ -2412,7 +2416,8 @@ void rvh_select_task_rq_fair_pixel_mod(void *data, struct task_struct *p, int pr /* prefer prev cpu */ if (cpu_active(prev_cpu) && cpu_is_idle(prev_cpu) && - task_fits_capacity(p, prev_cpu) && check_preferred_idle_mask(p, prev_cpu)) { + task_fits_capacity(p, prev_cpu) && check_preferred_idle_mask(p, prev_cpu) && + !cpumask_test_cpu(prev_cpu, &cpu_skip_mask)) { struct cpuidle_state *idle_state; unsigned int exit_lat = UINT_MAX; @@ -2613,6 +2618,12 @@ void sched_newidle_balance_pixel_mod(void *data, struct rq *this_rq, struct rq_f return; /* + * Do not pull tasks in skip mask. + */ + if(cpumask_test_cpu(this_cpu, &cpu_skip_mask)) + return; + + /* * This is OK, because current is on_cpu, which avoids it being picked * for load-balance and preemption/IRQs are still disabled avoiding * further scheduler activity on it and we're being very careful to @@ -2726,6 +2737,11 @@ void rvh_can_migrate_task_pixel_mod(void *data, struct task_struct *mp, if (!get_prefer_idle(mp)) return; + if (cpumask_test_cpu(dst_cpu, &cpu_skip_mask)) { + *can_migrate = 0; + return; + } + if (atomic_read(&vrq->num_adpf_tasks)) *can_migrate = 0; } diff --git a/drivers/soc/google/vh/kernel/sched/procfs_node.c b/drivers/soc/google/vh/kernel/sched/procfs_node.c index b032692b1..eea8ea1eb 100644 --- a/drivers/soc/google/vh/kernel/sched/procfs_node.c +++ b/drivers/soc/google/vh/kernel/sched/procfs_node.c @@ -26,7 +26,9 @@ DECLARE_PER_CPU(struct uclamp_stats, uclamp_stats); unsigned int __read_mostly vendor_sched_util_post_init_scale = DEF_UTIL_POST_INIT_SCALE; bool __read_mostly vendor_sched_npi_packing = true; //non prefer idle packing bool __read_mostly vendor_sched_reduce_prefer_idle = true; +bool __read_mostly vendor_sched_auto_prefer_idle = false; bool __read_mostly vendor_sched_boost_adpf_prio = true; +struct cpumask cpu_skip_mask; static struct proc_dir_entry *vendor_sched; struct proc_dir_entry *group_dirs[VG_MAX]; extern struct vendor_group_list vendor_group_list[VG_MAX]; @@ -1622,6 +1624,37 @@ static ssize_t reduce_prefer_idle_store(struct file *filp, const char __user *ub PROC_OPS_RW(reduce_prefer_idle); +static int auto_prefer_idle_show(struct seq_file *m, void *v) +{ + seq_printf(m, "%s\n", vendor_sched_auto_prefer_idle ? "true" : "false"); + + return 0; +} + +static ssize_t auto_prefer_idle_store(struct file *filp, const char __user *ubuf, + size_t count, loff_t *pos) +{ + bool enable; + char buf[MAX_PROC_SIZE]; + + if (count >= sizeof(buf)) + return -EINVAL; + + if (copy_from_user(buf, ubuf, count)) + return -EFAULT; + + buf[count] = '\0'; + + if (kstrtobool(buf, &enable)) + return -EINVAL; + + vendor_sched_auto_prefer_idle = enable; + + return count; +} + +PROC_OPS_RW(auto_prefer_idle); + static int boost_adpf_prio_show(struct seq_file *m, void *v) { seq_printf(m, "%s\n", vendor_sched_boost_adpf_prio ? "true" : "false"); @@ -2184,6 +2217,29 @@ static ssize_t ug_bg_auto_prio_store(struct file *filp, const char __user *ubuf, PROC_OPS_RW(ug_bg_auto_prio); #endif +static int cpu_skip_mask_show(struct seq_file *m, void *v) +{ + seq_printf(m, "0x%lx\n", cpu_skip_mask.bits[0]); + + return 0; +} +static ssize_t cpu_skip_mask_store(struct file *filp, + const char __user *ubuf, + size_t count, loff_t *pos) +{ + int ret; + unsigned long val; + + ret = kstrtoul_from_user(ubuf, count, 0, &val); + if (ret) + return ret; + + cpu_skip_mask.bits[0] = val; + + return count; +} +PROC_OPS_RW(cpu_skip_mask); + struct pentry { const char *name; enum vendor_procfs_type type; @@ -2233,6 +2289,7 @@ static struct pentry entries[] = { PROC_ENTRY(util_post_init_scale), PROC_ENTRY(npi_packing), PROC_ENTRY(reduce_prefer_idle), + PROC_ENTRY(auto_prefer_idle), PROC_ENTRY(boost_adpf_prio), PROC_ENTRY(dump_task), // pmu limit attribute @@ -2262,6 +2319,8 @@ static struct pentry entries[] = { PROC_ENTRY(tapered_dvfs_headroom_enable), // teo PROC_ENTRY(teo_util_threshold), + // skip mask for RT wake up + PROC_ENTRY(cpu_skip_mask), }; diff --git a/drivers/soc/google/vh/kernel/sched/rt.c b/drivers/soc/google/vh/kernel/sched/rt.c index df9a03e64..96b956953 100644 --- a/drivers/soc/google/vh/kernel/sched/rt.c +++ b/drivers/soc/google/vh/kernel/sched/rt.c @@ -24,6 +24,8 @@ extern int ___update_load_sum(u64 now, struct sched_avg *sa, unsigned long load, extern void ___update_load_avg(struct sched_avg *sa, unsigned long load); extern int get_cluster_enabled(int cluster); +extern struct cpumask cpu_skip_mask; + /*****************************************************************************/ /* Upstream Code Section */ /*****************************************************************************/ @@ -44,7 +46,7 @@ static inline bool should_honor_rt_sync(struct rq *rq, struct task_struct *p, */ return sync && task_has_rt_policy(rq->curr) && p->prio <= rq->rt.highest_prio.next && - rq->rt.rt_nr_running <= 2; + rq->rt.rt_nr_running <= 2 && !cpumask_test_cpu(rq->cpu, &cpu_skip_mask); } #else static inline bool should_honor_rt_sync(struct rq *rq, struct task_struct *p, @@ -188,6 +190,9 @@ static int find_least_loaded_cpu(struct task_struct *p, struct cpumask *lowest_m exit_lat[cpu] = pixel_cpd_exit_latency[pixel_cpu_to_cluster[cpu]]; } + if (cpumask_test_cpu(cpu, &cpu_skip_mask)) + cpu_importance[cpu] = UINT_MAX; + trace_sched_cpu_util_rt(cpu, capacity[cpu], capacity_of(cpu), util[cpu], exit_lat[cpu], cpu_importance[cpu], task_fits[cpu], task_fits_original[cpu], overutilize[cpu], is_idle); diff --git a/drivers/soc/google/vh/kernel/sched/sched_priv.h b/drivers/soc/google/vh/kernel/sched/sched_priv.h index 8f3e5aa0c..afa728baa 100644 --- a/drivers/soc/google/vh/kernel/sched/sched_priv.h +++ b/drivers/soc/google/vh/kernel/sched/sched_priv.h @@ -181,6 +181,7 @@ ANDROID_VENDOR_CHECK_SIZE_ALIGN(u64 android_vendor_data1[4], struct vendor_task_ #endif extern bool vendor_sched_reduce_prefer_idle; +extern bool vendor_sched_auto_prefer_idle; extern struct vendor_group_property vg[VG_MAX]; DECLARE_STATIC_KEY_FALSE(uclamp_min_filter_enable); @@ -424,18 +425,19 @@ static inline bool get_uclamp_fork_reset(struct task_struct *p, bool inherited) static inline bool get_prefer_idle(struct task_struct *p) { - // For group based prefer_idle vote, filter our smaller or low prio or - // have throttled uclamp.max settings - // Ignore all checks, if the prefer_idle is from per-task API. - struct vendor_task_struct *vp = get_vendor_task_struct(p); struct vendor_binder_task_struct *vbinder = get_vendor_binder_task_struct(p); + // Always perfer idle for ADPF tasks or tasks with prefer_idle set explicitly. + // In auto_prefer_idle case, only allow high prio tasks of the prefer_idle group, + // or high prio task with wake_q_count value greater than 0 in top-app. if (get_uclamp_fork_reset(p, true) || vp->prefer_idle || vbinder->prefer_idle) return true; + else if (vendor_sched_auto_prefer_idle) + return vp->group == VG_TOPAPP && p->prio <= DEFAULT_PRIO && p->wake_q_count; else if (vendor_sched_reduce_prefer_idle) - return vg[vp->group].prefer_idle && p->prio <= DEFAULT_PRIO && - uclamp_eff_value_pixel_mod(p, UCLAMP_MAX) == SCHED_CAPACITY_SCALE; + return (vg[vp->group].prefer_idle && p->prio <= DEFAULT_PRIO && + uclamp_eff_value_pixel_mod(p, UCLAMP_MAX) == SCHED_CAPACITY_SCALE); else return vg[vp->group].prefer_idle; } diff --git a/drivers/thermal/google/google_bcl_core.c b/drivers/thermal/google/google_bcl_core.c index 025ada730..c0b46fd78 100644 --- a/drivers/thermal/google/google_bcl_core.c +++ b/drivers/thermal/google/google_bcl_core.c @@ -36,6 +36,7 @@ #include <linux/debugfs.h> #include <linux/seq_file.h> #endif +#include "soc/google/exynos-modem-ctrl.h" static const struct platform_device_id google_id_table[] = { {.name = "google_mitigation",}, @@ -78,16 +79,45 @@ static void bin_incr_ifpmic(struct bcl_device *bcl_dev, enum BCL_BATT_IRQ batt, enum CONCURRENT_PWRWARN_IRQ pwrwarn, ktime_t end_time) { ktime_t time_delta; + u8 lsb, msb, thr; + u16 odpm_pwr; + if (bcl_dev->ifpmic_irq_bins[batt][pwrwarn].start_time == 0) return; time_delta = ktime_sub(end_time, bcl_dev->ifpmic_irq_bins[batt][pwrwarn].start_time); - if (ktime_compare(time_delta, DELTA_10MS) < 0) + if (ktime_compare(time_delta, DELTA_5MS) < 0) atomic_inc(&bcl_dev->ifpmic_irq_bins[batt][pwrwarn].lt_5ms_count); - else if (ktime_compare(time_delta, DELTA_50MS) < 0) + else if (ktime_compare(time_delta, DELTA_10MS) < 0) atomic_inc(&bcl_dev->ifpmic_irq_bins[batt][pwrwarn].bt_5ms_10ms_count); - else + else { atomic_inc(&bcl_dev->ifpmic_irq_bins[batt][pwrwarn].gt_10ms_count); + if (bcl_dev->rffe_mitigation_enable && pwrwarn == RFFE_BCL_BIN && + (batt == BATOILO_IRQ_BIN)) { + if (meter_read(CORE_PMIC_MAIN, bcl_dev, PWRWARN_LPF_RFFE_DATA_MAIN_0, + &lsb)) { + dev_err(bcl_dev->device, "cannot read rffe power\n"); + goto end_bin_incr_ifpmic; + } + if (meter_read(CORE_PMIC_MAIN, bcl_dev, PWRWARN_LPF_RFFE_DATA_MAIN_1, + &msb)) { + dev_err(bcl_dev->device, "cannot read rffe power\n"); + goto end_bin_incr_ifpmic; + } + if (meter_read(CORE_PMIC_MAIN, bcl_dev, PWRWARN_THRESH_MAIN, &thr)) { + dev_err(bcl_dev->device, "cannot read rffe power\n"); + goto end_bin_incr_ifpmic; + } + odpm_pwr = (lsb | ((msb & PWRWARN_LPF_RFFE_MSB_MASK) << 8)) >> + PWRWARN_LPF_RFFE_RSHIFT; + if (odpm_pwr < thr) + goto end_bin_incr_ifpmic; + modem_force_crash_exit_ext(); + dev_err(bcl_dev->device, "BCL: RFFE ODPM pwr: %i, thresh: %i trig crash", + odpm_pwr, thr); + } + } +end_bin_incr_ifpmic: bcl_dev->ifpmic_irq_bins[batt][pwrwarn].start_time = 0; } @@ -190,9 +220,9 @@ static void pwrwarn_update_end_time(struct bcl_device *bcl_dev, int id, return; time_delta = ktime_sub(end_time, bins[id].start_time); - if (ktime_compare(time_delta, DELTA_10MS) < 0) + if (ktime_compare(time_delta, DELTA_5MS) < 0) atomic_inc(&(bins[id].lt_5ms_count)); - else if (ktime_compare(time_delta, DELTA_50MS) < 0) + else if (ktime_compare(time_delta, DELTA_10MS) < 0) atomic_inc(&(bins[id].bt_5ms_10ms_count)); else atomic_inc(&(bins[id].gt_10ms_count)); diff --git a/drivers/thermal/google/google_bcl_sysfs.c b/drivers/thermal/google/google_bcl_sysfs.c index b59689590..d767473a9 100644 --- a/drivers/thermal/google/google_bcl_sysfs.c +++ b/drivers/thermal/google/google_bcl_sysfs.c @@ -684,6 +684,35 @@ static ssize_t enable_mitigation_store(struct device *dev, struct device_attribu static DEVICE_ATTR_RW(enable_mitigation); +static ssize_t enable_rffe_mitigation_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, dev); + struct bcl_device *bcl_dev = platform_get_drvdata(pdev); + + return sysfs_emit(buf, "%d\n", bcl_dev->rffe_mitigation_enable); +} + +static ssize_t enable_rffe_mitigation_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t size) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, dev); + struct bcl_device *bcl_dev = platform_get_drvdata(pdev); + bool value; + int ret; + + ret = kstrtobool(buf, &value); + if (ret) + return ret; + + if (bcl_dev->rffe_mitigation_enable == value) + return size; + + bcl_dev->rffe_mitigation_enable = value; + return size; +} +static DEVICE_ATTR_RW(enable_rffe_mitigation); + static ssize_t main_offsrc1_show(struct device *dev, struct device_attribute *attr, char *buf) { struct platform_device *pdev = container_of(dev, struct platform_device, dev); @@ -747,6 +776,7 @@ static struct attribute *instr_attrs[] = { &dev_attr_mid_db_settings.attr, &dev_attr_big_db_settings.attr, &dev_attr_enable_mitigation.attr, + &dev_attr_enable_rffe_mitigation.attr, &dev_attr_main_offsrc1.attr, &dev_attr_main_offsrc2.attr, &dev_attr_sub_offsrc1.attr, diff --git a/include/dt-bindings/lwis/platform/zuma/isp_fe.h b/include/dt-bindings/lwis/platform/zuma/isp_fe.h index 5ba165b77..162a2ad37 100644 --- a/include/dt-bindings/lwis/platform/zuma/isp_fe.h +++ b/include/dt-bindings/lwis/platform/zuma/isp_fe.h @@ -1557,6 +1557,8 @@ #define ISP_FE_CSIS_INT0_CTX0_ERR_OVER 4 #define ISP_FE_CSIS_INT0_CTX0_ERR_CRC_PH 5 #define ISP_FE_CSIS_INT0_CTX0_MAL_CRC 6 +#define ISP_FE_CSIS_INT0_CTX0_ERR_SKEW 7 +#define ISP_FE_CSIS_INT0_CTX0_ERR_DESKEW_OVER 8 #define ISP_FE_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE0 12 #define ISP_FE_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE1 13 #define ISP_FE_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE2 14 @@ -1569,6 +1571,7 @@ #define ISP_FE_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE1 21 #define ISP_FE_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE2 22 #define ISP_FE_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE3 23 +#define ISP_FE_CSIS_INT0_CTX0_PHY_TIMING_ERR 24 #define ISP_FE_CSIS_INT0_CTX1_BASE (HW_EVENT_MASK + 4960) @@ -1579,6 +1582,8 @@ #define ISP_FE_CSIS_INT0_CTX1_ERR_OVER 4 #define ISP_FE_CSIS_INT0_CTX1_ERR_CRC_PH 5 #define ISP_FE_CSIS_INT0_CTX1_MAL_CRC 6 +#define ISP_FE_CSIS_INT0_CTX1_ERR_SKEW 7 +#define ISP_FE_CSIS_INT0_CTX1_ERR_DESKEW_OVER 8 #define ISP_FE_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE0 12 #define ISP_FE_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE1 13 #define ISP_FE_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE2 14 @@ -1591,6 +1596,7 @@ #define ISP_FE_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE1 21 #define ISP_FE_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE2 22 #define ISP_FE_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE3 23 +#define ISP_FE_CSIS_INT0_CTX1_PHY_TIMING_ERR 24 #define ISP_FE_CSIS_INT0_CTX2_BASE (HW_EVENT_MASK + 4992) @@ -1601,6 +1607,8 @@ #define ISP_FE_CSIS_INT0_CTX2_ERR_OVER 4 #define ISP_FE_CSIS_INT0_CTX2_ERR_CRC_PH 5 #define ISP_FE_CSIS_INT0_CTX2_MAL_CRC 6 +#define ISP_FE_CSIS_INT0_CTX2_ERR_SKEW 7 +#define ISP_FE_CSIS_INT0_CTX2_ERR_DESKEW_OVER 8 #define ISP_FE_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE0 12 #define ISP_FE_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE1 13 #define ISP_FE_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE2 14 @@ -1613,6 +1621,7 @@ #define ISP_FE_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE1 21 #define ISP_FE_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE2 22 #define ISP_FE_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE3 23 +#define ISP_FE_CSIS_INT0_CTX2_PHY_TIMING_ERR 24 #define ISP_FE_CSIS_INT0_CTX3_BASE (HW_EVENT_MASK + 5024) @@ -1623,6 +1632,8 @@ #define ISP_FE_CSIS_INT0_CTX3_ERR_OVER 4 #define ISP_FE_CSIS_INT0_CTX3_ERR_CRC_PH 5 #define ISP_FE_CSIS_INT0_CTX3_MAL_CRC 6 +#define ISP_FE_CSIS_INT0_CTX3_ERR_SKEW 7 +#define ISP_FE_CSIS_INT0_CTX3_ERR_DESKEW_OVER 8 #define ISP_FE_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE0 12 #define ISP_FE_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE1 13 #define ISP_FE_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE2 14 @@ -1635,6 +1646,7 @@ #define ISP_FE_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE1 21 #define ISP_FE_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE2 22 #define ISP_FE_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE3 23 +#define ISP_FE_CSIS_INT0_CTX3_PHY_TIMING_ERR 24 #define ISP_FE_CSIS_INT0_CTX4_BASE (HW_EVENT_MASK + 5056) @@ -1645,6 +1657,8 @@ #define ISP_FE_CSIS_INT0_CTX4_ERR_OVER 4 #define ISP_FE_CSIS_INT0_CTX4_ERR_CRC_PH 5 #define ISP_FE_CSIS_INT0_CTX4_MAL_CRC 6 +#define ISP_FE_CSIS_INT0_CTX4_ERR_SKEW 7 +#define ISP_FE_CSIS_INT0_CTX4_ERR_DESKEW_OVER 8 #define ISP_FE_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE0 12 #define ISP_FE_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE1 13 #define ISP_FE_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE2 14 @@ -1657,6 +1671,7 @@ #define ISP_FE_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE1 21 #define ISP_FE_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE2 22 #define ISP_FE_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE3 23 +#define ISP_FE_CSIS_INT0_CTX4_PHY_TIMING_ERR 24 #define ISP_FE_CSIS_INT0_CTX5_BASE (HW_EVENT_MASK + 5088) @@ -1667,6 +1682,8 @@ #define ISP_FE_CSIS_INT0_CTX5_ERR_OVER 4 #define ISP_FE_CSIS_INT0_CTX5_ERR_CRC_PH 5 #define ISP_FE_CSIS_INT0_CTX5_MAL_CRC 6 +#define ISP_FE_CSIS_INT0_CTX5_ERR_SKEW 7 +#define ISP_FE_CSIS_INT0_CTX5_ERR_DESKEW_OVER 8 #define ISP_FE_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE0 12 #define ISP_FE_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE1 13 #define ISP_FE_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE2 14 @@ -1679,6 +1696,7 @@ #define ISP_FE_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE1 21 #define ISP_FE_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE2 22 #define ISP_FE_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE3 23 +#define ISP_FE_CSIS_INT0_CTX5_PHY_TIMING_ERR 24 #define ISP_FE_CSIS_INT0_CTX6_BASE (HW_EVENT_MASK + 5120) @@ -1689,6 +1707,8 @@ #define ISP_FE_CSIS_INT0_CTX6_ERR_OVER 4 #define ISP_FE_CSIS_INT0_CTX6_ERR_CRC_PH 5 #define ISP_FE_CSIS_INT0_CTX6_MAL_CRC 6 +#define ISP_FE_CSIS_INT0_CTX6_ERR_SKEW 7 +#define ISP_FE_CSIS_INT0_CTX6_ERR_DESKEW_OVER 8 #define ISP_FE_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE0 12 #define ISP_FE_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE1 13 #define ISP_FE_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE2 14 @@ -1701,6 +1721,7 @@ #define ISP_FE_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE1 21 #define ISP_FE_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE2 22 #define ISP_FE_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE3 23 +#define ISP_FE_CSIS_INT0_CTX6_PHY_TIMING_ERR 24 #define ISP_FE_CSIS_INT0_CTX7_BASE (HW_EVENT_MASK + 5152) @@ -1711,6 +1732,8 @@ #define ISP_FE_CSIS_INT0_CTX7_ERR_OVER 4 #define ISP_FE_CSIS_INT0_CTX7_ERR_CRC_PH 5 #define ISP_FE_CSIS_INT0_CTX7_MAL_CRC 6 +#define ISP_FE_CSIS_INT0_CTX7_ERR_SKEW 7 +#define ISP_FE_CSIS_INT0_CTX7_ERR_DESKEW_OVER 8 #define ISP_FE_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE0 12 #define ISP_FE_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE1 13 #define ISP_FE_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE2 14 @@ -1723,6 +1746,7 @@ #define ISP_FE_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE1 21 #define ISP_FE_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE2 22 #define ISP_FE_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE3 23 +#define ISP_FE_CSIS_INT0_CTX7_PHY_TIMING_ERR 24 #define ISP_FE_CSIS_INT0_CTX8_BASE (HW_EVENT_MASK + 5184) @@ -1733,6 +1757,8 @@ #define ISP_FE_CSIS_INT0_CTX8_ERR_OVER 4 #define ISP_FE_CSIS_INT0_CTX8_ERR_CRC_PH 5 #define ISP_FE_CSIS_INT0_CTX8_MAL_CRC 6 +#define ISP_FE_CSIS_INT0_CTX8_ERR_SKEW 7 +#define ISP_FE_CSIS_INT0_CTX8_ERR_DESKEW_OVER 8 #define ISP_FE_CSIS_INT0_CTX8_RX_INVALID_CODE_HS_LANE0 12 #define ISP_FE_CSIS_INT0_CTX8_RX_INVALID_CODE_HS_LANE1 13 #define ISP_FE_CSIS_INT0_CTX8_RX_INVALID_CODE_HS_LANE2 14 @@ -1745,6 +1771,7 @@ #define ISP_FE_CSIS_INT0_CTX8_ERR_SOT_SYNC_HS_LANE1 21 #define ISP_FE_CSIS_INT0_CTX8_ERR_SOT_SYNC_HS_LANE2 22 #define ISP_FE_CSIS_INT0_CTX8_ERR_SOT_SYNC_HS_LANE3 23 +#define ISP_FE_CSIS_INT0_CTX8_PHY_TIMING_ERR 24 #define ISP_FE_CSIS_INT0_CTX9_BASE (HW_EVENT_MASK + 5216) @@ -1755,6 +1782,8 @@ #define ISP_FE_CSIS_INT0_CTX9_ERR_OVER 4 #define ISP_FE_CSIS_INT0_CTX9_ERR_CRC_PH 5 #define ISP_FE_CSIS_INT0_CTX9_MAL_CRC 6 +#define ISP_FE_CSIS_INT0_CTX9_ERR_SKEW 7 +#define ISP_FE_CSIS_INT0_CTX9_ERR_DESKEW_OVER 8 #define ISP_FE_CSIS_INT0_CTX9_RX_INVALID_CODE_HS_LANE0 12 #define ISP_FE_CSIS_INT0_CTX9_RX_INVALID_CODE_HS_LANE1 13 #define ISP_FE_CSIS_INT0_CTX9_RX_INVALID_CODE_HS_LANE2 14 @@ -1767,6 +1796,7 @@ #define ISP_FE_CSIS_INT0_CTX9_ERR_SOT_SYNC_HS_LANE1 21 #define ISP_FE_CSIS_INT0_CTX9_ERR_SOT_SYNC_HS_LANE2 22 #define ISP_FE_CSIS_INT0_CTX9_ERR_SOT_SYNC_HS_LANE3 23 +#define ISP_FE_CSIS_INT0_CTX9_PHY_TIMING_ERR 24 #define ISP_FE_CSIS_INT0_CTX10_BASE (HW_EVENT_MASK + 5248) @@ -1777,6 +1807,8 @@ #define ISP_FE_CSIS_INT0_CTX10_ERR_OVER 4 #define ISP_FE_CSIS_INT0_CTX10_ERR_CRC_PH 5 #define ISP_FE_CSIS_INT0_CTX10_MAL_CRC 6 +#define ISP_FE_CSIS_INT0_CTX10_ERR_SKEW 7 +#define ISP_FE_CSIS_INT0_CTX10_ERR_DESKEW_OVER 8 #define ISP_FE_CSIS_INT0_CTX10_RX_INVALID_CODE_HS_LANE0 12 #define ISP_FE_CSIS_INT0_CTX10_RX_INVALID_CODE_HS_LANE1 13 #define ISP_FE_CSIS_INT0_CTX10_RX_INVALID_CODE_HS_LANE2 14 @@ -1789,6 +1821,7 @@ #define ISP_FE_CSIS_INT0_CTX10_ERR_SOT_SYNC_HS_LANE1 21 #define ISP_FE_CSIS_INT0_CTX10_ERR_SOT_SYNC_HS_LANE2 22 #define ISP_FE_CSIS_INT0_CTX10_ERR_SOT_SYNC_HS_LANE3 23 +#define ISP_FE_CSIS_INT0_CTX10_PHY_TIMING_ERR 24 #define ISP_FE_CSIS_INT0_CTX11_BASE (HW_EVENT_MASK + 5280) @@ -1799,6 +1832,8 @@ #define ISP_FE_CSIS_INT0_CTX11_ERR_OVER 4 #define ISP_FE_CSIS_INT0_CTX11_ERR_CRC_PH 5 #define ISP_FE_CSIS_INT0_CTX11_MAL_CRC 6 +#define ISP_FE_CSIS_INT0_CTX11_ERR_SKEW 7 +#define ISP_FE_CSIS_INT0_CTX11_ERR_DESKEW_OVER 8 #define ISP_FE_CSIS_INT0_CTX11_RX_INVALID_CODE_HS_LANE0 12 #define ISP_FE_CSIS_INT0_CTX11_RX_INVALID_CODE_HS_LANE1 13 #define ISP_FE_CSIS_INT0_CTX11_RX_INVALID_CODE_HS_LANE2 14 @@ -1811,6 +1846,7 @@ #define ISP_FE_CSIS_INT0_CTX11_ERR_SOT_SYNC_HS_LANE1 21 #define ISP_FE_CSIS_INT0_CTX11_ERR_SOT_SYNC_HS_LANE2 22 #define ISP_FE_CSIS_INT0_CTX11_ERR_SOT_SYNC_HS_LANE3 23 +#define ISP_FE_CSIS_INT0_CTX11_PHY_TIMING_ERR 24 #define ISP_FE_CSIS_INT1_CTX0_BASE (HW_EVENT_MASK + 5312) @@ -6171,6 +6207,12 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_MAL_CRC \ EVENT_ID(ISP_FE_CSIS_INT0_CTX0_BASE, \ ISP_FE_CSIS_INT0_CTX0_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_ERR_SKEW \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX0_BASE, \ + ISP_FE_CSIS_INT0_CTX0_ERR_SKEW) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_ERR_DESKEW_OVER \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX0_BASE, \ + ISP_FE_CSIS_INT0_CTX0_ERR_DESKEW_OVER) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE0 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX0_BASE, \ ISP_FE_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE0) @@ -6207,6 +6249,9 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE3 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX0_BASE, \ ISP_FE_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX0_PHY_TIMING_ERR \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX0_BASE, \ + ISP_FE_CSIS_INT0_CTX0_PHY_TIMING_ERR) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_ERR_ID \ EVENT_ID(ISP_FE_CSIS_INT0_CTX1_BASE, \ @@ -6229,6 +6274,12 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_MAL_CRC \ EVENT_ID(ISP_FE_CSIS_INT0_CTX1_BASE, \ ISP_FE_CSIS_INT0_CTX1_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_ERR_SKEW \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX1_BASE, \ + ISP_FE_CSIS_INT0_CTX1_ERR_SKEW) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_ERR_DESKEW_OVER \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX1_BASE, \ + ISP_FE_CSIS_INT0_CTX1_ERR_DESKEW_OVER) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE0 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX1_BASE, \ ISP_FE_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE0) @@ -6265,6 +6316,9 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE3 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX1_BASE, \ ISP_FE_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX1_PHY_TIMING_ERR \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX1_BASE, \ + ISP_FE_CSIS_INT0_CTX1_PHY_TIMING_ERR) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_ERR_ID \ EVENT_ID(ISP_FE_CSIS_INT0_CTX2_BASE, \ @@ -6287,6 +6341,12 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_MAL_CRC \ EVENT_ID(ISP_FE_CSIS_INT0_CTX2_BASE, \ ISP_FE_CSIS_INT0_CTX2_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_ERR_SKEW \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX2_BASE, \ + ISP_FE_CSIS_INT0_CTX2_ERR_SKEW) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_ERR_DESKEW_OVER \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX2_BASE, \ + ISP_FE_CSIS_INT0_CTX2_ERR_DESKEW_OVER) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE0 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX2_BASE, \ ISP_FE_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE0) @@ -6323,6 +6383,9 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE3 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX2_BASE, \ ISP_FE_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX2_PHY_TIMING_ERR \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX2_BASE, \ + ISP_FE_CSIS_INT0_CTX2_PHY_TIMING_ERR) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_ERR_ID \ EVENT_ID(ISP_FE_CSIS_INT0_CTX3_BASE, \ @@ -6345,6 +6408,12 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_MAL_CRC \ EVENT_ID(ISP_FE_CSIS_INT0_CTX3_BASE, \ ISP_FE_CSIS_INT0_CTX3_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_ERR_SKEW \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX3_BASE, \ + ISP_FE_CSIS_INT0_CTX3_ERR_SKEW) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_ERR_DESKEW_OVER \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX3_BASE, \ + ISP_FE_CSIS_INT0_CTX3_ERR_DESKEW_OVER) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE0 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX3_BASE, \ ISP_FE_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE0) @@ -6381,6 +6450,9 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE3 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX3_BASE, \ ISP_FE_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX3_PHY_TIMING_ERR \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX3_BASE, \ + ISP_FE_CSIS_INT0_CTX3_PHY_TIMING_ERR) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_ERR_ID \ EVENT_ID(ISP_FE_CSIS_INT0_CTX4_BASE, \ @@ -6403,6 +6475,12 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_MAL_CRC \ EVENT_ID(ISP_FE_CSIS_INT0_CTX4_BASE, \ ISP_FE_CSIS_INT0_CTX4_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_ERR_SKEW \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX4_BASE, \ + ISP_FE_CSIS_INT0_CTX4_ERR_SKEW) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_ERR_DESKEW_OVER \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX4_BASE, \ + ISP_FE_CSIS_INT0_CTX4_ERR_DESKEW_OVER) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE0 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX4_BASE, \ ISP_FE_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE0) @@ -6439,6 +6517,9 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE3 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX4_BASE, \ ISP_FE_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX4_PHY_TIMING_ERR \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX4_BASE, \ + ISP_FE_CSIS_INT0_CTX4_PHY_TIMING_ERR) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_ERR_ID \ EVENT_ID(ISP_FE_CSIS_INT0_CTX5_BASE, \ @@ -6461,6 +6542,12 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_MAL_CRC \ EVENT_ID(ISP_FE_CSIS_INT0_CTX5_BASE, \ ISP_FE_CSIS_INT0_CTX5_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_ERR_SKEW \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX5_BASE, \ + ISP_FE_CSIS_INT0_CTX5_ERR_SKEW) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_ERR_DESKEW_OVER \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX5_BASE, \ + ISP_FE_CSIS_INT0_CTX5_ERR_DESKEW_OVER) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE0 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX5_BASE, \ ISP_FE_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE0) @@ -6497,6 +6584,9 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE3 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX5_BASE, \ ISP_FE_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX5_PHY_TIMING_ERR \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX5_BASE, \ + ISP_FE_CSIS_INT0_CTX5_PHY_TIMING_ERR) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_ERR_ID \ EVENT_ID(ISP_FE_CSIS_INT0_CTX6_BASE, \ @@ -6519,6 +6609,12 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_MAL_CRC \ EVENT_ID(ISP_FE_CSIS_INT0_CTX6_BASE, \ ISP_FE_CSIS_INT0_CTX6_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_ERR_SKEW \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX6_BASE, \ + ISP_FE_CSIS_INT0_CTX6_ERR_SKEW) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_ERR_DESKEW_OVER \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX6_BASE, \ + ISP_FE_CSIS_INT0_CTX6_ERR_DESKEW_OVER) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE0 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX6_BASE, \ ISP_FE_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE0) @@ -6555,6 +6651,9 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE3 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX6_BASE, \ ISP_FE_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX6_PHY_TIMING_ERR \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX6_BASE, \ + ISP_FE_CSIS_INT0_CTX6_PHY_TIMING_ERR) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_ERR_ID \ EVENT_ID(ISP_FE_CSIS_INT0_CTX7_BASE, \ @@ -6577,6 +6676,12 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_MAL_CRC \ EVENT_ID(ISP_FE_CSIS_INT0_CTX7_BASE, \ ISP_FE_CSIS_INT0_CTX7_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_ERR_SKEW \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX7_BASE, \ + ISP_FE_CSIS_INT0_CTX7_ERR_SKEW) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_ERR_DESKEW_OVER \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX7_BASE, \ + ISP_FE_CSIS_INT0_CTX7_ERR_DESKEW_OVER) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE0 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX7_BASE, \ ISP_FE_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE0) @@ -6613,6 +6718,9 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE3 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX7_BASE, \ ISP_FE_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX7_PHY_TIMING_ERR \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX7_BASE, \ + ISP_FE_CSIS_INT0_CTX7_PHY_TIMING_ERR) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_ERR_ID \ EVENT_ID(ISP_FE_CSIS_INT0_CTX8_BASE, \ @@ -6635,6 +6743,12 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_MAL_CRC \ EVENT_ID(ISP_FE_CSIS_INT0_CTX8_BASE, \ ISP_FE_CSIS_INT0_CTX8_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_ERR_SKEW \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX8_BASE, \ + ISP_FE_CSIS_INT0_CTX8_ERR_SKEW) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_ERR_DESKEW_OVER \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX8_BASE, \ + ISP_FE_CSIS_INT0_CTX8_ERR_DESKEW_OVER) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_RX_INVALID_CODE_HS_LANE0 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX8_BASE, \ ISP_FE_CSIS_INT0_CTX8_RX_INVALID_CODE_HS_LANE0) @@ -6671,6 +6785,9 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_ERR_SOT_SYNC_HS_LANE3 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX8_BASE, \ ISP_FE_CSIS_INT0_CTX8_ERR_SOT_SYNC_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX8_PHY_TIMING_ERR \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX8_BASE, \ + ISP_FE_CSIS_INT0_CTX8_PHY_TIMING_ERR) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_ERR_ID \ EVENT_ID(ISP_FE_CSIS_INT0_CTX9_BASE, \ @@ -6693,6 +6810,12 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_MAL_CRC \ EVENT_ID(ISP_FE_CSIS_INT0_CTX9_BASE, \ ISP_FE_CSIS_INT0_CTX9_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_ERR_SKEW \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX9_BASE, \ + ISP_FE_CSIS_INT0_CTX9_ERR_SKEW) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_ERR_DESKEW_OVER \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX9_BASE, \ + ISP_FE_CSIS_INT0_CTX9_ERR_DESKEW_OVER) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_RX_INVALID_CODE_HS_LANE0 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX9_BASE, \ ISP_FE_CSIS_INT0_CTX9_RX_INVALID_CODE_HS_LANE0) @@ -6729,6 +6852,9 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_ERR_SOT_SYNC_HS_LANE3 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX9_BASE, \ ISP_FE_CSIS_INT0_CTX9_ERR_SOT_SYNC_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX9_PHY_TIMING_ERR \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX9_BASE, \ + ISP_FE_CSIS_INT0_CTX9_PHY_TIMING_ERR) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_ERR_ID \ EVENT_ID(ISP_FE_CSIS_INT0_CTX10_BASE, \ @@ -6751,6 +6877,12 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_MAL_CRC \ EVENT_ID(ISP_FE_CSIS_INT0_CTX10_BASE, \ ISP_FE_CSIS_INT0_CTX10_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_ERR_SKEW \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX10_BASE, \ + ISP_FE_CSIS_INT0_CTX10_ERR_SKEW) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_ERR_DESKEW_OVER \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX10_BASE, \ + ISP_FE_CSIS_INT0_CTX10_ERR_DESKEW_OVER) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_RX_INVALID_CODE_HS_LANE0 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX10_BASE, \ ISP_FE_CSIS_INT0_CTX10_RX_INVALID_CODE_HS_LANE0) @@ -6787,6 +6919,9 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_ERR_SOT_SYNC_HS_LANE3 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX10_BASE, \ ISP_FE_CSIS_INT0_CTX10_ERR_SOT_SYNC_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX10_PHY_TIMING_ERR \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX10_BASE, \ + ISP_FE_CSIS_INT0_CTX10_PHY_TIMING_ERR) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_ERR_ID \ EVENT_ID(ISP_FE_CSIS_INT0_CTX11_BASE, \ @@ -6809,6 +6944,12 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_MAL_CRC \ EVENT_ID(ISP_FE_CSIS_INT0_CTX11_BASE, \ ISP_FE_CSIS_INT0_CTX11_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_ERR_SKEW \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX11_BASE, \ + ISP_FE_CSIS_INT0_CTX11_ERR_SKEW) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_ERR_DESKEW_OVER \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX11_BASE, \ + ISP_FE_CSIS_INT0_CTX11_ERR_DESKEW_OVER) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_RX_INVALID_CODE_HS_LANE0 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX11_BASE, \ ISP_FE_CSIS_INT0_CTX11_RX_INVALID_CODE_HS_LANE0) @@ -6845,6 +6986,9 @@ #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_ERR_SOT_SYNC_HS_LANE3 \ EVENT_ID(ISP_FE_CSIS_INT0_CTX11_BASE, \ ISP_FE_CSIS_INT0_CTX11_ERR_SOT_SYNC_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT0_CTX11_PHY_TIMING_ERR \ + EVENT_ID(ISP_FE_CSIS_INT0_CTX11_BASE, \ + ISP_FE_CSIS_INT0_CTX11_PHY_TIMING_ERR) #define LWIS_PLATFORM_EVENT_ID_ISP_FE_CSIS_INT1_CTX0_LINE_END \ EVENT_ID(ISP_FE_CSIS_INT1_CTX0_BASE, \ diff --git a/include/soc/google/bcl.h b/include/soc/google/bcl.h index 67d29be5d..a028c6999 100644 --- a/include/soc/google/bcl.h +++ b/include/soc/google/bcl.h @@ -38,11 +38,16 @@ /* This driver determines if HW was throttled due to SMPL/OCP */ -#define DELTA_10MS (10 * NSEC_PER_MSEC) -#define DELTA_50MS (50 * NSEC_PER_MSEC) -#define VSHUNT_MULTIPLIER 10000 -#define MILLI_TO_MICRO 1000 -#define IRQ_ENABLE_DELAY_MS 50 +#define DELTA_5MS (5 * NSEC_PER_MSEC) +#define DELTA_10MS (10 * NSEC_PER_MSEC) +#define VSHUNT_MULTIPLIER 10000 +#define MILLI_TO_MICRO 1000 +#define IRQ_ENABLE_DELAY_MS 50 +#define PWRWARN_LPF_RFFE_DATA_MAIN_0 0xCF +#define PWRWARN_LPF_RFFE_DATA_MAIN_1 0xD0 +#define PWRWARN_THRESH_MAIN 0x3C +#define PWRWARN_LPF_RFFE_MSB_MASK 0x0F +#define PWRWARN_LPF_RFFE_RSHIFT 4 enum CPU_CLUSTER { LITTLE_CLUSTER, @@ -267,6 +272,8 @@ struct bcl_device { int cpu0_cluster; int cpu1_cluster; int cpu2_cluster; + + bool rffe_mitigation_enable; }; extern void google_bcl_irq_update_lvl(struct bcl_device *bcl_dev, int index, unsigned int lvl); |