diff options
| author | Sajid Dalvi <sdalvi@google.com> | 2023-07-19 22:51:40 -0500 |
|---|---|---|
| committer | Ting-Hsin Chen <tinghsin@google.com> | 2023-07-20 11:49:53 +0000 |
| commit | f9bf2505ee99c21c49c5e8f0095278e7c75fcb0b (patch) | |
| tree | 697e79910ab61bf5b3bbcd891dceac7f8e28b7f9 | |
| parent | 8bc113f56c5adabd649ceb29e5de6e49dbd34ee1 (diff) | |
| download | gs-f9bf2505ee99c21c49c5e8f0095278e7c75fcb0b.tar.gz | |
pcie: exynos: Increase delay between SoC OSCCLK and OSCCLK
While powering off the PCIe PHY increase the delay between switching
from SoC OSCCLK to OSCCLK. This prevents an ITMON while accessing the
Ext PLL register at 0x1213C700 during the next pcie poweron.
Bug: 287328303
Change-Id: I4f26126590166bd17ae88f1202da46398547ea63
Signed-off-by: Sajid Dalvi <sdalvi@google.com>
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-exynos-zuma-rc-cal.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/controller/dwc/pcie-exynos-zuma-rc-cal.c b/drivers/pci/controller/dwc/pcie-exynos-zuma-rc-cal.c index c351a7dd4..76949c849 100644 --- a/drivers/pci/controller/dwc/pcie-exynos-zuma-rc-cal.c +++ b/drivers/pci/controller/dwc/pcie-exynos-zuma-rc-cal.c @@ -105,7 +105,7 @@ void exynos_pcie_rc_phy_all_pwrdn(struct exynos_pcie *exynos_pcie, int ch_num) writel(0x0A, phy_base_regs + 0x000C); // For the process time of clock switching from SOC OSCCLK to OSCCLK - udelay(50); + udelay(100); // External PLL for PCIe PHY val = readl(udbg_base_regs + 0xC700) | (0x1 << 1); |