Revert "pcie: exynos: check pcie register accesss"

This reverts commit 38d6e0ae8051b3bd5443b631c813e4285aef1330.

Bug: 287328303
Change-Id: I6dcd83dd22de43e5726c7f14443594a3510ea8e4
Signed-off-by: Sajid Dalvi <sdalvi@google.com>

2 files changed, 3 insertions, 28 deletions

diff --git a/arch/arm64/boot/dts/google/zuma-pcie.dtsi b/arch/arm64/boot/dts/google/zuma-pcie.dtsi
index 8f5350a1b..818188658 100644
--- a/arch/arm64/boot/dts/google/zuma-pcie.dtsi
+++ b/arch/arm64/boot/dts/google/zuma-pcie.dtsi
@@ -13,7 +13,7 @@
 		compatible = "samsung,exynos-pcie-rc";
 		gpios = <&gph0 0 0x1 /* PERST */>;
 		reg = <0x0 0x12100000 0x2000	/* elbi base */
-			0x0 0x12110000 0x7000   /* soc base */
+			0x0 0x12110000 0x5000   /* soc base */
 			0x0 0x12130000 0xD000   /* udbg base */
 			0x0 0x12140000 0x3000	/* phy base */
 			0x0 0x12020000 0x2000	/* sysreg base */
diff --git a/drivers/pci/controller/dwc/pcie-exynos-zuma-rc-cal.c b/drivers/pci/controller/dwc/pcie-exynos-zuma-rc-cal.c
index 2a1398074..46a8d37de 100644
--- a/drivers/pci/controller/dwc/pcie-exynos-zuma-rc-cal.c
+++ b/drivers/pci/controller/dwc/pcie-exynos-zuma-rc-cal.c
@@ -110,7 +110,6 @@ void exynos_pcie_rc_phy_all_pwrdn(struct exynos_pcie *exynos_pcie, int ch_num)
 		// External PLL for PCIe PHY
 		val = readl(udbg_base_regs + 0xC700) | (0x1 << 1);
 		writel(val, udbg_base_regs + 0xC700);
-		udelay(10);
 	}
 }
 
@@ -119,8 +118,6 @@ void exynos_pcie_rc_phy_all_pwrdn_clear(struct exynos_pcie *exynos_pcie, int ch_
 {
 	void __iomem *phy_base_regs = exynos_pcie->phy_base;
 	void __iomem *udbg_base_regs = exynos_pcie->udbg_base;
-	void __iomem *phy_pcs_base_regs = exynos_pcie->phy_pcs_base;
-	void __iomem *soc_base_regs = exynos_pcie->soc_base;
 	u32 val, val1, val2;
 
 	dev_dbg(exynos_pcie->pci->dev, "[CAL: %s]\n", __func__);
@@ -165,12 +162,8 @@ void exynos_pcie_rc_phy_all_pwrdn_clear(struct exynos_pcie *exynos_pcie, int ch_
 
 			// 0x2b00 : HSI1_CONFIGURATION
 			// [0] : 0 is off / 1 is on
-
-			// setting HSI conf to 0 causes an ITMON
-			// so comment that out.
-			//regmap_update_bits(exynos_pcie->pmureg,
-			//			0x2B00, 0x1, 0x0);
-
+			regmap_update_bits(exynos_pcie->pmureg,
+						0x2B00, 0x1, 0x0);
 			regmap_update_bits(exynos_pcie->pmureg,
 						0x2B00, 0x1, 0x1);
 
@@ -198,24 +191,6 @@ void exynos_pcie_rc_phy_all_pwrdn_clear(struct exynos_pcie *exynos_pcie, int ch_
 
 		}
 
-		/* HSI1 block check routine for ITMON issue */
-		/* 1. check soc_ctrl : it use 'bus_clock' */
-		writel(0x1, soc_base_regs + 0x6004);
-		val = readl(soc_base_regs + 0x6004);
-		writel(0x0, soc_base_regs + 0x6004);
-		val2 = readl(soc_base_regs + 0x6004);
-		dev_info(exynos_pcie->pci->dev, "Check soc %#x, %#x\n",
-			 val2, val);
-
-		/* 2. check pcs: it use clock from mux */
-		val = readl(phy_pcs_base_regs);
-		writel(0xffffffff, phy_pcs_base_regs);
-		val2 = readl(phy_pcs_base_regs);
-		writel(val, phy_pcs_base_regs);
-		val = readl(phy_pcs_base_regs);
-		dev_info(exynos_pcie->pci->dev, "Check PCS %#x, %#x\n",
-			 val2, val);
-
 		val = readl(udbg_base_regs + 0xC700) & ~(0x1 << 1);
 		writel(val, udbg_base_regs + 0xC700);
 		udelay(100);