diff options
| author | tinghsin <tinghsin@google.com> | 2023-08-01 12:50:49 +0800 |
|---|---|---|
| committer | Ting-Hsin Chen <tinghsin@google.com> | 2023-08-02 01:31:04 +0000 |
| commit | 8a03208d23dea9f82a97f8aedbd447b39d624546 (patch) | |
| tree | 1ed49d6dd843629653dd4627f4c052e11f617206 | |
| parent | fe9a735c2fed13b8cd47b7e0dd7fb3d6575a8857 (diff) | |
| download | gs-8a03208d23dea9f82a97f8aedbd447b39d624546.tar.gz | |
pcie: exynos: Add 10us delay after turning off EXT PLL
Bug: 287328303
Change-Id: Ia89ac02f02748d5db5d9209087fe8ff6526f2a46
Signed-off-by: tinghsin <tinghsin@google.com>
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-exynos-zuma-rc-cal.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-exynos-zuma-rc-cal.c b/drivers/pci/controller/dwc/pcie-exynos-zuma-rc-cal.c index df371f40d..2361de015 100644 --- a/drivers/pci/controller/dwc/pcie-exynos-zuma-rc-cal.c +++ b/drivers/pci/controller/dwc/pcie-exynos-zuma-rc-cal.c @@ -110,6 +110,7 @@ void exynos_pcie_rc_phy_all_pwrdn(struct exynos_pcie *exynos_pcie, int ch_num) // External PLL for PCIe PHY val = readl(udbg_base_regs + 0xC700) | (0x1 << 1); writel(val, udbg_base_regs + 0xC700); + udelay(10); } } |