usb: phy: update eUSB phy code

Update eUSB phy cal

1. Define the condition for applying the phy cal
 a. ZUMA
  - eUSB phy controller version = 0x0700

2. Update the phy cal
 a. ZUMA
  - fix fsls_vref_tune to 0 related to eusb-repeater compatibility

Bug: 306144368

Change-Id: Iddacf1b094782a81741a7de79921ea46699516b9
Signed-off-by: Shin <cm2.shin@samsung.com>

2 files changed, 98 insertions, 24 deletions

diff --git a/drivers/phy/samsung/phy-exynos-eusb.c b/drivers/phy/samsung/phy-exynos-eusb.c
index ed245f758..5d3b1b3c0 100644
--- a/drivers/phy/samsung/phy-exynos-eusb.c
+++ b/drivers/phy/samsung/phy-exynos-eusb.c
@@ -131,17 +131,36 @@ void phy_exynos_eusb_initiate(struct exynos_usbphy_info *info)
 		 * phy_cfg_pll_fb_div[11:0] 	: 368
 		 * phy_cfg_pll_ref_div[3:0]		: 0
 		 */
-		/* ref_freq_sel */
-		((EUSBPHY_REG_CMN_CTRL_p) (&reg))->b.ref_freq_sel = 0;
-		writel(reg, base + EUSBCON_REG_CMN_CTRL);
-		/* phy_cfg_pll_fb_div[11:0] */
-		reg = readl(base + EUSBCON_REG_PLLCFG0);
-		((EUSBPHY_REG_PLLCFG0_p) (&reg))->b.pll_fb_div = 368;
-		writel(reg, base + EUSBCON_REG_PLLCFG0);
-		/* phy_cfg_pll_ref_div[3:0]	*/
-		reg = readl(base + EUSBCON_REG_PLLCFG1);
-		((EUSBPHY_REG_PLLCFG1_p) (&reg))->b.pll_ref_div = 0;
-		writel(reg, base + EUSBCON_REG_PLLCFG1);
+		 if ((EXYNOS_USBCON_VER_MINOR(info->version) == 0) ||
+			(EXYNOS_USBCON_VER_MINOR(info->version) == 1)) { // 4nm eusb phy
+			/* ref_freq_sel */
+			((EUSBPHY_REG_CMN_CTRL_p) (&reg))->b.ref_freq_sel = 0;
+			writel(reg, base + EUSBCON_REG_CMN_CTRL);
+			/* phy_cfg_pll_fb_div[11:0] */
+			reg = readl(base + EUSBCON_REG_PLLCFG0);
+			((EUSBPHY_REG_PLLCFG0_p) (&reg))->b.pll_fb_div = 368;
+			writel(reg, base + EUSBCON_REG_PLLCFG0);
+			/* phy_cfg_pll_ref_div[3:0] */
+			reg = readl(base + EUSBCON_REG_PLLCFG1);
+			((EUSBPHY_REG_PLLCFG1_p) (&reg))->b.pll_ref_div = 0;
+			writel(reg, base + EUSBCON_REG_PLLCFG1);
+		} else if (EXYNOS_USBCON_VER_MINOR(info->version) == 2) { // 3nm eusb phy
+			/* ref_freq_sel */
+			((EUSBPHY_REG_CMN_CTRL_p) (&reg))->b.ref_freq_sel = 0;
+			writel(reg, base + EUSBCON_REG_CMN_CTRL);
+			/* phy_cfg_pll_fb_div[11:0] */
+			reg = readl(base + EUSBCON_REG_PLLCFG0);
+			((EUSBPHY_REG_PLLCFG0_p) (&reg))->b.pll_fb_div = 368;
+			((EUSBPHY_REG_PLLCFG0_p) (&reg))->b.pll_int_cntrl = 4;
+			((EUSBPHY_REG_PLLCFG0_p) (&reg))->b.pll_gmp_cntrl = 2;
+			writel(reg, base + EUSBCON_REG_PLLCFG0);
+			/* phy_cfg_pll_ref_div[3:0]	*/
+			reg = readl(base + EUSBCON_REG_PLLCFG1);
+			((EUSBPHY_REG_PLLCFG1_p) (&reg))->b.pll_ref_div = 0;
+			((EUSBPHY_REG_PLLCFG1_p) (&reg))->b.pll_vref_tune = 0;
+			((EUSBPHY_REG_PLLCFG1_p) (&reg))->b.pll_prop_cntrl = 8;
+			writel(reg, base + EUSBCON_REG_PLLCFG1);
+		}
 		pr_info("%s: 19.2\n", __func__);
 	} else if ((info->refclk == USBPHY_REFCLK_DIFF_20MHZ) ||
 			(info->refclk == USBPHY_REFCLK_EXT_20MHZ)) {
@@ -188,17 +207,36 @@ void phy_exynos_eusb_initiate(struct exynos_usbphy_info *info)
 		 * phy_cfg_pll_fb_div[11:0] 	: 263
 		 * phy_cfg_pll_ref_div[3:0]		: 0
 		 */
-		/* ref_freq_sel */
-		((EUSBPHY_REG_CMN_CTRL_p) (&reg))->b.ref_freq_sel = 3;
-		writel(reg, base + EUSBCON_REG_CMN_CTRL);
-		/* phy_cfg_pll_fb_div[11:0] */
-		reg = readl(base + EUSBCON_REG_PLLCFG0);
-		((EUSBPHY_REG_PLLCFG0_p) (&reg))->b.pll_fb_div = 263;
-		writel(reg, base + EUSBCON_REG_PLLCFG0);
-		/* phy_cfg_pll_ref_div[3:0]	*/
-		reg = readl(base + EUSBCON_REG_PLLCFG1);
-		((EUSBPHY_REG_PLLCFG1_p) (&reg))->b.pll_ref_div = 0;
-		writel(reg, base + EUSBCON_REG_PLLCFG1);
+		 if ((EXYNOS_USBCON_VER_MINOR(info->version) == 0) ||
+			(EXYNOS_USBCON_VER_MINOR(info->version) == 1)) { // 4nm eusb phy
+			/* ref_freq_sel */
+			((EUSBPHY_REG_CMN_CTRL_p) (&reg))->b.ref_freq_sel = 3;
+			writel(reg, base + EUSBCON_REG_CMN_CTRL);
+			/* phy_cfg_pll_fb_div[11:0] */
+			reg = readl(base + EUSBCON_REG_PLLCFG0);
+			((EUSBPHY_REG_PLLCFG0_p) (&reg))->b.pll_fb_div = 263;
+			writel(reg, base + EUSBCON_REG_PLLCFG0);
+			/* phy_cfg_pll_ref_div[3:0] */
+			reg = readl(base + EUSBCON_REG_PLLCFG1);
+			((EUSBPHY_REG_PLLCFG1_p) (&reg))->b.pll_ref_div = 0;
+			writel(reg, base + EUSBCON_REG_PLLCFG1);
+		} else if (EXYNOS_USBCON_VER_MINOR(info->version) == 2) { // 3nm eusb phy
+			/* ref_freq_sel */
+			((EUSBPHY_REG_CMN_CTRL_p) (&reg))->b.ref_freq_sel = 3;
+			writel(reg, base + EUSBCON_REG_CMN_CTRL);
+			/* phy_cfg_pll_fb_div[11:0] */
+			reg = readl(base + EUSBCON_REG_PLLCFG0);
+			((EUSBPHY_REG_PLLCFG0_p) (&reg))->b.pll_fb_div = 263;
+			((EUSBPHY_REG_PLLCFG0_p) (&reg))->b.pll_int_cntrl = 4;
+			((EUSBPHY_REG_PLLCFG0_p) (&reg))->b.pll_gmp_cntrl = 2;
+			writel(reg, base + EUSBCON_REG_PLLCFG0);
+			/* phy_cfg_pll_ref_div[3:0]	*/
+			reg = readl(base + EUSBCON_REG_PLLCFG1);
+			((EUSBPHY_REG_PLLCFG1_p) (&reg))->b.pll_ref_div = 0;
+			((EUSBPHY_REG_PLLCFG1_p) (&reg))->b.pll_vref_tune = 0;
+			((EUSBPHY_REG_PLLCFG1_p) (&reg))->b.pll_prop_cntrl = 7;
+			writel(reg, base + EUSBCON_REG_PLLCFG1);
+		}
 		pr_info("%s: 26\n", __func__);
 	} else if ((info->refclk == USBPHY_REFCLK_DIFF_48MHZ) ||
 			(info->refclk == USBPHY_REFCLK_EXT_48MHZ)) {
@@ -222,6 +260,24 @@ void phy_exynos_eusb_initiate(struct exynos_usbphy_info *info)
 		/* Not supported clock, so skip */
 	}
 
+	if (EXYNOS_USBCON_VER_MINOR(info->version) == 0) {
+		/* use default value
+			26MHz : 3 - pll_cpbias_cntrl
+			19.2MHz : 1 - pll_cpbias_cntrl
+		*/
+	} else if (EXYNOS_USBCON_VER_MINOR(info->version) == 1) {
+		reg = readl(base + EUSBCON_REG_PLLCFG0);
+		((EUSBPHY_REG_PLLCFG0_p) (&reg))->b.pll_cpbias_cntrl = 0;
+		writel(reg, base + EUSBCON_REG_PLLCFG0);
+	} else if (EXYNOS_USBCON_VER_MINOR(info->version) == 2) {
+		reg = readl(base + EUSBCON_REG_PLLCFG0);
+		((EUSBPHY_REG_PLLCFG0_p) (&reg))->b.pll_cpbias_cntrl = 0;
+		writel(reg, base + EUSBCON_REG_PLLCFG0);
+	}
+
+	reg = readl(base + EUSBCON_REG_TXTUNE);
+	((EUSBPHY_REG_TXTUNE_p) (&reg))->b.fsls_vref_tune = 0;
+	writel(reg, base + EUSBCON_REG_TXTUNE);
 	phy_exynos_eusb_tune(info);
 
 	/* 3. Set all inputs to a default state as necessary for
@@ -292,9 +348,16 @@ void phy_exynos_eusb_terminate(struct exynos_usbphy_info *info)
 
 	base = info->regs_base;
 
+	udelay(2500);
+	reg = readl(base + EUSBCON_REG_CMN_CTRL);
+	((EUSBPHY_REG_CMN_CTRL_p) (&reg))->b.phy_enable = 0;
+	writel(reg, base + EUSBCON_REG_CMN_CTRL);
 	reg = readl(base + EUSBCON_REG_RST_CTRL);
 	((EUSBPHY_REG_RST_CTRL_p) (&reg))->b.phy_reset = 1;
 	writel(reg, base + EUSBCON_REG_RST_CTRL);
+	reg = readl(base + EUSBCON_REG_TESTSE);
+	((EUSBPHY_REG_TESTSE_p) (&reg))->b.test_iddq = 1;
+	writel(reg, base + EUSBCON_REG_TESTSE);
 }
 
 u8 phy_exynos_eusb_get_eusb_state(struct exynos_usbphy_info *info)
diff --git a/drivers/phy/samsung/phy-samsung-usb-cal.h b/drivers/phy/samsung/phy-samsung-usb-cal.h
index 68d2ae8a1..507b7c3f9 100644
--- a/drivers/phy/samsung/phy-samsung-usb-cal.h
+++ b/drivers/phy/samsung/phy-samsung-usb-cal.h
@@ -46,11 +46,14 @@
 #define EXYNOS_USBCON_VER_06_MAX 0x06FF
 
 /* eUSB phy contorller */
-#define EXYNOS_USBCON_VER_07_0_0 0x0700 /* eUSB PHY controller */
+#define EXYNOS_USBCON_VER_07_0_0 0x0700 /* 4nm cp_bias_cntrl = default - eUSB PHY controller */
+#define EXYNOS_USBCON_VER_07_0_1 0x0701 /* 4nm cp_bias_cntrl = 0 - eUSB PHY controller */
+#define EXYNOS_USBCON_VER_07_0_2 0x0702 /* 3nm cp_bias_cntrl = 0 - eUSB PHY controller */
 #define EXYNOS_USBCON_VER_07_8_0 0x0780 /* dwc eUSB PHY register interface */
 
 /* synopsys usbdp phy contorller */
-#define EXYNOS_USBCON_VER_08_0_0 0x0800 /* dwc usb3p2/dp PHY controller */
+#define EXYNOS_USBCON_VER_08_0_0 0x0800 /* dwc usb3p2/dp PHY controller 9865 */
+#define EXYNOS_USBCON_VER_08_0_1 0x0801 /* dwc usb3p2/dp PHY controller, 9875 */
 
 #define EXYNOS_USBCON_VER_F2_0_0	0xF200
 #define EXYNOS_USBCON_VER_F2_MAX	0xF2FF
@@ -260,8 +263,14 @@ struct exynos_usbphy_info {
 
 	/* Dual PHY */
 	bool dual_phy;
+
+	/* SOF tick for UDMA */
+	int sel_sof;
+	int usbdp_mode;
+	unsigned int add_val_magic;
 };
 
+#define CAL_INFO_ADD_INFO_MAGIC 0xCA10ADD4
 struct usb_eom_result_s {
 	u32 phase;
 	u32 vref;
@@ -271,5 +280,7 @@ struct usb_eom_result_s {
 #define EOM_PH_SEL_MAX      72
 #define EOM_DEF_VREF_MAX    256
 
+#define SNPS_USBDP_ROM_MODE 0
+#define SNPS_USBDP_RAM_MODE 1
 void phy_usb_exynos_register_cal_infor(struct exynos_usbphy_info *cal_info);
 #endif	/* __PHY_SAMSUNG_USB_FW_CAL_H__ */