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authorMark Rawling <mwr@google.com>2022-07-11 19:19:44 -0700
committerMark Rawling <mwr@google.com>2022-07-11 19:23:51 -0700
commitc38880c3ecb5e14ca499dcce96bc7227dab0b8a0 (patch)
tree012b9614fcd90b944b09b7813372310241afe7a5
parentb546fb648a5a04c0c3abe55033b58c066247e6c5 (diff)
downloadnanohub-c38880c3ecb5e14ca499dcce96bc7227dab0b8a0.tar.gz
Disable 32KHz clock prior to MCU boot
Uses SPMI to disable the MCU peripheral clock. Bug: 236890964 Test: logic analyzer Change-Id: Ie4fe861ba5584e721b58ebaca72c3195fc5d8810 Signed-off-by: Mark Rawling <mwr@google.com>
-rw-r--r--main.c13
-rw-r--r--nanohub.h1
2 files changed, 14 insertions, 0 deletions
diff --git a/main.c b/main.c
index 50c22fc..91c7509 100644
--- a/main.c
+++ b/main.c
@@ -822,6 +822,11 @@ static void __nanohub_hw_reset(struct nanohub_data *data, int boot_mode)
if (ret != 0)
pr_warn("nanohub: failed to disable afe_tx_sup ret=%x\n", ret);
+ // Disable 32KHz clock prior to MCU boot
+ ret = regmap_write(pdata->pmic_regmap, pdata->clk32_control_reg, 0);
+ if (ret != 0)
+ pr_warn("nanohub: failed to disable 32KHz clock ret=%x\n", ret);
+
// Reset MCU
gpio_set_value(pdata->nreset_gpio, 0);
usleep_range(1000, 2000);
@@ -1863,6 +1868,14 @@ static struct nanohub_platform_data *nanohub_parse_dt(struct device *dev)
goto free_pdata;
}
+ /* required MCU 32KHz clock control register */
+ ret = of_property_read_u32(dt, "sensorhub,clk32_control",
+ &pdata->clk32_control_reg);
+ if (ret < 0) {
+ pr_err("nanohub: missing sensorhub,clk32_control in device tree\n");
+ goto free_pdata;
+ }
+
#ifdef CONFIG_NANOHUB_BL_ST
/* optional (bl-max-frequency) */
pdata->bl_max_speed_hz = BL_MAX_SPEED_HZ;
diff --git a/nanohub.h b/nanohub.h
index 3b528ea..5693a91 100644
--- a/nanohub.h
+++ b/nanohub.h
@@ -16,6 +16,7 @@ struct nanohub_platform_data {
u32 spi_cs_gpio;
struct regmap *pmic_regmap;
u32 afe_control_reg;
+ u32 clk32_control_reg;
#ifdef CONFIG_NANOHUB_BL_ST
u32 bl_max_speed_hz;
u32 bl_addr;