diff options
| author | Kevin Park <youngeun.park@arm.com> | 2023-07-26 12:35:54 +0100 |
|---|---|---|
| committer | Guus Sliepen <gsliepen@google.com> | 2023-08-22 08:01:38 +0000 |
| commit | a0a0021e080c185aaff8b7173604de78e30bf65b (patch) | |
| tree | fe0e802ba19fab539841f58757a9dd8e343e7ebb | |
| parent | ca522e4491584d5a2a5f122ee90e3edb3581182b (diff) | |
| download | gpu-a0a0021e080c185aaff8b7173604de78e30bf65b.tar.gz | |
[Official] MIDCET-4806,GPUCORE-38732 Continue FLUSH_MEM after power transition timeout
This patch continues FLUSH_MEM operation at function caller and increases the timeout value for the core power transition.
Change-Id: I8cf5417976ab31b8d1e9e33e6359a91455d37144
(cherry picked from commit 71f7017252aabbb0013a2f151d894959b7c7c226)
Bug: 295942377
Provenance: https://code.ipdelivery.arm.com/c/GPU/mali-ddk/+/5812
| -rw-r--r-- | mali_kbase/mmu/mali_kbase_mmu_hw_direct.c | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/mali_kbase/mmu/mali_kbase_mmu_hw_direct.c b/mali_kbase/mmu/mali_kbase_mmu_hw_direct.c index 122e9ef..50eeb4e 100644 --- a/mali_kbase/mmu/mali_kbase_mmu_hw_direct.c +++ b/mali_kbase/mmu/mali_kbase_mmu_hw_direct.c @@ -174,7 +174,7 @@ static int write_cmd(struct kbase_device *kbdev, int as_nr, u32 cmd) #if MALI_USE_CSF && !IS_ENABLED(CONFIG_MALI_NO_MALI) static int wait_cores_power_trans_complete(struct kbase_device *kbdev) { -#define WAIT_TIMEOUT 1000 /* 1ms timeout */ +#define WAIT_TIMEOUT 50000 /* 50ms timeout */ #define DELAY_TIME_IN_US 1 const int max_iterations = WAIT_TIMEOUT; int loop; @@ -194,7 +194,9 @@ static int wait_cores_power_trans_complete(struct kbase_device *kbdev) } if (loop == max_iterations) { - dev_warn(kbdev->dev, "SHADER_PWRTRANS set for too long"); + dev_warn(kbdev->dev, "SHADER_PWRTRANS %08x%08x set for too long", + kbase_reg_read(kbdev, GPU_CONTROL_REG(SHADER_PWRTRANS_HI)), + kbase_reg_read(kbdev, GPU_CONTROL_REG(SHADER_PWRTRANS_LO))); return -ETIMEDOUT; } @@ -230,9 +232,8 @@ static int apply_hw_issue_GPU2019_3901_wa(struct kbase_device *kbdev, * the workaround can be safely skipped. */ if (kbdev->pm.backend.l2_state != KBASE_L2_OFF) { - if (*mmu_cmd != AS_COMMAND_FLUSH_MEM) { - dev_warn(kbdev->dev, - "Unexpected mmu command received"); + if (unlikely(*mmu_cmd != AS_COMMAND_FLUSH_MEM)) { + dev_warn(kbdev->dev, "Unexpected MMU command(%u) received", *mmu_cmd); ret = -EINVAL; goto unlock; } @@ -502,8 +503,14 @@ static int mmu_hw_do_flush(struct kbase_device *kbdev, struct kbase_as *as, if (mmu_cmd == AS_COMMAND_FLUSH_MEM) { ret = apply_hw_issue_GPU2019_3901_wa(kbdev, &mmu_cmd, as->number, hwaccess_locked); - if (ret) - return ret; + if (ret) { + dev_warn(kbdev->dev, + "Failed to apply WA for HW issue when doing MMU flush op on VA range %llx-%llx for AS %u", + op_param->vpfn << PAGE_SHIFT, + ((op_param->vpfn + op_param->nr) << PAGE_SHIFT) - 1, + as->number); + /* Continue with the MMU flush operation */ + } } #endif |