Merge android14-gs-pixel-5.15-24Q2 into android14-gs-pixel-5.15

SBMerger: 571992243
Change-Id: I8b5a827aaf34007a2a6f18b39ea5bd26ee739532
Signed-off-by: SecurityBot <android-nexus-securitybot@system.gserviceaccount.com>

3 files changed, 79 insertions, 94 deletions

diff --git a/samsung/cal_9865/dp_reg.c b/samsung/cal_9865/dp_reg.c
index 7b43270..28d27bc 100644
--- a/samsung/cal_9865/dp_reg.c
+++ b/samsung/cal_9865/dp_reg.c
@@ -496,17 +496,17 @@ static void dpphy_reg_set_config10_tx_eq_pre(u32 eq_pre_val, u32 eq_pre_mask)
 	dp_phy_write_mask(SST1, DP_CONFIG10, eq_pre_val, eq_pre_mask);
 }
 
-static void dpphy_reg_set_config11_tx_pstate(enum lane_usage lane)
+static void dpphy_reg_set_config11_tx_pstate(u32 en, enum lane_usage lane)
 {
-	/* P2(0b11) is power down */
-	u32 val = 0;
+	u32 val = DP_TX_PSTATE_SET_0LANES;
 
-	if (lane == DP_USE_0_LANES)
-		val = DP_TX_PSTATE_SET_0LANES; // Power Down for 4 Lanes
+	/* P2(0b11) is power down */
+	if (!en || lane == DP_USE_0_LANES)
+		val = DP_TX_PSTATE_SET_0LANES;
 	else if (lane == DP_USE_2_LANES)
-		val = DP_TX_PSTATE_SET_2LANES; // Power Up for 2 lanes
+		val = DP_TX_PSTATE_SET_2LANES;
 	else if (lane == DP_USE_4_LANES)
-		val = DP_TX_PSTATE_SET_4LANES; // Power Up for 4 lanes
+		val = DP_TX_PSTATE_SET_4LANES;
 
 	dp_phy_write_mask(SST1, DP_CONFIG11, val, DP_TX_PSTATE_MASK);
 }
@@ -515,8 +515,7 @@ static void dpphy_reg_wait_config12_tx_ack(enum lane_usage lane)
 {
 	u32 val = 0;
 
-	if (readl_poll_timeout_atomic(regs_dp[REGS_PHY][SST1].regs +
-					      DP_CONFIG12,
+	if (readl_poll_timeout_atomic(regs_dp[REGS_PHY][SST1].regs + DP_CONFIG12,
 				      val, !DP_TX_ACK_GET(val), 10, 2000)) {
 		cal_log_err(0, "is timeout. Fail to ack DP TX.\n");
 		cal_log_err(0, "val(0x%08x) DP_CONFIG12 read:0x%08x\n", val,
@@ -524,34 +523,30 @@ static void dpphy_reg_wait_config12_tx_ack(enum lane_usage lane)
 	}
 }
 
-static void dpphy_reg_set_config12_status_update(enum lane_usage lane)
+static void dpphy_reg_set_config12_status_update(void)
 {
 	u32 val = 0;
 
-	if (lane == DP_USE_0_LANES)
-		return;
-	else if (lane == DP_USE_2_LANES)
-		val = DP_TX_REQ_STATUS_SET_2LANES;
-	else if (lane == DP_USE_4_LANES)
-		val = DP_TX_REQ_STATUS_SET_4LANES;
-
-	dp_phy_write_mask(SST1, DP_CONFIG12, val, DP_TX_REQ_STATUS_MASK);
+	/* Set DP TX Request */
+	dp_phy_write_mask(SST1, DP_CONFIG12, DP_TX_REQ_SET_4LANES, DP_TX_REQ_MASK);
 
-	if (readl_poll_timeout_atomic(
-		    regs_dp[REGS_PHY][SST1].regs + DP_CONFIG12, val,
-		    !DP_TX_REQ_STATUS_GET(val), 10, 2000)) {
-		cal_log_err(0, "is timeout. Fail to update DP TX status.\n");
+	/* Wait for DP TX Request Clear */
+	if (readl_poll_timeout_atomic(regs_dp[REGS_PHY][SST1].regs + DP_CONFIG12,
+				      val, !DP_TX_REQ_GET(val), 10, 2000)) {
+		cal_log_err(0, "is timeout. Fail to request DP TX update.\n");
 		cal_log_err(0, "val(0x%08x) DP_CONFIG12 read:0x%08x\n", val,
 			    readl(regs_dp[REGS_PHY][SST1].regs + DP_CONFIG12));
-	} else
-		cal_log_debug(0, "Success to update DP TX status.\n");
+	}
+
+	/* Wait for TX Acknowledge to confirm DP TX request is applied */
+	dpphy_reg_wait_config12_tx_ack(DP_USE_4_LANES);
 }
 
-static void dpphy_reg_set_config12_tx_mpllb_en(enum lane_usage lane)
+static void dpphy_reg_set_config12_tx_mpllb_en(u32 en, enum lane_usage lane)
 {
-	u32 val = 0;
+	u32 val = DP_TX_MPLL_EN_SET_0LANES;
 
-	if (lane == DP_USE_0_LANES)
+	if (!en || lane == DP_USE_0_LANES)
 		val = DP_TX_MPLL_EN_SET_0LANES;
 	else if (lane == DP_USE_2_LANES)
 		val = DP_TX_MPLL_EN_SET_2LANES;
@@ -561,11 +556,12 @@ static void dpphy_reg_set_config12_tx_mpllb_en(enum lane_usage lane)
 	dp_phy_write_mask(SST1, DP_CONFIG12, val, DP_TX_MPLL_EN_MASK);
 }
 
-static void dpphy_reg_set_config12_tx_width(enum lane_usage lane)
+static void dpphy_reg_set_config12_tx_width(u32 en, enum lane_usage lane)
 {
 	u32 val = 0;
 
-	if (lane == DP_USE_0_LANES)
+	/* "0b11" is 20bit DP TX lane width */
+	if (!en || lane == DP_USE_0_LANES)
 		val = DP_TX_WIDTH_SET_0LANES;
 	else if (lane == DP_USE_2_LANES)
 		val = DP_TX_WIDTH_SET_2LANES;
@@ -577,47 +573,31 @@ static void dpphy_reg_set_config12_tx_width(enum lane_usage lane)
 
 static void dpphy_reg_set_config13_tx_reset(u32 en)
 {
-	u32 val = 0;
-
-	if (en)
-		val = DP_TX_RESET_ALL;
-	else
-		val = DP_TX_RESET_RELEASE;
-
-	dp_phy_write_mask(SST1, DP_CONFIG13, val, DP_TX_RESET_MASK);
-}
-
-static void dpphy_reg_set_config13_tx_enable(enum lane_usage lane)
-{
-	u32 val = 0;
-
-	if (lane == DP_USE_2_LANES)
-		val = DP_TX_ENABLE_SET_2LANES;
-	else if (lane == DP_USE_4_LANES)
-		val = DP_TX_ENABLE_SET_4LANES;
-
-	dp_phy_write_mask(SST1, DP_CONFIG13, val, DP_TX_DISABLE_MASK);
+	dp_phy_write_mask(SST1, DP_CONFIG13,
+			  en ? DP_TX_RESET_ALL : DP_TX_RESET_RELEASE,
+			  DP_TX_RESET_MASK);
 }
 
-static void dpphy_reg_set_config13_tx_disable(enum lane_usage lane)
+static void dpphy_reg_set_config13_tx_enable(u32 en, enum lane_usage lane)
 {
 	u32 val = 0;
 
-	if (lane == DP_USE_2_LANES)
+	/* "0b1" disables DP TX lane, "0b0" enables DP TX lane */
+	if (!en || lane == DP_USE_0_LANES)
+		val = DP_TX_DISABLE_SET_4LANES;
+	else if (lane == DP_USE_2_LANES)
 		val = DP_TX_DISABLE_SET_2LANES;
 	else if (lane == DP_USE_4_LANES)
-		val = DP_TX_DISABLE_SET_4LANES;
+		val = DP_TX_DISABLE_SET_0LANES;
 
 	dp_phy_write_mask(SST1, DP_CONFIG13, val, DP_TX_DISABLE_MASK);
 }
 
-static void dpphy_reg_set_config17_dcc_byp_ac_cap(u32 dcc_byp_ac_cap,
-						  enum lane_usage lane)
+static void dpphy_reg_set_config17_dcc_byp_ac_cap(u32 en, enum lane_usage lane)
 {
-	// Need to check this function
 	u32 val = 0;
 
-	if (lane == DP_USE_0_LANES)
+	if (!en || lane == DP_USE_0_LANES)
 		val = DP_TX_DCC_BYP_AC_CAP_SET_0LANES;
 	else if (lane == DP_USE_2_LANES)
 		val = DP_TX_DCC_BYP_AC_CAP_SET_2LANES;
@@ -692,11 +672,11 @@ static void dpphy_reg_reset_tx_lanes(void)
 {
 	// Assert all TX lanes reset
 	dpphy_reg_set_config13_tx_reset(1);
-	dpphy_reg_set_config13_tx_disable(DP_USE_4_LANES);
+	dpphy_reg_set_config13_tx_enable(0, DP_USE_4_LANES);
 	cal_log_debug(0, "disable all lanes.\n");
 
 	// Disable all TX lanes' power state: P2
-	dpphy_reg_set_config11_tx_pstate(DP_USE_0_LANES);
+	dpphy_reg_set_config11_tx_pstate(0, DP_USE_4_LANES);
 	cal_log_debug(0, "power off for all lanes.\n");
 
 	// Set TCA_TCPC Valid
@@ -707,8 +687,6 @@ static void dpphy_reg_reset_tx_lanes(void)
 
 	// De-Assert all TX lanes reset
 	dpphy_reg_set_config13_tx_reset(0);
-	dpphy_reg_set_config13_tx_enable(DP_USE_4_LANES);
-	cal_log_debug(0, "enable all lanes.\n");
 
 	// Wait TX_ACK De-Assert
 	dpphy_reg_wait_config12_tx_ack(DP_USE_4_LANES);
@@ -718,18 +696,18 @@ static void dpphy_reg_reset_mpllb(u32 en)
 {
 	if (en) {
 		// Assert USBDP PHY MPLLB reset
-		dpphy_reg_set_config12_tx_mpllb_en(DP_USE_0_LANES);
-		dpphy_reg_set_config11_tx_pstate(DP_USE_0_LANES);
+		dpphy_reg_set_config12_tx_mpllb_en(0, DP_USE_4_LANES);
+		dpphy_reg_set_config11_tx_pstate(0, DP_USE_4_LANES);
 		cal_log_debug(0, "disable mpllb and power off for all lanes\n");
 	} else {
 		// De-assert USBDP PHY MPLLB reset
-		dpphy_reg_set_config12_tx_mpllb_en(DP_USE_4_LANES);
-		dpphy_reg_set_config11_tx_pstate(DP_USE_4_LANES);
-		cal_log_debug(0, "enable mpllb and power off for all lanes\n");
+		dpphy_reg_set_config12_tx_mpllb_en(1, DP_USE_4_LANES);
+		dpphy_reg_set_config11_tx_pstate(1, DP_USE_4_LANES);
+		cal_log_debug(0, "enable mpllb and power on for all lanes\n");
 	}
 
 	// Request to update TX status
-	dpphy_reg_set_config12_status_update(DP_USE_4_LANES);
+	dpphy_reg_set_config12_status_update();
 	cal_log_debug(0, "status update for all lanes.\n");
 }
 
@@ -758,8 +736,6 @@ static void dpphy_reg_set_mpllb(struct dp_hw_config *hw_config, bool reconfig)
 	u32 mpllb_ssc_up_spread = 0, mpllb_tx_clk_div = 0, mpllb_v2i = 0,
 	    mpllb_word_div2_en = 0;
 	u32 ref_clk_en = 1;
-	// CONFIG17
-	u32 dcc_byp_ac_cap = 0;
 
 	if (hw_config->use_ssc) {
 		mpllb_ssc_en = 1;
@@ -820,7 +796,6 @@ static void dpphy_reg_set_mpllb(struct dp_hw_config *hw_config, bool reconfig)
 		mpllb_multiplier = 0x130;
 		mpllb_tx_clk_div = 0x2;
 		mpllb_v2i = 0x2;
-		dcc_byp_ac_cap = 0x1;
 		if (mpllb_ssc_en) {
 			/* Max down-spread (-0.5%) for RBR SSC */
 			mpllb_ssc_peak = 0xD800;
@@ -856,7 +831,9 @@ static void dpphy_reg_set_mpllb(struct dp_hw_config *hw_config, bool reconfig)
 
 	// Configure Reference Clock for DP
 	dpphy_reg_set_config7_refclk_en(ref_clk_en);
-	dpphy_reg_set_config17_dcc_byp_ac_cap(dcc_byp_ac_cap, DP_USE_4_LANES);
+
+	/* Enable the bypassing AC Capacitor for all lanes */
+	dpphy_reg_set_config17_dcc_byp_ac_cap(1, DP_USE_4_LANES);
 }
 
 static enum lane_usage dp_get_and_inform_lanes(struct dp_hw_config *hw_config)
@@ -918,17 +895,26 @@ static void dpphy_reg_switch_to_dp(enum lane_usage num_lane)
 	dpphytca_reg_wait_mode_change(num_lane);
 }
 
-static void dpphy_reg_set_lanes(enum lane_usage num_lane)
+static void dpphy_reg_set_lanes(struct dp_hw_config *hw_config, enum lane_usage num_lane)
 {
-	dpphy_reg_set_config13_tx_enable(num_lane);
-	cal_log_debug(0, "enable %d lanes.\n", num_lane);
+	dpphy_reg_set_config12_tx_width(1, num_lane);
+	dpphy_reg_set_config12_tx_mpllb_en(1, num_lane);
+	dpphy_reg_set_config11_tx_pstate(1, num_lane);
+	cal_log_debug(0, "enable mpllb/power for %d lanes.\n", num_lane);
+
+	dpphy_reg_set_config12_status_update();
+	cal_log_debug(0, "status update for all lanes.\n");
 
-	dpphy_reg_set_config12_tx_width(num_lane);
-	dpphy_reg_set_config12_tx_mpllb_en(num_lane);
-	cal_log_debug(0, "enable mpllb for %d lanes.\n", num_lane);
+	if (hw_config->link_rate > LINK_RATE_RBR) {
+		/*
+		 * Disable the bypassing AC capacitor for HBRx mode only.
+		 * RBR mode is using the bypassing AC capacitor as default.
+		 */
+		dpphy_reg_set_config17_dcc_byp_ac_cap(0, num_lane);
+	}
 
-	dpphy_reg_set_config12_status_update(num_lane);
-	cal_log_debug(0, "status update for %d lanes.\n", num_lane);
+	dpphy_reg_set_config13_tx_enable(1, num_lane);
+	cal_log_debug(0, "enable %d lanes.\n", num_lane);
 }
 
 static void dpphy_reg_init(struct dp_hw_config *hw_config, bool reconfig)
@@ -961,7 +947,7 @@ static void dpphy_reg_init(struct dp_hw_config *hw_config, bool reconfig)
 	cal_log_debug(0, "switch from USB to DP.\n");
 
 	/* Set DP TX lanes */
-	dpphy_reg_set_lanes(num_lane);
+	dpphy_reg_set_lanes(hw_config, num_lane);
 	cal_log_debug(0, "set DP TX lanes.\n");
 
 	/* De-assert DP Alt-mode Disable ACK */
@@ -1482,12 +1468,12 @@ static void dp_hw_set_data_path(struct dp_hw_config *hw_config)
 		break;
 	}
 
-	// SNPS PHY Clock Enable
-	dp_reg_set_snps_tx_clk_en(num_lane);
-
 	// SNPS PHY Clock Ready
 	dp_reg_set_snps_tx_clk_rdy(num_lane);
 
+	// SNPS PHY Clock Enable
+	dp_reg_set_snps_tx_clk_en(num_lane);
+
 	// SNPS PHY Data Enable
 	dp_reg_set_snps_tx_data_en(num_lane);
 }
diff --git a/samsung/cal_9865/regs-usbdpphy_ctrl.h b/samsung/cal_9865/regs-usbdpphy_ctrl.h
index b03f9ea..d36bc74 100644
--- a/samsung/cal_9865/regs-usbdpphy_ctrl.h
+++ b/samsung/cal_9865/regs-usbdpphy_ctrl.h
@@ -400,14 +400,14 @@
 #define DP_TX1_ACK			     (0x1 << 17)
 #define DP_TX0_ACK			     (0x1 << 16)
 #define DP_TX_ACK_GET(_v)		     (((_v) >> 16) & 0xF)
-#define DP_TX3_REQ_STATUS		     (0x1 << 15)
-#define DP_TX2_REQ_STATUS		     (0x1 << 14)
-#define DP_TX1_REQ_STATUS		     (0x1 << 13)
-#define DP_TX0_REQ_STATUS		     (0x1 << 12)
-#define DP_TX_REQ_STATUS_GET(_v)	     (((_v) >> 12) & 0xF)
-#define DP_TX_REQ_STATUS_SET_4LANES	     ((0xF & 0xF) << 12)
-#define DP_TX_REQ_STATUS_SET_2LANES	     ((0x3 & 0xF) << 12)
-#define DP_TX_REQ_STATUS_MASK		     (0xF << 12)
+#define DP_TX_ACK_MASK			     (0xF << 16)
+#define DP_TX3_REQ			     (0x1 << 15)
+#define DP_TX2_REQ			     (0x1 << 14)
+#define DP_TX1_REQ			     (0x1 << 13)
+#define DP_TX0_REQ			     (0x1 << 12)
+#define DP_TX_REQ_GET(_v)		     (((_v) >> 12) & 0xF)
+#define DP_TX_REQ_SET_4LANES		     ((0xF & 0xF) << 12)
+#define DP_TX_REQ_MASK			     (0xF << 12)
 #define DP_TX3_MPLL_EN			     (0x1 << 11)
 #define DP_TX2_MPLL_EN			     (0x1 << 10)
 #define DP_TX1_MPLL_EN			     (0x1 << 9)
@@ -457,10 +457,9 @@
 #define DP_TX2_DISABLE			     (0x1 << 2)
 #define DP_TX1_DISABLE			     (0x1 << 1)
 #define DP_TX0_DISABLE			     (0x1 << 0)
-#define DP_TX_ENABLE_SET_4LANES		     ((0x0 & 0xF) << 0)
 #define DP_TX_DISABLE_SET_4LANES	     ((0xF & 0xF) << 0)
-#define DP_TX_ENABLE_SET_2LANES		     ((0xC & 0xF) << 0)
-#define DP_TX_DISABLE_SET_2LANES	     ((0xF & 0xF) << 0)
+#define DP_TX_DISABLE_SET_2LANES	     ((0xC & 0xF) << 0)
+#define DP_TX_DISABLE_SET_0LANES	     ((0x0 & 0xF) << 0)
 #define DP_TX_DISABLE_MASK		     (0xF << 0)
 
 #define DP_CONFIG14			     (0x023C)
diff --git a/samsung/exynos_drm_dp.c b/samsung/exynos_drm_dp.c
index 105a004..604f01e 100644
--- a/samsung/exynos_drm_dp.c
+++ b/samsung/exynos_drm_dp.c
@@ -174,7 +174,7 @@ static bool dp_fec = false;
 module_param(dp_fec, bool, 0664);
 MODULE_PARM_DESC(dp_fec, "Enable/disable DP link forward error correction");
 
-static bool dp_ssc = false;
+static bool dp_ssc = true;
 module_param(dp_ssc, bool, 0664);
 MODULE_PARM_DESC(dp_ssc, "Enable/disable DP link spread spectrum clocking");