Merge android13-gs-pixel-5.10-24Q1 into android13-gs-pixel-5.10-24Q2

SBMerger: 571992243
Change-Id: I03436c202ae3a42d5f53308e3adecffbe7459cd5
Signed-off-by: SecurityBot <android-nexus-securitybot@system.gserviceaccount.com>

1 files changed, 21 insertions, 6 deletions

diff --git a/samsung/panel/panel-boe-nt37290.c b/samsung/panel/panel-boe-nt37290.c
index 337ff61..0870ce6 100644
--- a/samsung/panel/panel-boe-nt37290.c
+++ b/samsung/panel/panel-boe-nt37290.c
@@ -903,6 +903,19 @@ static void nt37290_set_lp_mode(struct exynos_panel *ctx,
 	dev_dbg(ctx->dev, "%s: done\n", __func__);
 }
 
+#define TE_WIDTH_USEC 162
+static void nt37290_wait_for_vsync_done(struct exynos_panel *ctx, u32 vrefresh)
+{
+	if (vrefresh != 60 && vrefresh != 120) {
+		dev_err(ctx->dev, "%s: unsupported refresh rate (%d)\n",
+			__func__, vrefresh);
+		return;
+	}
+
+	exynos_panel_wait_for_vsync_done(ctx, TE_WIDTH_USEC,
+			EXYNOS_VREFRESH_TO_PERIOD_USEC(vrefresh));
+}
+
 static void nt37290_wait_one_vblank(struct exynos_panel *ctx,
 				    const struct exynos_panel_mode *pmode)
 {
@@ -960,6 +973,7 @@ static int nt37290_enable(struct drm_panel *panel)
 	const struct drm_display_mode *mode;
 	const bool needs_reset = !is_panel_enabled(ctx);
 	bool is_fhd;
+	u32 vrefresh;
 
 	if (!pmode) {
 		dev_err(ctx->dev, "no current mode set\n");
@@ -968,6 +982,7 @@ static int nt37290_enable(struct drm_panel *panel)
 
 	mode = &pmode->mode;
 	is_fhd = mode->hdisplay == 1080;
+	vrefresh = needs_reset ? 60 : drm_mode_vrefresh(mode);
 
 	dev_dbg(ctx->dev, "%s (%s)\n", __func__, is_fhd ? "fhd" : "wqhd");
 
@@ -981,6 +996,12 @@ static int nt37290_enable(struct drm_panel *panel)
 		nt37290_update_panel_feat(ctx, pmode, true);
 	}
 
+	/* make sure both DPU and panel PPS are set in the same VSYNC */
+	if (ctx->mode_in_progress == MODE_RES_IN_PROGRESS)
+		nt37290_wait_for_vsync_done(ctx, vrefresh);
+	else if (ctx->mode_in_progress == MODE_RES_AND_RR_IN_PROGRESS)
+		nt37290_wait_for_vsync_done(ctx, ctx->last_rr);
+
 	exynos_panel_send_cmd_set(ctx,
 				  is_fhd ? &nt37290_dsc_fhd_cmd_set : &nt37290_dsc_wqhd_cmd_set);
 
@@ -1886,12 +1907,6 @@ const struct exynos_panel_desc boe_nt37290 = {
 	.binned_lp = nt37290_binned_lp,
 	.num_binned_lp = ARRAY_SIZE(nt37290_binned_lp),
 	.is_panel_idle_supported = true,
-	/*
-	 * After waiting for TE, wait for extra time to make sure the frame start
-	 * happens after both DPU and panel PPS are set and before the next VSYNC.
-	 * This reserves about 6ms for finishing both PPS and frame start.
-	 */
-	.delay_dsc_reg_init_us = 6000,
 	.panel_func = &nt37290_drm_funcs,
 	.exynos_panel_func = &nt37290_exynos_funcs,
 };