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| author | Midas Chien <midaschieh@google.com> | 2023-07-10 10:20:56 +0000 |
|---|---|---|
| committer | Midas Chien <midaschieh@google.com> | 2023-07-12 08:55:55 +0000 |
| commit | 3d626007717a5613f79c6f26609884cb0cd0373c (patch) | |
| tree | 77ace0271dda46c86772075b31a820a58c6e7db8 | |
| parent | 493053994da3d4f6afe0fafe8e06a409ee0fd5b5 (diff) | |
| download | shusky-3d626007717a5613f79c6f26609884cb0cd0373c.tar.gz | |
display: shoreline: correct 0x53h when turn on HBM
Correct 0x53h command to 0x20/0x28 when turn on HBM.
Bug: 279068446
Test: HBM on/off
Change-Id: Ibd8b309256cf8d721fb096f702b948f4d6e49b84
Signed-off-by: Midas Chien <midaschieh@google.com>
| -rw-r--r-- | display/panel-google-shoreline.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/display/panel-google-shoreline.c b/display/panel-google-shoreline.c index b24ed59..a3c8e33 100644 --- a/display/panel-google-shoreline.c +++ b/display/panel-google-shoreline.c @@ -78,7 +78,6 @@ static const struct drm_dsc_config pps_config = { #define SHORELINE_WRCTRLD_DIMMING_BIT 0x08 #define SHORELINE_WRCTRLD_BCTRL_BIT 0x20 -#define SHORELINE_WRCTRLD_HBM_BIT 0xC0 #define SHORELINE_WRCTRLD_LOCAL_HBM_BIT 0x10 #define SHORELINE_TE2_RISING_EDGE_60HZ 0x12D0 @@ -455,9 +454,6 @@ static void shoreline_update_wrctrld(struct exynos_panel *ctx) { u8 val = SHORELINE_WRCTRLD_BCTRL_BIT; - if (IS_HBM_ON(ctx->hbm_mode)) - val |= SHORELINE_WRCTRLD_HBM_BIT; - if (ctx->hbm.local_hbm.enabled) val |= SHORELINE_WRCTRLD_LOCAL_HBM_BIT; |