gpu: update the gpu driver for sc2 [2/2]

PD#SWPL-25844

Problem:
no support for sc2

Solution:
compatible with g12a/b, tl1, tm2
add sc2 support

Verify:
ptm board1/3
gpu.fill_buffer pass
gpu.gl2_basic pass
compute_particles pass

Change-Id: I6143a2b401022733075cc79a35d4adcc376e3d70
Signed-off-by: Jiyu Yang <Jiyu.Yang@amlogic.com>

5 files changed, 121 insertions, 124 deletions

diff --git a/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/mali_clock.c b/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/mali_clock.c
index 2f52dcc..097137f 100644
--- a/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/mali_clock.c
+++ b/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/mali_clock.c
@@ -529,7 +529,19 @@ int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata)
 	_dev_info(&pdev->dev, "hiu io source  0x%p\n", mpdata->reg_base_hiubus);
 
 	mpdata->reg_base_aobus = of_iomap(gpu_dn, 2);
-	_dev_info(&pdev->dev, "hiu io source  0x%p\n", mpdata->reg_base_aobus);
+	_dev_info(&pdev->dev, "aobus base 0x%p\n", mpdata->reg_base_aobus);
+
+	mpdata->reg_base_reset = of_iomap(gpu_dn, 1);
+	_dev_info(&pdev->dev, "reset bus 0x%p\n", mpdata->reg_base_reset);
+
+	mpdata->reset_g12a = 0;
+	ret = of_property_read_u32(gpu_dn,"clk_cntl_reg",
+			&mpdata->sc_mpp);
+	if (ret) {
+		mpdata->clk_cntl_reg = 0x6c;
+		mpdata->reset_g12a = 1;
+	}
+	_dev_info(&pdev->dev, "clk cntl reg = 0x%x\n", mpdata->clk_cntl_reg);
 
 	ret = of_property_read_u32(gpu_dn,"sc_mpp",
 			&mpdata->sc_mpp);
diff --git a/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/mali_kbase_runtime_pm.c b/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/mali_kbase_runtime_pm.c
index b734380..da7bf91 100644
--- a/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/mali_kbase_runtime_pm.c
+++ b/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/mali_kbase_runtime_pm.c
@@ -15,6 +15,7 @@
  *
  */
 
+//#define DEBUG
 #include <mali_kbase.h>
 #include <mali_kbase_defs.h>
 #include <linux/pm_runtime.h>
@@ -26,6 +27,8 @@
 #include <backend/gpu/mali_kbase_device_internal.h>
 #include "mali_kbase_config_platform.h"
 
+#include "mali_scaling.h"
+
 static void enable_gpu_power_control(struct kbase_device *kbdev)
 {
 #if 0
@@ -70,24 +73,24 @@ static void disable_gpu_power_control(struct kbase_device *kbdev)
 #endif
 }
 
-void *reg_base_hiubus = NULL;
-u32  override_value_aml = 0;
 static int first = 1;
 
+//remove this if sc2 worked fine.
+//g12a
 #define RESET0_MASK    0x10
 #define RESET1_MASK    0x11
 #define RESET2_MASK    0x12
-
-#define RESET0_LEVEL    0x20
-#define RESET1_LEVEL    0x21
-#define RESET2_LEVEL    0x22
-#define Rd(r)                           readl((reg_base_hiubus) + ((r)<<2))
-#define Wr(r, v)                        writel((v), ((reg_base_hiubus) + ((r)<<2)))
-#define Mali_WrReg(regnum, value)   kbase_reg_write(kbdev, (regnum), (value))
-#define Mali_RdReg(regnum)          kbase_reg_read(kbdev, (regnum))
-#define stimulus_print   printk
-#define stimulus_display printk
-#define Mali_pwr_off(x)  Mali_pwr_off_with_kdev(kbdev, (x))
+#define RESET0_LEVEL   0x20
+#define RESET1_LEVEL   0x21
+#define RESET2_LEVEL   0x22
+//sc2
+#define RESETCTRL_RESET1_LEVEL  0x11
+#define RESETCTRL_RESET1_MASK   0x21
+
+#define Rd(r)                           readl((reg_base_reset) + ((r)<<2))
+#define Wr(r, v)                        writel((v), ((reg_base_reset) + ((r)<<2)))
+#define Mali_WrReg(regnum, value)       writel((value), kbdev->reg + (regnum))
+#define Mali_RdReg(regnum)              readl(kbdev->reg + (regnum))
 
 extern u64 kbase_pm_get_ready_cores(struct kbase_device *kbdev, enum kbase_pm_core_type type);
 
@@ -125,8 +128,7 @@ static void  Mali_pwr_on_with_kdev ( struct kbase_device *kbdev, uint32_t  mask)
     }
 
     part1_done = Mali_RdReg(0x0000020);
-    while((part1_done ==0)) { part1_done = Mali_RdReg(0x00000020); }
-    stimulus_display("Mali_pwr_on:gpu_irq : %x\n", part1_done);
+    while (0 == part1_done) { part1_done = Mali_RdReg(0x00000020); }
     Mali_WrReg(0x0000024, 0xffffffff); // clear interrupts
 }
 
@@ -156,7 +158,6 @@ static void  Mali_pwr_off_with_kdev( struct kbase_device *kbdev, uint32_t  mask)
 
     part1_done = Mali_RdReg(0x0000020);
     while((part1_done ==0)) { part1_done = Mali_RdReg(0x00000020); }
-    stimulus_display("Mali_pwr_off:gpu_irq : %x\n", part1_done);
     Mali_WrReg(0x0000024, 0xffffffff); // clear interrupts
 }
 #endif
@@ -165,88 +166,71 @@ static int pm_callback_power_on(struct kbase_device *kbdev)
 {
 	int ret = 1; /* Assume GPU has been powered off */
 	int error;
-	struct platform_device *pdev = to_platform_device(kbdev->dev);
-	struct resource *reg_res;
-	u64 core_ready;
-	u64 l2_ready;
-	u64 tiler_ready;
+#if 1
+	//remove this if sc2 worked fine.
+	struct mali_plat_info_t *mpdata  = (struct mali_plat_info_t *) kbdev->platform_context;
+	void *reg_base_reset = mpdata->reg_base_reset;
 	u32 value;
+	int reset_g12a = mpdata->reset_g12a;
+#endif
 
-    //printk("20151013, %s, %d\n", __FILE__, __LINE__);
-    if (first == 0) goto ret;
-
-    reg_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-    if (!reg_res) {
-        dev_err(kbdev->dev, "Invalid register resource\n");
-        ret = -ENOENT;
-    }
-    //printk("%s, %d\n", __FILE__, __LINE__);
-    if (NULL == reg_base_hiubus) 
-        reg_base_hiubus = ioremap(reg_res->start, resource_size(reg_res));
-
-    //printk("%s, %d\n", __FILE__, __LINE__);
-    if (NULL == reg_base_hiubus) {
-        dev_err(kbdev->dev, "Invalid register resource\n");
-        ret = -ENOENT;
-    }
-
-    //printk("%s, %d\n", __FILE__, __LINE__);
+	if (first == 0) goto out;
+
+	first = 0;
+
+	if (reset_g12a) {
+		value = Rd(RESET0_MASK);
+		value = value & (~(0x1<<20));
+		//printk("line(%d), value=%x\n", __LINE__, value);
+		Wr(RESET0_MASK, value);
+
+		value = Rd(RESET0_LEVEL);
+		value = value & (~(0x1<<20));
+		//printk("line(%d), value=%x\n", __LINE__, value);
+		Wr(RESET0_LEVEL, value);
+		///////////////
+		value = Rd(RESET2_MASK);
+		value = value & (~(0x1<<14));
+		//printk("line(%d), value=%x\n", __LINE__, value);
+		Wr(RESET2_MASK, value);
+
+		value = Rd(RESET2_LEVEL);
+		value = value & (~(0x1<<14));
+		//printk("line(%d), value=%x\n", __LINE__, value);
+		Wr(RESET2_LEVEL, value);
+
+		value = Rd(RESET0_LEVEL);
+		value = value | ((0x1<<20));
+		//printk("line(%d), value=%x\n", __LINE__, value);
+		Wr(RESET0_LEVEL, value);
+
+		value = Rd(RESET2_LEVEL);
+		value = value | ((0x1<<14));
+		//printk("line(%d), value=%x\n", __LINE__, value);
+		Wr(RESET2_LEVEL, value);
+	} else {
+		//JOHNT
+		//remove this if sc2 worked fine.
+		value = ~(1 << 2);
+		dev_dbg(kbdev->dev, "line(%d),mask ~(1<<14)\n", __LINE__);
+		Wr(RESETCTRL_RESET1_MASK, value);
+		dev_dbg(kbdev->dev, "line(%d),level ~(1<<14)\n", __LINE__);
+		Wr(RESETCTRL_RESET1_LEVEL, value);
+		dev_dbg(kbdev->dev, "line(%d),level 0xFFFFFFFF\n", __LINE__);
+		Wr(RESETCTRL_RESET1_LEVEL, 0xFFFFFFFF);
+	}
+	udelay(10); // OR POLL for reset done
+	dev_dbg(kbdev->dev, "delay 10us\n");
 
-//JOHNT
-    // Level reset mail
-
-    // Level reset mail
-    //Wr(P_RESET2_MASK, ~(0x1<<14));
-    //Wr(P_RESET2_LEVEL, ~(0x1<<14));
-
-    //Wr(P_RESET2_LEVEL, 0xffffffff);
-    //Wr(P_RESET0_LEVEL, 0xffffffff);
-
-    value = Rd(RESET0_MASK);
-    value = value & (~(0x1<<20));
-    //printk("line(%d), value=%x\n", __LINE__, value);
-    Wr(RESET0_MASK, value);
-
-    value = Rd(RESET0_LEVEL);
-    value = value & (~(0x1<<20));
-    //printk("line(%d), value=%x\n", __LINE__, value);
-    Wr(RESET0_LEVEL, value);
-///////////////
-    value = Rd(RESET2_MASK);
-    value = value & (~(0x1<<14));
-    //printk("line(%d), value=%x\n", __LINE__, value);
-    Wr(RESET2_MASK, value);
-
-    value = Rd(RESET2_LEVEL);
-    value = value & (~(0x1<<14));
-    //printk("line(%d), value=%x\n", __LINE__, value);
-    Wr(RESET2_LEVEL, value);
-
-    value = Rd(RESET0_LEVEL);
-    value = value | ((0x1<<20));
-    //printk("line(%d), value=%x\n", __LINE__, value);
-    Wr(RESET0_LEVEL, value);
-
-    value = Rd(RESET2_LEVEL);
-    value = value | ((0x1<<14));
-    //printk("line(%d), value=%x\n", __LINE__, value);
-    Wr(RESET2_LEVEL, value);
-
-    udelay(10); // OR POLL for reset done
-
-    kbase_reg_write(kbdev, GPU_CONTROL_REG(PWR_KEY), 0x2968A819);
-    kbase_reg_write(kbdev, GPU_CONTROL_REG(PWR_OVERRIDE1), 0xfff | (0x20<<16));
-
-    Mali_pwr_on_with_kdev(kbdev, 0x1);
-    //printk("set PWR_ORRIDE, reg=%p, reg_start=%llx, reg_size=%zx, reg_mapped=%p\n",
-    //        kbdev->reg, kbdev->reg_start, kbdev->reg_size, reg_base_hiubus);
+	Mali_WrReg(GPU_CONTROL_REG(PWR_KEY), 0x2968A819);
+	Mali_WrReg(GPU_CONTROL_REG(PWR_OVERRIDE1), 0xfff | (0x20<<16));
+	Mali_pwr_on_with_kdev(kbdev, 0x1);
 	dev_dbg(kbdev->dev, "pm_callback_power_on %p\n",
 			(void *)kbdev->dev->pm_domain);
 
-    enable_gpu_power_control(kbdev);
-    first = 0;
-    //printk("%s, %d\n", __FILE__, __LINE__);
-ret:
+	enable_gpu_power_control(kbdev);
+
+out:
 	error = pm_runtime_get_sync(kbdev->dev);
 	if (error == 1) {
 		/*
@@ -256,14 +240,6 @@ ret:
 		ret = 0;
 	}
 	udelay(100);
-#if 1
-
-    core_ready = kbase_pm_get_ready_cores(kbdev, KBASE_PM_CORE_SHADER);
-    l2_ready = kbase_pm_get_ready_cores(kbdev, KBASE_PM_CORE_L2);
-    tiler_ready = kbase_pm_get_ready_cores(kbdev, KBASE_PM_CORE_TILER);
-    //printk("core_ready=%llx, l2_ready=%llx, tiler_ready=%llx\n", core_ready, l2_ready, tiler_ready);
-#endif
-	dev_dbg(kbdev->dev, "pm_runtime_get_sync returned %d\n", error);
 
 	return ret;
 }
@@ -272,10 +248,6 @@ static void pm_callback_power_off(struct kbase_device *kbdev)
 {
 	dev_dbg(kbdev->dev, "pm_callback_power_off\n");
     //printk("%s, %d\n", __FILE__, __LINE__);
-#if 0
-    iounmap(reg_base_hiubus);
-    reg_base_hiubus = NULL;
-#endif
 	pm_runtime_mark_last_busy(kbdev->dev);
 	pm_runtime_put_autosuspend(kbdev->dev);
 
diff --git a/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/mali_scaling.h b/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/mali_scaling.h
index aaab5da..225e888 100644
--- a/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/mali_scaling.h
+++ b/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/mali_scaling.h
@@ -99,6 +99,9 @@ typedef struct mali_plat_info_t {
     struct clk *clk_mali;
     struct clk *clk_mali_0;
     struct clk *clk_mali_1;
+    void __iomem *reg_base_reset;
+    u32 clk_cntl_reg;
+    s32 reset_g12a;
 } mali_plat_info_t;
 mali_plat_info_t* get_mali_plat_data(void);
 
diff --git a/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/platform_gx.c b/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/platform_gx.c
index ac49caa..c8ff2f5 100644
--- a/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/platform_gx.c
+++ b/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/platform_gx.c
@@ -35,6 +35,9 @@
 #include <linux/amlogic/meson_cooldev.h>
 #endif
 
+#include <mali_kbase.h>
+#include <mali_kbase_defs.h>
+
 #include "mali_scaling.h"
 #include "mali_clock.h"
 #include "meson_main2.h"
@@ -132,11 +135,8 @@ static u32 get_limit_mali_freq(void)
 #ifdef CONFIG_DEVFREQ_THERMAL
 static u32 get_mali_utilization(void)
 {
-#ifndef MESON_DRV_BRING
-    return 55;
-#else
-    return (_mali_ukk_utilization_pp() * 100) / 256;
-#endif
+    u32 util= mpgpu_get_utilization();
+    return (util * 100) / 256;
 }
 #endif
 #endif
@@ -163,29 +163,37 @@ quit:
     return ret;
 }
 #ifdef CONFIG_DEVFREQ_THERMAL
+extern u64 kbase_pm_get_ready_cores(struct kbase_device *kbdev, enum kbase_pm_core_type type);
 static u32 mali_get_online_pp(void)
 {
-    unsigned int val;
+    u64 core_ready;
+    u64 l2_ready;
+    u64 tiler_ready;
     mali_plat_info_t* pmali_plat = get_mali_plat_data();
+    struct platform_device* ptr_plt_dev = pmali_plat->pdev;
+    struct kbase_device *kbdev = dev_get_drvdata(&ptr_plt_dev->dev);
 
-    val = readl(pmali_plat->reg_base_aobus + 0xf0) & 0xff;
-    if (val == 0x07)    /* No pp is working */
+    core_ready = kbase_pm_get_ready_cores(kbdev, KBASE_PM_CORE_SHADER);
+    l2_ready = kbase_pm_get_ready_cores(kbdev, KBASE_PM_CORE_L2);
+    tiler_ready = kbase_pm_get_ready_cores(kbdev, KBASE_PM_CORE_TILER);
+
+    if (!core_ready && !l2_ready && !tiler_ready) {
         return 0;
+    }
 
-#ifndef MESON_DRV_BRING
     return 2;
-#else
-    return mali_executor_get_num_cores_enabled();
-#endif
 }
 #endif
 #endif
 
 int mali_meson_init_start(struct platform_device* ptr_plt_dev)
 {
-    //dev_set_drvdata(&ptr_plt_dev->dev, &mali_plat_data);
+    struct kbase_device *kbdev = dev_get_drvdata(&ptr_plt_dev->dev);
+
     mali_dt_info(ptr_plt_dev, &mali_plat_data);
     mali_clock_init_clk_tree(ptr_plt_dev);
+
+    kbdev->platform_context = &mali_plat_data;
     return 0;
 }
 
diff --git a/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/scaling.c b/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/scaling.c
index 12c5081..2caff3c 100644
--- a/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/scaling.c
+++ b/dvalin/kernel/drivers/gpu/arm/midgard/platform/devicetree/scaling.c
@@ -295,7 +295,6 @@ int mali_core_scaling_init(mali_plat_info_t *mali_plat)
 	}
 
 	pmali_plat = mali_plat;
-    printk("mali_plat=%p\n", mali_plat);
 	num_cores_enabled = pmali_plat->sc_mpp;
 #if AMLOGIC_GPU_USE_GPPLL
 	gp_pll_user_gpu = gp_pll_user_register("gpu", 1,
@@ -593,12 +592,15 @@ void mali_dev_freeze(void)
 
 void mali_dev_restore(void)
 {
-
-	mplt_write(HHI_MALI_CLK_CNTL, clk_cntl_save);
-	if (pmali_plat && pmali_plat->pdev) {
-		mali_clock_init_clk_tree(pmali_plat->pdev);
-	} else {
+	u32 reg = 0;
+	if (!pmali_plat  || !pmali_plat->pdev) {
 		printk("error: init clock failed, pmali_plat=%p, pmali_plat->pdev=%p\n",
 				pmali_plat, pmali_plat == NULL ? NULL: pmali_plat->pdev);
+		return ;
 	}
+
+	reg = pmali_plat->clk_cntl_reg;
+
+	mplt_write(reg, clk_cntl_save);
+	mali_clock_init_clk_tree(pmali_plat->pdev);
 }