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| author | Jiyu Yang <jiyu.yang@amlogic.com> | 2017-11-01 16:20:26 +0800 |
|---|---|---|
| committer | Jiyu Yang <Jiyu.Yang@amlogic.com> | 2017-11-01 16:25:08 +0800 |
| commit | 77e364837427ec991544f9b55a8f3a6275ddb706 (patch) | |
| tree | 42e1766efd74cedf637ffa0f9c52e43cbc5e77ae | |
| parent | f6e2449846229d1e816281f5c7ce341702fc5a0d (diff) | |
| download | mali-driver-77e364837427ec991544f9b55a8f3a6275ddb706.tar.gz | |
gpu: check def_clk when probe
PD#152825:
Change-Id: I9fb943fb13a0c3644d9247ce63eb394a0bcd1dbf
Signed-off-by: Jiyu Yang <jiyu.yang@amlogic.com>
| -rw-r--r-- | utgard/platform/meson_bu/mali_clock.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/utgard/platform/meson_bu/mali_clock.c b/utgard/platform/meson_bu/mali_clock.c index 81cce49..18076ac 100644 --- a/utgard/platform/meson_bu/mali_clock.c +++ b/utgard/platform/meson_bu/mali_clock.c @@ -358,6 +358,8 @@ int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata) dev_notice(&pdev->dev, "default clk set to %d\n", mpdata->dvfs_table_size/2-1); mpdata->def_clock = mpdata->dvfs_table_size/2 - 1; } + if (mpdata->def_clock > mpdata->scale_info.maxclk) + mpdata->def_clock = mpdata->scale_info.maxclk; _dev_info(&pdev->dev, "default clk is %d\n", mpdata->def_clock); dvfs_tbl = mpdata->dvfs_table; @@ -642,6 +644,8 @@ int mali_dt_info(struct platform_device *pdev, struct mali_plat_info_t *mpdata) dev_notice(&pdev->dev, "default clk set to %d\n", mpdata->dvfs_table_size/2-1); mpdata->def_clock = mpdata->dvfs_table_size/2 - 1; } + if (mpdata->def_clock > mpdata->scale_info.maxclk) + mpdata->def_clock = mpdata->scale_info.maxclk; _dev_info(&pdev->dev, "default clk is %d\n", mpdata->def_clock); dvfs_tbl = mpdata->dvfs_table; |